TWI641133B - Semiconductor cell - Google Patents

Abstract

A semiconductor unit includes a substrate, a channel layer, a first barrier layer, a laminate, a first electrode, and a second electrode. The channel layer has a first energy gap and is located above the substrate; the first barrier layer is above the channel layer, has a second energy gap, and the second energy gap is larger than the first energy gap; the stack is above the first barrier layer a non-three-five semiconductor epitaxial layer or a tantalum nitride layer, and a p-type semiconductor layer; the first electrode is located above the first barrier layer; and the second electrode is located above the first barrier layer, and The first electrode is separated.

Description

Semiconductor unit

The present invention relates to a semiconductor unit, and more particularly to a semiconductor unit having a protective layer.

The aluminum gallium nitride/gallium nitride high electron mobility transistor is a next generation high power component with potential for development. Due to their superior material properties, stable component characteristics can be maintained at high temperatures and pressures.

The invention provides a semiconductor unit comprising a substrate, a buffer layer, a channel layer, a first barrier layer, a stack, a source, a drain and a gate. The buffer layer is located above the substrate; the channel layer has a first energy gap and is located above the buffer layer; the first barrier layer is located above the channel layer, has a second energy gap, and the second energy gap is larger than the first energy gap; The layer is located above the first barrier layer and comprises a tantalum nitride layer and a first conductivity type compound semiconductor layer; the source is located above the first barrier layer; the drain is located above the first barrier layer and is opposite to the source Separate; the gate is located between the source and the drain.

The invention provides a semiconductor unit comprising a substrate, a channel layer, a first barrier layer, a laminate, a first electrode and a second electrode. The channel layer has a first energy gap and is located above the substrate; the first barrier layer is above the channel layer, has a second energy gap, and the second energy gap is larger than the first energy gap; the stack is above the first barrier layer a non-three-five semiconductor epitaxial layer or a tantalum nitride layer, and a p-type semiconductor layer; the first electrode is located above the first barrier layer; and the second electrode is located above the first barrier layer, and The first electrode is separated.

The implementation of the present invention is, for example, the same or similar parts as those shown in the drawings.

Please refer to FIG. 1, which is a top view of a semiconductor device S according to a first embodiment of the present invention. The semiconductor element S is, for example, a three-terminal element. In the present embodiment, the semiconductor element S includes a source pad S70, a drain pad S80, a gate pad S90, and a plurality of semiconductor units 1. The semiconductor unit 1 is, for example, a field effect transistor, and in particular may be a high electron mobility transistor (HEMT). Further, when distinguished by an operation, the semiconductor unit 1 may be a normally-on transistor or a normally-off transistor. In the first embodiment, the semiconductor unit 1 includes a source 70 electrically connected to the source pad S70, a drain electrically connected to the drain pad S80, a gate 90 electrically connected to the gate pad S90, and a semiconductor stack. (Unlabeled), the material, location and design of the laminate can be adjusted according to actual needs. Further, the plurality of semiconductor units 1 included in the semiconductor element S are applicable to the semiconductor unit in other embodiments, for example, the semiconductor units 2, 3, 4, 5, 6 in the second to sixth embodiments can be used. The semiconductor unit 1 of the first embodiment is replaced. In order to clearly explain the detailed structure of the semiconductor units 2, 3, 4, 5, and 6 in the different embodiments, the semiconductor units 2, 3, 4, 5, and 6 are partially enlarged. For details, please refer to FIG. 2A, FIG. 3A, and FIG. 4A, 5A, and 6A. The position of the enlarged portion of the semiconductor cells 2, 3, 4, 5, 6 with respect to the semiconductor S is indicated in the region E in Fig. 1.

Please refer to the semiconductor unit 2 of the second embodiment of the present invention shown in FIGS. 2A to 2B. 2A is a partial top view of the semiconductor unit 2, corresponding to the position of the region E; and FIG. 2B is a schematic cross-sectional view of the semiconductor unit 2. In the second embodiment, the semiconductor unit 2 may be a normally-on transistor or a normally-off transistor. The semiconductor unit 2 includes a substrate 10, a nucleation layer 20, a buffer layer 30, a channel layer 40, a first barrier layer 50, a laminate 260, a source 70, a drain 80, and a gate 90. The nucleation layer 20 and the buffer layer 30 are sequentially located above the substrate 10; the channel layer 40 has a first energy gap and is located above the buffer layer 30; the first barrier layer 50 is located above the channel layer 40, and has a second energy. And a second energy gap is larger than the first energy gap; the layer 260 is located above the first barrier layer 50, and includes a first protective layer 261 and a first conductive type compound semiconductor layer 263; the source 70 is located at the first barrier layer Above one of the portions 50; the drain 80 is located above the other portion of the first barrier layer 50 and is separated from the source 70; the gate 90 is located between the source 70 and the drain 80.

In this embodiment, the substrate 10 is, for example, a germanium substrate having a thickness of about 1000 to 1200 um, and the nucleation layer 20, the buffer layer 30, the channel layer 40, the first barrier layer 50, and the layer 260 are grown by epitaxy. On the (111) plane of the substrate 10, it grows in the [0001] direction. The epitaxial method is, for example, metal-organic chemical vapor deposition (MOCVD) or molecular-beam epitaxy (MBE). The substrate 10 may be a conductive substrate or an insulating substrate, and the material of the substrate 10 may be germanium (Si), tantalum carbide (SiC), gallium nitride (GaN) or sapphire. In other embodiments, part of the substrate 10 can also be removed to reduce the leakage path to achieve the effect of reducing leakage.

The nucleation layer 20 is located above the substrate 10 and has a thickness of about several tens of nanometers or hundreds of nanometers to reduce the lattice difference between the substrate 10 and the first barrier layer 40. The nucleation layer 20 is, for example, a tri-five material including materials such as aluminum nitride (AlN), gallium nitride (GaN), or aluminum gallium nitride (AlGaN). The buffer layer 30 is located above the nucleation layer 20 and has a thickness of about several micrometers or tens of micrometers. The material of the buffer layer 30 can be a tri-five material, which is also used to reduce the lattice difference between the substrate 10 and the first barrier layer 40. Reduce lattice defects. In this embodiment, the buffer layer 30 may include a super lattice multilayer including materials such as aluminum nitride (AlN), gallium nitride (GaN), or aluminum gallium nitride (AlGaN). The lattice stack is composed of a laminate of two different materials, and may be stacked alternately in two or two. The material may be a group of three or five materials, for example, an aluminum nitride layer (AlN) and a gallium nitride aluminum layer (AlGaN). The material of the buffer layer 30 can also be composed of a carbon-doped gallium nitride layer, and the carbon-doped gallium nitride layer (GaN) has a carbon doping concentration which is gradual or fixed.

The channel layer 40 has a thickness ranging from 50 to 300 nm and is formed on the buffer layer 30 and has a first energy gap. The first barrier layer 50 has a thickness ranging from 20 to 50 nm, is formed on the channel layer 40, and has a second energy gap. The second energy gap is higher than the first energy gap, and the lattice constant ratio of the first barrier layer 50 is lower. The channel layer 40 is small. In the present embodiment, the channel layer 40 comprises indium gallium nitride (In _x Ga _(1-x) N), 0 ≦ x < 1, and the first barrier layer 50 comprises aluminum indium gallium nitride (Al _y In _z Ga _(1-z) N), 0 < y < 1, 0 ≦ z < 1. The channel layer 40 and the first barrier layer 50 themselves form spontaneous polarization, and piezoelectric polarization is formed due to different lattice constants thereof, and further between the channel layer 40 and the first barrier layer 50. The heterojunction produces a two-dimensional electron gas (shown in phantom in the figure). In this embodiment, the channel layer 40 and the first barrier layer 50 may be intrinsic semiconductors.

The laminate 260 is grown on the first barrier layer 50 in an epitaxial growth manner, and includes a first protective layer 261 and a first conductive type compound semiconductor layer 263. The first protective layer 261 and the first conductive type compound semiconductor layer 263 are formed in the same order, and as shown in FIG. 2B, the first conductive type compound semiconductor layer 263 may be formed after the first protective layer 261 is formed, or may be another The cross section of the semiconductor unit 2 of one embodiment is shown in FIG. 2C, and the first conductive type compound semiconductor layer 263 is formed first to form the first protective layer 261.

The first protective layer 261 serves to protect the surface of the first barrier layer 50 underneath to improve leakage current of the surface and to prevent moisture from penetrating. In general, the first protective layer 261 may be grown on the first barrier layer 50 by deposition or the like when the first protective layer 261 is formed. In this embodiment, in order to avoid contamination or damage to the semiconductor unit 1, In order to improve the quality and compactness of the first protective layer 261, the first protective layer 261 may be grown in an epitaxial manner. The first protective layer 261 is, for example, a metal-organic chemical vapor deposition method. Depositing, MOCVD) or molecular-beam epitaxy (MBE) or the like, the epitaxially grown tantalum nitride layer (insitu SiNx), but the invention is not limited thereto, and the first protective layer 261 can also Epitaxial growth is performed over the first barrier layer 50 in a manner different from that described above. The first protective layer 261 may also be an oxide such as hafnium oxide. The first conductive type compound semiconductor layer 263 material comprises a p-type or n-type semiconductor material, and the n-type semiconductor material comprises an n-type impurity doped or undoped intrinsic semiconductor, which may be an n-type tri-five compound semiconductor, for example, an n-type Aluminum gallium nitride n-AlGaN. In the present embodiment, the material of the first conductive type compound semiconductor layer 263 is, for example, a p-type tri-five semiconductor such as a p-type gallium nitride layer (p-GaN), which functions to reduce two-dimensional electrons under the gate 90. The gas concentration further increases the on-resistance such that the semiconductor unit 2 is normally off in a state where the gate is not biased. In other words, in the second embodiment, the semiconductor unit 2 is a normally off type high electron turnover transistor.

After the stack 260 is formed, the source 70, the drain 80, and the gate 90 are respectively formed over the first barrier layer 50 as an end point electrically connected to the outside. The source 70 and the drain 80 are respectively disposed on both sides of the first barrier layer 50, and the gate 90 is located above the stack 260 and between the source 70 and the drain 80. In other words, the stack 260 is located below the gate 90 and between the source 70 and the drain 80. In this embodiment, the drain electrode 80 and the source 70 and the first barrier layer 50 can be separated by selecting an appropriate source and drain material and/or by a process such as thermal annealing. An ohmic contact is formed. Similarly, the gate 90 and the first conductive type compound semiconductor layer 263 may form a Schottky contact by selecting an appropriate material of the gate. The material of the source 70 and the drain 80 may be selected from titanium (Ti) and aluminum (Al), and the material of the gate 90 may be selected from nickel (Ni), gold (Au), tungsten (W), and titanium nitride (TiN). ).

In the present embodiment, before the source 70, the drain 80 and the gate 90 are formed, the dielectric layer 100 shown in FIG. 2D of the semiconductor unit 2 of another embodiment may be formed on the laminate 260. And a portion of the upper surface of the first barrier layer 50. A portion of the dielectric layer 100 is located below the gate 90 and between the gate 90 and the stack 260, which can further reduce surface leakage current, improve the operating bias range of the gate 90, and improve component reliability. The dielectric layer 100 may be an oxide or a nitride, for example, an oxide such as ruthenium oxide or aluminum oxide, or a nitride such as tantalum nitride or gallium nitride. However, the present invention is not limited thereto, and the dielectric layer 100 may not be formed in other embodiments. In addition, after forming the source 70, the drain 80 and the gate 90 described above, a second protective layer (not shown) may be further formed to cover the dielectric layer 100, the laminate 260, the source 70, and the drain 80. The surface of the gate 90 is used to prevent the electrical properties of the channel layer 40 from being affected. In this embodiment, the second protective layer may be an oxide or a nitride, such as an oxide such as yttrium oxide or aluminum oxide, or a nitride such as tantalum nitride or gallium nitride. Then, the second protective layer is further etched to expose a portion of the source 70, the drain 80 and the gate 90 to be electrically connected to the outside. The source 70, the drain 80 and the gate 90 may have a portion of the surface not being protected by the second protective layer. Covered to increase the convenience of electrical connection with the outside world.

The semiconductor unit 2 of the second embodiment includes a laminate 260 composed of a first protective layer 261 and a first conductive type compound semiconductor layer 263. The first protective layer 261 may be an epitaxially grown tantalum nitride layer, thereby improving the surface leakage current and protecting the epitaxial surface, and the first conductive type compound semiconductor layer 263 is, for example, p-type gallium nitride. The effect of reducing the two-dimensional electron gas concentration to improve the on-resistance under the gate 90 is achieved.

3A and 3B, FIG. 3A is a partial top view of the semiconductor unit 3 according to the third embodiment of the present invention; FIG. 3B is a schematic cross-sectional view of the semiconductor unit 3 according to the third embodiment of the present invention. As described above, the semiconductor element S may include a plurality of semiconductor units 3 shown in FIGS. 3A to 3B in addition to the plurality of semiconductor units 1 or 2. The semiconductor unit 3 includes a substrate 10, a nucleation layer 20, a buffer layer 30, a channel layer 40, a first barrier layer 50, a second barrier layer 52, a laminate 360, a source 70, a drain 80, and a gate 90.

The semiconductor unit 3 of the third embodiment is, for example, a field effect transistor, and may be a normally-on high-electron mobility transistor, which is turned on without applying a bias voltage to the gate. In the manufacturing method of the third embodiment, the nucleation layer 20, the buffer layer 30, the channel layer 40, and the first barrier layer 50 are first formed on the substrate 10 in this order. After the first barrier layer 50 is formed, a second barrier layer 52 is formed thereon. Next, a laminate 360 is formed over the second barrier layer 52, wherein the laminate 360 includes a first protective layer 361 and a first conductive type compound semiconductor layer 363, and the first protective layer 361 may be epitaxially grown nitrogen.矽 layer.

After forming the layer 360, the pattern is defined by a yellow light developing process, and then the portion of the layer 360 is etched to expose a portion of the second barrier layer 52, and then the source 70 is formed on the exposed second barrier layer 52. The pole 80 is then thermally annealed such that the source 70 and the drain 80 form an ohmic contact with the second barrier layer 52. After the source 70 and the drain 80 are formed, the pattern is defined by a yellow light developing process, and then the portion of the layer 360 is etched to expose the second barrier layer 52, and then the gate is formed on the exposed second barrier layer 52. The pole 90, wherein the gate 90 and the second barrier layer 52 are in Schottky contact.

In the present embodiment, the second barrier layer 52 is located between the laminate 360 and the first barrier layer 50 and serves as an etch stop layer. In addition, this embodiment etches the laminate 360 by dry etching. When the portion of the stack 360 is etched using the etching gas, since the etch rate of the second barrier layer 52 is lower than the etch rate of the first barrier layer 50, the depth of the etch may substantially stop at the second barrier layer 52. Upper surface. The material of the second barrier layer 52 is, for example, a three-five-semiconductor layer, which may be aluminum nitride or an aluminum-aluminum gallium layer composed of high aluminum, the aluminum composition of which is larger than the aluminum composition of the first barrier layer 50, and The energy gap of the second barrier layer 52 is greater than the first energy gap of the channel layer 40 and the second energy gap of the first barrier layer 50. The laminate 360 is located between the source 70 and the gate 90 and between the gate 80 and the gate 90, and the first conductive type compound semiconductor layer 363 of the laminate 360 is located at the first protective layer 361 and the second barrier layer Between 52, and the first conductive type compound semiconductor layer 363 and the gate 90 are not connected, there is a gap therebetween. In the present embodiment, in order to increase the two-dimensional electron gas concentration under the source 70 and the gate 90 or the drain 80 and the gate 90, the first conductive type compound semiconductor layer 363 may be an n-type tri-five compound semiconductor layer. For example, it is an n-type aluminum gallium nitride, but the present application is not limited to the above. In other embodiments, in order to change the spontaneous polarization and the piezoelectric polarization effect, the channel layer 40 and the first barrier layer 50 may be a doped semiconductor layer, and the doped material may be decane (SiH ₄ ). Used to dope the ruthenium. The material, thickness range and function of the substrate 10, the nucleation layer 20, the buffer layer 30, the channel layer 40, the first barrier layer 50, the source 70, the drain 80 and the gate 90 are described in the second embodiment.

Please refer to FIG. 4A to FIG. 4B. FIG. 4A is a partial top view of the semiconductor unit according to the fourth embodiment of the present invention. 4B is a schematic cross-sectional view showing a semiconductor unit according to a fourth embodiment of the present invention. The semiconductor element S may be electrically connected by a plurality of semiconductor units 1 or 2 or 3, or may be electrically connected by a plurality of semiconductor units 4 shown in FIGS. 4A to 4B. The semiconductor unit 4 includes a substrate 10, a nucleation layer 20, a buffer layer 30, a channel layer 40, a first barrier layer 50, a second barrier layer 52, a laminate 460, a source 70, a drain 80, and a gate 90.

The semiconductor unit 4 shown in FIGS. 4A to 4B is similar to the semiconductor unit 3 of FIGS. 3A to 3B, and is a normally open type high electron mobility transistor, which differs in the first protective layer of the laminate 460. The order of formation of 461 (such as a tantalum nitride layer) and the first conductive type compound semiconductor layer 463. In the third embodiment, the first conductive type compound semiconductor layer 363 is formed first, and then the first protective layer 361 (such as a tantalum nitride layer) is formed. In the manufacturing method of the fourth embodiment, the nucleation layer 20, the buffer layer 30, the channel layer 40, the first barrier layer 50, and the second barrier layer 52 are sequentially formed on the substrate 10, and then The first protective layer 461 is formed on the second barrier layer 52, and then the first conductive type compound semiconductor layer 463 is formed on the first protective layer 461. After forming the layer 460, the pattern is defined by a yellow light developing process, and then the portion of the layer 460 is etched to expose a portion of the second barrier layer 52, and then the source 70 is formed on the exposed second barrier layer 52. The pole 80 is then thermally annealed such that the source 70 and the drain 80 form an ohmic contact with the second barrier layer 52. After the source 70 and the drain 80 are formed, the gate 90 is formed again.

When the gate electrode 90 of the fourth embodiment is formed, a pattern is defined by using a yellow light developing process, and then a portion of the first conductive type compound semiconductor layer 463 and the first protective layer 461 are exposed to expose a second barrier layer. 52. A gate 90 is then formed on the exposed second barrier layer 52, wherein the gate 90 is connected to the first protective layer 461. In the present embodiment, since the etching rate of the etching gas to the first protective layer 461 and the first conductive type compound semiconductor layer 463 is not the same, more of the first conductive type compound semiconductor layer 463 is etched, and the bare portion is exposed. The first protective layer 461. In addition, since the first protective layer 461 is connected to the gate 90, the first protective layer 461 and the gate 90, the source 70, and the drain 80 substantially cover the upper surface of the entire second barrier layer 52, thus It can effectively prevent moisture from entering and avoid surface leakage current. Moreover, as shown, the first protective layer 461 is connected to the gate 90. For the gate 90, the tantalum nitride layer 461 provides a lateral supporting force to prevent the gate 90 from collapsing. For the material, thickness range and function of the substrate 10, the nucleation layer 20, the buffer layer 30, the channel layer 40, the first barrier layer 50, the source 70, the drain 80 and the gate 90, please refer to the related description of the second embodiment. . For the material selection of the second barrier layer 52 and the laminate 460, please refer to the description of the second barrier layer 52 and the laminate 360 in the third embodiment.

Referring to FIGS. 5A to 5B, FIG. 5A is a partial top plan view showing a semiconductor unit according to a fifth embodiment of the present invention. Fig. 5B is a schematic cross-sectional view showing a semiconductor unit according to a fifth embodiment of the present invention. The semiconductor element S may be electrically connected by a plurality of semiconductor units 1 to 4, or may be electrically connected by a plurality of semiconductor units 5 shown in FIGS. 5A to 5B. In the present embodiment, the semiconductor unit 5 includes a substrate 10, a nucleation layer 20, a buffer layer 30, a channel layer 40, a first barrier layer 50, a stack 560, a source 70, a drain 80, and a gate 90'. .

The semiconductor unit 5 shown in FIGS. 5A to 5B is similar to the semiconductor unit 3 of FIGS. 3A to 3B, and is also a normally-open type high electron mobility transistor, and the main difference between the two is the shape of the gate. In the manufacturing method of the fifth embodiment, the nucleation layer 20, the buffer layer 30, the channel layer 40, the first barrier layer 50, and the layer stack 560 are sequentially formed on the substrate 10 to form the layer stack 560. Thereafter, a pattern is defined by a yellow light developing process, and then a portion of the stack 560 is etched to expose a portion of the second barrier layer 52, and then a source 70, a drain 80 is formed on the exposed second barrier layer 52, and then The thermal annealing causes the source 70 and the drain 80 to form an ohmic contact with the second barrier layer 52. After the source 70 and the drain 80 are formed, the gate 90' is formed again.

When the gate electrode 90' of the fifth embodiment is formed, the pattern is defined by the yellow light developing process, and then the first protective layer 561 and the first conductive type compound semiconductor layer 563 are etched to expose the first barrier of the exposed portion. Layer 50, followed by gate 90' is formed on exposed first barrier layer 50.

In the present embodiment, the first protective layer 561 and the first conductive type compound semiconductor layer 563 are etched by dry etching. In general, dry etched etch gases will correspond to different etch rates for different materials. In the present embodiment, since the etching rate of the etching gas to the first protective layer 561 is lower than the etching rate of the first conductive type compound semiconductor layer 563, more of the first conductive type compound semiconductor layer 563 is etched. . In other words, the notch diameter d1 formed by the etching of the first protective layer 561 is smaller than the notch diameter d2 formed by the etching of the first conductive type compound semiconductor layer 563. When the gate 90' is formed, a portion of the material for forming the gate 90' is deposited on the exposed first barrier layer 50 through the gap of the first protective layer 561 and the gap of the first conductive type compound semiconductor layer 563. The other portion of the material used to form the gate 90' is deposited directly adjacent the gap of the first protective layer 561, thereby forming a T-type gate 90'. In the present embodiment, the first protective layer 561 of the stack 560 (such as a tantalum nitride layer) is located above the first conductive type compound half layer 563 and connected to the T-shaped gate 90'. For the gate 90', The first protective layer 561 provides lateral support to avoid collapse of the gate 90'. In addition, since the first protective layer 561 is connected to the gate 90 ′, the upper surface of the first barrier layer 50 is substantially covered by the first protective layer 561 and the gate 90 ′, the source 70 , and the drain 80 . In this way, water vapor can be effectively prevented from entering and surface leakage current can be avoided. The material, thickness range and function of the substrate 10, the nucleation layer 20, the buffer layer 30, the channel layer 40, the first barrier layer 50, the source 70, the drain 80 and the gate 90' are referred to in the second embodiment. description. For the material selection of the laminate 560, please refer to the description of the laminate 360 in the third embodiment.

The semiconductor units 3, 4, and 5 of the third embodiment to the fifth embodiment respectively include a stack 360 composed of the first protective layers 361, 461, and 561 and the first conductive type compound semiconductor layers 363, 463, and 563. 460, 560. The first protective layer 361, 461, 561 may be an epitaxially grown tantalum nitride layer, whereby the effect of improving surface leakage current and protecting the epitaxial surface can be achieved. The first conductive type compound semiconductor layers 363, 463, and 563 are, for example, n-type aluminum gallium nitride, which can improve the two-dimensional electron gas concentration and further reduce the on-resistance.

Referring to FIGS. 6A and 6B, FIG. 6A is a partial top plan view of a semiconductor unit according to a sixth embodiment of the present invention. 6B is a cross-sectional view showing a semiconductor unit according to a sixth embodiment of the present invention. The semiconductor element S may be electrically connected by a plurality of semiconductor units 1 to 5, or may be electrically connected by a plurality of semiconductor units 6 shown in FIGS. 6A to 6B. The semiconductor unit 6 includes a substrate 10, a nucleation layer 20, a buffer layer 30, a channel layer 40, a first barrier layer 50, a second barrier layer 52, a third barrier layer 54, a stack 660, a source 70, Bungee 80 and gate 90.

The semiconductor unit 6 shown in FIGS. 6A to 6B is similar to the semiconductor unit 2 of FIGS. 2A to 2D, and is also a normally off type high electron mobility transistor. The main difference between the two is that The sixth embodiment further includes a third barrier layer 54. In the manufacturing method of the sixth embodiment, the nucleation layer 20, the buffer layer 30, the channel layer 40, the first barrier layer 50, and the second barrier layer 52 are sequentially formed on the substrate 10, and then the first layer is formed. A triple barrier layer 54 is over the second barrier layer 52 and then a stack 660 is formed over the third barrier layer 54. The material or composition of the third barrier layer 54 may be the same as or different from that of the first barrier layer 50. In the embodiment, the materials of the third barrier layer 54 and the first barrier layer 50 are all aluminum gallium nitride, but The aluminum composition of the third barrier layer 54 is higher than the aluminum composition of the first barrier layer 50.

The laminate 660 includes a first protective layer 661 and a first conductive type compound semiconductor layer 663. The first protective layer 661 and the first conductive type compound semiconductor layer 663 are disposed in the third barrier layer 54 in a sequential or reverse order. Above, the third barrier layer 54 is located between the stack 660 and the second barrier layer 52, and the second barrier layer 52 can serve as a stop layer in a subsequent etching process. After forming the stack 660, an etching step is performed, first defining a pattern using a yellow lithography process, then etching away portions of the stack 660 to expose portions of the third barrier layer 54, and then forming the source 70 and the drain 80 to be exposed The third barrier layer 54 is subjected to a thermal annealing step such that the source 70 is in ohmic contact with the drain 80 and the third barrier layer 54. Next, the yellow light lithography process is also used to define the pattern, and then the portion of the layer 660 and the portion of the third barrier layer 54 are etched first, and the appropriate etching gas and etching conditions (such as temperature, etching duration, etc.) are used. The etching depth is substantially stopped at the upper surface of the second barrier layer 52, and the exposed portion of the second barrier layer 52, the gate 90 is formed on the upper surface of the exposed second barrier layer 52. As shown, the source 70 and the drain 80 are disposed separately and are located at both ends of the second barrier layer 52, and the gate 90 is located between the source 70 and the drain 80. In this embodiment, a portion of the stack 660 is between the gate 90 and the source 70/drain 80. However, the invention is not limited to the above. The material, thickness range and function of the substrate 10, the nucleation layer 20, the buffer layer 30, the channel layer 40, the first barrier layer 50, the source 70, the drain 80, the gate 90', and the laminate 660 are referred to the second. For a description of the material of the second barrier layer 52, please refer to the related description in the third embodiment.

The semiconductor unit 6 of the sixth embodiment includes a laminate 660 composed of a first protective layer 661 and a first conductive type compound semiconductor layer 663. The first protective layer 661 may be an epitaxially grown tantalum nitride layer, whereby the effect of improving surface leakage current and protecting the epitaxial surface can be achieved. The first conductive type compound semiconductor layer 663 is, for example, p-type gallium nitride, which can reduce the two-dimensional electron gas concentration and further improve the on-resistance under the gate 90.

In the present application, the semiconductor element S may be an element of a three-terminal end in FIG. 1, such as a power element, and may also be an element at both ends, such as a Schottky diode element. When the semiconductor element S is a two-point element, it includes an anode pad, a cathode pad, and a plurality of terminal semiconductor units electrically connected to the anode pad and the cathode pad, respectively. Referring to FIGS. 7A and 7B, FIG. 7A is a partial top view of the semiconductor unit 7 of the seventh embodiment of the present invention. Fig. 7B is a cross-sectional view showing the semiconductor unit 7 of the seventh embodiment of the present invention. In this embodiment, the semiconductor unit 7 is a two-point element, such as a Schottky diode. The semiconductor unit 7 includes a substrate 10, a nucleation layer 20, a buffer layer 30, a channel layer 40, and a first barrier layer 50. Second barrier layer 52, laminate 760, anode A and cathode C.

The manner of fabricating the semiconductor unit 7 is similar to the manner of fabricating the semiconductor unit 3 first. First, the substrate 10 is provided, and then the nucleation layer 20, the buffer layer 30, the channel layer 40, the first barrier layer 50, and the first layer are sequentially formed on the substrate 10. The second barrier layer 52 is then formed over the second barrier layer 52, wherein the second barrier layer 52 serves as a stop layer in the subsequent etching process. The laminate 760 includes a first protective layer 761 (eg, an epitaxially grown tantalum nitride layer) and a first conductive type compound semiconductor layer 763, and the first conductive type compound semiconductor layer 763 and the first protective layer 761 are sequentially placed Above the second barrier layer 52, and after forming the stack 760, an etching step is performed. When etching is performed, the pattern is first defined by a yellow lithography process, and then the portion of the laminate 760 is etched away to expose the second barrier layer 52, and the etching depth is substantially stopped at the upper surface of the second barrier layer 52. The anode A and the cathode C are then formed on the exposed second barrier layer 52 with a spacing between the laminate 760 and the anode A, followed by appropriate material selection and/or thermal annealing and other processing steps to cause the anode A forms an ohmic contact with the cathode C and the second barrier layer 52, but the invention is not limited thereto. For the material, thickness range and function of the substrate 10, the nucleation layer 20, the buffer layer 30, the channel layer 40, the first barrier layer 50, the second barrier layer 52, and the laminate 760, please refer to the second embodiment and the third implementation. A description of the example.

Referring to FIGS. 8A and 8B, FIG. 8A is a partial top plan view of a semiconductor unit according to an eighth embodiment of the present invention. 8B is a cross-sectional view showing a semiconductor unit according to an eighth embodiment of the present invention. In this embodiment, the semiconductor unit 8 is a two-point element, such as a Schottky diode, and the semiconductor unit 8 includes a substrate 10, a nucleation layer 20, a buffer layer 30, a channel layer 40, and a first barrier layer 50. Second barrier layer 52, stack 860, anode A and cathode C.

The method of fabricating the semiconductor unit 8 is similar to the manner of fabricating the semiconductor unit 7 in the prior art. First, the substrate 10 is provided, and then the nucleation layer 20, the buffer layer 30, the channel layer 40, the first barrier layer 50, and the first layer are sequentially formed on the substrate 10. The second barrier layer 52 is then formed over the second barrier layer 52. The difference between the two is that the semiconductor unit 8 first forms the first protective layer 861 and then forms the first conductive type compound semiconductor layer 863, wherein the first protective layer 861 may be an epitaxially grown insitu silicon nitride. The first conductive type compound semiconductor layer 863 may be an n-type aluminum gallium nitride. After forming the stack 860, the pattern is defined by a yellow lithography process, followed by etching away portions of the stack 860 to expose portions of the second barrier layer 52, and then forming the anode A and the cathode C to the exposed second barrier layer 52. And a gap exists between the layer 860 and the anode A, and then the anode A and the cathode C and the second barrier layer 52 are in ohmic contact by a suitable material selection and/or a thermal annealing process. The invention is not limited to the above. In the present embodiment, the first protective layer 861 substantially covers the surface of the second barrier layer 52 that is not covered by the cathode C and the anode A. For the material, thickness range and function of the substrate 10, the nucleation layer 20, the buffer layer 30, the channel layer 40, the first barrier layer 50, the second barrier layer 52, and the laminate 760, please refer to the second embodiment and the third implementation. A description of the example.

The semiconductor units 7, 8 of the seventh embodiment and the eighth embodiment respectively include the stacks 766, 860 composed of the first protective layers 761, 861 and the first conductive type compound semiconductor layers 763, 863. The first protective layers 761, 861 may be epitaxially grown tantalum nitride layers, whereby the effect of improving surface leakage current and protecting the epitaxial surface can be achieved.

The above embodiments are merely illustrative of the principles of the invention and its advantages, and are not intended to limit the invention. Modifications and variations of the above-described embodiments of the present invention may be or are intended to be included in the present invention without departing from the spirit and scope of the invention.

A‧‧‧Anode

C‧‧‧ cathode

E‧‧‧ area

FF’‧‧‧ cut line

S‧‧‧Semiconductor components

1, 2, 3, 4, 5, 6, 7, 8‧‧‧ semiconductor units

10‧‧‧Substrate

20‧‧‧Nuclear layer

30‧‧‧buffer layer

40‧‧‧Channel layer

50‧‧‧First barrier layer

52‧‧‧second barrier layer

54‧‧‧ third barrier layer

260, 360, 460, 560, 660, 760, 860 ‧ ‧ stacks

261, 361, 461, 561, 661, 761, 861‧‧‧ first protective layer

263, 363, 463, 563, 663, 763, 863 ‧ ‧ first conductive compound semiconductor layer

70‧‧‧ source

80‧‧‧汲polar

90, 90’‧‧‧ gate

100‧‧‧ dielectric layer

The drawings are intended to facilitate an understanding of the invention and are part of the specification. The embodiments of the drawings are described in conjunction with the embodiments to explain the principles of the invention.

Fig. 1 is a top view of a semiconductor element according to a first embodiment of the present invention.

2A is a partial top plan view of a semiconductor unit in accordance with a second embodiment of the present invention.

2B is a schematic cross-sectional view showing a semiconductor unit according to a second embodiment of the present invention.

2C is another schematic cross-sectional view of the semiconductor unit of the second embodiment of the present invention.

2D is another schematic cross-sectional view of the semiconductor unit of the second embodiment of the present invention.

3A is a partial top plan view of a semiconductor unit according to a third embodiment of the present invention.

3B is a schematic cross-sectional view showing a semiconductor unit according to a third embodiment of the present invention.

4A is a partial top plan view showing a semiconductor unit according to a fourth embodiment of the present invention.

4B is a schematic cross-sectional view showing a semiconductor unit according to a fourth embodiment of the present invention.

Fig. 5A is a partial top plan view showing a semiconductor unit according to a fifth embodiment of the present invention.

Fig. 5B is a schematic cross-sectional view showing a semiconductor unit according to a fifth embodiment of the present invention.

Fig. 6A is a partial top plan view showing a semiconductor unit according to a sixth embodiment of the present invention.

6B is a cross-sectional view showing a semiconductor unit according to a sixth embodiment of the present invention.

Fig. 7A is a partial top plan view showing a semiconductor unit according to a seventh embodiment of the present invention.

Fig. 7B is a schematic cross-sectional view showing a semiconductor unit according to a seventh embodiment of the present invention.

Fig. 8A is a partial top plan view showing a semiconductor unit according to an eighth embodiment of the present invention.

8B is a cross-sectional view showing a semiconductor unit according to an eighth embodiment of the present invention.

no

Claims (9)

A semiconductor unit comprising: a substrate; a channel layer having a first energy gap and located above the substrate; a first barrier layer having a second energy gap greater than the first energy gap and located in the channel a layer above the first barrier layer, comprising a tantalum nitride layer, and a p-type semiconductor layer, wherein the tantalum nitride layer is between the first barrier layer and the p-type semiconductor layer a first electrode located above the first barrier layer; and a second electrode disposed above the first barrier layer and separated from the first electrode, further comprising a second barrier layer, The second barrier layer is located between the laminate and the first barrier layer, and the second barrier layer has an energy gap larger than the first barrier layer and the channel layer. The semiconductor unit of claim 1, wherein the laminate is interposed between the first electrode and the second electrode. The semiconductor unit of claim 1, further comprising a third electrode, the third electrode being located between the first electrode and the second electrode. The semiconductor unit of claim 3, wherein the p-type semiconductor layer is between the third electrode and the tantalum nitride layer. The semiconductor unit of claim 3, further comprising a dielectric layer between the third electrode and the laminate. The semiconductor unit of claim 1, wherein the second barrier layer is between the first electrode and the first barrier layer, and between the second electrode and the first barrier layer . The semiconductor unit of claim 1, wherein the second barrier layer is an aluminum nitride layer. The semiconductor unit of claim 1, further comprising a third barrier layer, wherein the third barrier layer is located between the laminate and the second barrier layer, or is located at the first electrode Between the second barrier layer and the second barrier layer. The semiconductor unit of claim 8, wherein the material of the third barrier layer is the same as the material or composition of the first barrier layer.