JP6824687B2 - Solid-state image sensor, image sensor, control method of solid-state image sensor, program, and storage medium - Google Patents

Description

The present invention relates to a solid-state image sensor that reduces random noise.

In recent years, there has been a demand for an image sensor capable of acquiring high-quality moving images by reducing the influence of random noise. Since the position and intensity at which random noise is generated constantly changes, it is difficult to reduce noise by correction, unlike fixed pattern noise. A method of reducing the influence of random noise by filtering is conceivable, but when filtering is performed, information on high-frequency components of the subject is also lost, and the image may be deteriorated.

By the way, conventionally, an image pickup device capable of outputting a digital signal by providing an AD converter for each row of pixels of the image pickup device has been known. Further, as one of the AD conversion methods, there is a reference signal comparison type AD conversion method. In the reference signal comparison type AD conversion method, a lamp signal whose potential changes with a certain inclination is used as a comparison signal, and a counting operation is started when the comparison between the analog signal and the reference signal is started. Then, when the magnitude relationship between the potentials of the analog signal and the reference signal is reversed, the counting operation is stopped or the count value at that time is latched, and the count value is treated as a digital signal.

In Patent Document 1, the same signal is repeated W times (W is a positive integer of 2 or more) to perform AD conversion by a reference signal comparison type AD conversion method, and addition processing is performed on the signal after AD conversion. The imaging device is disclosed. With such a configuration, it is considered that the signal is W times and the random noise generated in the circuit section is √W times, so that the random noise generated in the circuit section can be apparently reduced by √W times.

JP-A-2009-296423

However, in the image pickup apparatus of Patent Document 1, for example, after the first AD conversion is completed, the second and third AD conversions are repeated, so that the AD conversion time increases W times. Further, Patent Document 1 discloses a configuration in which the slope of the reference signal is steep when performing a plurality of AD conversions in order to shorten the AD conversion time. However, if the slope of the reference signal is steep, the AD conversion accuracy may deteriorate.

Therefore, the present invention provides a solid-state image sensor, an image pickup device, a control method for the solid-state image sensor, a program, and a storage medium capable of reducing random noise while suppressing an increase in AD conversion time and deterioration of AD conversion accuracy. With the goal.

The solid-state image sensor as one aspect of the present invention is provided for each pixel unit including a plurality of unit pixels arranged in a predetermined direction and a plurality of pixel sequences of the pixel unit and output from the plurality of unit pixels. A plurality of addition averaging circuits that perform addition averaging processing of the analog signals of the above and output a common signal relating to the plurality of unit pixels, and a plurality of addition averaging circuits provided for each pixel string of the pixel portion, and the common signal is provided for each of the plurality of unit pixels. It has a plurality of AD conversion units for converting into a plurality of digital signals corresponding to each, and a digital signal processing unit for performing addition processing or addition averaging processing of the plurality of digital signals.

The image pickup device as another aspect of the present invention includes the solid-state image pickup device and a control unit that controls the solid-state image pickup device.

The control method of the solid-state image sensor as another aspect of the present invention performs addition and averaging processing of a plurality of analog signals output from a plurality of unit pixels arranged in a predetermined direction, and is common to the plurality of unit pixels. A step of outputting a signal, a step of converting the common signal into a plurality of digital signals corresponding to each of the plurality of unit pixels by using a plurality of AD conversion units provided for each pixel row of the pixel unit, and a step of converting the common signal into a plurality of digital signals corresponding to each of the plurality of unit pixels. It has a step of performing addition processing or addition averaging processing of the plurality of digital signals.

A program as another aspect of the present invention causes a computer to execute the control method of the solid-state image sensor.

A storage medium as another aspect of the present invention stores the program.

Other objects and features of the present invention will be described in the following examples.

According to the present invention, there are provided a solid-state image sensor, an image pickup device, a control method for a solid-state image sensor, a program, and a storage medium capable of reducing random noise while suppressing an increase in AD conversion time and deterioration of AD conversion accuracy. be able to.

It is a block diagram of the imaging system in each embodiment. It is an equivalent circuit diagram of the image pickup device in Example 1. FIG. It is an equivalent circuit diagram of the unit pixel in Example 1. It is a timing chart of still image drive in Example 1. It is a timing chart of moving image drive in Example 1. It is an equivalent circuit diagram of the image pickup device in Example 2. It is a graph which shows the gain dependence of noise in Example 3. FIG. It is an equivalent circuit diagram of the image pickup device in Example 3. It is a timing chart of moving image drive in Example 3.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

[Imaging system]
First, an imaging system (an imaging device such as a digital camera) according to the present embodiment will be described with reference to FIG. FIG. 1 is a block diagram of the imaging system 100 according to the present embodiment.

The lens unit 101 (imaging optical system) forms (images) an optical image of the subject on the imaging element 105 (solid-state imaging element). The lens driving device 102 performs zoom control, focus control, aperture control, and the like on the lens unit 101. The shutter 103 is a mechanical shutter and is controlled by the shutter driving device 104. The image sensor 105 photoelectrically converts a subject image (optical image) formed through the lens unit 101 and outputs an image signal (image data).

The signal processing circuit 106 performs signal processing such as various corrections and data compression on the image signal output from the image sensor 105. The timing generation unit 107 (driving means) outputs various timing signals to the image sensor 105 and the signal processing circuit 106. The control unit 109 has a processor such as a CPU, performs various calculations, and controls each unit of the image pickup system 100 such as the image pickup element 105. The memory unit 108 (storage means) temporarily stores the image data output from the signal processing circuit 106. The I / F unit 110 is an interface for recording image data on the recording medium 111 and reading image data from the recording medium 111. The recording medium 111 is a detachable semiconductor memory (EEPROM) for recording and reading image data. The display unit 112 displays various information and captured images.

In the present embodiment, the image pickup system 100 includes an image pickup device main body including the image pickup element 105, and a lens device (interchangeable lens) including a lens unit 101 that can be attached to and detached from the image pickup device main body. However, the present embodiment is not limited to this, and can be applied to an imaging system (imaging apparatus) in which a lens apparatus and an imaging apparatus main body are integrally configured.

Next, the photographing operation of the imaging system 100 will be described. When the user turns on the main power supply (not shown), the power supply of the control system and the power supply of the imaging system circuit such as the signal processing circuit 106 are turned on. When the user presses the release button (not shown), the lens unit 101, the shutter 103, and the image sensor 105 are driven by output signals (control signals) from the lens drive device 102, the shutter drive device 104, and the timing generator 107, respectively. It is driven and performs a shooting operation. When the photographing operation is completed, the signal processing circuit 106 performs image processing on the image signal output from the image sensor 105, and the control unit 109 writes the image data after the image processing to the memory unit 108. Further, the control unit 109 records the image data stored in the memory unit 108 on the recording medium 111 via the I / F unit 110. In the present embodiment, the image data stored in the memory unit 108 may be directly input to an image processing device such as a computer via an external I / F unit (not shown) to process the image (image data). Good.

Hereinafter, the specific configuration of the image sensor 105 of the present embodiment will be described in detail in each embodiment.

[Equivalent circuit diagram of image sensor]
Next, the circuit of the image pickup device 105a (solid-state image pickup device) according to the first embodiment of the present invention will be described with reference to FIG. FIG. 2 is an equivalent circuit diagram of the image sensor 105a. The image sensor 105a of this embodiment is provided with a circuit (additional averaging circuit) for horizontally adding and averaging pixel signals of three pixels for each color in front of a plurality of AD conversion units arranged in each row. With such a configuration, horizontal addition averaging can be performed when the number of pixels is reduced according to the moving image format in moving image shooting.

The image pickup device 105a has a pixel unit 200 having a plurality of unit pixels 201 arranged in a matrix (column direction, that is, horizontal direction, and row direction, that is, vertical direction). That is, the pixel unit 200 constitutes a pixel array including a plurality of unit pixels 201 arranged in a predetermined direction (column direction), and a plurality of pixel sequences are arranged in a direction (row direction) perpendicular to the predetermined direction. .. Each unit pixel 201 is configured to include a microlens (ML), a photodiode (PD), a floating diffusion (FD), and the like. The detailed configuration of the unit pixel 201 will be described later. In FIG. 2, R, G, and B shown in the unit pixel 201 indicate pixels equipped with red (Red), green (Green), and blue (Blue) color filters, respectively. As shown in FIG. 2, the plurality of unit pixels 201 are arranged in a Bayer array.

The vertical scanning circuit 202 supplies drive signals (signals PRESS, PTX, PSEL) to each pixel line by line (in the vertical direction). The numbers 1, 2 and n (n is an integer of 3 or more) at the end of each drive signal indicate a line number, and for example, n indicates a drive signal to be supplied to each pixel on the nth line. ing. In this embodiment, if it is not necessary to specify the number of lines, the character indicating the number of lines at the end is omitted. The details of the drive signal will be described later together with the configuration of the unit pixel 201.

The output signal (pixel signal) of each pixel is transmitted to a subsequent circuit via a vertical signal line 203 arranged for each unit pixel row, and a constant current circuit 204 is connected to each vertical signal line 203. There is. The vertical signal line 203 is connected to the addition selector switches 205 and 206. The addition changeover switches 205 and 206 are driven by the signal PHADD. An addition averaging circuit 207 is connected to the other end of the addition changeover switch 206. A column amplifier 208 (amplifier) arranged corresponding to the pixel string to be read is connected to the other end of the addition changeover switch 205. The column amplifier 208 is an amplifier that amplifies an output signal (pixel signal) from a pixel (that is, amplifies a common signal output from the addition / averaging circuit 207). From the viewpoint of noise, the column amplifier 208 is preferably a gain amplifier that applies gain. However, in this embodiment, it is not essential to provide the column amplifier 208.

As described above, the addition averaging circuit 207 is a circuit that performs horizontal addition averaging of 3 pixels for each color, and is provided for each unit addition averaging sequence (3 pixels of the same color). In this embodiment, the addition averaging circuit 207 has a plurality of analog signals output from a plurality of unit pixels 201 (three pixels of the same color) arranged in a predetermined direction (column direction, horizontal direction). It functions as a signal generation unit that generates a common signal for the unit pixel 201. Preferably, the addition averaging circuit 207 performs addition averaging processing of a plurality of analog signals (pixel signals output from three pixels of the same color) to output a common signal.

The addition changeover switch 205 is composed of a pMOS switch, and the addition changeover switch 206 is composed of an nMOS switch. Therefore, when the signal PHADD is “L”, the addition changeover switch 205 is on and the addition changeover switch 206 is off. As a result, the pixel signal is input to the column amplifier 208 via the vertical signal line 203. On the other hand, when the signal PHADD is "H", the addition changeover switch 205 is off and the addition changeover switch 206 is on. As a result, the signal (pixel signal) of the vertical signal line 203 is input to the averaging circuit 207. The output signal from the averaging circuit 207 is input to the column amplifier 208.

As described above, in the present embodiment, the addition changeover switches 205 and 206 are changeover switches that can be set to the first mode or the second mode. In the first mode (when the signal PHADD is "H"), the averaging circuit 207 generates a common signal, and the digital averaging circuit 215 performs an averaging process or an averaging process. On the other hand, in the second mode (when the signal PHADD is “L”), the addition averaging circuit 207 does not generate a common signal, and the digital addition circuit 215 does not perform addition processing or addition averaging processing. Preferably, the first mode is a mode in which pixel signals are read from a plurality of unit pixels selected to be thinned out at a predetermined cycle in a predetermined direction (column direction) among all the unit pixels 201 of the pixel unit 200. is there. On the other hand, the second mode is a mode in which a pixel signal is read from all the unit pixels 201 of the pixel unit 200. Alternatively, both the first mode and the second mode output pixel signals from a plurality of unit pixels 201 selected to be thinned out in a predetermined direction at a predetermined cycle among all the unit pixels 201 of the pixel unit 200. It may be a read mode.

Here, assuming that the column number located at the center of the columns to be horizontally added is m, the m-th column and the m-2nd column, and the m-th column and the m + 2nd column are placed after the m-th column amplifier 208. Column connection switches 209 are arranged to connect the two to each other. That is, the column connection switch 209 (connection switch) transmits the common signal output from the averaging circuit 207 (in this embodiment, the common signal amplified by the column amplifier 208) to the plurality of AD conversion units. In this embodiment, the column connection switch 209 is composed of an nMOS switch, and is turned on when the signal PHADD is “H”. When the signal PHADD becomes “H”, the output signal of the column amplifier 208 in the m-th row is written to the column memory 210 in the m-2nd row, the m-th row, and the m + 2nd row via the row connection switch 209, respectively. .. In this embodiment, an example is shown in which the addition averaging of 3 pixels is performed in the horizontal direction and the added averaging signal is written to the column memory 210 of the 3rd row of the m-2nd row, the mth row, and the m + 2nd row. However, it is not limited to this. For example, it is configured to perform the addition averaging of 2 pixels in the horizontal direction and write the addition averaging signal to the column memory 210 in 2 columns, or the addition averaging of 3 pixels in the horizontal direction and the addition averaging signal. May be configured to write to the column memory 210 of the second column of the m-2nd column and the mth column.

A plurality of comparators 211 are provided corresponding to each row. A signal (pixel signal, that is, a common signal) held in the column memory 210 and a lamp signal VRAMP (reference signal) supplied from the DAC 212 (reference signal generator) are input to each comparator 211 for comparison. Instrument 211 compares these two input signals. Further, the comparator 211 outputs an inverted signal at a timing when the magnitude relation between the two input signals is reversed.

The counter 213 starts counting at the timing when the comparator 211 starts comparing the signal held in the column memory 210 with the lamp signal VRAMP. The count value of the counter 213 is input to the latch circuit 214. The latch circuit 214 holds a count value (a count value corresponding to the timing at which the inverting signal is input) indicated at the timing when the inverting signal is input from the comparator 211. In this embodiment, the comparator 211 and the latch circuit 214 form a plurality of AD conversion units (AD conversion circuits) provided corresponding to each of the plurality of unit pixels 201. The plurality of AD conversion units output a common signal output from the addition averaging circuit 207 (in this embodiment, a common signal output from the addition averaging circuit 207 and amplified by the column amplifier 208) to a plurality of unit pixels 201 (of the same color). It is converted into a plurality of digital signals corresponding to each of the three pixels). As described above, in this embodiment, the plurality of AD conversion units convert the common signal into a plurality of digital signals in parallel using the reference signal.

The digital addition circuit 215 (digital signal processing unit) adds a plurality of digital signals. The digital addition circuit 215 is controlled by the signal PHADD, and when the signal PHADD is "H", among the input digital signals, for example, a signal in the addition average unit such as the output signal in the m-2, m, m + 2nd column. Is added and output. On the other hand, when the signal PHADD is “L”, the digital addition circuit 215 outputs the input digital signal without adding the signals. In this embodiment, the digital addition circuit 215 may perform signal addition averaging processing instead of signal addition processing. In this way, the digital addition circuit 215 performs addition processing or addition averaging processing of a plurality of digital signals.

Here, thermal noise is generated during amplification by the column amplifier 208 (amplifier), and quantization noise is generated in the AD conversion circuit (AD conversion unit) composed of the comparator 211 and the latch circuit 214. Since each of these affects the image quality as random noise, it is necessary to reduce the random noise generated in a column circuit such as an amplifier or an AD conversion circuit.

[Equivalent circuit diagram of unit pixel]
Next, the circuit of the unit pixel 201 will be described with reference to FIG. The unit pixel 201 includes one microlens ML (not shown), one photodiode (PD), one floating diffusion (FD), and four transistors.

PD301 is a photoelectric conversion element that photoelectrically converts an optical image. The PD 301 is connected via the transfer switch 302 to the gate of the transistor 304 forming the source follower amplifier together with the constant current source connected to the vertical signal line 203. The transfer switch 302 is driven by the signal PTX. The FD 303 plays a role of converting the electric charge stored in the PD 301 into a voltage. Further, the FD 303 is connected to the potential VDD via a transistor 306 driven by the signal PRESS. Therefore, when the signal PRESS becomes “H”, the FD 303 is reset to the potential VDD. The transistor 305 is driven by the signal PSEL and acts as a switch that transmits an output signal from the transistor 304 to the vertical signal line 203.

[Still image drive method]
Next, a driving method (control method of the solid-state image sensor) when reading out the pixel signals of each row without reducing the number of pixels, that is, without horizontally adding the pixel signals of each row will be described. This driving method is used, for example, when shooting a still image having a higher resolution and a lower frame rate.

FIG. 4 is a timing chart driven by a still image, and shows a chart after all pixels are collectively reset and accumulated. In FIG. 4, in order from the top, a timing chart when reading each pixel signal, a graph showing the signal VC held in the column memory 210 on the time axis, and the lamp signal VRAMP (potential) output from the DAC 212, and It is a graph of the count value of the counter 213. As shown in FIG. 4, in the driving method of reading out the pixel signals of each column without horizontal addition, the signal PHADD is always set to “L”.

First, all the pixels are reset at once, and after accumulating for a predetermined period, the signal PSEL1 corresponding to the first line is set to "H" at time t401, and the signal of the first line is output. .. Further, by setting the signal PRESS1 to "H" in the period of time t401 to t402, the FD 303 is reset by the potential VDD. Since the signal PHADD is "L", the signal reset by the potential VDD (reset signal) is amplified by the column amplifier 208 arranged corresponding to the pixel to be read without going through the addition averaging circuit 207, and then is amplified. Written to column memory 210. At time t402 after a predetermined time has elapsed from the time when the reset signal is written to the column memory 210 until it stabilizes, the DAC 212 starts the output of the lamp signal VRAMP and starts the AD conversion of the reset signal.

The counter 213 counts during the time t402 to t403, which is the AD conversion period of the reset signal. The latch circuit 214 holds a count value of the time when the signal VC of the column memory 210 and the lamp signal VRAMP match each other and the inverting signal is output from the comparator 211. At the time t403 when the AD conversion period ends, the signal PRESS1 becomes “L”, and the count value held by the latch circuit 214 is sent to the digital addition circuit 215. At this time, since the signal PHADD is “L”, the signal VC (non-addition) of each column is output without adding the signal VC (reset signal) of each column. The counter 213 is reset to the initial value at the time t403 when the AD conversion ends. The latch circuit 214 is reset to the initial value after the reset signal of each column is output.

Subsequently, the optical signal is read out. At time t404, the signal PTX1 becomes “H”, and in addition to the reset signal, the accumulated charge of PD301 is transferred to FD303. Similar to the reset signal, the signal (optical signal) corresponding to the amount of light received by the PD 301 is amplified by the row amplifier 208 arranged in the row corresponding to the pixel to be read, and then written to the row memory 210. At time t405, which is required to stabilize after the optical signal is written to the column memory 210, the DAC 212 outputs the lamp signal VRAMP and starts AD conversion of the optical signal. The counter 213 counts during the time t405 to t406, which is the AD conversion period of the optical signal. The latch circuit 214 holds a count value of the time when the signal VC of the column memory 210 and the lamp signal VRAMP match each other and the inverting signal is output from the comparator 211. At the time t406 when the AD conversion period ends, the signal PRESS1 becomes “L”, and the count value held by the latch circuit 214 is sent to the digital adder circuit 215 in the same manner as the reset signal. At this time, since the signal PHADD is “L”, the signal VC of each column is output without adding the signal VC of each column (without addition). The counter 213 is reset to the initial value at the time t406 when the AD conversion ends. The latch circuit 214 is reset to the initial value after the optical signals of each row are output.

The above operation is sequentially performed for each line from the first line to the nth line, and the read operation is completed. The reset signal and the optical signal output from the image pickup device 105a are each subjected to arithmetic processing by the signal processing circuit 106 in the subsequent stage to obtain an optical signal from which reset noise has been removed.

[Video drive method]
Next, as an example, a driving method (control method of the solid-state image sensor) when the pixel signals of the same color signal are read out by performing horizontal addition averaging of three rows to reduce the number of pixels will be described. This driving method is used, for example, when shooting a moving image in which the number of pixels may be reduced instead of requiring a high frame rate. As described above, the image sensor 105a of the present embodiment is provided with a circuit (additional averaging circuit 207) for performing addition averaging of three rows of the same color in the preceding stage of the AD conversion circuit (comparator 211 and latch circuit 214). There is.

When the conventional technology is driven, two rows of AD conversion circuits become surplus. On the other hand, by driving the present embodiment, the surplus AD conversion circuit can be effectively utilized. By driving this embodiment, the random noise generated in the AD conversion circuit can be reduced.

FIG. 5 is a moving image drive timing chart, and shows a timing chart at the time of signal reading of the slit rolling drive. Similar to FIG. 4, in FIG. 5, in order from the top, a timing chart for reading each pixel signal, a graph showing the signal VC and the lamp signal VRAMP (potential) on the time axis, and the count value of the counter 213. It is a graph. Further, the characters m-2, m, and m + 2 written at the end of the signal VC indicate the number of columns when the number of columns located at the center of the horizontally added columns is m as described above. .. As shown in FIG. 5, in the driving method in which the pixel signals in each column are horizontally added and averaged and read out, the signal PHADD is always set to "H".

First, all the pixels are reset at once, and after accumulating for a predetermined period, the signal PSEL1 corresponding to the first line is set to "H" at time t501, and the signal of the first line is output. .. Further, by setting the signal PRESS1 to "H" in the period of time t501 to t502, the FD 303 is reset by the potential VDD. Since the signal PHADD is "H", the signal reset by the potential VDD (reset signal) is transmitted to the averaging circuit 207 corresponding to the column to be read.

The addition averaging circuit 207 performs addition averaging on the reset signals in the m-2, m, and m + 2nd columns. The signal added and averaged by the addition average circuit 207 is amplified by the column amplifier 208 in the m-th column. At this time, since the row amplifier 208 in the m-2 and m + 2nd rows is not used, the power consumption can be reduced by saving the power. Similarly, since the signal PHADD is "H", the output signal from the column amplifier 208 in the m-th row is written to the column memory 210 in the m-2, m, m + 2nd row via the column connection switch 209. .. At time t502 after a predetermined time elapses from the time when the summed and averaged reset signal is written to the column memory 210 until it stabilizes, the DAC212 outputs the lamp signal VRAMP, and the AD conversion circuit in the m-2, m, and m + 2nd columns. Starts AD conversion of the reset signal.

The counter 213 counts during the time t502 to t503, which is the AD conversion period of the reset signal. The latch circuit 214 holds a count value of the time when the signal VC of the column memory 210 and the lamp signal VRAMP match each other and the inverting signal is output from the comparator 211. At the time t503 when the AD conversion period ends, the signal PRESS1 becomes “L”, and the count value held by the latch circuit 214 is sent to the digital adder circuit 215. At this time, since the signal PHADD is “H”, the reset signals (signals VC _{m-2, m, m + 2} ) in the second column of _{m-2, m, m + 2} are added and output. The counter 213 is reset to the initial value at the time t503 when the AD conversion ends. The latch circuit 214 is reset to the initial value after the reset signal of each column is output.

Subsequently, the optical signal is read out. At time t504, the signal PTX1 becomes “H”, and in addition to the reset signal, the accumulated charge of PD301 is transferred to FD303. Since the signal PTADD is "H", the optical signal is transmitted to the averaging circuit 207 corresponding to the column to be read, similar to the reset signal. The signal obtained by averaging the optical signals in the m-2, m, and m + 2nd rows by the averaging circuit 207 is amplified by the row amplifier 208 in the mth row. Since the signal PHADD is "H", the output signal from the row amplifier 208 in the m-th row is written to the row memory 210 in the m-2, m, m + 2nd row via the row connection switch 209. At time t505 after a predetermined time elapses after the summed and averaged optical signal is written to the column memory 210 and after a predetermined time elapses, the DAC 212 outputs the lamp signal VRAMP and performs AD conversion in the m-2, m, and m + 2nd columns. The circuit initiates AD conversion of the optical signal.

The counter 213 counts during the time t505 to t506, which is the AD conversion period of the optical signal. The latch circuit 214 holds a count value of the time when the signal VC of the column memory 210 and the lamp signal VRAMP match each other and the inverting signal is output from the comparator 211. At the time t506 at which the AD conversion period ends, the signal PSEL1 becomes “L”, and the count value held by the latch circuit 214 is sent to the digital adder circuit 215 in the same manner as the reset signal. At this time, since the signal PHADD is “H”, the optical signals in the m-2, m, m + 2nd row (signals VC _{m-2, m, m + 2} ) are added and output. The counter 213 is reset to the initial value at the time t506 when the AD conversion ends. The latch circuit 214 is reset to the initial value after the optical signals of each row are output.

The above operation is sequentially performed for each line from the first line to the nth line, and the read operation is completed. The reset signal and the optical signal output from the image pickup device 105a are each subjected to arithmetic processing by the signal processing circuit 106 in the subsequent stage to obtain an optical signal from which reset noise has been removed. However, each of the reset signal and the optical signal (count value with respect to) includes different random noises generated in the AD conversion circuit of the m-2, m, and m + 2nd columns. When a signal containing such random noise is added by the digital adder circuit 215, the signal is tripled and the random noise generated during AD conversion is √3 times, and the S / N ratio is improved.

Further, in this embodiment, since the surplus column circuit is utilized when driving the low pixel count of a moving image or the like, the driving can be performed without sacrificing the AD conversion period and the AD conversion accuracy. Further, in this embodiment, since the same signal is read out by using a plurality of column circuits and the signals are added, the signal is obtained by integrating the fixed noise generated due to the variation of the column circuits and the like. In order to remove such fixed noise, for example, an OB (optical black) pixel in which the upper part of the PD301 is shielded with aluminum or the like is provided on a part of the image sensor 105a, and the signal of the corresponding OB pixel sequence is subtracted from the aperture pixel. be able to. In this embodiment, a mechanism or function for correcting the fixed noise component of the column circuit by driving to remove the variation in the column circuit may be separately provided.

Next, the circuit of the image pickup device 105b (solid-state image pickup device) according to the second embodiment of the present invention will be described with reference to FIG. FIG. 6 is an equivalent circuit diagram of the image sensor 105b. With respect to FIG. 6, only the portion different from FIG. 2 will be described, and the description of the portion common to FIG. 2 will be omitted.

In the image sensor 105a of the first embodiment, the pixel signals are added and averaged in the horizontal direction, and the signals amplified by the single row amplifier 208 are written to the adjacent surplus (plural) row memories 210. Then, the random noise generated at the time of AD conversion is reduced by adding the signals after performing AD conversion with a plurality of different AD conversion circuits. At this time, focusing on the column amplifier 208, it is possible to reduce the power consumption by saving the power of the unused column amplifier 208, but it is not possible to reduce the random noise generated in the column amplifier 208.

The image sensor 105b of this embodiment utilizes the surplus column amplifier 208 to reduce the random noise generated by the column amplifier 208 in addition to the random noise that can be reduced by the image sensor 105a of the first embodiment. can do.

The image sensor 105a of the first embodiment has one addition averaging circuit 207 (for each of a plurality of pixel strings) in the horizontal addition averaging unit, whereas the image sensor 105b of the present embodiment has one addition for each pixel sequence. It has an average circuit 217. In the image sensor 105b of this embodiment, a pixel signal of the averaging unit is input to each of the plurality of averaging circuits 217, and each averaging circuit 217 outputs the averaging signal. That is, the signal generation unit of this embodiment has a plurality of addition averaging circuits 217 corresponding to each of the plurality of unit pixels 201. In this embodiment, one addition averaging circuit 217 is provided for each pixel string, but the present invention is not limited to this. For example, as in the first embodiment, one addition averaging circuit 217 is provided in the horizontal addition averaging unit (for each of a plurality of pixel strings), and the output signal from the addition averaging circuit 217 is used as a surplus column amplifier 208 in the same color sequence. It may be configured to transmit an averaging signal by providing a switch capable of inputting.

As shown in FIG. 6, the image pickup device 105b of this embodiment has a plurality of column amplifiers 208 (amplifiers) that amplify a common signal output from the plurality of averaging circuits 217. The plurality of AD converters (comparator 211 and latch circuit 214) convert the common signal amplified by the plurality of column amplifiers 208 into a plurality of digital signals. The image sensor 105b of this embodiment does not have the column connection switch 209 provided in the image sensor 105a of Example 1. Since the other configuration of the image sensor 105b is the same as that of the image sensor 105a described in the first embodiment with reference to FIG. 2, the description thereof will be omitted. Further, since the driving method of the image pickup device 105b is the same as the driving method described in the first embodiment with reference to FIGS. 4 and 5, the description thereof will be omitted.

In this embodiment, by performing the same driving as in the first embodiment according to the above configuration, the signals added and averaged by the addition and averaging circuit 217 are input to a plurality of column amplifiers 208 different from each other and amplified. Then, each signal amplified by the plurality of column amplifiers 208 is AD-converted by the AD conversion circuit corresponding to each of the plurality of column amplifiers 208, and the digital signal is added and output by the digital addition circuit 215. At this time, the plurality of signals added by the digital adder circuit 215 each include random noise generated by the corresponding column amplifier 208 and the AD conversion circuit (comparator 211 and latch circuit 214). By adding these signals with the digital adder circuit 215, it is possible to reduce not only the random noise generated by the AD conversion circuit but also the random noise generated by the column amplifier 208. Further, in the present embodiment, as in the first embodiment, the drive can be performed without sacrificing the AD conversion period and the AD conversion accuracy.

Next, the image pickup device 105c (solid-state image pickup device) according to the third embodiment of the present invention will be described. In the driving methods of the first and second embodiments, random noise generated in the column circuit is generated by utilizing the column circuits (comparator 211, latch circuit 214, and column amplifier 208) that are surplus during horizontal addition average driving. To reduce. Such a driving method can reduce the random noise generated in the column circuit without affecting the AD conversion period and the AD conversion accuracy. However, on the other hand, since the surplus column circuit is driven, the power consumption increases.

Therefore, on the premise that the column amplifier 208 is a gain amplifier, the image sensor 105c is subjected to the present implementation for reducing random noise in a low gain region where a sufficient effect of reducing random noise can be obtained when total noise is considered. The driving method of the example (the proposed driving) is used. On the other hand, the image sensor 105c uses a drive method (conventional drive) for power-saving the surplus column circuit in a high gain region where the random noise reduction effect of the drive method of this embodiment cannot be sufficiently obtained. By combining such driving, it is possible to perform appropriate driving according to the gain from the viewpoint of both random noise and power consumption.

Here, the proposed drive and the conventional drive will be described with reference to FIG. 7. FIG. 7 is a graph showing the gain dependence of noise. In FIG. 7, the relationship between the pixel noise generated in the pixel section, the column noise generated in the column circuit, and the total noise obtained by combining the two with respect to the gain given to the column amplifier 208 is described in the proposed drive and the conventional drive. The two cases of are shown. In FIG. 7, it is assumed that the noise value generated in the pixel portion depending on the gain is 1 (when the gain is “x1”) and the noise value generated in the column circuit independent of the gain is 4.

In both the proposed drive and the conventional drive, if the gains are the same, the pixel noises are the same values. On the other hand, the row noise in the proposed drive is 1 / √3 times that in the conventional drive. As each noise is assumed to be generated in accordance with a normal distribution, as represented by the following formula (1), the total noise N _T is taking the square root sum of squares of pixel noise N _P column noise N _C Obtained as a value. FIG. 7 uses the value calculated by the equation (1).

Here, referring to the total noise in each of the proposed drive and the conventional drive shown in FIG. 7, noise reduction of 7% or more can be expected for the gains “× 1” to “× 8” of the column amplifier 208. On the other hand, when the gain is “× 16” or more, the noise reduction is limited to 2% or less. Therefore, in the present embodiment, the proposed drive is performed when the gain of the column amplifier 208 is "x1" to "x8", and the conventional drive is performed when the gain is "x16" to "x64". However, the gain (threshold gain) for switching between the proposed drive and the conventional drive can be arbitrarily determined according to the performance of the image sensor 105c.

Next, the circuit of the image pickup device 105c will be described with reference to FIG. FIG. 8 is an equivalent circuit diagram of the image sensor 105c. With respect to FIG. 8, only the portion different from FIG. 6 will be described, and the description of the portion common to FIG. 6 will be omitted.

As shown in FIG. 8, the image pickup device 105c has an AND circuit 801 in addition to the configuration of the image pickup device 105b shown in FIG. The signal PHADD and the signal PCOL are input to the AND circuit 801. That is, the digital addition circuit 215 adds the signal of the addition average unit input when both the signal PHADD and the signal PCOL are “H”. Then, when either one or both of the signal PHADD and the signal PCOL is "L", the digital adder circuit 215 outputs a signal without addition. Further, although the signal line is omitted, the signal PCOL is also input to the column amplifier, comparator, and latch circuit of the column which becomes a surplus at the time of horizontal addition averaging. When the signal PCOL is "L", each circuit saves power.

FIG. 9 is a moving image drive timing chart when the gain of the column amplifier 208 is “× 1” to “× 8” and when the gain of the column amplifier 208 is “× 16” to “× 64}. In the case of "x1" to "x8", the same as in the second embodiment except that the signal PCOL is always input as "H". When the gain of the column amplifier 208 is “× 16” to “× 64”, the signal PCOL is always input as “L”, and the surplus column amplifier 208, the comparator 211, and the latch circuit 214 are power-saved. Will be done. That is, the signal added and averaged by the addition average circuit 207 is amplified by one column circuit for each addition average unit, AD-converted, and output. With such a configuration, random noise can be reduced in the low gain region of "x1" to "x8", and power consumption can be suppressed in the high gain region of "x16" to "x64". It will be possible.

As described above, in the present embodiment, in the AND circuit 801 (determination unit), the digital addition circuit 215 performs addition processing or addition averaging processing according to at least one amplification factor (gain) of the plurality of column amplifiers 208 (amplifiers). Decide whether to do it or not. Preferably, the AND circuit 801 determines that the digital adder circuit 215 performs the addition process or the addition average process when the amplification factor is smaller than the predetermined amplification factor (in the low gain region). On the other hand, the AND circuit 801 determines that the digital adder circuit 215 does not perform the addition process or the addition averaging process when the amplification factor is larger than the predetermined amplification factor (in the high gain region).

In this embodiment, an example in which the driving method of the second embodiment is used in the low gain region and the conventional driving method is used in the high gain region has been described, but the present invention is not limited thereto. For example, the driving method of the first embodiment may be used in the low gain region, and the conventional driving method may be used in the high gain region.

(Other Examples)
The present invention supplies a program that realizes one or more functions of the above-described embodiment to a system or device via a network or storage medium, and one or more processors in the computer of the system or device reads and executes the program. It can also be realized by the processing to be performed. It can also be realized by a circuit (for example, ASIC) that realizes one or more functions.

According to each embodiment, a solid-state image sensor, an image pickup device, a control method for the solid-state image sensor, a program, and a storage medium capable of reducing random noise while suppressing an increase in AD conversion time and deterioration of AD conversion accuracy are provided. can do.

Although preferable examples of the present invention have been described above, the present invention is not limited to these examples, and various modifications and modifications can be made within the scope of the gist thereof.

105 image sensor (solid-state image sensor)
200 Pixel section 201 Unit pixel 207, 217 Addition averaging circuit (Signal generator)
211 Comparator (AD converter)
214 Latch circuit (AD converter)
215 Digital adder circuit (digital signal processing unit)

Claims (13)

A pixel portion containing a plurality of unit pixels arranged in a predetermined direction,
Provided for each pixel column of the pixel unit, by performing averaging processing of a plurality of analog signals output from said plurality of unit pixels, a plurality of averaging circuit for outputting a common signal regarding the unit pixels of the plurality of,
A plurality of AD conversion units provided for each pixel row of the pixel unit and converting the common signal into a plurality of digital signals corresponding to each of the plurality of unit pixels.
A solid-state image pickup device comprising a digital signal processing unit that performs addition processing or addition averaging processing of the plurality of digital signals. Further having a plurality of amplifiers for amplifying the common signal output from the plurality of averaging circuits.
The solid-state imaging device according to claim 1 , wherein the plurality of AD conversion units convert the common signal amplified by the plurality of amplifiers into the plurality of digital signals. 2. The second aspect of the present invention is characterized in that the digital signal processing unit further includes a determination unit that determines whether or not to perform the addition processing or the addition averaging processing according to the amplification factor of at least one of the plurality of amplifiers. The solid-state imaging device described. The decision unit
When the amplification factor is smaller than a predetermined amplification factor, it is determined that the digital signal processing unit performs the addition processing or the addition averaging processing.
The solid-state image sensor according to claim 3 , wherein when the amplification factor is larger than the predetermined amplification factor, the digital signal processing unit determines that the addition processing or the addition averaging processing is not performed. It also has a changeover switch that can be set to the first mode or the second mode.
In the first mode, the plurality of addition averaging circuits generate the common signal, and the digital signal processing unit performs the addition processing or the addition averaging process.
The first to fourth aspects of claim 1 to 4 , wherein in the second mode, the plurality of addition averaging circuits do not generate the common signal, and the digital signal processing unit does not perform the addition processing or the addition averaging process. The solid-state image sensor according to any one item. The first mode is a mode for reading a pixel signal from the plurality of unit pixels selected to be thinned out at a predetermined cycle in the predetermined direction among all the unit pixels of the pixel portion.
The solid-state image sensor according to claim 5 , wherein the second mode is a mode for reading a pixel signal from all the unit pixels of the pixel unit. Further, it has a reference signal generation unit that generates a reference signal that is commonly supplied to the plurality of AD conversion units.
The solid-state imaging device according to any one of claims 1 to 6 , wherein the plurality of AD conversion units convert the common signal into the plurality of digital signals in parallel using the reference signal. Each of the plurality of AD conversion units
A comparator that compares the reference signal with the common signal,
The solid-state imaging device according to claim 7 , further comprising a latch circuit that holds a count value corresponding to a timing at which a predetermined signal (inverted signal) is input from the comparator. The pixel column solid-state imaging device according to any one of claims 1 to 8, wherein the early days including the plurality of unit pixels arranged in the predetermined direction perpendicular to the direction. The solid-state image sensor according to any one of claims 1 to 9 ,
An image pickup apparatus comprising: a control unit for controlling the solid-state image pickup device. A step of performing addition averaging processing of a plurality of analog signals output from a plurality of unit pixels arranged in a predetermined direction and outputting a common signal related to the plurality of unit pixels.
A step of converting the common signal into a plurality of digital signals corresponding to each of the plurality of unit pixels by using a plurality of AD conversion units provided for each pixel sequence of the pixel unit.
A method for controlling a solid-state image sensor, which comprises a step of performing addition processing or addition averaging processing of a plurality of digital signals. A step of performing addition averaging processing of a plurality of analog signals output from a plurality of unit pixels arranged in a predetermined direction and outputting a common signal related to the plurality of unit pixels.
A step of converting the common signal into a plurality of digital signals corresponding to each of the plurality of unit pixels by using a plurality of AD conversion units provided for each pixel sequence of the pixel unit.
A program characterized by having a computer execute a step of performing addition processing or addition averaging processing of a plurality of digital signals. A computer-readable storage medium that stores the program according to claim 12 .