JP6124697B2 - Image sensor - Google Patents

Description

  The present invention relates to a pixel signal reading technique in an image sensor.

  Conventionally, a CMOS sensor in which a photodiode and a MOS transistor are integrated on a single chip is used as a solid-state image sensor as a solid-state image sensor that converts incident imaging light of an object into an electrical signal. Compared with a CCD, a CMOS sensor has advantages such as low power consumption, low driving power, and high speed. In recent years, proposals have been made to increase the readout speed of pixel signals using an analog / digital converter (ADC) provided for each column using this CMOS sensor.

  For example, an image sensor having a structure in which two or more ADCs are provided for one pixel column of a pixel portion has been proposed (see Patent Document 1). Whereas a conventional CMOS sensor reads out a pixel signal of one pixel column with one ADC, reading speed is improved by reading out with a plurality of ADCs.

  As another method, there is a successive approximation type image sensor as an example in which high-speed ADCs are stacked (see Patent Document 2). The successive approximation type has a voltage comparator, a digital memory, and a reference voltage generator using a digital / analog converter in each column. A signal from the pixel is applied to one end of the voltage comparator, and a voltage from the reference voltage generator is applied to the other end. The reference voltage generator sequentially changes the value based on the comparison result of the comparator.

JP 2005-347932 A US Pat. No. 5,880,691

  However, it has been recognized that the conventional method has a problem of increasing the circuit scale of the ADC provided for each column. Even with the configurations described in Patent Document 1 and Patent Document 2, it is possible to increase the readout speed of the pixel signal, but the circuit of the ADC section is larger than the conventional CMOS sensor, and the chip size is very large. There is a problem of becoming larger.

  On the other hand, when considered as a camera, in many situations where it is required to increase the readout speed of pixel signals, video signal acquisition and photometry are not performed when signal readout is performed on all pixels in an image sensor that is frequently used in still image photography. This is a case where pixel addition reading or thinning-out reading is performed for a distance measuring operation or the like.

  The present invention has been made in view of the above-described problems, and an object of the present invention is to provide an imaging device that can increase the readout speed of a pixel signal while suppressing an increase in the circuit scale of an ADC.

In order to solve the above-described problems and achieve the object, an imaging element according to the present invention includes a plurality of pixels in the same row as a pixel portion in which a plurality of pixels each including a photoelectric conversion portion are arranged in a matrix. And a plurality of ADs , each of which is provided for each pixel column of the pixel unit and converts the mixed pixel signal mixed by the mixing unit into a digital signal . It has a converter, and the distribution means which distributes the mixed pixel signal of each line of the said pixel part to a different AD converter among these AD converters, It is characterized by the above-mentioned.
A pixel unit in which a plurality of pixels each including a photoelectric conversion unit are arranged in a matrix; a mixing unit that mixes pixel signals output from a plurality of pixels in different columns of the same row; and A plurality of AD converters that are provided one for each pixel column and convert the mixed pixel signal mixed by the mixing unit into a digital signal, and the same mixed pixel signal in each row of the pixel unit Distribution means for distributing to different AD converters among the AD converters.

  ADVANTAGE OF THE INVENTION According to this invention, it becomes possible to provide the image pick-up element which can speed up the reading speed of the pixel signal which added several pixel output, suppressing the increase in the circuit scale of ADC.

1 is a circuit diagram illustrating a solid-state imaging element according to a first embodiment of the present invention. FIG. 6 is a timing chart for driving pixels. The block diagram of the AD converter of 1st Embodiment. The timing chart of the drive of AD converter. 5 is a timing chart of pixel signal readout according to the first embodiment. 4 is a timing chart of all-pixel readout driving according to the first embodiment. Explanatory drawing of operation | movement of 1st Embodiment. 2 is a timing chart of 1/2 thinning driving according to the first embodiment. Explanatory drawing of an addition buffer. The timing chart of the operation of the addition buffer. Explanatory drawing of operation | movement of 1st Embodiment. The circuit diagram showing the solid-state image sensor concerning the 2nd Embodiment of this invention. Explanatory drawing of operation | movement of 2nd Embodiment. The block diagram of the AD converter of 2nd Embodiment. 10 is a timing chart of pixel signal readout according to the second embodiment. The timing chart of 1/2 thinning drive of a 2nd embodiment. Explanatory drawing of operation | movement of 2nd Embodiment. The circuit diagram showing the solid-state image sensor concerning the 3rd Embodiment of this invention. FIG. 20 is a circuit diagram illustrating an example of a configuration of a pixel portion in FIG. 19. The figure which shows the switching state for every mode. The timing diagram which shows the drive method of a solid-state imaging device. The circuit diagram showing the solid-state image sensor concerning the 4th Embodiment of this invention. The timing diagram which shows the drive method of a solid-state imaging device. The circuit diagram showing the solid-state image sensor concerning the 5th Embodiment of this invention. The circuit diagram showing the solid-state image sensor concerning the 6th Embodiment of this invention. The figure which shows the switching state for every mode. The figure which shows the imaging device which concerns on the 7th Embodiment of this invention. The figure which shows the Bayer arrangement | sequence of a solid-state image sensor.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

(First embodiment)
FIG. 1 is a circuit diagram showing a solid-state imaging device according to the first embodiment of the present invention. The pixel portion 101 includes a photoelectric conversion element (photoelectric conversion portion) that converts incident light into electric charges, and a plurality of pixels 102 that output electric charges as analog electric signals are arranged in a matrix in N rows and M columns. ing. Here, as an example, a pixel portion arranged in 6 pixels in the row direction and 4 pixels in the column direction is shown. Each pixel 102 is provided with a color filter having a Bayer arrangement as shown in FIG. 29, and each pixel outputs a pixel value corresponding to the color of the color filter. In FIG. 29, a G filter arranged in the same column as the B filter is a G1 filter, and a G filter arranged in the same column as the R filter is a G2 filter. As shown in FIG. 29, an RG column in which R pixels and G2 pixels are arranged and a GB column in which G1 pixels and B pixels are arranged are alternately repeated. In the embodiment described below, in order to make the description easy to understand, the GB column is not shown, and a plurality of RG columns are continuously arranged. A GB column configured in the same manner as the RG column is arranged.

  The pixel 102 is connected to the horizontal register 103 via the row selection line 104, and six pixels connected to the selected row selection line 104 are selected simultaneously. Here, the row selection lines 104 from the first to fourth rows are Pv1 to Pv4. When the row selection line 104 is HIGH, a row is selected, and an analog electric signal is output from the pixel 102 to the column output line 105. When the row selection line 104 is LOW, the row selection is canceled and the connection between the pixel 102 and the column output line 105 is disconnected. By selecting Pv1 to Pv4 of the row selection line 104 one by one, the analog electric signals of the pixels in the first to fourth rows are sequentially output to the column output line 105.

  The AD converter (ADC) 106 converts the analog electric signal output to the column output line 105 into a digital signal. Between each column output line 105 and the A / D converter 106, there is an addition buffer 111 (addition unit), a column transistor 107, and an AD transistor 108. Further, the row transistor 109 is between the column transistor 107 and the AD transistor 108, and can be connected / disconnected to other columns. The column transistor 107, the AD transistor 108, and the row transistor 109 are connected and disconnected by the vertical register 110.

  When the column transistor 107 is connected, an analog electric signal on the column output line 105 can be read out. Further, when the column transistor 107 is disconnected, the analog electric signal on the column output line 105 cannot be read out. When the AD transistor 108 is connected, the AD converter 106 can read an analog electric signal. Further, when the AD transistor 108 is cut, the AD converter 106 cannot read the analog electric signal. The row transistor 109 is used when an analog electric signal output from a pixel in a certain column to the column output line 105 is AD converted using the AD converter 106 in another column.

  Next, a detailed structure of the pixel 102 in FIG. 1 will be described with reference to FIG. A photodiode (hereinafter referred to as PD) 301 generates a charge corresponding to incident light by photoelectric conversion. A transfer transistor 302 is arranged between the PD 301 and a floating diffusion (hereinafter referred to as FD) region 303. When the transfer control pulse pTX is LOW, the PD 301 and the FD region 303 are disconnected, and the transfer control pulse When pTX is HIGH, the connection is established and the charge generated in the PD 301 is transferred to the FD region 303.

  The reset transistor 304 is disposed between the reset power supply and the FD region 303, and is in a disconnected state when the reset control pulse pRES is LOW. When the reset control pulse pRES is HIGH, the reset power supply and the FD region 303 are connected. At this time, the FD region 303 has the same potential as the reset power supply. At this time, if the transfer control pulse pTX is also set to HIGH, the PD 301 also has the same potential as the reset voltage. In this way, the reset control pulse pRES is set to HIGH to perform a reset operation so that each unit has the same potential as the reset voltage.

  The selection transistor 305 is disposed between the pixel power supply and the amplification transistor 306, disconnects the amplification transistor 306 and the pixel power supply when the selection control pulse pSEL is LOW, and connects when the selection control pulse pSEL is HIGH. Here, when the selection control pulse pSEL is HIGH, the amplification transistor 306 amplifies a voltage corresponding to the electric charge held in the FD region 303 and outputs the amplified voltage to the column output line 105 as an analog electric signal.

  The capacitor 309 is a capacitor for holding an analog electric signal during a period in which the analog electric signal output to the column output line 105 is AD converted. An output line transistor 308 is disposed between the column output line 105 and the capacitor 309. When the control pulse pSIG is LOW, the column output line 105 and the capacitor 309 are disconnected, and the control pulse pSIG is HIGH. In the case of, it is connected.

  Next, the specific operation of FIG. 2 will be described with reference to FIG. Here, the operation of outputting the analog electrical signal of the reference component and the analog electrical signal of the signal component to the column output line will be described.

  At time t401, the row selection control pulse pSEL for the readout pixel is set to HIGH. By this operation, the voltage of the FD region 303 input to the gate of the amplification transistor 306 in the read row is amplified and output to the column output line 105.

  Next, at time t402, the transfer control pulse pTX and the reset control pulse pRES are set to HIGH. By this operation, the reset power supply, the voltage of the PD 301, and the voltage of the FD region 303 become the same voltage, and the PD 301 and the FD region 303 are reset.

  Next, at time t403, the transfer control pulse pTX and the reset control pulse pRES are set to LOW. With this operation, the reset operation of the PD 301 and the FD area 303 is completed. Further, the charge accumulation of the PD 301 is started from the time when the reset operation is completed.

  Next, at time t404, the control pulse pSIG is set to HIGH. By this operation, the column output line 105 and the capacitor 309 are electrically connected, and the reference component analog electric signal output to the column output line 105 is input to the capacitor 309. Next, at time t405, the control pulse pSIG is set to LOW. By this operation, the column output line 105 and the capacitor 309 are electrically disconnected, and the capacitor 309 holds the voltage of the analog electric signal at this time. Further, the voltage of the capacitor 309 held at the time t405 is read by the ADC 106 at the subsequent stage.

  Next, at time t406, the transfer control pulse pTX is set to HIGH. With this operation, charges accumulated by photoelectric conversion in the PD 301 are transferred to the FD region 303. Next, the transfer control pulse pTX is set to LOW at time t407. With this operation, the transfer of charges from the PD 301 to the FD region 303 is completed. The period from time t403 to t407 is the charge accumulation time. At time t 407, a voltage corresponding to the charge of the signal component accumulated during the accumulation time is amplified by the amplification transistor 306 and output to the column output line 105.

  Next, the control pulse pSIG is set to HIGH at time t408. By this operation, the column output line 105 and the capacitor 309 are electrically connected, and the analog electric signal of the signal component output to the column output line 105 is input to the capacitor 309. Next, at time t409, the control pulse pSIG is set to LOW. By this operation, the column output line 105 and the capacitor 309 are electrically disconnected, and the capacitor 309 holds the voltage of the analog electric signal at this time.

  Next, at time t410, the selection control pulse pSEL for the row of readout pixels is set to LOW. By this operation, the output of the analog electric signal to the column output line 105 of the amplification transistor 306 in the readout row is stopped. Thereafter, the pixel signal can be read out by repeating the same operation for the pixels in the next row.

  Next, the detailed structure of the ADC 106 in FIG. 1 will be described with reference to FIG. The output line transistor 308 and the capacitor 309 in FIG. 4 are the same as the output line transistor 308 and the capacitor 309 in FIG.

  The amplification amplifier 503 amplifies the differential voltage between the analog electrical signal ASIG and the reference voltage VREF and outputs it to the comparator 506. Here, the amplification factor of the amplification amplifier 503 is determined by the capacitor 504.

  The ramp signal generator 505 outputs a ramp wave (ramp signal) to the comparator 506. The comparator 506 compares the amplified analog electrical signal pGSIG with the ramp signal pLAMP of the ramp signal generator 505, and when the magnitude relationship of the voltages is reversed, the output signal pCOMP is inverted. Here, LOW is output when the voltage of the ramp signal pLAMP of the ramp signal generator is lower than the voltage of the amplified analog electrical signal pGSIG, and HIGH is output when the voltage of the ramp signal pLAMP of the ramp signal generator is higher.

  The gray code counter 507 starts counting at the timing of starting the operation of the ramp signal generator 505 and inputs the count value to the memory 508. The memory 508 holds the count value of the Gray code counter 507 when the input signal from the comparator 506 becomes HIGH.

  After the output of the ramp signal generator 505 operates for one cycle, the count value held in the memory 508 is read. The clock 509 generates a synchronizing signal for the ramp signal generator 505 and the Gray code counter 507.

  Next, the operation of the ADC 106 for converting the analog electric signal shown in FIG. 4 into a digital signal will be described with reference to FIG.

  At time t601, the control pulse pSIG is set to HIGH. With this operation, the capacitor 309 is charged with the voltage of the amplified analog electric signal pVSIG in FIG. At the same time, the analog electric signal pVSIG is input to the amplification amplifier 503 in FIG. 4, and the signal pGSIG obtained by amplifying the analog electric signal pVSIG is output to the comparator 506. Next, at time t602, the control pulse pSIG is set to LOW. By this operation, the capacitor 309 holds the voltage of the analog electric signal of pVSIG.

  Next, the ramp signal generator 505 outputs the ramp signal pLAMP at time t603. At the same time, the gray code signal pCNT is output from the gray code counter 507 to the memory 508. Here, in order to make the description easy to understand, a description will be given using a 3-bit gray code counter. Further, the gray code signal pCNT changes in synchronization with the voltage of the ramp signal pLAMP. This counting is performed until time t605.

  Here, the comparator 506 compares the signal pGSIG with the ramp signal pLAMP. When the ramp signal pLAMP is lower than the signal pGSIG, the output signal pCOMP is LOW, and when the ramp signal pLAMP is higher than the signal pGSIG, the output signal pCOMP is Become HIGH. Assuming that the time when the output signal pCOMP becomes HIGH is t604, the memory 508 stores the output signal pCNT inputted at this time.

  Next, a pixel signal reading operation using the AD converter 106 will be described. In FIG. 1, the reference component ΔV (N signal) including the noise of the pixel signal is read out from each pixel 102 in the selected row of the pixel portion 101 as an analog electric signal in the first reading operation. The signal component Vsig (S signal) is read by the operation. Then, the reference component ΔV and the signal component Vsig are input to the AD converter 106 through the column output line 105.

  The reference component ΔV read out for the first time includes fixed pattern noise that varies for each pixel 102 as an offset. In the second read operation, Vsig + ΔV obtained by adding the reference component ΔV and the signal component Vsig corresponding to the amount of incident light for each pixel 102 is read. The signal value Vsig to be obtained is obtained from the difference between the second reading (Vsig + ΔV) and the first reading (ΔV).

  When the first AD conversion process is performed for the reference component ΔV, the second AD conversion process is a process for the signal obtained by adding the signal component Vsig to the reference component ΔV.

  Next, a detailed operation of the AD converter will be described with reference to FIG. First, AD conversion of the reference component ΔV will be described.

  At time t71, an analog electrical signal of the reference component ΔV is input from the pixel 102. Next, at time t72 to t74, the reference voltage RAMP is changed by a fixed amount every unit time. At this time, the reference voltage RAMP is compared with the analog electric signal, and the time t73 when the voltages match is measured. Here, the product of the voltage change amount per unit time of the reference voltage RAMP and the time from t72 to t73 is converted into digital data as the reference component ΔV.

  Next, AD conversion of the signal component Vsig will be described. At time t <b> 75, the signal component Vsig is input from the pixel 102. Next, at time t76 to t78, the reference voltage RAMP is changed by a fixed amount every unit time. At this time, the reference voltage RAMP is compared with the analog electric signal, and the time t77 when the voltages match is measured. Here, the product of the voltage change amount per unit time of the reference voltage RAMP and the time from t76 to t78 is converted into digital data as the signal component Vsig.

  The difference between the second readout (Vsig + ΔV) obtained here and the first readout (ΔV) is output as a pixel signal value.

  Next, driving of all pixel readout when the image sensor of FIG. 1 is used will be described. In the all-pixel reading drive, the analog electric signal of the pixel 102 in each column is read by the AD converter 106 in each column in which the pixel 102 exists.

  Therefore, all the column transistors 107 and AD transistors 108 are set to HIGH to be connected, and all the row transistors 109 are set to LOW to be disconnected. Thus, in the image sensor of FIG. 1, the signal of the pixel 102 is read out by the AD converter in the column where the pixel 102 is located.

  Next, a specific operation when reading all pixels will be described with reference to FIG. First, at t801, the row selection signal Pv1 and the columns Tr1 to Tr6 that are control pulses of the column transistor 107 and the ADCTr1 to ADCTr1 to 6 that are control pulses of the AD transistor 108 become HIGH. When the row selection signal Pv1 becomes HIGH, the analog electric signals of the pixels 11 to 16 in the first row are output to the column output line 105 of each column.

  Further, when the columns Tr1 to 6 and the ADCTr1 to 6 are HIGH, the analog electric signal of the column output line 105 of each column is output to the AD converter 106 of each column. The state of the AD converter 106 at this time corresponds to the state of t71 in FIG. Further, t801 to t802 correspond to t71 to t72 in FIG. 6, and an analog electric signal is input to the AD converter 106 between t801 to t802.

  Next, at t802, readout of the reference component ΔV corresponding to t72 in FIG. 6 is started for the pixels 102 in the first row. Here, ADCTr1-6 are set to LOW, and the connection between the column output line 105 and the AD converter 106 is disconnected. As a result, the AD converter 106 holds the voltage of the analog electrical signal of the reference component ΔV. At the same time, the comparison operation between the analog electrical signal of the reference component ΔV and the reference voltage RAMP is started.

  Next, at t803, the reading of the reference component ΔV for the pixels 102 in the first row ends. The operation of the AD converter 106 corresponds to the state at t74 in FIG. Further, ADCTr1 to ADCTr6 are set to HIGH to start reading the signal component Vsig of the pixel unit 102 in the first row.

  Next, at t804, readout of the signal component Vsig corresponding to t76 in FIG. 6 is started for the pixels 102 in the first row. Here, ADCTr1 to ADCTr6 are set to LOW, and the connection between the column output line 105 and the AD converter 106 is disconnected. Thereby, the AD converter 106 holds the voltage of the analog electric signal of the signal component Vsig. At the same time, the comparison operation between the analog electrical signal of the signal component Vsig and the reference voltage RAMP is started.

  Further, t804 to t805 correspond to t76 to t78 in FIG. 6, and an analog electric signal is input to the AD converter 106 between t804 and t805. Then, at t805, the comparison operation between the analog electrical signal of the signal component Vsig and the reference voltage RAMP is finished. Further, the row selection signal Pv1 is set to LOW, and the row selection signal Pv2, the columns Tr1 to 6 and the ADCTr1 to ADC6 are set to HIGH. By this control, reading of signal values of the pixels 102 in the second row is started.

  Thereafter, the analog electric signals of the reference component and the signal component are A / D converted and the signal value is read out as in the first row.

Next, a driving method for performing half-thinning readout in the direction along the row when the image sensor of FIG. 1 is used will be described. In this embodiment, when the image pickup device is driven to perform pixel thinning, the readout pixel signal is distributed and input to the AD converter 106 of the readout pixel column and the AD converter 106 of the thinning pixel column, and AD conversion is performed. As a result, as the thinning amount increases, the number of AD converters that can use one readout column can be increased, the number of AD conversions required for reading out one frame of pixel signals can be reduced, and the time required for AD conversion can be shortened. it can.
The outline of the operation of this embodiment will be described with reference to FIG. The half-thinning operation will be described with reference to FIG. As shown in (1) of FIG. 8A, here, the pixel signals of the first, third, and fifth columns are read, and the pixel signals of the second, fourth, and sixth columns are not read. First, in (2) of FIG. 8A, the pixel signals in the first row are transferred to the AD converters in the first, third, and fifth columns. Next, in (3) of FIG. 8A, the pixel signals in the second row are transferred to the AD converters of 2, 4, and 6 columns. Then, the read operation of the AD converter is started in (4) of FIG.
With the above operation, signals for two rows can be AD converted simultaneously in a single read operation. Further, FIG. 8B similarly illustrates the 1/3 decimation operation, and in this operation, signals for three rows can be simultaneously AD converted.

  In the conventional image sensor, the AD converter 106 in a certain column of each pixel performs AD conversion on the signal of the pixel 102. For this reason, as the amount of addition or decimation in the direction along the row increases, the number of AD converters that do not read pixel signals has increased. However, in this embodiment, when addition / column thinning readout driving in the direction along the row is performed, a pixel signal is also input to the AD converter 106 of the thinned column and readout is performed. By doing so, it is possible to increase the number of rows for which AD conversion is performed at a time (simultaneously) according to the column thinning amount.

  Next, a specific operation when the half-thinning readout driving is performed in the direction along the row will be described with reference to FIG.

  First, an analog electrical signal of the reference component ΔV of the pixels 102 in the first row is input to the AD converter 106. At t901, the row selection signal Pv1 and the columns Tr1, 3, 5 of the columns Tr1 to Tr6 and the ADCTr1, 3, 5 of the ADCTr1 to ADCTr6 become HIGH. When the row selection signal Pv1 becomes HIGH, the analog electric signal of the reference component ΔV of the pixels 11, 13, and 15 in the first row becomes the column output line 105 in each of the first, third, and fifth columns. Is output. Further, since the columns Tr1, 3, 5 and ADCTr1, 3, 5 are HIGH, the analog electric signals of the column output lines of the first column, the third column, and the fifth column are converted into AD converters of the respective columns. The data is output to 106.

  Next, at t <b> 902, the connection between the pixel 102 in the first row and the AD converter 106 is disconnected, and the analog electrical signal of the reference component ΔV of the pixel 102 in the second row is input to the AD converter 106. First, Pv1 and ADCTr1, 3, and 5 are set to LOW. By this control, the AD converters in the first, third, and fifth columns hold the voltage of the analog electrical signal of the reference component ΔV of the pixels 11, 13, and 15 in the first row. Then, ADCTr2, 4, 6 of Pv2 and ADCTr1 to ADCTr6, and rows Tr1, 3, 5 of row Tr1 to Tr5 are set to HIGH. When the row selection signal Pv2 becomes HIGH, the analog electric signal of the reference component ΔV of the pixels 11, 13, and 15 in the second row becomes the column output line 105 in each of the first, third, and fifth columns. Is output.

  Next, at t903, the connection between the pixels 102 in the second row and the AD converter 106 is disconnected, and the analog electrical signal of the reference component ΔV of the pixels 102 in the first row and the second row held by the AD converter 106 is read out. To start.

  First, Pv2 and ADCTr2, 4, 6, and rows Tr1, 3, 5 are set to LOW. With this control, the AD converters in the second, fourth, and sixth columns hold the voltage of the analog electrical signal of the reference component ΔV of the pixels 21, 23, and 25 in the second row. Then, ADCRES is set to HIGH, and readout of analog electric signals of reference components of the pixels in the first and second rows is started by the operation at t72 in FIG.

  Next, at t904, the reading of the analog electrical signal of the reference component ΔV of the pixels in the first row and the second row is finished, and the signal component Vsig is read. First, ADCRES is set to LOW, and the reference component reading operation of the AD converter 106 is completed.

  Next, similarly to t901, the row selection signal Pv1 and the columns Tr1, 3, 5 of the columns Tr1 to Tr6 and the ADCTr1, 3, 5 of the ADCTr1 to ADCTr6 are set to HIGH. By setting the row selection signal Pv1 to HIGH, the analog electric signal of the signal component Vsig of the pixels 11, 13, and 15 in the first row is output to the vertical output line 105 of each column. Further, when the columns Tr1, 3, 5 and ADCTr1, 3, 5 are set to HIGH, the analog electric signals of the vertical output lines of the first column, the third column, and the fifth column are converted into the AD converter 106 of each column. Is output.

  Next, at t905, the connection between the pixel 102 in the first row and the AD converter 106 is disconnected, and the analog electric signal of the signal component Vsig of the pixel 102 in the second row is input to the AD converter 106. First, Pv1 and ADCTr1, 3, and 5 are set to LOW. By this operation, the AD converters in the first, third, and fifth columns hold the voltage of the analog electrical signal of the signal component Vsig of the pixels 11, 13, and 15 in the first row.

  Then, ADCTr2, 4, 6 of Pv2 and ADCTr1 to ADCTr6, and rows Tr1, 3, 5 of row Tr1 to Tr5 are set to HIGH. When the row selection signal Pv2 becomes HIGH, the analog electric signals of the pixels 11, 13, and 15 in the second row are output to the column output lines 105 in the first, third, and fifth columns. .

  Next, at t906, the connection between the pixel 102 in the second row and the AD converter 106 is disconnected, and the analog electric signal of the signal component Vsig of the pixels in the first row and the second row held by the AD converter 106 is read out. To start. First, Pv2 and ADCTr2, 4, 6, and rows Tr1, 3, 5 are set to LOW. By this control, the AD converters in the second column, the fourth column, and the sixth column hold the voltages of the analog electrical signals of the signal components of the pixels 21, 23, and 25 in the second row.

  Then, ADCSIG is set to HIGH, and readout of analog electric signals of the signal components of the pixels in the first and second rows is started by the operation at t72 in FIG.

  Next, at t907, the reading of the analog electric signal of the signal component Vsig of the pixels in the first row and the second row is finished, and the reading of the reference component ΔV in the third row is performed.

  Then, ADCSIG is set to LOW, and the reference component reading operation of the AD converter 106 is completed. Next, the row selection signal Pv3 is set to HIGH, the columns Tr1, 3, 5, and ADCTr1, 3, and 5 are set to HIGH in the same manner as t901, and the row selection signal Pv3 is set to HIGH, whereby the pixel 31 in the third row. , 33, and 35 are output to the column output line 105 of each column.

  Further, when the columns Tr1, 3, 5 and the ADCTr1, 3, 5 are set to HIGH, the analog electric signal of the column output line of each column is output to the AD converter 106 of each column.

Subsequently, the reference component and signal component readout operations are performed in the same manner as the readout operations of the first and second rows.
Next, a case where pixel signals are added using the addition buffer 111 will be described. In this embodiment, as an example of the addition buffer 111, a three-column addition buffer using a charge addition averaging circuit is used. The charge addition averaging circuit introduced here is merely an example, and other configurations may be used, or a charge addition circuit that adds charges may be used.

  Next, the configuration of the addition buffer will be described. The configuration of the addition buffer is shown in FIG. Analog electric signals from the column output lines are input via the input lines pVIN1 to pVIN1-3. Moreover, an analog electric signal is output via the output lines pVOUT1 to pVOUT1-3.

  The input transistors 1101 to 1103 are controlled by control signals pISIG1 to 3, and the output transistors 1107 to 1109 are controlled by control signals pOSIG1 to pOSIG1. Further, the addition source follower (hereinafter referred to as addition SF) 1110 to 1112 converts the gate charge signal into an analog electric signal and outputs it when the control signal pOSIG of the output transistor connected in series is HIGH.

  The addition transistors 1113 and 1114 are controlled by control signals pSHR1 and pSHR2, and when the addition transistors are connected, the charges (pixel signals) of the capacitors 1104 to 1106 at both ends are averaged. In the case of the addition buffer of FIG. 10, when the control signal pSHR1 is HIGH, the charges accumulated in the capacitors 1104 and 1105 are averaged, and when the control signals pSHR1 and pSHR2 are HIGH, they are accumulated in the capacitors 1104 to 1106. Charges are added and averaged to generate an added signal.

  Next, the three-pixel addition average operation will be described with reference to FIG. The analog electric signal of the column output line is input to the input lines pVIN1 to pVIN1-3, and the control signals pISIG1 to 3 are set to HIGH at time t1201. Then, analog electric signals of column output lines corresponding to the capacitors 1104 to 1106 are input.

  Next, at time t1202, the control signals pISIG1 to 3 are set to LOW. By this operation, the analog electric signal of the column output line is held. Next, at time t1203, the control signals pSHR1 and pSHR2 are set to HIGH. By this operation, the charges of the capacitors 1104 to 1106 are added. When the addition operation is performed, the added voltages of the capacitors C1104 to 1106 are all constant as shown in FIG. Further, by changing the capacitance values of the capacitors 1104 to 1106, the charge to be accumulated can be changed, and it is also possible to add with weighting for each column.

  Next, at time t1204, the control signals pSHR1 and pSHR2 are set to LOW to complete the pixel addition.

  Next, the output transistor of the column that outputs the addition result is turned ON. Here, in order to output the addition result to the column of the output line pVOUT1, the control signal pOSIG1 is set to HIGH at time t1205. When the output to the ADC is completed, the control signal pOSIG1 is set to LOW at time t1206.

  In the present embodiment, AD conversion of pixel signals in a plurality of rows is simultaneously performed when pixel addition driving of the image sensor. In this way, as the amount of addition increases, the number of AD conversions per frame can be reduced, and the time required for AD conversion can be shortened. In each of the following embodiments, it is desirable that pixel signals input to the addition buffer and added are pixels of the same color.

  Next, the outline of the operation of the present embodiment will be described with reference to FIG. The operation of adding two pixels will be described with reference to FIG. Here, the signals of the 1st column + 2th column, the 3rd column + 4th column, and the 5th column + 6th column are respectively added and read.

  First, in (2) of FIG. 12A, pixel signals of each column in the first row are added by two columns in the addition buffer, and transferred to AD converters of 1, 3, and 5 columns. Next, in (3) of FIG. 12A, the pixel signals of each column in the second row are added by two columns in the addition buffer and transferred to the AD converters of 2, 4, and 6 columns. Then, the read operation of the AD converter is started in (4) of FIG.

  With the above operation, it is possible to simultaneously AD-convert signals for two rows obtained by adding two pixels by a single readout operation.

  FIG. 12B similarly illustrates the operation of adding three pixels. In this operation, signals for three rows can be simultaneously AD converted. Since operations other than the addition averaging operation of the addition buffer are the same as in the case of performing column thinning readout driving, description thereof is omitted.

(Second Embodiment)
FIG. 13 is a circuit diagram showing a solid-state imaging device according to the second embodiment of the present invention. The circuit diagram of the second embodiment is the same as that of FIG. 1 except that the column transistor 107 is omitted. In the present embodiment, when the image sensor is driven to perform pixel thinning or when the image sensor is driven to add pixels, AD conversion of pixel signals in an arbitrary row is performed using a plurality of AD converters. In this way, as the thinning amount increases, the number of AD converters that can be used for reading one pixel can be increased, and the time required for AD conversion can be shortened. Further, as the amount of addition increases, the number of AD converters that can be used for reading signals after addition can be increased, and the time required for AD conversion can be shortened.

  Next, the outline of the operation of the present embodiment will be described with reference to FIG. The operation of 1/2 decimation will be described with reference to FIG.

  As shown in (1) of FIG. 14A, here, the pixel signals of the first, third, and fifth columns are read, and the pixel signals of the second, fourth, and sixth columns are thinned out. First, in (2) of FIG. 14A, the pixel signals of the first column, the third column, and the fifth column in the first row are respectively converted by the AD converters of the first column, the second column, the third column, the fourth column, and the fifth column and the sixth column. A / D conversion is performed, and the AD converter read operation is started in (3) of FIG. With the above operation, two AD converters can be used per pixel.

  FIG. 14B similarly illustrates the 1/3 thinning-out operation. In this operation, three AD converters can be used per pixel.

  In this embodiment, when a pixel signal is read by thinning-out readout, analog electric signals having the same reference component / signal component are input to a plurality of AD converters 1406, and AD conversion processing is performed. FIG. 15 shows a circuit diagram of the AD converter. The AD converter of FIG. 15 has the same configuration as that of FIG. 4 except that a DC voltage adding circuit 1610 is added. The DC voltage adding circuit 1610 can switch the presence / absence of input of a determined DC voltage at an arbitrary timing.

  Next, the operation of the AD converter 1406 in FIG. 15 will be described using the timing chart in FIG. Here, since the operation until the analog electric signal is input from the pixel 1402 to the AD converter 1406 and the AD conversion mechanism of the AD converter are the same as those in the first embodiment, description thereof is omitted. Here, as an example, two AD converters are respectively referred to as an AD converter a and an AD converter b, the operation using the AD converter a is shown in FIG. 16A, and the operation using the AD converter b is shown in FIG. Will be described.

  First, AD conversion of the reference component ΔV will be described. From FIG. 16, the reference component ΔV is input from the pixel 1402 at time t1701. Next, at times t1702 to t1704, the reference voltage RAMP is changed by a fixed amount every unit time. At this time, the reference voltage RAMP and the analog electrical signal of the reference component ΔV are compared, and a time t1703 at which the voltages match is measured. Here, the product of the voltage change amount per unit time of the reference voltage RAMP and the time from t1702 to t1703 is converted into digital data as the reference component ΔV.

  Next, AD conversion of the signal component Vsig will be described. At time t1705, the signal component Vsig is input from the pixel 1402. At time t1706, the voltage of the DC voltage adding circuit is added to the reference voltage RAMP2 that is the input voltage to the AD converter b and input.

  Here, when the voltage range that can be converted by AD conversion is an input voltage range, in this embodiment, the AD converters a and b divide the input voltage range into upper and lower levels, and the lower level is read by the AD converter a. The higher order is read by the AD converter b. Specifically, the AD converter b adds the DC voltage of the DC voltage adding circuit to the reference voltage RAMP2, and compares signals from a reference signal offset voltage different from that of the AD converter a.

  Next, at times t1707 to t1709, the reference voltages RAMP1 and RAMP2 are changed by a fixed amount every unit time. At this time, the reference voltages RAMP1 and RAMP2 and the analog electric signal of the signal component Vsig are compared, and a time t1708 at which the voltage of one of the AD converters a and b matches is measured. Here, the product of the voltage change amount per unit time of the reference voltages RAMP1 and RAM2 and the time from t1707 to t1708 is converted into digital data as the signal component Vsig. The difference between the second readout (Vsig + ΔV) obtained here and the first readout (ΔV) is output as a pixel signal value.

  When the AD conversion ends, at time t1710, the input of the DC voltage to the DC voltage adding circuit of the reference voltage RAMP2 is stopped, so that the reference voltage RAMP1 and the reference voltage RAMP2 are set to the same voltage.

  Next, a description will be given of a driving method in which reading is performed by thinning out in half in the direction along the row when the image sensor of FIG. 13 is used. In the conventional image sensor, the AD converter of each column of the pixel 1402 performs AD conversion on the signal of the pixel 1402. Therefore, as the amount of thinning out in the direction along the row increases, AD converters that are not used for reading out pixel signals remain. However, in this embodiment, when column thinning readout driving is performed, reading is also performed using the AD converter 1406 of the thinned column. By doing so, it is possible to increase the number of rows for which AD conversion is performed at a time (simultaneously) according to the column thinning amount.

  Next, a specific operation when the half-thinning readout driving is performed in the direction along the row will be described with reference to FIG. First, an analog electrical signal of the reference component ΔV of the pixels 1402 in the first row is input to the AD converter 1406. At t1801, the row selection signal Pv1, the rows Tr1, 3, and 5 among the ADC Tr1 to 6 and the rows Tr1 to Tr5 are set to HIGH. When the row selection signal Pv1 becomes HIGH, the analog electric signal of the reference component ΔV of the pixels 11, 13, and 15 in the first row is output to the column output line 1405 of each column. Further, the ADC Tr1 to 6 and the rows Tr1, 3 and 5 become HIGH, so that the analog electric signal of the vertical output line of the pixel column from which the pixel signal is read out is read column, readout pixel column and row Tr. It is output to the AD converter 1406 of the connected column.

  Next, at t1802, the connection between the pixel 1402 in the first row and the AD converter 1406 is disconnected, and reading of the analog electrical signal of the reference component ΔV of the pixel in the first row held by the AD converter 1406 is started. First, Pv1 and ADCTr1-6 are set to LOW. By this control, the AD converters in the first and second columns hold the voltage of the analog electric signal of the reference component ΔV of the pixel 11.

Similarly, the AD converters in the third and fourth columns hold the voltage of the analog electric signal of the reference component ΔV of the pixel 13, and the AD converters in the fifth and sixth columns hold the voltage of the analog electric signal of the reference component ΔV of the pixel 15. To do. Then, ADCRES is set to HIGH, and reading of the analog electric signal of the reference component ΔV of the pixel in the first row is started by the operation at t1702 in FIGS. 16A and 16B. Next, at t1803, the first row The reading of the analog electrical signal of the reference component ΔV is finished, and the signal component Vsig is read. First, ADCRES is set to LOW, and the reference component reading operation of the AD converter 1406 is completed.
Next, similarly to t1801, the row selection signal Pv1 and ADCTr1 to 6 are set to HIGH. By setting the row selection signal Pv1 to HIGH, the analog electric signal of the signal component Vsig of the pixels 11, 13, and 15 in the first row is output to the column output line 105 of each column. Further, when ADCTr1 to 6 are set to HIGH, the analog electric signal of the column output line of each column is output to the AD converter 1406 of each column.

  Next, at t1804, the connection between the pixel 1402 in the first row and the AD converter 1406 is disconnected, and a DC voltage is applied to the reference signal RAMP of the AD converter. First, Pv1 and ADCTr1-6 are set to LOW. By this control, the AD converters in the first to sixth columns hold the voltage of the analog electric signal of the signal component Vsig of the pixels 11, 13, and 15. Then, ADCOFFSET is set to HIGH, and a desired DC voltage is applied to the reference signal RAMP for each AD converter by the operation at t1706 in FIG.

  Next, at t1805, reading of the analog electric signal of the signal component Vsig of the pixel in the first row held by the AD converter 1406 is started. With ADCSIG set to HIGH, readout of the analog electric signal of the signal component Vsig of the pixel in the first row is started by the operation at t1707 in FIG. Next, at t1806, the readout of the analog electric signal of the signal component Vsig of the pixel in the first row is finished. ADCSIG is set to LOW, and the signal component reading operation of the AD converter 1406 is completed.

  Next, at t1807, the input of the DC voltage applied to the reference signal RAMP of the AD converter is stopped, and the reference component ΔV of the pixel 1402 in the second row is input to the AD converter 1406. At T1807, ADCOFFSET is set to LOW, and the DC voltage applied to the reference signal RAMP of each AD converter in the operation at t1710 in FIG. 16 is input.

  Next, the row selection signal Pv2, ADCTr1-6, and rows Tr1, 3, 5 are set to HIGH. When the row selection signal Pv2 becomes HIGH, the analog electric signal of the reference component ΔV of the pixels 11, 13, and 15 in the second row is output to the column output line 1405 of each column. Further, the ADC Tr1 to 6 and the rows Tr1, 3 and 5 become HIGH, so that the analog electric signal of the column output line of the column of the pixel from which the pixel signal is read out, the column of the readout pixel, the column of the readout pixel, and the row transistor Are output to the AD converter 1406 of the connected column.

  Thereafter, the reference component and the signal component are read out in the same manner as the first row readout operation.

  Next, a case where pixel signals are added by the addition buffer 1910 will be described with reference to FIG. The operation of adding two pixels will be described with reference to FIG. Here, the signals of the 1st column + 2th column, the 3rd column + 4th column, and the 5th column + 6th column are respectively added and read.

  First, pixel signals obtained by adding two columns in the first row in (2) of FIG. 18A are respectively input to AD converters of the first column, the second column, the third column, the fourth column, the fifth column, and the sixth column, Then, the read operation of the AD converter is started in (3) of FIG.

  With the above operation, two AD converters can be used per pixel. Further, FIG. 18B similarly illustrates the operation of adding three pixels. In this operation, three AD converters can be used for one signal after the addition. Since operations other than the addition averaging operation of the addition buffer are the same as in the case of performing column thinning readout driving, description thereof is omitted.

(Third embodiment)
Hereinafter, a third embodiment of the present invention will be described. FIG. 19 is a circuit diagram illustrating a solid-state imaging device according to the third embodiment. The pixels 171-1 and 171-2 output signals based on incident light by photoelectric conversion, and the pixels 171 are arranged in N rows and M columns in the imaging unit 172. The column output lines 173-1 and 173-2 output the pixel output of the row selected by the row selection unit 174 for each column. The solid-state imaging device of the present embodiment has two column output lines 173-1 and 173-2 per pixel column, and every other row of pixels in the same pixel column alternately displays the column output lines 173. -1, 173-2. In the present embodiment, the pixel 171-1 is connected to the output line 173-1, and the pixel 171-2 is connected to the output line 173-2.

  The column amplifier 175 receives the signal from the column output line 173, amplifies the signal, and outputs the amplified signal to an AD conversion circuit 177 provided for each column. A column amplifier reference voltage 176 is supplied to the column amplifier of each column. The clamp SW 114 clamps the signal.

  The ramp signal generation circuit 111 generates a ramp signal. Further, the latch memory circuits 178-1 and 178-2 can temporarily store the AD conversion results and read them out to the digital output lines 180-1 and 180-2. The column selection circuit 179 sequentially selects the latch memory circuit and sequentially transfers the digital signal to the digital output line 110.

  The S signal memory 178-1 and the output line 110-1 store and output the S signal, and the N signal memory 178-2 and the output line 110-2 store and output the N signal. Also, the pixel columns 130-1 and 130-2 indicate one pixel column unit. In this embodiment, two column output lines, one column amplifier, and a column AD conversion circuit are provided for one pixel column. It has a configuration of one. The gray code counter 113 counts the gray code, and the digital processing circuit 112 performs digital processing.

  The adder circuit 120 can add the pixel signals output from the pixel column 130-1 and the pixel column 130-2. The adding circuit 120 is formed by a plurality of switches and a plurality of capacitors. And it was output to the column output line 173-1 by turning on and off the switches 121-1, 121-2, 122-1, 122-2, 123-1, 123-2, 124-1, and 124-2. The pixel signal is read out, the pixel signal output to the column output line 173-2 is read out, or the pixel signal output to the column output line 173-1 or 173-2 is input to the column output line 173 of the adjacent pixel column. -1 or 173-2 can be switched to add the pixel signal.

  The feature of this embodiment is that an AD conversion circuit 177 provided for a pixel column, an addition circuit 120 that adds signals of a plurality of pixel columns, and an arbitrary AD conversion of the added pixel signal according to shooting conditions It has a changeover switch which inputs into a circuit.

  The AD conversion circuit 177 is a comparator having a differential input configuration, and the output signal of the column amplifier 175 is input to the + input terminal. Also, the output of the ramp signal generation circuit 111 is input to the − input terminal, and when the voltage at the + input terminal is higher than that at the − input terminal, a High level is output, and the voltage at the + input terminal is from the − input terminal. If it is lower, a low level is output.

  The latch memory circuits 178-1 and 178-2 are latch memory circuits that latch and store the count value of the Gray code counter 113 at the inversion timing of the comparator. In the present embodiment, the output of the gray code counter when the output of the comparator 177 is switched from Hi to Lo is held.

  FIG. 20 is a circuit diagram illustrating an example of a circuit configuration of the pixel portion 171 in FIG. The photodiode 152 generates a charge corresponding to incident light by photoelectric conversion. The transfer transistor 153 has a source electrically connected to a photodiode 152, a gate electrically connected to a transfer control line 162, and a drain electrically connected to a floating diffusion (hereinafter referred to as FD) region 154.

  The FD region 154 is a region that temporarily holds charges transferred from the PD 152 via the transfer transistor 153. The reset transistor 155 has a source electrically connected to the FD region 154, a gate electrically connected to the reset control line 161, and a drain electrically connected to the power supply voltage. The amplifying transistor 156 has a gate that is a control electrode electrically connected to the FD region 154, a drain electrically connected to the power supply voltage, and a source electrically connected to the select transistor 157. The selection transistor 157 has a gate connected to the selection control line 163, a source connected to the column output line 173, and a drain connected to the source of the amplification transistor 156.

  The amplification transistor 156 amplifies and outputs a signal based on the charge held in the FD region 154 to the column output line 173 via the selection transistor 157. The reset control line 161, the transfer control line 162, and the selection control line 163 are electrically connected to the row selection unit 104, respectively.

  In FIG. 20, the column output line 173, the reset control line 161, the transfer control line 162, and the selection control line 163 are 1 in order to explain the driving of the first row and the second row of the row selection unit 174 separately. "-1" is attached to the line and "-2" is attached to the second line. However, the elements represented by 152 to 157 such as photodiodes have the same movement, and therefore the description and reference for each row are omitted.

  FIG. 21 is an enlarged view of the adder circuit 120 shown in FIG. In FIG. 21, the switches 121-1, 123-1, 121-2, and 123-2 are in an on state, and the switches 122-1, 124-1, 122-2, and 124-2 are in an off state. Yes. These switches perform switching control as shown in FIGS. 21B and 21C, respectively, and can be switched between an on state and an off state.

  FIG. 21A, FIG. 21B, and FIG. 21C each show a switching state for each mode, and FIG. 21A shows a mode for reading a pixel signal output to the column output line 173-1. FIG. 21B shows a mode for reading the pixel signal output to the column output line 173-2. In FIG. 21C, the pixel signal output to the column output line 173-1 of the pixel column 130-1 is added to the pixel signal output to the column output line 173-1 of the adjacent pixel column 130-2. The pixel signal output to the column output line 173-2 of the pixel column 130-1 is added to the pixel signal output to the column output line 173-2 of the adjacent pixel column 130-2. And output to the AD converter. In the modes of FIGS. 21A and 21B, the pixel signal of the column output line 173-1 and the pixel signal of the column output line 173-2 can be read simultaneously, so that they can be read at high speed. It becomes.

  In the present embodiment, two adjacent columns are added. However, the embodiment is not limited to this, and the same effect can be obtained by performing addition with one column or columns separated by a plurality of columns. Further, the combination of addition columns and the weighting of addition are not limited to this, and addition without deviation of the color centroid is also conceivable.

  FIG. 22 is a timing diagram illustrating a method for driving the solid-state imaging device illustrated in FIGS. 19, 20, and 21. 22A shows the timing when the adder circuit 120 is in the switch connection state of FIGS. 21A and 21B, and FIG. 22B shows the timing when the adder circuit 120 is in the state of FIG. 21C. It is.

  In the timing diagram illustrated in FIG. 22, when the control pulse is at a high level (hereinafter referred to as “H level”), the MOS transistor to which the control pulse is applied is electrically connected between the source and the drain. On the other hand, in the case of the Low level (hereinafter referred to as L level), the source and the drain are electrically disconnected. When a MOS transistor in which the source and the drain are conductive by applying an L level control pulse to the gate is used, the H level and the L level of the pulse shown in FIG. 22 are reversed. The operation similar to that of the present embodiment can be performed.

  Hereinafter, based on the timing chart of FIG. 22A, the circuit operation of FIGS. 19, 20, and 21 will be described in order from the time t0 for the driving method of the solid-state imaging device of the present embodiment.

  First, at time t0, the selection control pulse output to the selection control line 163-1 of the row to be read becomes H level, and the first row is selected as the reading row. Next, at time t1, the FD region 154 is reset by changing the reset control pulse output to the reset control line 161-1 from the H level to the L level. As a result, the voltage V173 of the column output line 173-1 changes to the reset level at time t1. At time t2 when the output of the column output line is stabilized, the control pulse 170 is set to the L level and the clamping operation is performed.

  Thereafter, AD conversion is started at t3. Here, the switching operation relationship of the adder circuit 120 shown in FIG. 21 is in the state shown in FIG. Therefore, the output of the hydraulic output line 173-1 is directly connected to the same column amplifier and column AD converter.

  The voltage V204− decreases from time t3 according to the slope of the lamp. At the same time, the counter 202 starts counting and the counter output 203 changes. A waveform D203 indicates a value converted into an output value based on the digital code of the counter.

  At time t4, the output of the comparator is inverted at the timing when the voltage V204− and the voltage V204 + are inverted, and the counter value D203 at this time is held. This held value is the reset level AD conversion result. At t5, the AD conversion at the reset level ends, and the ramp changes to the initial level. Next, the transfer control pulse output to the transfer control line 161-1 at t6 is set to H level, the charge generated in the photodiode 102 is transferred to the FD region 174, and the post-transfer pulse is set to L level at t7. The signal level is confirmed. At time t8, AD conversion is started. Similar to the AD conversion at the reset level, the output of the comparator is inverted at time t9, and the counter value D203 at this time is held. The difference A between the hold value of the reset level and the hold value of the signal level is the AD conversion result. This difference processing is performed by the digital processing circuit 112.

  Next, at t10, the selection control pulse output to the select control line 163-2 becomes H level, and the second row is selected as the read row. Further, the control pulses output to the select control line 163-1, the transfer control line 162-1 and the reset control line 161-1 return to the L level, respectively. Since the operation is the same except that the selected row changes and the pixel signal is output to the column output line 173-2 at a timing earlier than this, the description is omitted. However, the switching operation relationship of the adder circuit 120 shown in FIG. 21 is in the state shown in FIG. Therefore, the output of the column output line 173-1 is switched by switching and connected to the column amplifier and column AD converter in the same column.

  Next, the timing chart of FIG. 22B will be described. First, at time t0, the selection control pulses output to the selection control lines 163-1 and 163-2 of the row to be read are both at the H level, and both the first row and the second row are selected as the read rows. . Next, at time t1, the FD region is reset by changing the reset control pulses output to the reset control lines 161-1 and 161-2 from the H level to the L level. As a result, the voltage V173 of the column output lines 173-1 and 173-2 changes to the reset level at time t1. That is, two rows of pixel signals are read out simultaneously.

  By the switching control of the adder circuit 120 as shown in FIG. 21C, the pixel signal of the column output line 173-1 of the pixel column 130-1 and the pixel signal of the column output line 173-1 of the adjacent pixel column 130-2. Are input to the same column amplifier via a capacitor. Thereby, the pixel signal of the column output line 173-1 of the pixel column 130-1 and the pixel signal of the column output line 173-1 of the adjacent pixel column 130-2 are added. In the adjacent column, the pixel signal of the column output line 173-2 of the pixel column 130-1 and the pixel signal of the column output line 173-2 of the adjacent column 130-2 are input to the same column amplifier via a capacitor. ing. By connecting the result of addition in this way to each column AD and simultaneously performing AD conversion, two rows can be read simultaneously, and the reading speed is increased. Hereinafter, after time t2, it is the same as FIG.

  In the following description, an example in which a pixel is configured with an N-channel transistor will be described. Even when the pixel is configured by a P-channel transistor, the present invention can be applied by reversing the polarity of the voltage as compared with the case of configuring the pixel by an N-channel transistor. In addition, the AD conversion method is not limited to the present embodiment, and the connection between the adder circuit and the AD conversion device is possible even in the case of using column counters, successive ratio comparison methods, or AD conversion using sigma delta. If it can be changed, the same effect can be obtained.

(Fourth embodiment)
FIG. 23 is a circuit diagram showing the fourth embodiment. The same circuits as those in FIG. 19 in the third embodiment are denoted by the same reference numerals, and the description thereof is omitted. In this embodiment, a column amplifier is not used. Even in such a configuration, the pixel signals of the column output line 173-1 and the column output line 173-2 are sampled and held using switches and capacitors. Thereafter, averaging can be performed by averaging. Hereinafter, the driving method in the present embodiment will be described.

  Switching control when reading out the pixel signals of the column output lines 173-1 and 173-2 is the same as that in FIGS. 21A and 21B of the third embodiment, and thus the description thereof is omitted. FIG. 24 shows drive timings when the pixel signals of the column output lines 173-1 and 173-2 are added and read. Since the switches 121-1, -2 and the like move in the same manner, the timing is omitted.

  First, at time t0, the selection control pulses output to the selection control lines 163-1 and 163-2 of the row to be read are both at the H level, and both the first row and the second row are selected as the read rows. . Next, at time t1, the FD region is reset by changing the reset control pulses output to the reset control lines 161-1 and 161-2 from the H level to the L level. As a result, the voltage V173 of the column output lines 173-1 and 173-2 changes to the reset level at time t1. That is, two rows of pixel signals are read out simultaneously.

  In this case, the switches 121-1, 122-2, 124-1, and 124-2 are on. Therefore, the voltage of the column output line 173-1 in the pixel column 130-1 is input to the capacitor 125-1, and the voltage of the output line 173-2 is input to the capacitor 125-2. The capacitor 126-1 samples the voltage of the column output line 173-1 in the pixel column 130-2, and the capacitor 126-2 samples the voltage of the column output line 173-2 in the pixel column 130-2. Has been. At time t2, the switches 121 and 124 are turned off from on to sample the reset levels of the column output lines 173-1 and 173-2.

  At time t3, when the switches 123-1 and 123-2 are turned on, the capacitors 125-1 and 126-1 and the capacitors 125-2 and 126-2 are short-circuited, and the two signals are averaged. The Thereafter, at time T4, the switch 123 is turned off, and AD conversion is started from time t5. Since the operation after time t6 is the same as that of the third embodiment, the description thereof is omitted.

  Thereafter, at time t7, the transfer control pulse of the transfer control line is set to the H level and the signal is read. In this case, the sampling operation of the switches 121 and 124 is the same as the operation from t1 to t4 when the reset signal is output. . In this way, addition is performed by performing sample hold and averaging using the switch and the capacitor, and switching is performed so that the added sum pixel signal is input to an arbitrary AD conversion circuit, thereby simultaneously performing AD conversion and reading. Is speeding up.

(Fifth embodiment)
FIG. 25 is a circuit diagram showing the fifth embodiment. The solid-state imaging device of this embodiment has four column output lines 173-1, 173-2, 173-3, and 173-4 per pixel column. In the present embodiment, four rows of pixels that are continuous in the column direction in the same pixel column are connected to each of the four column output lines 173-1 to 173-4. The row selection circuit 174 can select and read out four rows simultaneously.

  Therefore, in this embodiment, two column amplifiers and column AD conversion circuits are provided for one pixel column. However, as in the third embodiment and the like, the added sum pixel signal is input to an arbitrary column. By switching to input to the AD conversion circuit, AD conversion can be performed at the same time, and reading speed can be increased.

(Sixth embodiment)
FIG. 26 is a circuit diagram showing the sixth embodiment. The adder circuit 121 of the present embodiment is a three-column adder circuit that adds the pixel signals of the three column output lines 173-1 of the pixel columns 130-1, 130-2, and 130-3 and adds them. The pixel signal is input to the AD conversion circuit 177 of the pixel column 130-1. Further, the pixel signals of the three column output lines 173-2 of the pixel columns 130-1, 130-2, and 130-3 are added, and the added pixel signal is input to the AD conversion circuit 177 of the pixel column 130-2. doing. FIG. 27 shows the connection state of the switches of the adder circuit. As in the other embodiments, switching is performed so that the added pixel signal is input to an arbitrary AD conversion circuit, so that AD conversion can be performed simultaneously and reading can be performed at high speed.

  27 (a), 27 (b), and 27 (c) each show a switching state for each mode. FIG. 27 (a) shows the pixel signal output to the column output line 173-1 as a pixel column. FIG. 27B shows a mode in which the pixel signal output to the column output line 173-2 is read out for each pixel column. In FIG. 27C, the pixel signal output to the column output line 173-1 of the pixel column 130-1 is output to the column output line 173-1 of the adjacent pixel columns 130-2 and 130-3, respectively. The pixel signal is added to the AD converter and output to the AD converter, and the pixel signal output to the column output line 173-2 of the pixel column 130-1 is added to the column output line 103- of the adjacent pixel columns 130-2 and 130-3. In this mode, the pixel signal output to 2 is added to the AD converter and output to the AD converter. With respect to the modes of FIGS. 27A and 27B, the pixel signals of the column output line 173-1 and the column output line 173-2 can be read out simultaneously, so that they can be read out at high speed.

  In the present embodiment, two adjacent columns are added. However, the embodiment is not limited to this, and the same effect can be obtained by performing addition with one column or columns separated by a plurality of columns. Further, the combination of addition columns and the weighting of addition are not limited to this, and addition without deviation of the color centroid is also conceivable.

Further, since the column AD conversion circuit of the pixel column 130-3 is not used, the power may be reduced without being operated. Alternatively, the number of column output lines may be further increased, and the speed may be increased by using the AD conversion when the pixel signals are read out simultaneously in three rows.
(Seventh embodiment)
FIG. 28 is a block diagram illustrating the overall configuration of the imaging apparatus according to the seventh embodiment. The taking lens 1010 is an optical system that forms an optical image of a subject on the image sensor 100, and zoom control, focus control, aperture control, and the like are performed by a lens driving circuit 1009. The image sensor 100 is for taking in a subject image formed by the photographing lens 1010 as an image signal, and has any of the configurations described in the first to sixth embodiments. The signal processing circuit 1003 performs various corrections on the image signal output from the image sensor 100 and compresses data. The timing generation circuit 1002 outputs a drive timing signal to the image sensor 100. The overall control / arithmetic circuit 1004 performs various calculations and controls the entire imaging apparatus. The memory circuit 1005 temporarily stores image data, and the display circuit 1006 displays various information and captured images. A recording circuit 1007 is a detachable recording circuit such as a semiconductor memory for recording or reading image data. The operation circuit 1008 electrically receives an operation on an operation member of the digital camera.

Claims (6)

A pixel portion in which a plurality of pixels each including a photoelectric conversion portion are arranged in a matrix;
Mixing means for mixing pixel signals output from a plurality of pixels in the same row;
A plurality of AD converters that are provided one for each pixel column of the pixel unit and convert the mixed pixel signal mixed by the mixing unit into a digital signal ;
A distribution unit that distributes the mixed pixel signals of each row of the pixel unit to different AD converters of the plurality of AD converters;
An image pickup device comprising: Said mixing means, the imaging device according to claim 1, characterized in that mixing the pixel signals to each other pixels of the same color. Said mixing means, the imaging device according to claim 2, characterized by mixing the pixel signals to each other of the same color pixels of different pixel columns. The image sensor according to any one of claims 1 to 3, wherein a signal distributed to the AD converter is AD-converted simultaneously. To each pixel row plurality of column output lines provided, according to any one of claims 1 to 4 pixels of the same pixel column, characterized in that it is connected to one of said plurality of column output lines Image sensor. A pixel portion in which a plurality of pixels each including a photoelectric conversion portion are arranged in a matrix;
Mixing means for mixing pixel signals output from a plurality of pixels in different columns of the same row;
A plurality of AD converters that are provided one for each pixel column of the pixel unit and convert the mixed pixel signal mixed by the mixing unit into a digital signal;
A distribution unit that distributes the same mixed pixel signal in each row of the pixel unit to a different AD converter of the plurality of AD converters;
An image pickup device comprising:

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