JP6880429B2 - 素子内蔵型印刷回路基板及びその製造方法 - Google Patents
素子内蔵型印刷回路基板及びその製造方法 Download PDFInfo
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Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/007—Manufacture or processing of a substrate for a printed circuit board supported by a temporary or sacrificial carrier
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
- H05K1/186—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or connecting to patterned circuits before or during embedding
- H05K1/187—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or connecting to patterned circuits before or during embedding the patterned circuits being prefabricated circuits, which are not yet attached to a permanent insulating substrate, e.g. on a temporary carrier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
- H01L2224/251—Disposition
- H01L2224/2518—Disposition being disposed on at least two different sides of the body, e.g. dual array
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92144—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10007—Types of components
- H05K2201/10015—Non-printed capacitor
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
図1は、本発明の一実施形態に係る素子内蔵型印刷回路基板を示す断面図であり、図2は、本発明の他の実施形態に係る素子内蔵型印刷回路基板を示す断面図である。
図5から図21は、本発明の一実施形態に係る素子内蔵型印刷回路基板100の製造方法を説明するための工程図であり、重複する構成についての説明は省略する。
7 非伝導性接着剤層
18 突出パターン(第2回路パターン)
19 埋め込みパターン(第1回路パターン)
20 第1回路層
26 ビア
30 第2回路層
40 絶縁層
50 積層体
54 コア層
56 金属層
60 キャリア部材
70 ソルダレジスト層
90 素子
91、92 めっきレジスト層
100 印刷回路基板
(a) 回路部
(b) 素子実装部
Claims (10)
- 互いに向かい合う第1面及び第2面を有する絶縁層、前記絶縁層の前記第1面に形成された第1回路層、及び前記絶縁層の前記第2面に形成された第2回路層を含む基板と、
電極部を有し、前記電極部の少なくとも一面の少なくとも一部が前記絶縁層の前記第1面を介して前記絶縁層から露出するように前記絶縁層に埋め込まれた素子と、を含み、
前記第1回路層は、前記絶縁層の内側に埋め込まれた埋め込みパターンと前記絶縁層の外側に突出した突出パターンとを含み、
前記素子は、前記素子の前記第1回路層が形成されている外側表面に形成された非伝導性接着剤層をさらに含み、
前記埋め込みパターン及び前記突出パターンのそれぞれの少なくとも一部は、前記絶縁層の前記第1面において互いに物理的に接し、
前記素子の前記電極部の少なくとも一面の少なくとも一部は、前記突出パターンと連結され、前記突出パターンの一面は、前記埋め込みパターンと接する領域で段差を有する、素子内蔵型印刷回路基板。 - 前記埋め込みパターンは、前記素子の外周に形成された回路パターンを含む請求項1に記載の素子内蔵型印刷回路基板。
- 前記素子の電極部と第2回路層との間には、電気的接続のために前記絶縁層の少なくとも一部を貫通するマイクロビアが形成される請求項1または2に記載の素子内蔵型印刷回路基板。
- 前記第1回路層と第2回路層との間には、電気的接続のために前記絶縁層の少なくとも一部を貫通する貫通ビアが形成される請求項1から3のいずれか一項に記載の素子内蔵型印刷回路基板。
- 前記素子は、受動素子である請求項1から4のいずれか一項に記載の素子内蔵型印刷回路基板。
- 一面または両面に素子実装部と回路部とを有するキャリア部材を準備するステップと、
前記キャリア部材の回路部に第1回路パターンを形成するステップと、
前記キャリア部材の素子実装部に電極部を有する素子を実装するステップと、
前記素子が実装されたキャリア部材上に前記素子を埋め込む絶縁層を積層して積層体を形成するステップと、
前記キャリア部材から前記積層体を分離するステップと、
前記積層体の一面に、第2回路パターンを含む第1回路層を形成し、他面に第2回路層を形成するステップと、
を含み、
前記素子を実装するステップは、前記素子を実装する前に、前記キャリア部材上に前記素子が実装されて接触する領域に非伝導性接着剤層を形成するステップをさらに含み、
前記電極部の少なくとも一面の少なくとも一部が前記絶縁層の第1面を介して前記絶縁層から露出し、
前記第1回路パターンは前記絶縁層の内側に埋め込まれ、
前記第2回路パターンは前記絶縁層の外側に突出し、
前記第1回路パターン及び第2回路パターンのそれぞれの少なくとも一部は、前記絶縁層の前記第1面において互いに物理的に接し、
前記素子の前記電極部の少なくとも一面の少なくとも一部は前記第2回路パターンと連結され、前記第2回路パターンの一面は、前記第1回路パターンと物理的に接する領域で段差を有する、素子内蔵型印刷回路基板の製造方法。 - 前記素子が実装されたキャリア部材上に積層される絶縁層には、前記素子を収容するためのキャビティが形成されている請求項6に記載の素子内蔵型印刷回路基板の製造方法。
- 前記第1回路パターンは、前記素子の外周に形成された回路パターンを含む請求項6または7に記載の素子内蔵型印刷回路基板の製造方法。
- 前記第1回路層及び第2回路層を形成するステップは、前記素子の電極部と第2回路層との間に電気的接続のための前記絶縁層の少なくとも一部を貫通する複数のマイクロビアと、前記第1回路層と第2回路層との間に電気的接続のための前記絶縁層の少なくとも一部を貫通する複数の貫通ビアとを形成するステップをさらに含む請求項6から8のいずれか一項に記載の素子内蔵型印刷回路基板の製造方法。
- 前記素子は、受動素子である請求項6から9のいずれか一項に記載の素子内蔵型印刷回路基板の製造方法。
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DE102014219126A1 (de) * | 2014-09-23 | 2016-03-24 | Continental Automotive Gmbh | Anordnung mit Schaltungsträger für ein elektronisches Gerät |
WO2018123969A1 (ja) * | 2016-12-27 | 2018-07-05 | 株式会社村田製作所 | 電子部品装置、高周波フロントエンド回路、及び通信装置 |
KR102425754B1 (ko) * | 2017-05-24 | 2022-07-28 | 삼성전기주식회사 | 전자부품 내장 인쇄회로기판 |
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CN112103193B (zh) | 2020-08-21 | 2021-12-03 | 珠海越亚半导体股份有限公司 | 一种嵌埋结构及制备方法、基板 |
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JP3910045B2 (ja) | 2001-11-05 | 2007-04-25 | シャープ株式会社 | 電子部品内装配線板の製造方法 |
JP4841806B2 (ja) * | 2004-02-02 | 2011-12-21 | 新光電気工業株式会社 | キャパシタ装置とそれを備えた半導体装置、及びキャパシタ装置の製造方法 |
FI20040592A (fi) * | 2004-04-27 | 2005-10-28 | Imbera Electronics Oy | Lämmön johtaminen upotetusta komponentista |
WO2006134220A1 (en) | 2005-06-16 | 2006-12-21 | Imbera Electronics Oy | Method for manufacturing a circuit board structure, and a circuit board structure |
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