JP6318914B2 - Silicon carbide semiconductor device manufacturing method and silicon carbide semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a silicon carbide semiconductor device and a silicon carbide semiconductor device.

  Conventionally, silicon has been widely used as a material constituting semiconductor devices. In recent years, adoption of silicon carbide is being promoted as a material constituting a semiconductor device.

  Silicon carbide is a wide band gap semiconductor having a band gap larger than that of silicon. By adopting silicon carbide as a material constituting the semiconductor device, the semiconductor device can have a high breakdown voltage and a low loss and can be used in a high temperature environment.

  As an application example of a silicon carbide semiconductor device, a transistor having a gate electrode such as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) or an IGBT (Insulated Gate Bipolar Transistor) has been proposed. Furthermore, from the viewpoint of low on-resistance and large current, it has been proposed that the transistor is constituted by a vertical element having a trench gate.

  For example, Japanese Patent Laying-Open No. 2000-31003 (Patent Document 1) discloses a method for forming a trench in a silicon carbide semiconductor substrate. This method includes a step of etching a surface of a silicon carbide substrate that is a (111) Si surface of β-SiC or a (0001) Si surface of α-SiC to form a recess in the surface, and particles from above the surface. A step of forming a damaged layer on at least the bottom surface of the recess by irradiating a line; and a heat treatment of the silicon carbide substrate in an oxidizing atmosphere to form at least the side surface of the recess and the bottom surface on which the damaged layer is formed. And forming a thin oxide film on the side surface of the recess and forming a thick oxide film on the bottom surface, and forming a gate electrode on the oxide film. Specifically, in the step of forming the damaged layer, ions are implanted into the substrate surface from above the substrate surface in a direction substantially perpendicular to the substrate surface. By this ion beam irradiation, an irradiation damage layer is formed on the bottom surface of the trench structure and the substrate surface near the recess.

JP 2000-31003 A

  When a voltage is applied to the gate electrode, there is a possibility that a leak current flows through the gate insulating film, particularly at the corner at the upper end of the trench opening. According to JP 2000-31003 A, a damaged layer is formed on the bottom of the trench and the main surface of the silicon carbide substrate by ion implantation. A thick oxide film can be formed on the bottom of the trench and the main surface of the silicon carbide substrate. However, the oxide film on the side wall of the trench cannot be made sufficiently thick. In order to reduce the possibility of gate leakage, it is preferable to make the thickness of the insulating film (oxide film) covering the opening corner of the trench gate as large as possible.

  An object of the present invention is to provide a method for manufacturing a silicon carbide semiconductor device having a trench gate and capable of reducing the possibility of gate leakage, and a method of manufacturing a silicon carbide semiconductor device having a trench gate and the possibility of gate leakage. It is to provide a silicon carbide semiconductor device that can be reduced.

  A method for manufacturing a silicon carbide semiconductor device according to one aspect of the present invention includes a step of preparing a silicon carbide substrate having a first main surface and a second main surface located on the opposite side of the first main surface. A silicon carbide substrate includes a drift layer having a first conductivity type, a body region having a second conductivity type different from the first conductivity type and disposed inside the drift layer, and a first conductivity type And a source region formed inside the body region and in contact with the first main surface of the silicon carbide substrate. The manufacturing method further includes a step of forming a first silicon dioxide film covering the first main surface of the silicon carbide substrate, and an opening exposing the source region by removing a part of the first silicon dioxide film. Forming a portion on the first silicon dioxide film, and subjecting the silicon carbide substrate to chemical etching through the opening of the first silicon dioxide film, the source region and the body region from the first main surface. And forming a trench having a side wall portion that reaches the drift layer. The trench has an opening having a width larger than the width of the opening of the first silicon dioxide film on the first main surface. The manufacturing method further includes a step of forming a second silicon dioxide film connected to the first silicon dioxide film on at least a side wall portion of the trench, and heat-treating the silicon carbide substrate in an inert gas atmosphere. A step of softening the first silicon dioxide film so that the silicon dioxide film covers the corner portion located on the first main surface side in the side wall portion of the trench, and by subjecting the silicon carbide substrate to thermal oxidation treatment And forming a gate insulating film in contact with the sidewall of the trench.

  A silicon carbide semiconductor device according to one embodiment of the present invention includes a silicon carbide substrate having a first main surface and a second main surface located on the opposite side of the first main surface. The silicon carbide substrate includes a drift layer having a first conductivity type, a body region having a second conductivity type different from the first conductivity type and disposed inside the drift layer, and a first conductivity type. And a source region formed inside the body region and in contact with the first main surface of the silicon carbide substrate. A trench having a side wall portion penetrating the source region and the body region from the first main surface and reaching the drift layer is formed in the silicon carbide substrate. The silicon carbide semiconductor device further includes a silicon dioxide film including a thermal oxide film that covers a corner portion located on the first main surface side in the sidewall portion of the trench, and heat that covers at least the sidewall portion of the trench and is connected to the silicon dioxide film. And a gate insulating film including an oxide film. When the direction perpendicular to the first main surface and from the first main surface toward the silicon dioxide film is the first direction, and the direction parallel to the first main surface and toward the trench is the second direction, The silicon dioxide film has a first thickness along the first direction and a second thickness along the second direction from the corner of the trench. The ratio of the second thickness to the first thickness is 50% or more.

  According to the above, a method for manufacturing a silicon carbide semiconductor device that has a trench gate and can reduce the possibility of gate leakage, and a method that has a trench gate and reduces the possibility of gate leakage. A possible silicon carbide semiconductor device can be provided.

1 is a cross sectional view schematically showing a structure of a silicon carbide semiconductor device according to a first embodiment of the present invention. It is an enlarged view of the area | region enclosed by the broken-line square shown in FIG. 3 is a flowchart schematically showing a method for manufacturing the silicon carbide semiconductor device according to the first embodiment of the present invention. It is the schematic for demonstrating the process (S10) and (S20) in the manufacturing method of the silicon carbide semiconductor device which concerns on 1st Embodiment. It is the schematic for demonstrating the process (S30) in the manufacturing method of the silicon carbide semiconductor device which concerns on 1st Embodiment. It is the schematic for demonstrating the process (S40) in the manufacturing method of the silicon carbide semiconductor device which concerns on 1st Embodiment. It is the schematic for demonstrating the process (S50) in the manufacturing method of the silicon carbide semiconductor device which concerns on 1st Embodiment. FIG. 10 is another schematic diagram for illustrating the step (S60) in the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. It is another schematic diagram for demonstrating the process (S70) in the manufacturing method of the silicon carbide semiconductor device which concerns on 1st Embodiment. It is the schematic for demonstrating the process (S80) in the manufacturing method of the silicon carbide semiconductor device which concerns on 1st Embodiment. It is the schematic for demonstrating the process (S90) in the manufacturing method of the silicon carbide semiconductor device which concerns on 1st Embodiment. It is the schematic for demonstrating the process (S100, S110) in the manufacturing method of the silicon carbide semiconductor device which concerns on 1st Embodiment. It is the schematic for demonstrating the process (S120) in the manufacturing method of the silicon carbide semiconductor device which concerns on 1st Embodiment. It is a 1st figure for demonstrating the trench formation process included in the manufacturing method of the silicon carbide semiconductor device which concerns on the 2nd Embodiment of this invention. It is a 2nd figure for demonstrating the trench formation process included in the manufacturing method of the silicon carbide semiconductor device which concerns on the 2nd Embodiment of this invention. It is a flowchart which shows the manufacturing method of the silicon carbide semiconductor device which concerns on the 3rd Embodiment of this invention. It is a figure for demonstrating the etching process (S65) included in the manufacturing method of the silicon carbide semiconductor device which concerns on 3rd Embodiment.

[Description of Embodiment of the Present Invention]
First, embodiments of the present invention will be listed and described. In this specification, the individual orientation is indicated by [], the collective orientation is indicated by <>, the individual plane is indicated by (), and the collective plane is indicated by {}. As for the negative index, “−” (bar) is attached on the number in crystallography, but in this specification, a negative sign is attached before the number. The “oxide film” means a silicon dioxide (SiO ₂ ) film.

  (1) The manufacturing method of the silicon carbide semiconductor device which concerns on 1 aspect of this invention WHEREIN: 2nd main surface (10B) located in the opposite side of 1st main surface (11A) and 1st main surface (11A). A step (S1) of preparing a silicon carbide substrate (5) having The silicon carbide substrate (5) has a drift layer (11) having a first conductivity type, a second conductivity type different from the first conductivity type, and is disposed inside the drift layer (11). A body region (13) and a source region (15) having a first conductivity type, formed inside the body region (13) and in contact with the first main surface (11A) of the silicon carbide substrate (5) Including. The manufacturing method further includes a step (S40) of forming a first silicon dioxide film (21) covering the first main surface (11A) of the silicon carbide substrate (5), and a first silicon dioxide film (21). A step (S50) of forming an opening (21a) exposing the source region (14) in the first silicon dioxide film (21) by removing a part of the first silicon dioxide film (21) By performing chemical etching on the silicon carbide substrate (5) through the opening (21a), the source region (14) and the body region (13) are penetrated from the first main surface (11A), Forming a trench (TR) having a sidewall (SW) reaching the drift layer (12) (S60). The trench (TR) has an opening having a width larger than the width of the opening (21a) of the first silicon dioxide film (21) on the first main surface (11A). The manufacturing method further includes a step (S70) of forming a second silicon dioxide film (22a) connected to the first silicon dioxide film (21) on at least the side wall (SW) of the trench (TR), and the inertness. By performing a heat treatment on the silicon carbide substrate in a gas atmosphere, the first silicon dioxide film (21) is positioned at the corner portion (11A) located on the first main surface side (11A) in the side wall (SW) of the trench (TR). A step (S80) of softening the first silicon dioxide film (21) so as to cover the UT), and a thermal oxidation treatment is performed on the silicon carbide substrate (5) to thereby form the sidewall portion (SW) of the trench (TR). Forming a gate insulating film (22) in contact with the substrate (S90).

  According to the above configuration, it is possible to manufacture a silicon carbide semiconductor device capable of reducing the possibility of gate leakage occurring at the corner at the upper end of the opening of the trench gate. By the step of softening the first silicon dioxide film, the side wall portion (corner portion) of the trench contacting the first main surface of silicon carbide is covered with the first silicon dioxide film. Thereby, the thickness of the insulating film (silicon dioxide film) covering the corners can be increased. Therefore, a silicon carbide semiconductor device with reduced possibility of gate leakage can be manufactured.

  (2) Preferably, the step of forming the first silicon dioxide film (21) includes a step of forming a thermal oxide film having a thickness of 50 nm or more and 100 nm or less by dry oxidation.

  According to the above configuration, in the step of softening the first silicon dioxide film, the corners of the trench can be covered with the silicon dioxide film having a sufficient thickness. Furthermore, this silicon dioxide film has high insulation by including a thermal oxide film. Thereby, a silicon carbide semiconductor device with reduced possibility of gate leakage can be manufactured.

  (3) Preferably, the step of softening the first silicon dioxide film (21) includes a step of heat-treating the silicon carbide substrate (5) at a temperature of 1200 ° C. or higher and 1400 ° C. or lower.

According to the said structure, a 1st silicon dioxide film can be softened more reliably.
(4) Preferably, in the step of forming the trench (TR), the edge of the opening (21a) of the first silicon dioxide film (21) is 0. 0 with respect to the corner (UT) of the trench (TR). A step of forming a trench (TR) so as to protrude in a range (L) of 1 μm or more and 0.3 μm or less.

  According to the above configuration, the corners can be covered with the first silicon dioxide film in the step of softening the first silicon dioxide film. Furthermore, the possibility that the on-resistance of the silicon carbide semiconductor device is increased can be reduced.

  (5) Preferably, in the manufacturing method, after the step of forming the trench (TR) and before the step of forming the second silicon dioxide film (22a), the first dioxide dioxide using buffered hydrofluoric acid is used. The method further includes a step of etching the surface layer portion of the silicon film (21).

  According to the above configuration, the surface of the first silicon dioxide film can be cleaned before the step of forming the second silicon dioxide film. In the step of forming the second silicon dioxide film or the step of softening the first silicon dioxide film, the amount of impurities taken into the first silicon dioxide film can be reduced. Thereby, a silicon carbide semiconductor device with reduced possibility of gate leakage can be manufactured.

  (6) Preferably, the step of forming the second silicon dioxide film (22a) includes a step of forming a thermal oxide film having a thickness of 1 nm or more by dry oxidation.

  According to the above configuration, the second silicon dioxide film can be more reliably connected to the first silicon dioxide film. By connecting the second silicon dioxide film to the first silicon dioxide film, when the heat treatment for softening the first silicon dioxide film is performed on the silicon carbide substrate, the corners are formed in the first dioxide film. It can be covered with a silicon film.

  (7) Preferably, the step of forming the second silicon dioxide film (22a) includes a step of forming a thermal oxide film at a temperature of 1000 ° C. or higher and 1200 ° C. or lower.

  According to the above configuration, the second silicon dioxide film can be more reliably connected to the first silicon dioxide film.

(8) Preferably, the chemical etching includes thermal etching using chlorine gas.
According to the above configuration, the possibility of gate leakage is reduced, and a silicon carbide semiconductor device having a low on-resistance can be manufactured.

  (9) Preferably, the step of forming the trench (TR) is a step of etching a part of the silicon carbide substrate (5) by performing reactive ion etching on the silicon carbide substrate (5) prior to the chemical etching. including.

According to the said structure, formation of the trench by chemical etching can be accelerated | stimulated.
(10) Preferably, the first main surface (11A) is a C surface.

  According to the above configuration, the possibility of gate leakage is reduced, and a silicon carbide semiconductor device having a low on-resistance can be manufactured. In this specification, the “C plane” includes a (000-1) plane and a plane having an off angle within a predetermined range (for example, within ± 8 °) with respect to the (000-1) plane. be able to.

  (11) Preferably, the side wall (SW) includes a surface inclined at an angle of 50 ° or more and 65 ° or less with respect to the C-plane.

  According to the above configuration, the possibility of gate leakage is reduced, and a silicon carbide semiconductor device having a low on-resistance can be manufactured.

(12) Preferably, the side wall (SW) includes a plane having a plane orientation {0-33-8}.
According to the above configuration, the possibility of gate leakage is reduced, and a silicon carbide semiconductor device having a low on-resistance can be manufactured.

  (13) Preferably, in the step of forming the gate insulating film (22), following the step of softening the first silicon dioxide film (21), the atmosphere gas is switched from an inert gas to an oxygen-containing gas to form silicon carbide. Including a step of subjecting the substrate (5) to a thermal oxidation treatment.

  According to the above configuration, the time required for manufacturing the silicon carbide semiconductor device can be shortened. Thereby, the productivity of the silicon carbide semiconductor device can be increased.

  (14) A silicon carbide semiconductor device according to one aspect of the present invention has a first main surface (11A) and a second main surface (10B) located on the opposite side of the first main surface (11A). A silicon substrate (5) is provided. The silicon carbide substrate (5) includes a drift layer (12) having a first conductivity type, and a body region (13 having a second conductivity type different from the first conductivity type) and disposed inside the drift layer. And a source region (14) having the first conductivity type, formed inside the body region and in contact with the first main surface of the silicon carbide substrate. A trench (TR) having a side wall (SW) extending from the first main surface (11A) through the source region (14) and the body region (13) to the drift layer (12) is formed on the silicon carbide substrate (5). ). The silicon carbide semiconductor device further includes a silicon dioxide film (21) including a thermal oxide film covering a corner (UT) located on the first main surface (11A) side in the sidewall (SW) of the trench (TR). And a gate insulating film (22) including a thermal oxide film that covers at least the sidewall (SW) of the trench (TR) and is connected to the silicon dioxide film (21). A direction perpendicular to the first main surface (11A) and going from the first main surface (11A) to the silicon dioxide film (21) is defined as a first direction (D1), and is parallel to the first main surface (11A). When the direction toward the trench (TR) is the second direction (D2), the silicon dioxide film (21) has the first thickness (T1) along the first direction (D1) and the trench (TR). And a second thickness (T2) along the second direction (D2) from the corner (UT). The ratio of the second thickness (T2) to the first thickness (T1) is 50% or more.

  According to the said structure, the side wall part (corner | corner part) of the trench which contacts the 1st main surface of silicon carbide is covered with a 1st silicon dioxide film. Thereby, the thickness of the insulating film (silicon dioxide film) covering the corners can be increased. Therefore, a silicon carbide semiconductor device capable of reducing the possibility of gate leakage can be realized.

(15) Preferably, the ratio is 100% or less.
According to the above configuration, the possibility of gate leakage occurring in the silicon carbide semiconductor device can be further reduced.

  (16) Preferably, the first main surface (11A) is a C surface. The side wall portion (SW) includes a surface inclined at an angle of 50 ° or more and 65 ° or less with respect to the C-plane.

  According to the above configuration, the possibility of gate leakage is reduced, and a silicon carbide semiconductor device having a low on-resistance can be realized. Since “C-plane” is defined below as described above, the description regarding “C-plane” will not be repeated.

(17) Preferably, the side wall includes a surface having a plane orientation {0-33-8}.
A possibility of gate leakage is reduced, and a silicon carbide semiconductor device having a low on-resistance can be realized.

(18) Preferably, the second thickness is not less than 50 nm and not more than 100 nm.
According to the above configuration, the possibility of gate leakage occurring in the silicon carbide semiconductor device having a trench gate can be further reduced.

  (19) Preferably, a direction different from the first direction (D1) is defined as a third direction (D3), and when the third direction (D3) matches the second direction (D2), When the angle formed by the third direction (D3) with respect to the first direction (D1) is defined as 90 °, the silicon dioxide film (21) has an extension direction of the first main surface (11A) and the trench direction. It has a third thickness (T3) passing through a position where the extending direction of the side wall (SW) intersects and along the third direction (D3). The ratio of the third thickness (T3) to the first thickness (T1) is 50% or more until the angle formed by the third direction (D3) with respect to the first direction (D1) is at least 95 °.

  According to the above configuration, the possibility of gate leakage occurring in the silicon carbide semiconductor device having a trench gate can be further reduced. The position where the extending direction of the first main surface and the extending direction of the sidewall portion of the trench intersect may be a position within the first main surface, and the first main surface and the sidewall portion of the trench. It may be a position away from both. For example, when the corner portion of the trench has a curvature, the position where the extending direction of the first main surface and the extending direction of the side wall portion of the trench intersect may be a position in the opening of the trench.

[Details of the embodiment of the present invention]
Next, specific examples of embodiments of the present invention will be described with reference to the drawings. In the following drawings, the same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.

<First Embodiment>
FIG. 1 is a cross sectional view schematically showing a structure of a silicon carbide semiconductor device according to the first embodiment of the present invention. Referring to FIG. 1, MOSFET 1 is a silicon carbide semiconductor device according to the first embodiment of the present invention. MOSFET 1 includes a silicon carbide substrate 5. Silicon carbide substrate 5 has a main surface 11A (first main surface) and a main surface 10B (second main surface). Main surface 10B is located on the opposite side of main surface 11A.

  Silicon carbide substrate 5 includes a silicon carbide single crystal substrate 10 and a drift layer 11. Silicon carbide single crystal substrate 10 is made of, for example, a polytype 4H hexagonal silicon carbide single crystal. Silicon carbide single crystal substrate 10 has a thickness of, for example, 700 μm or less, and preferably 500 μm or less.

  Silicon carbide single crystal substrate 10 has two main surfaces 10A and 10B located on opposite sides. Main surface 10 </ b> B corresponds to a second main surface of silicon carbide substrate 5. For example, the main surfaces 10A and 10B can be parallel to each other.

  The main surface 10A is a “C surface”. In general, the “C plane” is defined as a plane of a silicon carbide substrate whose outermost surface atoms are carbon atoms. In the present specification, the C plane may include not only the (000-1) plane but also a plane off by 8 ° or less from the (000-1) plane. In other words, the C plane is a plane having an off angle of −8 ° or more and 8 ° or less with respect to the (000-1) plane.

  The main surface 10B is a “Si surface”. In this specification, the “Si plane” may include not only the (0001) plane but also a plane off by about 8 ° or less from the (0001) plane. In other words, the Si surface is a surface having an off angle of −8 ° to 8 ° with respect to the (0001) plane.

  Silicon carbide single crystal substrate 10 has the first conductivity type. In this embodiment, the first conductivity type is n-type. Specifically, silicon carbide single crystal substrate 10 includes an n-type impurity (donor) such as nitrogen (N).

  Drift layer 11 is arranged on main surface 10 </ b> A of silicon carbide single crystal substrate 10. Drift layer 11 has a main surface 11A. Main surface 11 </ b> A corresponds to a first main surface of silicon carbide substrate 5. Specifically, the main surface 11A is a C surface that complies with the above definition.

  Drift layer 11 includes a drift region 12, a body region 13, a source region 14, and a contact region 15.

Drift region 12 has the first conductivity type (n-type). The concentration of n-type impurities in drift region 12 is lower than the concentration of n-type impurities in silicon carbide single crystal substrate 10. In one embodiment, the concentration of the n-type impurity in the drift region 12 is about 5.0 × 10 ¹⁵ cm ⁻³ .

Body region 13 is arranged inside drift layer 11 and has the second conductivity type. The second conductivity type is different from the first conductivity type. In other words, the second conductivity type is opposite to the first conductivity type. In this embodiment, the second conductivity type is p-type. Body region 13 includes a p-type impurity (acceptor) such as Al (aluminum) or B (boron). The concentration of the p-type impurity contained in body region 13 is, for example, about 1 × 10 ¹⁷ cm ⁻³ . A region other than body region 13 in drift layer 11 corresponds to drift region 12.

  Source region 14 is arranged inside body region 13 and is in contact with the first main surface (main surface 11 </ b> A) of silicon carbide substrate 5. Source region 14 is separated from drift region 12 by body region 13. Note that the source region 14 may contact the contact region 15.

Source region 14 has the first conductivity type (n-type). Specifically, the source region 14 includes an n-type impurity such as P (phosphorus). The n-type impurity concentration of the source region 14 is higher than the n-type impurity concentration of the drift region 12. In one embodiment, the concentration of the n-type impurity contained in the source region 14 is, for example, 1 × 10 ¹⁹ cm ⁻³ .

  Contact region 15 is arranged inside body region 13 and is in contact with the first main surface (main surface 11 </ b> A) of silicon carbide substrate 5. As described above, the contact region 15 may be in contact with the source region 14. Contact region 15 has the second conductivity type (p-type). Specifically, contact region 15 includes a p-type impurity such as aluminum or boron. Contact region 15 has a p-type impurity concentration higher than that of body region 13.

  In this embodiment, trench TR is formed in silicon carbide substrate 5. Trench TR opens to main surface 11 </ b> A side of silicon carbide substrate 5. Trench TR has side wall part SW and bottom part BW.

  Sidewall portion SW passes through source region 14 and body region 13 and reaches drift region 12 from main surface 11A. Sidewall portion SW can include a surface having an off angle of 50 ° or more and 65 ° or less with respect to the C surface of silicon carbide. As the measurement of the off angle, for example, a method using general X-ray diffraction can be used.

  Sidewall part SW may include a first surface having a plane orientation {0-33-8}. Preferably, the side wall part SW includes the first surface microscopically, and may further include the second surface having the plane orientation {0-11-1} microscopically. More preferably, the first surface and the second surface can include a composite surface having a plane orientation {0-11-2}. The “surface having an off angle of 50 ° or more and 65 ° or less with respect to the C surface” may include the first surface and the second surface. The resistance (channel resistance) in the channel region CH can be reduced by the side wall portion SW including the above surface. Therefore, a silicon carbide semiconductor device with reduced on-resistance can be realized.

  Bottom BW is connected to side wall SW. Bottom portion BW may have a surface parallel to main surface 11 </ b> A of silicon carbide substrate 5. Sidewall portion SW includes a surface inclined with respect to main surface 11 </ b> A of silicon carbide substrate 5. Accordingly, the bottom BW may be omitted depending on the size of the opening of the trench TR.

  MOSFET 1 further includes a protective insulating film 21, a gate insulating film 22, a gate electrode 30, a source electrode 40, an interlayer insulating film 50, a source wiring 60, and a drain electrode 70.

  FIG. 2 is an enlarged view of a region surrounded by a broken-line square shown in FIG. Referring to FIGS. 1 and 2, protective insulating film 21 covers main surface 11 </ b> A of silicon carbide substrate 5 and covers corner portion UT of trench TR. Corner portion UT is located on the upper end side (main surface 11A side) of side wall portion SW.

The protective insulating film 21 is a silicon dioxide (SiO ₂ ) film. More specifically, the protective insulating film 21 (first silicon dioxide film) is a thermal oxide film. Protective insulating film 21 is formed by thermally oxidizing the surface layer portion on the main surface 11A side of drift layer 11 (silicon carbide substrate 5).

  Gate insulating film 22 is formed in contact with sidewall portion SW and bottom portion BW of trench TR. The gate insulating film 22 is a silicon dioxide film. Specifically, gate insulating film 22 is formed by thermally oxidizing the surface layer portion of drift layer 11 (more specifically, sidewall portion SW and bottom portion BW of trench TR).

  The direction D1 is a direction perpendicular to the main surface 11A and from the main surface 11A toward the protective insulating film 21. The thickness T1 indicates the thickness of the protective insulating film 21 along the direction D1. In one embodiment, the thickness T1 is 50 nm or more. Preferably, the thickness T1 is 50 nm or more and 100 nm or less.

  The direction D2 is a direction parallel to the main surface 11A and toward the trench TR. The thickness T2 indicates the thickness of the protective insulating film 21 along the direction D2 from the corner portion UT of the trench TR. The ratio r is defined as the ratio of the thickness T2 to the thickness T1. That is, r = T2 / T1. In this embodiment, the ratio r (= T2 / T1) is 50% or more (r ≧ 0.5). Preferably, the ratio r is 50% or more and 100% or less. Accordingly, the thickness T2 is determined so as to satisfy the range of the ratio r. In one embodiment, the thickness T2 is not less than 50 nm and not more than 100 nm, preferably not less than 60 nm and not more than 80 nm.

  Furthermore, the direction D3 is defined as a direction different from the direction D1. In order to describe the direction D3, an angle formed by the direction D3 with respect to the direction D1 is used. When the direction D3 coincides with the direction D2, this angle is expressed as 90 °. The direction D1 can be rephrased as a direction of 0 °.

  Thickness T3 is a thickness along direction D3, passing through a position where the extending direction of main surface 11A intersects with the extending direction of sidewall portion SW of trench TR. In FIG. 2, the position where the extending direction of the main surface 11A intersects with the extending direction of the sidewall portion SW of the trench TR corresponds to the corner portion UT of the trench TR. In this embodiment, the ratio of the thickness T3 to the thickness T1 is 50% or more until the angle formed by the direction D3 with respect to the direction D1 is at least 95 °.

  The gate electrode 30 is disposed so as to contact the gate insulating film 22 and the protective insulating film 21. The gate electrode 30 is made of a conductor such as polysilicon (p-Si) doped with impurities or molybdenum (Mo).

  The interlayer insulating film 50 covers the gate insulating film 22 and the protective insulating film 21 and electrically insulates the gate electrode 30 from the source electrode 40 and the source wiring 60. Interlayer insulating film 50 is made of, for example, a silicon dioxide film. For example, a deposited oxide film can be applied to the interlayer insulating film 50.

Source electrode 40 is arranged on main surface 11 </ b> A of silicon carbide substrate 5 so as to be in contact with source region 14 and contact region 15. Source electrode 40 is electrically connected to source region 14. The source electrode 40 is preferably made of a material that can make ohmic contact with the source region 14. The source electrode 40, for example Ni _x Si _y (nickel silicide), Ti _x Si _y (titanium silicide), and the like Al _x Si _y (aluminum silicide) and Ti _x Al _y Si _z (titanium aluminum silicide).

  Drain electrode 70 is arranged in contact with main surface 10B (second main surface) of silicon carbide substrate 5 (silicon carbide single crystal substrate 10). Drain electrode 70 is electrically connected to silicon carbide single crystal substrate 10. Drain electrode 70 is preferably made of a material capable of making ohmic contact with silicon carbide single crystal substrate 10. For example, the drain electrode 70 may be made of the same material as the source electrode 40.

  The source wiring 60 is disposed so as to be in contact with the source electrode 40. Thereby, the source wiring 60 is electrically connected to the source electrode 40. Further, the source wiring 60 is electrically connected to the source region 14 through the source electrode 40. The source wiring 60 is made of a conductor (for example, aluminum).

  As shown in FIGS. 1 and 2, MOSFET 1 is an n-type MOSFET. A low voltage (for example, 0 V) is applied to the source region 14, the contact region 15, and the body region 13 through the source wiring 60 and the source electrode 40. When the MOSFET 1 is turned on, a voltage higher than the voltage of the source region 14 is applied to the gate electrode 30.

  When the voltage applied to the gate electrode 30 is less than the threshold voltage (the gate voltage is positive), a channel is formed in the body region 13 even if a voltage is applied between the source electrode 40 and the drain electrode 70. Not. Therefore, MOSFET 1 is in an off state (non-conducting state). On the other hand, when a voltage higher than the threshold voltage is applied to the gate electrode 30, a channel is formed in the body region 13 in a region near the gate insulating film 22. In FIGS. 1 and 2, a region where a channel is formed is shown as a channel region CH.

  As described above, main surface 11A of silicon carbide substrate 5 is the C surface. By forming the trench TR on this surface, the on-resistance of the MOSFET 1 can be reduced. Further, sidewall portion SW of trench TR includes a surface inclined at an angle of 50 ° to 65 ° with respect to the C surface. More preferably, sidewall portion SW includes a surface having a plane orientation {0-33-8}. Therefore, the on-resistance of MOSFET 1 can be further reduced.

  When the MOSFET 1 is turned on, a voltage difference is generated between the gate electrode 30 and the source region 14 (or body region 13). An insulating film (the protective insulating film 21 and the gate insulating film 22) exists between the gate electrode 30 and the source region 14.

  A corner portion UT is present on the upper end side (main surface 11A side) of trench TR. Electric field concentration tends to occur at the corner portion UT on the upper end side of the trench TR. In this embodiment, the corner UT on the upper end side of the trench TR is covered with the protective insulating film 21. Regarding the thickness of the protective insulating film 21 at the corner UT on the upper end side of the trench TR, the ratio r (= T2 / T1) when the angle is 90 ° is 50% or more. More specifically, the thickness T2 is 50 nm or more and 100 nm or less. Furthermore, the ratio of the thickness T3 to the thickness T1 is 50% or more until the angle formed by the direction D3 with respect to the direction D1 is at least + 95 °. Thereby, the thickness of the insulating film covering the corner portion UT on the upper end side of the trench TR can be increased. Therefore, the possibility of gate leakage can be reduced.

  Furthermore, according to this embodiment, sidewall portion SW of trench TR forms an obtuse angle with respect to the first main surface (main surface 11A) of silicon carbide substrate 5. Compared with the case where side wall part SW makes a right angle with respect to main surface 11A, the electric field strength in corner | angular part UT of trench TR can be weakened. This can reduce the possibility of gate leakage. Furthermore, the protective insulating film 21 can be easily covered with the corner portion UT of the trench TR. Also from this point, the possibility of gate leakage can be reduced.

  On the other hand, the thicker the gate insulating film 22 on the channel region CH, the higher the threshold voltage of the MOSFET 1. According to this embodiment, the range covered with the protective insulating film 21 is limited to the source region 14 in the sidewall portion SW of the trench TR. By preventing the body region 13 from being covered with the protective insulating film 21, the gate insulating film 22 on the channel region CH can have a thickness suitable for the operation of the MOSFET 1. As a result, it is possible to avoid an increase in the on-resistance of the MOSFET 1.

  Next, a method for manufacturing the silicon carbide semiconductor device according to this embodiment will be described. FIG. 3 is a flowchart schematically showing a method for manufacturing the silicon carbide semiconductor device according to the first embodiment of the present invention.

  Referring to FIGS. 3 and 4, first, a silicon carbide substrate preparation step is performed as a step (S10). In this step (S10), n-type silicon carbide single crystal substrate 10 is prepared by cutting an ingot (not shown) made of, for example, 4H—SiC and performing a polishing process or the like.

Next, an epitaxial growth step is performed as a step (S20). In this step (S20), drift layer 11 is formed on main surface 10A of silicon carbide single crystal substrate 10 by epitaxial growth using, for example, a CVD (Chemical Vapor Deposition) method. In one embodiment, a carrier gas containing hydrogen (H ₂ ) and a source gas containing monosilane (SiH ₄ ), propane (C ₃ H ₈ ), nitrogen (N ₂ ), and the like on silicon carbide single crystal substrate 10 Is supplied, and silicon carbide single crystal substrate 10 is heated to, for example, about 1500 ° C. to 1700 ° C. The thickness of the drift layer 11 (epitaxial layer) is not particularly limited, but is an appropriate value (for example, about 15 μm) within a range of about 10 μm to about 35 μm, for example. Through steps S10 and S20, silicon carbide substrate 5 is prepared. Silicon carbide substrate 5 has a main surface 11A and a main surface 10B. The main surface 11A (first main surface) corresponds to the C surface.

  Referring to FIGS. 3 and 5, next, an ion implantation step is performed as a step (S30). In this step (S30), for example, aluminum (Al) ions are implanted into main layer 11A of silicon carbide substrate 5 into drift layer 11. As a result, body region 13 having a p-type conductivity is formed in drift layer 11. The thickness of body region 13 (the aluminum ion implantation depth) is, for example, not less than 0.7 μm and not more than 0.8 μm.

  Next, for example, phosphorus (P) ions are implanted into the body region 13. Phosphorus ions are implanted into the drift layer 11 shallower than aluminum ions. As a result, the source region 14 having n type conductivity is formed in the body region 13.

  Subsequently, for example, aluminum (Al) ions are selectively implanted into the body region 13 at an implantation depth similar to that of the phosphorus ions. As a result, a contact region 15 having a p-type conductivity is formed in the body region 14. In the drift layer 11, a region where none of the body region 13, the source region 14, and the contact region 15 is formed becomes the drift region 12. Source region 14 is separated from drift region 12 by body region 13.

  Although not shown in FIG. 5, for selective ion implantation into silicon carbide substrate 5, for example, a silicon dioxide film is formed as a mask on main surface 11 </ b> A of silicon carbide substrate 5. By the photolithography technique and the etching technique, an opening for exposing a region where the contact region 15 is to be formed is formed in the silicon dioxide film. After the ion implantation is completed, the mask (silicon dioxide film) is removed. Thereafter, silicon carbide substrate 5 is heated in an inert gas atmosphere. By this heating step (annealing), impurity ions introduced into silicon carbide substrate 5 can be activated.

  In FIG. 3, the above-described steps S10, S20, and S30 are collectively shown as a step S1. That is, in the step (S1), the drift layer 11 having n-type, the body region 13 having p-type and disposed inside the drift layer 11, and the n-type drift layer 11 are disposed inside the body region 13. This corresponds to the step of preparing silicon carbide substrate 5 formed and including source region 14 in contact with main surface 11 </ b> A of silicon carbide substrate 5.

  Referring to FIGS. 3 and 6, a mask oxide film forming step is performed as a step (S40). In this step (S40), a mask oxide film is formed on main surface 11A of silicon carbide substrate 5. In one embodiment, a thermal oxide film is formed on main surface 11A of silicon carbide substrate 5 by dry oxidation in an oxygen-containing gas atmosphere. This thermal oxide film is used as a mask oxide film in a trench formation step (S60) to be described later, and thereafter used as a protective insulating film 21 of MOSFET 1 (silicon carbide semiconductor device). Therefore, in FIG. 6 and the drawings described later, the mask oxide film is indicated by the same reference numeral (21) as the protective insulating film. By employing a thermal oxide film as the protective insulating film 21, the insulating property of the protective insulating film 21 can be improved. Thereby, a silicon carbide semiconductor device with reduced possibility of gate leakage can be manufactured.

  In one embodiment, the thermal oxide film formed as the mask oxide film (and the protective insulating film 21) has a thickness of 50 nm or more and 100 nm or less. If the thickness of the thermal oxide film is less than 50 nm, the portion of the oxide film that covers the corner portion UT of the trench TR tends to be thin. For this reason, in the MOSFET 1, there is a high possibility that a gate leak occurs in the corner portion UT. On the other hand, when the thickness of the thermal oxide film is larger than 100 nm, the time required for forming the thermal oxide film having the thickness becomes longer. In the corner portion UT, in order to reduce the possibility of gate leakage, the oxide film covering the corner portion UT is preferably as dense as possible. For this purpose, it is preferable to use dry oxidation for forming a thermal oxide film. From the viewpoint of both the thickness of the insulating film (thermal oxide film) covering the corner portion UT and the time for forming the insulating film having the thickness, the heat formed as the mask oxide film (and the protective insulating film 21). The thickness of the oxide film is 50 nm or more and 100 nm or less.

  The mask oxide film is not limited to the thermal oxide film. Instead of the thermal oxide film, a deposited oxide film can be applied to the mask oxide film (silicon dioxide film). In this case, in order to reduce the possibility of gate leakage occurring in the corner portion UT of trench TR, the deposited oxide film is preferably an oxide film to which no impurity is added (non-doped).

  Referring to FIGS. 3 and 7, an opening forming step is performed as a step (S50). In this step (S50), an opening 21a is formed in the mask oxide film (protective insulating film 21) by a photolithography process and an etching process (both not shown). The opening 21a exposes a region in the main surface 11A where a trench is to be formed.

With reference to FIG. 3 and FIG. 8, a trench formation process is implemented as process (S60). In this step (S60), chemical etching is performed on silicon carbide substrate 5. In one embodiment, the chemical etching is thermal etching using a halogen-based gas (for example, chlorine (Cl ₂ ) gas). Trench TR having an opening on the main surface 11A side is formed in drift layer 11 by the trench formation step.

  Trench TR has side wall part SW and bottom part BW. Sidewall portion SW penetrates source region 14 and body region 13 from main surface 11 </ b> A and reaches drift region 12. Further, the side wall portion SW forms an obtuse angle with respect to the main surface 11A. In other words, the opening diameter of trench TR increases as it goes from bottom BW to main surface 11A. By forming sidewall portion SW by thermal etching, sidewall portion SW has a surface having an off angle of 50 ° or more and 65 ° or less with respect to the C-plane of silicon carbide (surface orientation {0-33 as one specific example). Surface having −8}. By forming the sidewall portion SW including such a surface, the resistance (channel resistance) in the channel region CH can be reduced.

  On main surface 11A, the edge of opening 21a of the mask oxide film protrudes toward the inside of the opening of trench TR rather than the edge of the opening of trench TR (corresponding to corner UT). In other words, in the main surface 11A, the width of the opening of the trench TR is larger than the width of the opening 21a of the mask oxide film.

  The length L indicates the length from the edge (corner portion UT) of the opening of the trench TR to the edge of the opening 21a of the mask oxide film. In one embodiment, the length L is not less than 0.1 μm and not more than 0.3 μm.

  Referring to FIGS. 3 and 9, a buffer oxide film forming step is performed as a step (S70). In this step (S70), first, cleaning (in one example, RCA cleaning) is performed on silicon carbide substrate 5 on which the mask oxide film (protective insulating film 21) is formed. Thereby, particles, metal ions, and the like attached to the surface of trench TR or the surface of mask oxide film (protective insulating film 21) are removed.

  Next, buffer oxide film 22a is formed to cover side wall portion SW and bottom portion BW of trench TR. In one embodiment, the buffer oxide film 22a having a thickness of 1 nm or more is formed by dry oxidation in an oxygen-containing gas atmosphere at a temperature of 1000 ° C. or more and 1200 ° C. or less.

  Similar to the side wall portion SW and the bottom portion BW of the trench TR, an oxide film is formed by combining silicon and oxygen in the surface layer portion of the silicon carbide substrate 5 located below the mask oxide film (protective insulating film 21). . Therefore, the buffer oxide film 22a can be connected to the mask oxide film (protective insulating film 21). In other words, in the step (S70), the buffer oxide film 22a integrated with the mask oxide film (protective insulating film 21) is formed.

  Referring to FIGS. 3 and 10, a mask oxide film softening step is performed as a step (S80). In this step, silicon carbide substrate 5 is heat-treated at a temperature of about 1200 ° C. or higher and about 1300 ° C. or lower, for example, in an inert gas atmosphere such as argon (Ar). Thereby, the mask oxide film (protective insulating film 21) is softened. The portion of the mask oxide film protruding from the upper corner portion UT of the trench TR hangs down from the corner portion UT to the sidewall portion SW of the trench TR, and as a result, comes into contact with the sidewall portion SW. As a result, the protective insulating film 21 covering the upper corner portion UT of the trench TR is formed.

  Without the buffer oxide film 22a, when the silicon carbide substrate 5 is heat-treated in an inert gas atmosphere, the portion of the mask oxide film that protrudes from the corner UT at the upper end of the trench TR contracts. There is a possibility that the mask oxide film is detached from main surface 11A of substrate 5 (interface between mask oxide film and silicon carbide substrate 5). Therefore, it may be difficult to cover the corner portion UT of the trench TR with the protective insulating film 21. On the other hand, in this embodiment, in step (S70), the buffer oxide film 22a is formed so as to be connected to the mask oxide film (protective insulating film 21). Thereby, in the step (S80), the mask oxide film can be softened while suppressing the shrinkage of the mask oxide film. Therefore, the corner portion UT of the trench TR can be covered with the mask oxide film (protective insulating film 21).

  When the length L shown in FIG. 8 is smaller than 0.1 μm, it is difficult to cover the upper corner portion UT of the trench TR with a mask oxide film. On the other hand, when the length L exceeds 0.3 μm, the entire upper corner portion UT of the trench TR can be covered with the mask oxide film (protective insulating film 21). However, the softened mask oxide film may cover the channel region CH. As a result, the thickness of the gate insulating film 22 may be increased. As the thickness of the gate insulating film 22 on the channel region CH is larger, the threshold voltage of the MOSFET 1 is higher.

  In the side wall portion SW, the boundary between the source region 14 and the body region 13 is at a position separated from the main surface 11A by about 0.3 μm or more. Therefore, if the length L shown in FIG. 8 is 0.3 μm or less, it is possible to prevent the softened mask oxide film from covering the source region 14 while covering the corner portion UT of the trench TR. Thereby, it can suppress that ON resistance of MOSFET1 increases. From the above viewpoint, the length L shown in FIG. 8 is preferably 0.1 μm or more and 0.3 μm or less.

  Further, in the step (S80), the mask oxide film is softened at a temperature of about 1200 ° C. to about 1400 ° C. and in an inert gas atmosphere. When the temperature is lower than 1200 ° C., it is difficult to soften the mask oxide film. On the other hand, when the ambient temperature exceeds 1400 ° C., for example, there is a possibility that the performance of the heating furnace that heats silicon carbide substrate 5 may be reduced or the life of the heating furnace may be shortened. Therefore, it is preferable to soften the mask oxide film at a temperature of about 1200 ° C. or more and about 1400 ° C. or less.

  Referring to FIG. 3 and FIG. 11, a gate insulating film forming step is performed as a step (S90). In this step, the surface layer portion of silicon carbide substrate 5 is oxidized by dry oxidation, for example, in an oxygen-containing gas atmosphere. Specifically, silicon carbide substrate 5 on which protective insulating film 21 and buffer oxide film 22a are formed at a temperature of about 1100 ° C. to 1400 ° C. (for example, 1300 ° C.) in an oxygen-containing gas atmosphere. Retained.

  In trench TR, the surface layer portion of silicon carbide substrate 5 located below buffer oxide film 22a is oxidized. The gate insulating film 22 is formed by the growth of the buffer oxide film 22a. Therefore, the buffer oxide film 22 a can be a part of the gate insulating film 22. Gate insulating film 22 is in contact with drift region 12, body region 13, and source region 14 in sidewall portion SW of trench TR. The thickness of the gate insulating film 22 is, for example, about 50 nm.

  In one embodiment, the mask oxide film softening step (S80) and the gate insulating film formation step (S90) are performed continuously. Specifically, silicon carbide substrate 5 is placed in a heating furnace, and a mask oxide film softening step (S80) is performed. The atmosphere gas is switched from an inert gas to an oxygen-containing gas while the silicon carbide substrate 5 is held inside the heating furnace. Subsequently, a gate insulating film forming step (S90) is performed. Thereby, the time required for manufacturing MOSFET 1 (silicon carbide semiconductor device) can be shortened. Therefore, the productivity of MOSFET 1 (silicon carbide semiconductor device) can be increased.

  Referring to FIGS. 3 and 12, a gate electrode forming step is performed as a step (S100). In this step (S100), the gate electrode 30 is formed so as to be in contact with the protective insulating film 21 and the gate insulating film 22, for example, by LP (Low Pressure) -CVD.

  Next, an interlayer insulation film formation process is implemented as process (S110). In this step (S110), an interlayer insulating film 50 made of silicon dioxide is formed so as to cover gate electrode 30, protective insulating film 21, and gate insulating film 22, for example, by P (Plasma) -CVD.

  With reference to FIG. 3 and FIG. 13, an ohmic electrode formation process is implemented as process (S120). In this step (S120), first, the interlayer insulating film 50, the protective insulating film 21, and the gate insulating film 22 are removed in a region where the source electrode 40 is to be formed. Thereby, a region where the source region 14 and the contact region 15 are exposed is formed. A metal film made of, for example, nickel (Ni) is formed on the region. On the other hand, a metal film made of nickel, for example, is formed on main surface 10B (second main surface) of silicon carbide substrate 5 (silicon carbide single crystal substrate 10).

  The silicon carbide substrate 5 is heated to silicide at least part of the metal film. Thereby, the source electrode 40 and the drain electrode 70 are formed.

  With reference to FIG. 1 and FIG. 3, a wiring formation process is implemented as process (S130). In this step (S130), the source wiring 60 made of a conductor such as aluminum (Al) is formed on the source electrode 40 by, for example, vapor deposition. By performing steps S10 to S130 described above, the silicon carbide semiconductor device (MOSFET 1) according to the first embodiment can be manufactured.

  As described above, in the method for manufacturing the silicon carbide semiconductor device according to the first embodiment, protective insulating film 21 is formed so as to cover corner UT at the upper end of trench TR by the mask oxide film softening process. The corner portion UT of the trench TR where electric field concentration is likely to occur can be covered with the protective insulating film 21 having a sufficient thickness. Therefore, the possibility of gate leakage can be reduced. On the other hand, the thickness of the gate insulating film 22 on the channel region CH can be maintained at a thickness necessary for the operation of the MOSFET 1 (a thickness for obtaining a desired threshold voltage). Thereby, an increase in on-resistance can be suppressed.

<Second Embodiment>
The method for manufacturing the silicon carbide semiconductor device according to the second embodiment is basically the same as the manufacturing method according to the first embodiment. The method for manufacturing the silicon carbide semiconductor device according to the second embodiment differs from that of the first embodiment in the step of forming trench TR. Specifically, the step of forming trench TR (step S60 shown in FIG. 3) includes a step of etching part of silicon carbide substrate 5 by performing reactive ion etching (RIE) on silicon carbide substrate 5; Subsequent to the step, a step of chemically etching silicon carbide substrate 5 is included.

  The configuration of the silicon carbide semiconductor device according to the second embodiment is the same as the configuration of the silicon carbide semiconductor device according to the first embodiment. Therefore, since the structure of the silicon carbide semiconductor device which concerns on 2nd Embodiment is shown by FIG. 1 etc., detailed description is not repeated.

FIG. 14 is a first diagram for illustrating a trench formation step included in the method for manufacturing the silicon carbide semiconductor device according to the second embodiment of the present invention. Referring to FIG. 14, using mask oxide film (protective insulating film 21) as a hard mask, the portion of silicon carbide substrate 5 exposed in the opening of the mask oxide film is removed by reactive ion etching (RIE). For reactive ion etching, inductively coupled plasma (ICP) RIE can be employed. Specifically, for example, silicon carbide substrate 5 can be etched by ICP-RIE using SF ₆ or a mixed gas of SF ₆ and O ₂ as a reaction gas. By such etching, a groove whose side wall is substantially perpendicular to main surface 11A of silicon carbide substrate 5 can be formed.

  The etching depth d from the main surface 11A is a depth for making the dimension of the opening of the trench TR formed in the subsequent process (chemical etching) a desired dimension. The “desired dimension” is a value at which the length L shown in FIGS. 8 and 15 is in the range of 0.1 μm to 0.3 μm.

  FIG. 15 is a second diagram for illustrating a trench formation step included in the method for manufacturing the silicon carbide semiconductor device according to the second embodiment of the present invention. Referring to FIG. 15, chemical etching is performed on silicon carbide substrate 5. Since this process is the same as the process according to the first embodiment, detailed description thereof will not be repeated.

  According to the second embodiment, in the step of forming the trench, reactive ion etching is performed on the silicon carbide substrate prior to chemical etching. Thereby, formation of trench TR can be promoted. Therefore, the silicon carbide semiconductor device (MOSFET 1) according to the embodiment of the present invention can be stably manufactured.

<Third Embodiment>
FIG. 16 is a flowchart showing a method for manufacturing the silicon carbide semiconductor device according to the third embodiment of the present invention. 3 and 16, in the method for manufacturing the silicon carbide semiconductor device according to the third embodiment, the etching step (S65) is performed between the trench formation step (S60) and the buffer oxide film step (S70). To be added. More specifically, in the method for manufacturing the silicon carbide semiconductor device according to the third embodiment, after the step of forming trench TR (S60) and before the step of forming buffer oxide film 22a (S70). And a step of etching the surface of the mask oxide film using buffered hydrofluoric acid (BHF). In this respect, the method for manufacturing the silicon carbide semiconductor device according to the third embodiment is different from the manufacturing method according to the first embodiment.

  The configuration of the silicon carbide semiconductor device according to the third embodiment is the same as the configuration of the silicon carbide semiconductor device according to the first embodiment. Therefore, since the structure of the silicon carbide semiconductor device which concerns on 3rd Embodiment is shown by FIG. 1 etc., detailed description is not repeated.

  FIG. 17 is a diagram for illustrating an etching step (S65) included in the method for manufacturing the silicon carbide semiconductor device according to the third embodiment. Referring to FIGS. 16 and 17, the surface layer portion (shown by a broken line) of the mask oxide film (protective insulating film 21) is etched by buffered hydrofluoric acid.

As the buffered hydrofluoric acid, for example, a mixed liquid of hydrofluoric acid (HF) and ammonium fluoride (NH ₄ F) can be used. The weight percent (wt%) and volume ratio (ratio of ammonium fluoride to hydrofluoric acid volume) of HF and NH ₄ F are not particularly limited. The etching time is determined so that the thickness of the mask oxide film (protective insulating film 21) after etching is about 50 nm to about 100 nm.

  For example, when the buffer oxide film forming step (S70), the mask oxide film softening step (S80), and the gate insulating film forming step (S90) are performed while the metal ions remain attached to the surface of the mask oxide film, the protective insulating film 21 Metal ions are easily taken in. As the amount of metal ions taken into the protective insulating film 21 increases, the possibility of gate leakage increases. According to the third embodiment, the surface of the mask oxide film is etched using buffered hydrofluoric acid (BHF). This makes it possible to clean the surface of the mask oxide film, so that the possibility that metal ions are taken into the protective insulating film 21 can be reduced. Therefore, according to the third embodiment, the possibility of gate leakage occurring in the silicon carbide semiconductor device can be further reduced.

  In addition, an etching process (S65) can also be added to the manufacturing method of the silicon carbide semiconductor device which concerns on 2nd Embodiment.

  MOSFET is illustrated as a silicon carbide semiconductor device concerning an embodiment of the invention. However, the silicon carbide semiconductor device according to the embodiment of the present invention may be a transistor having a trench gate. Therefore, the silicon carbide semiconductor device according to the embodiment of the present invention may be an IGBT.

  Further, in each of the above embodiments, the first conductivity type is n-type, and the second conductivity type is p-type. By forming the p-type region in the n-type silicon carbide layer, the ease of manufacturing the silicon carbide semiconductor device can be improved. However, the first conductivity type may be p-type and the second conductivity type may be n-type.

  The embodiment disclosed this time is to be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above-described embodiment but by the scope of claims, and is intended to include meanings equivalent to the scope of claims and all modifications within the scope.

1 MOSFET (silicon carbide semiconductor device)
5 Silicon carbide substrate 10 Silicon carbide single crystal substrate 10A, 10B, 11A Main surface 11 Drift layer 12 Drift region 13 Body region 14 Source region 15 Contact region 21 Protective insulating film 21a Opening 22 Gate insulating film 22a Buffer oxide film 30 Gate electrode 40 Source electrode 50 Interlayer insulating film 60 Source wiring 70 Drain electrode BW Bottom CH Channel region D1, D2, D3 direction L Length S1, S10 to S130 Process SW Side wall T1, T2, T3 Thickness TR Trench UT Corner d Etching depth The

Claims (19)

Providing a silicon carbide substrate having a first main surface and a second main surface located on the opposite side of the first main surface;
The silicon carbide substrate includes a drift layer having a first conductivity type, a body region having a second conductivity type different from the first conductivity type, and disposed inside the drift layer; And a source region formed inside the body region and in contact with the first main surface of the silicon carbide substrate, and
Forming a first silicon dioxide film covering the first main surface of the silicon carbide substrate;
Removing a part of the first silicon dioxide film to form an opening in the first silicon dioxide film to expose the source region;
The drift layer penetrates the source region and the body region from the first main surface by performing chemical etching on the silicon carbide substrate through the opening of the first silicon dioxide film. Forming a trench having a side wall portion reaching the first and second trenches, the trench having an opening having a width larger than the width of the opening of the first silicon dioxide film on the first main surface. And then
Forming a second silicon dioxide film connected to the first silicon dioxide film on at least the side wall of the trench;
By performing heat treatment on the silicon carbide substrate in an inert gas atmosphere, the first silicon dioxide film covers the corner portion located on the first main surface side in the side wall portion of the trench. Softening the first silicon dioxide film;
Forming a gate insulating film in contact with the side wall portion of the trench by subjecting the silicon carbide substrate to a thermal oxidation treatment. The step of forming the first silicon dioxide film includes
The method for manufacturing a silicon carbide semiconductor device according to claim 1, comprising a step of forming a thermal oxide film having a thickness of 50 nm or more and 100 nm or less by dry oxidation. The step of softening the first silicon dioxide film includes:
The method for manufacturing a silicon carbide semiconductor device according to claim 1, further comprising a step of performing the heat treatment on the silicon carbide substrate at a temperature of 1200 ° C. or higher and 1400 ° C. or lower. The step of forming the trench includes:
Forming the trench so that an edge of the opening of the first silicon dioxide film protrudes in a range of 0.1 μm to 0.3 μm with respect to the corner of the trench; The manufacturing method of the silicon carbide semiconductor device of any one of Claims 1-3.   After the step of forming the trench and before the step of forming the second silicon dioxide film, the method further comprises the step of etching the surface layer portion of the first silicon dioxide film using buffered hydrofluoric acid. The manufacturing method of the silicon carbide semiconductor device of any one of Claims 1-4. The step of forming the second silicon dioxide film includes
The method for manufacturing a silicon carbide semiconductor device according to claim 1, comprising a step of forming a thermal oxide film having a thickness of 1 nm or more by dry oxidation. The step of forming the second silicon dioxide film includes
The method for manufacturing a silicon carbide semiconductor device according to claim 6, comprising a step of forming the thermal oxide film at a temperature of 1000 ° C. or higher and 1200 ° C. or lower. The chemical etching is
The manufacturing method of the silicon carbide semiconductor device of any one of Claims 1-7 including the thermal etching using chlorine gas. The step of forming the trench includes:
The carbonization according to any one of claims 1 to 8, comprising a step of performing a reactive ion etching on the silicon carbide substrate and etching a part of the silicon carbide substrate prior to the chemical etching. A method for manufacturing a silicon semiconductor device.   The method for manufacturing a silicon carbide semiconductor device according to any one of claims 1 to 9, wherein the first main surface is a C-plane.   11. The method for manufacturing a silicon carbide semiconductor device according to claim 10, wherein said side wall includes a surface inclined at an angle of 50 ° or more and 65 ° or less with respect to said C-plane.   The said side wall part is a manufacturing method of the silicon carbide semiconductor device of any one of Claims 1-11 containing the surface which has a surface orientation {0-33-8}. The step of forming the gate insulating film includes:
The process of performing the thermal oxidation treatment on the silicon carbide substrate by switching the atmosphere gas from the inert gas to the oxygen-containing gas following the step of softening the first silicon dioxide film. 13. A method for manufacturing a silicon carbide semiconductor device according to any one of 12 above. A silicon carbide substrate having a first main surface and a second main surface located on the opposite side of the first main surface;
The silicon carbide substrate is
A drift layer having a first conductivity type;
A body region having a second conductivity type different from the first conductivity type and disposed inside the drift layer;
A source region having the first conductivity type, formed in the body region and in contact with the first main surface of the silicon carbide substrate;
A trench having a side wall portion that penetrates the source region and the body region from the first main surface and reaches the drift layer is formed in the silicon carbide substrate, and the side wall portion is formed on the first main surface. Is inclined with respect to
further,
A silicon dioxide film including a thermal oxide film covering a corner portion located on the first main surface side in the side wall portion of the trench;
A gate insulating film that includes at least the sidewall portion of the trench and includes a thermal oxide film connected to the silicon dioxide film;
A direction perpendicular to the first main surface and from the first main surface to the silicon dioxide film is a first direction,
When the direction parallel to the first main surface and toward the trench is the second direction,
The silicon dioxide film is
Having a shape that hangs down from the corner of the trench to the side wall,
A first thickness along the first direction;
A second thickness along the second direction from the corner of the trench;
The silicon carbide semiconductor device, wherein a ratio of the second thickness to the first thickness is 50% or more.   The silicon carbide semiconductor device according to claim 14, wherein the ratio is 100% or less. The first principal surface is a C-plane;
16. The silicon carbide semiconductor device according to claim 14, wherein said side wall includes a surface inclined at an angle of 50 ° to 65 ° with respect to said C surface.   17. The silicon carbide semiconductor device according to claim 14, wherein said sidewall portion includes a surface having a plane orientation {0-33-8}.   The silicon carbide semiconductor device according to any one of claims 14 to 17, wherein the second thickness is not less than 50 nm and not more than 100 nm. A direction different from the first direction is defined as a third direction,
When the angle formed by the third direction with respect to the first direction when the third direction matches the second direction is defined as 90 °,
The silicon dioxide film has a third thickness passing through a position where the extending direction of the first main surface and the extending direction of the side wall portion of the trench intersect and along the third direction. ,
The ratio of the third thickness to the first thickness is 50% or more until the angle formed by the third direction with respect to the first direction is at least 95 °. The silicon carbide semiconductor device according to any one of claims.

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