JP2016143788A - Manufacturing method of silicon carbide semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method of a silicon carbide semiconductor device, capable of suppressing increase of a contact resistance.SOLUTION: A silicon carbide substrate 10 having a first principal surface 10a and a second principal surface 10b is prepared. The silicon carbide substrate 10 includes: a first impurity region 12 having a first conductivity type; a second impurity region 13 that is arranged on the first impurity region 12 and has a second conductivity type; and a third impurity region 14 that is arranged on the second impurity region 13 so as to be separated from the first impurity region 12, comprises the first principal surface 10a, and has the first conductive type. In the first principal surface 10a, a protective layer 2 covering the third impurity region 14 is formed. In a state where the protective layer 2 covers the third impurity region 14, an oxide film 3 contacting to the second impurity region 13 is formed by thermal-oxidating the silicon carbide substrate 10. An electrode 16 connecting to the third impurity region 14 is formed. The protective layer 2 and the oxidation film 3 structure a gate insulation film 15.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a method for manufacturing a silicon carbide semiconductor device.

  2. Description of the Related Art In recent years, silicon carbide has been increasingly used as a material for semiconductor devices in order to enable higher breakdown voltages, lower losses, and use in high-temperature environments for semiconductor devices such as MOSFETs (Metal Oxide Field Effect Transistors). It is being

  The gate oxide film of MOSFET is formed, for example, by thermally oxidizing a silicon carbide epitaxial layer. International Publication No. 2012/017798 (Patent Document 1) forms a gate insulating film extending from the inside of a trench to the upper surface of an n-type source region and a p-type contact region by thermally oxidizing a silicon carbide epitaxial layer. It is disclosed.

International Publication No. 2012/017798

  However, when a gate insulating film is formed on the source region and then the gate insulating film on the source region is removed and a source electrode is formed on the source region, the contact resistance between the source region and the source electrode increases. There was a case.

  An object of the present invention is to provide a method for manufacturing a silicon carbide semiconductor device capable of suppressing an increase in contact resistance.

  A method for manufacturing a silicon carbide semiconductor device according to one embodiment of the present invention includes the following steps. A silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface is prepared. The silicon carbide substrate includes a first impurity region having a first conductivity type, a second impurity region provided on the first impurity region and having a second conductivity type different from the first conductivity type, and separated from the first impurity region. And a third impurity region which is provided on the second impurity region and forms the first main surface and has the first conductivity type. A protective layer covering the third impurity region is formed on the first main surface. An oxide film in contact with the second impurity region is formed by thermally oxidizing the silicon carbide substrate with the protective layer covering the third impurity region. An electrode in contact with the third impurity region is formed. The protective layer and the oxide film constitute a gate insulating film.

  According to one embodiment of the present invention, a method for manufacturing a silicon carbide semiconductor device capable of suppressing an increase in contact resistance can be provided.

1 is a schematic cross sectional view showing a configuration of a silicon carbide semiconductor device according to a first embodiment. FIG. 2 is a schematic perspective view showing the shape of a silicon carbide substrate included in the silicon carbide semiconductor device of FIG. 1. FIG. 5 is a flowchart schematically showing a method for manufacturing the silicon carbide semiconductor device according to the first embodiment. FIG. 3 is a schematic cross sectional view showing a first step of the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. FIG. 6 is a schematic cross sectional view showing a second step of the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. FIG. 6 is a schematic cross sectional view showing a third step of the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. FIG. 6 is a schematic cross sectional view showing a fourth step of the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. FIG. 9 is a schematic cross sectional view showing a fifth step of the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. FIG. 9 is a schematic cross sectional view showing a sixth step of the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. FIG. 9 is a schematic cross sectional view showing a seventh step of the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. It is a figure which shows roughly the relationship between the impurity concentration and position in a source region. FIG. 12 is a schematic cross sectional view showing an eighth step of the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. FIG. 11 is a schematic cross sectional view showing a ninth step of the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. FIG. 9 is a schematic cross sectional view showing a sixth step of the method for manufacturing the silicon carbide semiconductor device according to the second embodiment. FIG. 11 is a schematic cross sectional view showing a seventh step of the method for manufacturing the silicon carbide semiconductor device according to the second embodiment. FIG. 11 is a schematic cross sectional view showing a sixth step of the method for manufacturing the silicon carbide semiconductor device according to the third embodiment. FIG. 12 is a schematic cross sectional view showing a seventh step of the method for manufacturing the silicon carbide semiconductor device according to the third embodiment. 5 is a schematic cross sectional view showing a configuration of a modified example of the silicon carbide semiconductor device according to the first embodiment. It is a cross-sectional schematic diagram which shows the ion implantation process of a planar type silicon carbide semiconductor device.

  As a result of intensive studies on the cause of the increase in contact resistance, the inventor obtained the following knowledge and found one embodiment of the present invention.

  The source region of the MOSFET is formed by, for example, ion implantation of n-type impurities such as nitrogen from the surface side of the silicon carbide substrate. Therefore, as shown in FIG. 11, the concentration of n-type impurities such as nitrogen included in the n-type source region decreases from the front side to the back side of the silicon carbide substrate. In the step of thermally oxidizing the silicon carbide epitaxial layer, silicon carbide constituting the surface of the n-type source region reacts with oxygen in the atmosphere to become silicon dioxide. Therefore, the concentration (b1) of the n-type impurity on the surface (position a1) of the n-type source region after thermal oxidation is the concentration (b0) of the n-type impurity on the surface (position 0) of the n-type source region before thermal oxidation. Lower than. As a result, the contact resistance between the source electrode formed on the surface of the n-type source region and the n-type source region increases.

  The inventor covers the surface of the n-type source region with a protective layer not derived from a silicon carbide substrate, such as a silicon deposition layer, for example, before the thermal oxidation step, and the silicon carbide substrate covers the n-type source region. It has been devised that the amount of silicon carbide constituting the n-type source region to be silicon dioxide (hereinafter also referred to as consumption) is suppressed by thermally oxidizing. Thereby, the n-type impurity concentration on the surface of the n-type source region can be kept high. As a result, an increase in contact resistance between the n-type source region and the source electrode can be suppressed.

[Description of Embodiment of Present Invention]
(1) The manufacturing method of the silicon carbide semiconductor device 1 which concerns on 1 aspect of this invention is equipped with the following processes. A silicon carbide substrate 10 having first main surface 10a and second main surface 10b opposite to first main surface 10a is prepared. Silicon carbide substrate 10 includes a first impurity region 12 having a first conductivity type, a second impurity region 13 provided on first impurity region 12 and having a second conductivity type different from the first conductivity type, And a third impurity region 14 provided on second impurity region 13 so as to be separated from impurity region 12 and constituting first main surface 10a and having the first conductivity type. On the first major surface 10a, the protective layer 2 covering the third impurity region 14 is formed. In a state where protective layer 2 covers third impurity region 14, silicon carbide substrate 10 is thermally oxidized to form oxide film 3 in contact with second impurity region 13. An electrode 16 in contact with the third impurity region 14 is formed. The protective layer 2 and the oxide film 3 constitute a gate insulating film 15.

  According to the method for manufacturing silicon carbide semiconductor device 1 according to (1) above, silicon carbide substrate 10 is thermally oxidized in a state where protective layer 2 covers third impurity region 14, thereby forming second impurity region 13. An oxide film 3 in contact therewith is formed. Thereby, the reduction of the impurity concentration on the surface of the third impurity region 14 can be suppressed by suppressing the consumption amount of the third impurity region 14. As a result, an increase in contact resistance between the third impurity region 14 and the electrode 16 can be suppressed.

  (2) The method for manufacturing silicon carbide semiconductor device 1 according to (1) may further include a step of forming trench TR in first main surface 10a. Trench TR is defined by side SW passing through third impurity region 14 and second impurity region 13 and reaching first impurity region 12, and bottom BT located in first impurity region 12. In the step of forming oxide film 3, oxide film 3 is formed in contact with both bottom portion BT and side portion SW. As shown in FIG. 19, in the case of a planar silicon carbide semiconductor device, channel region CH formed in second impurity region 13 and third impurity region 14 are perpendicular to ion implantation direction I. The channel regions CH are adjacent to each other on the plane and are covered with the ion implantation mask 41. Therefore, when the dose amount of ion implantation for the third impurity region 14 is increased in order to compensate the impurity concentration, there is a low possibility that a crystal defect due to ion implantation occurs in the channel region CH. On the other hand, in trench-type silicon carbide semiconductor device 1, channel region CH and third impurity region 14 formed in second impurity region 13 are adjacent to each other on a plane substantially parallel to ion implantation direction I. (See FIG. 5 and FIG. 1). Therefore, when the dose amount of ion implantation for the third impurity region 14 is increased in order to compensate the impurity concentration, the ion-implanted impurity penetrates the third impurity region 14, and the channel region CH, the third impurity region 14, There is a high possibility that crystal defects will occur at the interface. As a result, there is a high possibility that the reliability of trench type silicon carbide semiconductor device 1 is lowered. Therefore, in the case of trench type silicon carbide semiconductor device 1, it is difficult to suppress the increase in contact resistance between third impurity region 14 and electrode 16 by increasing the dose amount of ion implantation for third impurity region 14. . That is, the method for manufacturing silicon carbide semiconductor device 1 according to the above (2) can be preferably used for trench type silicon carbide semiconductor device 1 rather than planar type silicon carbide semiconductor device 1.

  (3) In the method for manufacturing silicon carbide semiconductor device 1 according to (2) above, the step of forming trench TR may include the step of performing thermal etching on silicon carbide substrate 10 using protective layer 2 as a mask. Good. Thereby, since the process of removing the mask can be omitted, the manufacturing process is simplified.

  (4) In the method for manufacturing silicon carbide semiconductor device 1 according to any one of (1) to (3), protective layer 2 is formed by any one of a sputtering method and a chemical vapor deposition method. Thereby, the protective layer 2 can be formed by a simple method without performing thermal oxidation.

  (5) In the method for manufacturing silicon carbide semiconductor device 1 according to any one of (1) to (4), protective layer 2 includes at least one of silicon, silicon dioxide, and silicon nitride. Thereby, the insulation performance of the gate insulating film 15 can be improved.

  (6) In the method for manufacturing silicon carbide semiconductor device 1 according to any one of (1) to (5), thickness t of protective layer 2 is not less than 10 nm and not more than 100 nm. By setting the thickness t of the protective layer 2 to 10 nm or more, the consumption of the third impurity region 14 can be effectively reduced. By setting the thickness t of the protective layer 2 to 100 nm or less, it is possible to prevent a part of the protective layer 2 from remaining without being oxidized.

  (7) In the method for manufacturing silicon carbide semiconductor device 1 according to any one of (1) to (6), silicon carbide substrate 10 is second to first main surface 10a so as to penetrate third impurity region 14. Further, fourth impurity region 18 extending to impurity region 13 and having the second conductivity type is further included. In the step of forming the protective layer 2, the protective layer 2 is formed so as to cover the fourth impurity region 18. In the step of forming the electrode 16, the electrode 16 is formed in contact with the fourth impurity region 18. Thereby, the reduction of the impurity concentration on the surface of the fourth impurity region 18 can be suppressed by suppressing the consumption amount of the fourth impurity region 18. As a result, an increase in contact resistance between the fourth impurity region 18 and the electrode 16 can be suppressed.

  (8) In the method for manufacturing silicon carbide semiconductor device 1 according to any one of (1) to (7), in the step of forming protective layer 2, protective layer 2 includes channel region CH in second impurity region 13. It is formed so as to cover. The protective layer 2 becomes a part of the gate insulating film 15. Therefore, when the protective layer 2 covers the channel region CH, the thermal oxidation time for obtaining the gate insulating film 15 having the same thickness is shorter than when the protective layer 2 does not cover the channel region CH. Silicon of silicon carbide constituting the channel region CH reacts with oxygen and changes into silicon dioxide by thermal oxidation, and carbon remains in the channel region CH. Since carbon in the channel region CH forms an interface state, mobility becomes small. Since the carbon concentration in the channel region CH is reduced by shortening the thermal oxidation time, the formation of interface states is suppressed. As a result, it can suppress that mobility becomes small.

[Details of the embodiment of the present invention]
Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following drawings, the same or corresponding parts are denoted by the same reference numerals, and the description thereof will not be repeated. In the crystallographic description in this specification, the individual orientation is indicated by [], the collective orientation is indicated by <>, the individual plane is indicated by (), and the collective plane is indicated by {}. In addition, a negative crystallographic index is usually expressed by adding a “-” (bar) above a number, but in this specification a negative sign is added before the number. Yes.

(Embodiment 1)
First, the configuration of MOSFET as silicon carbide semiconductor device according to the first embodiment of the present invention will be described.

  As shown in FIGS. 1 and 2, MOSFET 1 according to the first embodiment includes silicon carbide substrate 10, gate insulating film 15, gate electrode 27, interlayer insulating film 22, source electrode 16, and source wiring. 19 and the drain electrode 20 are mainly included. Silicon carbide substrate 10 includes a silicon carbide single crystal substrate 11 and a silicon carbide epitaxial layer 24 provided on silicon carbide single crystal substrate 11. Silicon carbide substrate 10 has a third main surface 10c and a second main surface 10b opposite to the third main surface 10c. Silicon carbide epitaxial layer 24 constitutes third main surface 10c, and silicon carbide single crystal substrate 11 constitutes second main surface 10b. Silicon carbide single crystal substrate 11 is, for example, polytype 4H hexagonal silicon carbide. Silicon carbide single crystal substrate 11 includes an impurity such as nitrogen and has an n-type (first conductivity type) conductivity type. The silicon carbide epitaxial layer 24 includes a drift region 12 (first impurity region 12), a body region 13 (second impurity region 13), a source region 14 (third impurity region 14), and a contact region 18 (fourth impurity). Region 18).

Drift region 12 includes an n-type impurity such as nitrogen and has n-type conductivity. The concentration of the n-type impurity contained in the drift region 12 is preferably 1 × 10 ¹⁵ cm ⁻³ or more and 5 × 10 ¹⁶ cm ⁻³ or less, for example, 8 × 10 ¹⁵ cm ⁻³ .

Body region 13 is provided on drift region 12. Body region 13 includes a p-type impurity such as aluminum and has a p-type (second conductivity type) conductivity type. The concentration of the p-type impurity in the body region 13 is preferably 1 × 10 ¹⁷ cm ⁻³ or more and 5 × 10 ¹⁸ cm ⁻³ or less, for example, 1 × 10 ¹⁸ cm ⁻³ .

  Source region 14 is provided on body region 13 so as to be separated from drift region 12 by body region 13. Source region 14 includes an n-type impurity such as nitrogen or phosphorus and has an n-type conductivity type. Source region 14 constitutes third main surface 10 c of silicon carbide substrate 10. The concentration of the n-type impurity included in the source region 14 may be higher than the concentration of the n-type impurity included in the drift region 12.

  Contact region 18 is in contact with body region 13 and source region 14. Contact region 18 contains a p-type impurity such as aluminum and has p-type conductivity. The concentration of the p-type impurity included in the contact region 18 may be higher than the concentration of the p-type impurity included in the body region 13. Contact region 18 is provided through source region 14 so as to connect body region 13 and third main surface 10c.

  Trench TR is provided in third main surface 10c of silicon carbide substrate 10. Trench TR is defined by side SW and bottom BT formed continuously with side SW. Side SW passes through source region 14 and body region 13 and reaches drift region 12. Body region 13 includes channel region CH in contact with gate insulating film 15. The bottom portion BT is located in the drift region 12.

  Side SW of trench TR is preferably inclined with respect to third main surface 10c. In a cross-sectional view (a visual field viewed along a direction parallel to second main surface 10b of silicon carbide substrate 10), side portion SW is inclined such that the width of trench TR is tapered toward bottom portion BT. Also good. The plane orientation of the side SW is preferably 50 ° or more and 70 ° or less with respect to the {0001} plane, and 50 ° or more and 70 ° or less with respect to the (000-1) plane. More preferred. Note that the side portion SW of the trench TR may be formed perpendicular to the third main surface 10c. Bottom portion BT of trench TR may have a flat shape substantially parallel to third main surface 10c. In cross-sectional view, the shape of the trench TR may be U-shaped or V-shaped.

  FIG. 2 shows the silicon carbide substrate 10 taken out from the MOSFET 1 of FIG. As shown in FIG. 2, source region 14 and body region 13 are exposed at side SW of trench TR. Drift region 12 is exposed at each of side SW and bottom BT of trench TR. A portion where bottom portion BT and side portion SW are connected constitutes a corner portion of trench TR. In a plan view (a visual field viewed along a direction perpendicular to second main surface 10b of silicon carbide substrate 10), trench TR may extend so as to form a mesh having a honeycomb structure. In plan view, third main surface 10c of silicon carbide substrate 10 formed of source region 14 and contact region 18 has a polygonal shape, preferably a hexagonal shape. In plan view, each of body region 13, source region 14, and contact region 18 has a hexagonal outer shape.

  As shown in FIG. 1, gate insulating film 15 is in contact with bottom portion BT and side portion SW of trench TR. Gate insulating film 15 includes first insulating film 3 in contact with bottom BT and side SW of trench TR, and second insulating film 2 provided on first insulating film 3 and in contact with gate electrode 27. The first insulating film 3 is a thermal oxide film and contains silicon dioxide. The second insulating film 2 is a film obtained by oxidizing the deposited insulating film. Second insulating film 2 is a material containing, for example, silicon dioxide. First insulating film 3 is in contact with drift region 12 at bottom BT of trench TR, and is in contact with source region 14, body region 13 and drift region 12 at side SW of trench TR.

  Gate electrode 27 is provided inside trench TR so as to be in contact with gate insulating film 15 inside trench TR. The gate electrode 27 is made of polysilicon containing impurities, for example.

  Source electrode 16 is in contact with each of source region 14 and contact region 18 on third main surface 10c. The source electrode 16 is made of a material containing, for example, Ti, Al, and Si. Preferably, source electrode 16 is in ohmic contact with source region 14 and contact region 18. The source wiring 19 is in contact with the source electrode 16. Source wiring 19 is made of, for example, a material containing aluminum.

  The interlayer insulating film 22 is provided in contact with the gate electrode 27 and the gate insulating film 15, and extends from one source electrode 16 to the other source electrode 16. Interlayer insulating film 22 is made of, for example, a material containing silicon dioxide. The interlayer insulating film 22 electrically insulates the gate electrode 27 and the source electrode 16 from each other.

  Drain electrode 20 is in contact with silicon carbide single crystal substrate 11 on second main surface 10 b and is electrically connected to drift region 12. The drain electrode 20 is made of a material containing, for example, NiSi or TiAlSi.

Next, a method for manufacturing MOSFET 1 according to the first embodiment will be described.
First, a step of preparing a silicon carbide substrate (S10: FIG. 3) is performed. As shown in FIG. 4, silicon carbide epitaxial layer 24 is formed on silicon carbide single crystal substrate 11. Specifically, for example, by a CVD (Chemical Vapor Deposition) method using a mixed gas of silane (SiH ₄ ) and propane (C ₃ H ₈ ) as a source gas and using, for example, hydrogen gas (H ₂ ) as a carrier gas. Silicon carbide epitaxial layer 24 is formed on silicon carbide single crystal substrate 11. In the epitaxial growth, it is preferable to introduce, for example, nitrogen (N) or phosphorus (P) as impurities. Silicon carbide epitaxial layer 24 has n type conductivity. Silicon carbide substrate 10 has a first main surface 10a constituting silicon carbide epitaxial layer 24, and a second main surface 10b opposite to first main surface 10a and constituting silicon carbide single crystal substrate 11. The first major surface 10a is, for example, a {0001} plane, preferably a (000-1) plane. The first major surface 10a may be a surface that is off by 8 ° or less from the {0001} plane.

  Next, body region 13 is formed by ion implantation of a p-type impurity such as aluminum into first main surface 10a. Source region 14 is formed by implanting n-type impurity such as phosphorus into body region 13 at a depth shallower than body region 13. Next, contact region 18 is formed by ion implantation of a p-type impurity such as aluminum into source region 14. The contact region 18 is formed so as to penetrate the source region 14 and contact the body region 13.

  Next, activation annealing is performed to activate the impurities ion-implanted into silicon carbide substrate 10. The temperature of activation annealing is preferably 1500 ° C. or higher and 1900 ° C. or lower, for example, about 1700 ° C. The activation annealing time is, for example, about 30 minutes. The atmosphere of activation annealing is preferably an inert gas atmosphere, for example, an Ar atmosphere. As described above, silicon carbide substrate 10 having first main surface 10a and second main surface 10b opposite to first main surface 10a is prepared. Silicon carbide substrate 10 includes an n-type drift region 12, a body region 13 having a p-type different from the n-type, a source region 14 having an n-type, and a contact having a p-type. Region 18. The source region 14 is provided on the body region 13 so as to be separated from the drift region 12, and constitutes the first main surface 10a. Contact region 18 extends from first main surface 10a to body region 13 so as to penetrate source region 14 (see FIG. 5).

  Next, a step of forming a trench (S20: FIG. 3) is performed. As shown in FIG. 6, a mask layer 40 having an opening OP is formed on first main surface 10 a composed of source region 14 and contact region 18. The mask layer 40 may be formed by any one of a sputtering method and a chemical vapor deposition method. As mask layer 40, for example, a silicon oxide film or the like can be used. The opening OP is formed corresponding to the position of the trench TR (FIG. 1).

In the opening OP of the mask layer 40, the source region 14, the body region 13, and a part of the drift region 12 are removed by etching. As an etching method, for example, reactive ion etching, particularly inductively coupled plasma reactive ion etching can be used. Specifically, for example, inductively coupled plasma reactive ion etching using SF ₆ or a mixed gas of SF ₆ and O ₂ as a reaction gas can be used. In the region where trench TR (FIG. 1) is to be formed by etching, a side portion substantially perpendicular to first main surface 10a and a bottom portion connected to the side portion and substantially parallel to first main surface 10a A recess having the shape is formed.

Next, thermal etching is performed in the recess. The thermal etching can be performed, for example, by heating in an atmosphere containing a reactive gas having at least one or more types of halogen atoms. The at least one or more types of halogen atom includes at least one of a chlorine (Cl) atom and a fluorine (F) atom. The atmosphere includes, for example, Cl ₂ , BCL ₃ , SF ₆ , or CF ₄ . For example, thermal etching is performed using a mixed gas of chlorine gas and oxygen gas as a reaction gas and a heat treatment temperature of, for example, 700 ° C. or more and 1000 ° C. or less. Note that the reaction gas may contain a carrier gas in addition to the above-described chlorine gas and oxygen gas. As the carrier gas, for example, nitrogen (N ₂ ) gas, argon gas, helium gas or the like can be used. During the thermal etching, the mask layer 40 has a very high selectivity with respect to SiC, so that it is not substantially etched during the etching of SiC.

  As shown in FIG. 7, trench TR is formed in first main surface 10a of silicon carbide substrate 10 by the thermal etching. Trench TR is defined by side SW passing through source region 14 and body region 13 to drift region 12, and bottom BT located in drift region 12. Preferably, the side part SW is inclined with respect to the bottom part BT, and the angle of the side part SW with respect to the bottom part BT is, for example, 50 ° or more and 70 ° or less. Side SW is, for example, the (0-33-8) plane. When each of source region 14, body region 13, and drift region 12 is thermally etched to form side portion SW of trench TR, mask layer 40 is not substantially etched. Therefore, mask layer 40 is left so as to protrude from first main surface 10a to side SW of trench TR. Next, the mask layer 40 is removed from, for example, hydrofluoric acid (HF) (see FIG. 8).

  Next, a step of forming a protective film (S30: FIG. 3) is performed. In first main surface 10a, protective layer 2 covering source region 14 is formed. Preferably, the protective layer 2 is formed so as to cover the contact region 18. As shown in FIG. 9, protective layer 2 is in contact with source region 14 and contact region 18, for example, on first main surface 10 a, and on side SW, source region 14, body region 13, drift region 12, and so on. And may be provided in contact with the drift region 12 at the bottom BT.

  Protective layer 2 is formed without thermally oxidizing silicon carbide substrate 10. Preferably, the protective layer 2 is formed by any one of a sputtering method and a chemical vapor deposition method. Specifically, the protective layer may be formed by plasma CVD or thermal CVD. The protective layer 2 may include at least one of silicon, silicon dioxide, and silicon nitride. The thickness t of the protective layer 2 is, for example, not less than 10 nm and not more than 100 nm, preferably not less than 20 nm and not more than 50 nm. Preferably, protective layer 2 is formed to cover channel region CH in body region 13. The protective layer 2 may be formed so as to cover the bottom part BT and the side part SW.

  Next, a step of forming an oxide film (S40: FIG. 3) is performed. As shown in FIG. 10, silicon carbide substrate 10 is thermally oxidized with protective layer 2 covering source region 14 and contact region 18, so that source region 14, body region 13, drift region 12, An oxide film 3 in contact with is formed. Specifically, protective layer 2 covers source region 14 and contact region 18 at first main surface 10a, covers source region 14, body region 13 and drift region 12 at side SW, and drift region 12 at bottom BT. In a state of covering, silicon carbide substrate 10 is heated, for example, at a temperature of 1300 ° C. or higher and 1400 ° C. or lower in an atmosphere containing oxygen. Thereby, oxygen that has passed through protective layer 2 reacts with silicon carbide, and oxide film 3 is formed between silicon carbide substrate 10 and protective layer 2. By thermally oxidizing first main surface 10a, the silicon carbide layer including first main surface 10a becomes a silicon dioxide layer. As a result, the third main surface 10c located on the second main surface 10b side with respect to the position of the first main surface 10a is formed. The third major surface 10 c is composed of the source region 14 and the contact region 18. Preferably, oxide film 3 is formed in contact with both bottom portion BT and side portion SW of trench TR. The protective layer 2 and the oxide film 3 constitute a gate insulating film 15. In the step of forming the oxide film, the protective layer 2 may be oxidized to silicon dioxide.

  FIG. 11 shows the relationship between the concentration of the n-type impurity included in the source region 14 and the position in the direction perpendicular to the second major surface 10b. The position 0 corresponds to the position of the first main surface 10a before the step of forming the oxide film (S40: FIG. 3), and the position a1 is the position after the step of forming the oxide film (S40: FIG. 3). This corresponds to the position of the three principal surfaces 10c. As shown in FIG. 11, the concentration of the n-type impurity included in the source region 14 monotonously decreases from the first main surface 10a toward the second main surface 10b. As shown in FIG. 11, the concentration b1 of the n-type impurity at the position a1 of the third main surface 10c is lower than the concentration b0 of the n-type impurity at the position 0 of the first main surface 10a. Similarly, the concentration of the p-type impurity contained in the contact region 18 may be monotonously reduced as it goes from the first main surface 10a to the second main surface 10b. In this case, the concentration of the p-type impurity at the position a1 of the third main surface 10c is lower than the concentration of the p-type impurity at the position 0 of the first main surface 10a.

After thermally oxidizing silicon carbide substrate 10, heat treatment (NO annealing) may be performed on silicon carbide substrate 10 in a nitrogen monoxide (NO) gas atmosphere. In NO annealing, silicon carbide substrate 10 is held for about 1 hour under conditions of, for example, 1100 ° C. or higher and 1300 ° C. or lower. As a result, nitrogen atoms are introduced into the interface region between the gate insulating film 15 and the body region 13. As a result, the formation of interface states in the interface region is suppressed, so that channel mobility can be improved. As long as such nitrogen atoms can be introduced, a gas other than NO gas (for example, N ₂ O) may be used as the atmospheric gas. Ar annealing using argon (Ar) as an atmospheric gas may be further performed after the NO annealing. The heating temperature for Ar annealing is, for example, equal to or higher than the heating temperature for NO annealing. The Ar annealing time is, for example, about 1 hour. As a result, the formation of interface states in the interface region between the gate insulating film 15 and the body region 13 is further suppressed. Note that other inert gas such as nitrogen gas may be used as the atmospheric gas instead of Ar gas.

  Next, a step of forming a gate electrode (S50: FIG. 3) is performed. As shown in FIG. 12, gate electrode 27 in contact with second insulating film 2 of gate insulating film 15 is formed inside trench TR. Gate electrode 27 is arranged inside trench TR and is formed to face each of side SW and bottom BT of trench TR via gate insulating film 15. The gate electrode 27 is formed by, for example, LPCVD (Low Pressure Chemical Vapor Deposition).

  Next, an interlayer insulating film 22 is formed. Specifically, the interlayer insulating film 22 is formed so as to cover the gate electrode 27 and to be in contact with the gate insulating film 15. Preferably, the interlayer insulating film 22 is formed by a deposition method, more preferably a chemical vapor deposition method. Interlayer insulating film 22 is a material containing, for example, silicon dioxide.

  Next, a step of forming a source electrode (S60: FIG. 3) is performed. Specifically, etching is performed so that openings are formed in the interlayer insulating film 22 and the gate insulating film 15, so that the source region 14 and the contact region 18 are formed in the openings in the interlayer insulating film 22 and the gate insulating film. 15 is exposed. Source region 14 and contact region 18 constitute third main surface 10 c of silicon carbide substrate 10. Next, source electrode 16 in contact with source region 14 and contact region 18 is formed on third main surface 10c (see FIG. 13). The source electrode 16 is formed by, for example, a sputtering method. The source electrode 16 is made of a material containing, for example, Ti, Al, and Si. Next, alloying annealing is performed. Specifically, the source electrode 16 in contact with the source region 14 and the contact region 18 is held for about 5 minutes at a temperature of 900 ° C. or higher and 1100 ° C. or lower, for example. Thereby, at least a part of source electrode 16 reacts with silicon included in silicon carbide substrate 10 to be silicided. As a result, the source electrode 16 that is in ohmic contact with the source region 14 is formed. Preferably, the source electrode 16 is in ohmic contact with the contact region 18.

  Next, a source wiring 19 that is electrically connected to the source electrode 16 is formed. The source wiring 19 is formed on the source electrode 16 and the interlayer insulating film 22. Next, drain electrode 20 is formed in contact with second main surface 10b of silicon carbide substrate 10. Thus, MOSFET 1 (FIG. 1) according to the first embodiment is completed.

  The first main surface 10a is preferably a carbon surface or a surface off by 8 ° or less from the carbon surface. Since the carbon surface has a higher oxidation rate than surfaces other than the carbon surface, silicon carbide is easily consumed. By forming protective layer 2 on the carbon surface, consumption of silicon carbide can be effectively suppressed.

  The source region 14 preferably has n-type conductivity. Since n-type silicon carbide has a higher oxidation rate than p-type silicon carbide, silicon carbide is easily consumed. By forming protective layer 2 on n-type source region 14, consumption of silicon carbide can be effectively suppressed.

Next, the function and effect of the MOSFET according to the first embodiment will be described.
According to the method for manufacturing MOSFET 1 according to the first embodiment, oxide film 3 in contact with body region 13 is formed by thermally oxidizing silicon carbide substrate 10 with protective layer 2 covering source region 14. . Thereby, the reduction of the impurity concentration on the surface of the source region 14 can be suppressed by suppressing the consumption amount of the source region 14. As a result, an increase in contact resistance between the source region 14 and the source electrode 16 can be suppressed.

  In addition, according to the method for manufacturing MOSFET 1 according to the first embodiment, a step of forming trench TR in first main surface 10a may be further provided. Trench TR is defined by side SW passing through source region 14 and body region 13 to drift region 12, and bottom BT located in drift region 12. In the step of forming oxide film 3, oxide film 3 is formed in contact with both bottom portion BT and side portion SW. As shown in FIG. 19, in the case of a planar MOSFET, the channel region CH formed in the body region 13 and the source region 14 are positioned adjacent to each other on a plane perpendicular to the ion implantation direction I. The channel region CH is covered with an ion implantation mask 41. Therefore, when the dose amount of ion implantation for the source region 14 is increased in order to compensate the impurity concentration, there is a low possibility that crystal defects due to ion implantation occur in the channel region CH. On the other hand, in the case of trench type MOSFET 1, channel region CH and source region 14 formed in body region 13 are located adjacent to each other on a plane substantially parallel to ion implantation direction I (FIGS. 5 and 5). 1). Therefore, when increasing the dose of ion implantation to the source region 14 in order to compensate the impurity concentration, the ion implanted impurity penetrates the source region 14 and a crystal defect is present at the interface between the channel region CH and the source region 14. It is more likely to occur. As a result, there is a high possibility that the reliability of the MOSFET 1 is lowered. Therefore, in the case of the trench type MOSFET 1, it is difficult to suppress an increase in contact resistance between the source region 14 and the source electrode 16 by increasing the dose amount of ion implantation into the source region 14. That is, the method for manufacturing MOSFET 1 according to the first embodiment can be preferably used for trench MOSFET 1 rather than planar MOSFET 1.

  Furthermore, according to the method for manufacturing MOSFET 1 according to the first embodiment, protective layer 2 is formed by one of a sputtering method and a chemical vapor deposition method. Thereby, the protective layer 2 can be formed by a simple method without performing thermal oxidation.

  Furthermore, according to the method for manufacturing MOSFET 1 according to the first embodiment, protective layer 2 includes at least one of silicon, silicon dioxide, and silicon nitride. Thereby, the insulation performance of the gate insulating film 15 can be improved.

  Furthermore, according to the method for manufacturing MOSFET 1 according to the first embodiment, the thickness t of the protective layer 2 is not less than 10 nm and not more than 100 nm. By setting the thickness t of the protective layer 2 to 10 nm or more, the consumption of the third impurity region 14 can be effectively reduced. By setting the thickness t of the protective layer 2 to 100 nm or less, it is possible to prevent a part of the protective layer 2 from remaining without being oxidized.

  Furthermore, according to the method for manufacturing MOSFET 1 according to the first embodiment, silicon carbide substrate 10 extends from first main surface 10a to body region 13 so as to penetrate source region 14 and has a p-type contact region. 18 is further included. In the step of forming the protective layer 2, the protective layer 2 is formed so as to cover the contact region 18. In the step of forming the source electrode 16, the source electrode 16 is formed in contact with the contact region 18. Thereby, the reduction of the impurity concentration on the surface of the contact region 18 can be suppressed by suppressing the consumption amount of the contact region 18. As a result, an increase in contact resistance between the contact region 18 and the source electrode 16 can be suppressed.

  Furthermore, according to the method for manufacturing MOSFET 1 according to the first embodiment, in the step of forming protective layer 2, protective layer 2 is formed so as to cover channel region CH in second impurity region 13. The protective layer 2 becomes a part of the gate insulating film 15. Therefore, when the protective layer 2 covers the channel region CH, the thermal oxidation time for obtaining the gate insulating film 15 having the same thickness is shorter than when the protective layer 2 does not cover the channel region CH. Silicon of silicon carbide constituting the channel region CH reacts with oxygen and changes into silicon dioxide by thermal oxidation, and carbon remains in the channel region CH. Since carbon in the channel region CH forms an interface state, mobility becomes small. Since the carbon concentration in the channel region CH is reduced by shortening the thermal oxidation time, the formation of interface states is suppressed. As a result, it can suppress that mobility becomes small.

(Embodiment 2)
Next, a method for manufacturing MOSFET 1 according to the second embodiment of the present invention will be described. MOSFET 1 manufacturing method according to the second embodiment is implemented in that protective layer 2 is formed apart from side SW and bottom BT of trench TR in the step of forming a protective layer (S30: FIG. 3). The method is different from the method for manufacturing MOSFET 1 according to the first embodiment, and the others are substantially the same as the method for manufacturing MOSFET 1 according to the first embodiment. Therefore, the same code | symbol is attached | subjected about the same or corresponding element, and the description is not repeated.

  First, by the method described in the first embodiment, a step of preparing a silicon carbide substrate (S10: FIG. 3), a step of forming a trench (S20: FIG. 3), and a step of forming a protective layer (S30: FIG. And 3) are performed. As shown in FIG. 14, in the step of forming a protective layer (S30: FIG. 3), the protective layer 2 covers the source region 14 and the contact region 18 on the first main surface 10a, and the side SW of the trench TR. And may be formed apart from the bottom portion BT. That is, protective layer 2 may be formed on first main surface 10a so as not to cover side portion SW and bottom portion BT of trench TR.

  Next, a step of forming an oxide film (S40: FIG. 3) is performed. In the step of forming the oxide film (S40: FIG. 3), the protective layer 2 covers the source region 14 and the contact region 18 on the first main surface 10a and is separated from the side SW and the bottom BT of the trench TR. The silicon carbide substrate 10 is thermally oxidized. Silicon carbide constituting side SW and bottom BT is thermally oxidized to form oxide film 3 in contact with side SW and bottom BT (see FIG. 15). Similarly, silicon carbide constituting source region 14 and contact region 18 is thermally oxidized to form oxide film 3 in contact with third main surface 10c.

(Embodiment 3)
Next, a method for manufacturing MOSFET 1 according to the third embodiment of the present invention will be described. The manufacturing method of MOSFET 1 according to the third embodiment is different from the manufacturing method of MOSFET 1 according to the first embodiment in that a mask for thermal etching is used as a protective layer. It is almost the same as the manufacturing method. Therefore, the same code | symbol is attached | subjected about the same or corresponding element, and the description is not repeated.

  First, the step of preparing a silicon carbide substrate (S10: FIG. 3) is performed by the method described in the first embodiment. Next, a step of forming a protective layer (S30: FIG. 3) is performed.

  As shown in FIG. 6, in the step of forming the protective layer, a mask layer 40 including a protective layer that functions as a mask in the thermal etching step is formed on the first main surface 10a. Mask layer 40 is formed to cover source region 14 and contact region 18 on first main surface 10a. An opening OP is formed in the mask layer 40, and a part of the source region 14 is exposed to the opening OP.

  Next, a step of performing thermal etching on the silicon carbide substrate is performed using mask layer 40 including the protective layer as a mask. As shown in FIG. 7, trench TR is formed in first main surface 10 a of silicon carbide substrate 10 by performing thermal etching using mask layer 40 including protective layer 40 a. Trench TR is defined by side SW passing through source region 14 and body region 13 to drift region 12, and bottom BT located in drift region 12. After the thermal etching step, the mask layer 40 is left so as to protrude from the first main surface 10a onto the side portion SW of the trench TR (see FIG. 7). The mask layer 40 includes a protective layer 40a and an overhanging portion 40b in contact with the protective layer 40a. Next, the overhanging portion 40b is removed by an arbitrary method such as etching while maintaining the state where the protective layer 40a covers the source region 14 and the contact region 18 (see FIG. 16).

  Next, a step of forming an oxide film (S40: FIG. 3) is performed. As shown in FIG. 17, silicon carbide substrate 10 is heated in an oxygen atmosphere with protective layer 40a covering source region 14 and contact region 18 on first main surface 10a. Thus, the first main surface 10a, the side SW of the trench TR, and the bottom BT are thermally oxidized, thereby forming the oxide film 3 in contact with the side SW, the bottom BT, and the third main surface 10c. Is done. The oxide film 3 and the protective layer 40a constitute the gate insulating film 15.

  According to the method for manufacturing MOSFET 1 according to the third embodiment, the step of forming trench TR includes the step of performing thermal etching on silicon carbide substrate 10 using protective layer 2 as a mask. Thereby, since the process of removing the mask can be omitted, the manufacturing process is simplified.

  In each of the above embodiments, the trench type MOSFET has been described as an example of the silicon carbide semiconductor device. However, the silicon carbide semiconductor device may be a planar MOSFET. As shown in FIG. 18, the planar MOSFET 1 does not have the trench TR (see FIG. 1) provided in the third main surface 10a. The first insulating film 3 of the gate insulating film 15 is in contact with the source region 14, the body region 13, and the drift region 12 on the third main surface 10 c. The second insulating film 2 is provided on the first insulating film 3 and faces the source region 14, the body region 13, and the drift region 12. The gate electrode 27 is provided so as to face the third main surface 10c. Since other configurations are substantially the same as those of the trench MOSFET (FIG. 1), the same or corresponding parts are denoted by the same reference numerals, and description thereof is omitted.

  The silicon carbide semiconductor device may be an IGBT (Insulated Gate Bipolar Transistor). In each of the above embodiments, the n-type is the first conductivity type and the p-type is the second conductivity type. However, the p-type is the first conductivity type and the n-type is the second conductivity type. Good. The silicon carbide semiconductor device does not necessarily have to have a silicon carbide single crystal substrate, and the silicon carbide single crystal substrate may be omitted.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

1 MOSFET (silicon carbide semiconductor device)
2 Protective layer (second insulating film)
3 Oxide film (first insulating film)
10 Silicon carbide substrate 10a First main surface 10b Second main surface 10c Third main surface 11 Silicon carbide single crystal substrate 12 Drift region (first impurity region)
13 Body region (second impurity region)
14 Source region (third impurity region)
15 Gate insulating film 16 Source electrode (electrode)
18 Contact region (fourth impurity region)
19 Source wiring 20 Drain electrode 22 Interlayer insulating film 24 Silicon carbide epitaxial layer 27 Gate electrode 40 Mask layer 40a Protective layer 40b Overhang portion 41 Ion implantation mask BT Bottom CH Channel region OP Opening portion SW Side portion TR Trench

Claims (8)

Providing a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface;
The silicon carbide substrate includes a first impurity region having a first conductivity type;
A second impurity region provided on the first impurity region and having a second conductivity type different from the first conductivity type;
A third impurity region provided on the second impurity region so as to be separated from the first impurity region, constituting the first main surface and having the first conductivity type, and
Forming a protective layer covering the third impurity region on the first main surface;
Forming the oxide film in contact with the second impurity region by thermally oxidizing the silicon carbide substrate in a state where the protective layer covers the third impurity region;
Forming an electrode in contact with the third impurity region,
The method for manufacturing a silicon carbide semiconductor device, wherein the protective layer and the oxide film form a gate insulating film. Further comprising forming a trench in the first main surface;
The trench is defined by a side portion that penetrates the third impurity region and the second impurity region to reach the first impurity region, and a bottom portion that is located in the first impurity region,
The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein in the step of forming the oxide film, the oxide film is formed in contact with both the bottom portion and the side portion.   The method for manufacturing a silicon carbide semiconductor device according to claim 2, wherein the step of forming the trench includes a step of performing thermal etching on the silicon carbide substrate using the protective layer as a mask.   The method for manufacturing a silicon carbide semiconductor device according to any one of claims 1 to 3, wherein the protective layer is formed by any one of a sputtering method and a chemical vapor deposition method.   The said protective layer is a manufacturing method of the silicon carbide semiconductor device of any one of Claims 1-4 containing at least any one of silicon, silicon dioxide, and silicon nitride.   The thickness of the said protective layer is a manufacturing method of the silicon carbide semiconductor device of any one of Claims 1-5 which are 10 nm or more and 100 nm or less. The silicon carbide substrate further includes a fourth impurity region extending from the first main surface to the second impurity region so as to penetrate the third impurity region and having the second conductivity type,
In the step of forming the protective layer, the protective layer is formed so as to cover the fourth impurity region,
The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein in the step of forming the electrode, the electrode is formed in contact with the fourth impurity region.   8. The silicon carbide semiconductor device according to claim 1, wherein in the step of forming the protective layer, the protective layer is formed so as to cover a channel region in the second impurity region. Manufacturing method.

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