JP6298491B2 - Display device - Google Patents

Description

The present invention relates to a display device having a circuit formed using a transistor. In particular, the present invention relates to a display device using an electro-optic element such as liquid crystal or a light emitting element as a display medium, and a driving method thereof.

In recent years, display devices have been actively developed due to an increase in large display devices such as liquid crystal televisions. In particular, a technique for integrally forming a driver circuit (hereinafter also referred to as an internal circuit) including a pixel circuit and a shift register using a transistor formed of an amorphous semiconductor (hereinafter also referred to as amorphous silicon) on an insulating substrate is described. In order to greatly contribute to the reduction of power consumption and cost, development is being actively promoted. An internal circuit formed on the insulator is connected to a controller IC or the like (hereinafter also referred to as an external circuit) via an FPC or the like, and its operation is controlled.

Among the internal circuits shown above, a shift register using a transistor formed of an amorphous semiconductor (hereinafter also referred to as an amorphous silicon transistor) has been devised.
A structure of a flip-flop included in a conventional shift register is illustrated in FIG. 124A (Patent Document 1). The flip-flop in FIG. 124A includes a transistor 11, a transistor 12,
A transistor 13, a transistor 14, a transistor 15 and a transistor 17;
The signal line 21, the signal line 22, the wiring 23, the signal line 24, the power supply line 25, and the power supply line 26 are connected. A start signal, a reset signal, a clock signal, a power supply potential VDD, and a power supply potential VSS are input to the signal line 21, the signal line 22, the signal line 24, the power supply line 25, and the power supply line 26, respectively. The operation period of the flip-flop in FIG. 124A is divided into a set period, a selection period, a reset period, and a non-selection period as shown in the timing chart of FIG. Selection period.

Here, the transistor 12 and the transistor 16 are on in the non-selection period. Therefore, since amorphous silicon is used for the semiconductor layers of the transistors 12 and 16, the threshold voltage (Vth) varies due to deterioration or the like. More specifically, the threshold voltage increases. That is, the conventional shift register cannot be turned on because the threshold voltages of the transistors 12 and 16 are increased, so that VSS cannot be supplied to the node 41 and the wiring 23 and malfunction occurs.

In order to solve this problem, Non-Patent Document 1, Non-Patent Document 2, and Non-Patent Document 3 devise shift registers that can suppress the shift of the threshold voltage of the transistor 12. In Non-Patent Document 1, Non-Patent Document 2, and Non-Patent Document 3, a new transistor (referred to as a first transistor) is arranged in parallel with a transistor 12 (referred to as a second transistor). By inputting inverted signals to the gate electrode of the first transistor and the gate electrode of the second transistor, the threshold voltage shift of the first transistor and the second transistor is suppressed.

Further, Non-Patent Document 4 devises a shift register that can suppress the shift of the threshold voltage of the transistor 16 as well as the transistor 12. In Non-Patent Document 4, a new transistor (referred to as a first transistor) is arranged in parallel with a transistor 12 (referred to as a second transistor), and another new transistor (referred to as a third transistor) is provided as a transistor. 16 (referred to as a fourth transistor) is arranged in parallel. In the non-selection period, inverted signals are input to the gate electrode of the first transistor and the gate electrode of the second transistor, respectively, and inverted to the gate electrode of the third transistor and the gate electrode of the fourth transistor, respectively. By inputting a signal, a shift in threshold voltage of the first transistor, the second transistor, the third transistor, and the fourth transistor is suppressed.

Further, in Non-Patent Document 5, the shift of the threshold voltage of the transistor 12 is suppressed by applying an AC pulse to the gate electrode of the transistor 12.

Note that the display devices of Non-Patent Document 6 and Non-Patent Document 7 use a shift register formed of an amorphous silicon transistor as a scanning line driving circuit, and further video from one signal line to R, G, and B subpixels. By inputting signals, the number of signal lines is reduced to 1/3. Thus, the display devices of Non-Patent Document 6 and Non-Patent Document 7 reduce the number of connections between the display panel and the driver IC.

JP 2004-157508 A

Soo Young Yoon, et al. , "Highly Stable Integrated Gate Driver A-Si TFT with Dual Pull-down STRUCTURE", SICIETY FOR INFORMATION DISPLAY. 348-351 Binn Kim, et al. , "A-Si Gate Driver Integration with Time Shared Data Driving", Proceedings of The 12th International Display Workshops in Conjunction. 1073-1076 Mindoo Chun, et al. , "Integrated Gate Driver Using Highly Stable a-Si TFT's", Proceedings of The 12th International Display Workshops in junction with Asp. 1077-1080 Chun-Ching, et al. , “Integrated Gate Driver Using a-Si TFT”, Processeds of The 12th International Display Workshops in junction with Asia Disp. 5, 1023-1026 Yong Ho Jang, et al. , “A-Si TFT Integrated Gate Driver with AC-Driving Single Pull-Down Structure X, SOCIETY FOR INFORMATION DISPLAY TECHNO TECHNO TECHNO TECHN 208-211 Jin Young Choi, et al. , “A Compact and Cost-Efficient TFT-LCD through the Triple-Gate Pixel Structure II XOPIC TECHN TECHN TECHNO TECHN TECHN 274-276 Yong Soon Lee, et al. , "Advanced TFT-LCD Data Line Reduction Method", SOCIETY FOR INFORMATION DISPLAY 2006 INTERNIONAL SYMPOSIUM DIGITAL OF TECHNICAL PAPERS, X. 1083-1086

According to the conventional technique, the shift of the threshold voltage of the transistor is suppressed by applying an AC pulse to the gate of the transistor that is easily deteriorated. However, when amorphous silicon is used as the semiconductor layer of the transistor, it is a problem that the transistor constituting the circuit that generates the AC pulse also causes a threshold voltage shift.
In addition, it has been proposed to reduce the number of contact points between the display panel and the driver IC by reducing the number of signal lines to 1/3 (Non-Patent Document 6 and Non-Patent Document 7). There is a need to further reduce the number of IC contacts.

That is, as a problem that cannot be solved by the conventional technique, a circuit technique that suppresses the fluctuation of the threshold voltage of the transistor remains as a problem. A technique for reducing the number of contact points of a driver IC mounted on a display panel remains as a problem. Lowering power consumption of display devices remains a problem. There remains a problem of enlargement or high definition of the display device.

An object of the invention disclosed in this specification is to provide an industrially useful technique by solving one or more of these problems.

The display device according to the present invention inputs a signal to the gate electrode of a transistor that is easily deteriorated through the turned-on transistor, thereby shifting the threshold voltage of the transistor that is easily deteriorated and the threshold voltage of the turned-on transistor. This suppresses the shift. That is,
The present invention includes a configuration in which an AC pulse is applied to a gate electrode of a transistor that easily deteriorates through a transistor to which a high potential (VDD) is applied to the gate electrode (or through an element having a resistance component). .

The switch described in this specification can be used in various forms. Examples include electrical switches and mechanical switches. That is, it is only necessary to be able to control the current flow, and is not limited to a specific one. For example, as a switch, a transistor (for example,
Bipolar transistor, MOS transistor, etc.), diode (for example, PN diode, PIN diode, Schottky diode, MIM (Metal Insult)
orMetal) diode, MIS (Metal Insulator Semiconductor)
uctor) diodes, diode-connected transistors, etc.), thyristors, etc. can be used. Alternatively, a logic circuit combining these can be used as a switch.

In the case where a transistor is used as a switch, the transistor operates as a mere switch, and thus the polarity (conductivity type) of the transistor is not particularly limited. However, when it is desired to suppress off-state current, it is desirable to use a transistor having a polarity with smaller off-state current. As a transistor with low off-state current, a transistor having an LDD region, a transistor having a multi-gate structure, and the like can be given. Alternatively, in the case where the transistor operates as a switch with a source terminal potential close to a low potential power source (VSS, GND, 0 V, or the like), an N-channel transistor is preferably used. On the other hand, the potential of the source terminal is
When operating in a state close to a high-potential side power supply (VDD or the like), it is desirable to use a P-channel transistor. This is because when the N-channel transistor operates with the source terminal close to the low-potential side power supply, and the P-channel transistor operates with the source terminal close to the high-potential side power supply, the absolute value of the gate-source voltage is Since it can be increased, the switching characteristics are improved. Moreover, since the source follower operation is rarely performed, the output voltage is rarely reduced.

A CMOS switch may be used as a switch by using both an N-channel transistor and a P-channel transistor. When a CMOS switch is used, a current flows when one of the P-channel transistor and the N-channel transistor is turned on, so that the switch can easily function as a switch. For example, the voltage can be appropriately output regardless of whether the voltage of the input signal to the switch is high or low. Furthermore, since the voltage amplitude value of the signal for turning on / off the switch can be reduced, the power consumption can be reduced.

When a transistor is used as a switch, the switch includes an input terminal (one of a source terminal or a drain terminal), an output terminal (the other of the source terminal or the drain terminal), and a terminal (gate terminal) that controls conduction. Yes. On the other hand, when a diode is used as the switch, the switch may not have a terminal for controlling conduction. Therefore, the use of a diode as a switch rather than a transistor can reduce the wiring for controlling the terminal.

In this specification, when “A and B are connected” is explicitly described, A and B are electrically connected and A and B are functionally connected. And the case where A and B are directly connected. Here, A and B are objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.). Therefore, the configuration disclosed in this specification is not limited to a predetermined connection relationship, for example, the connection relationship illustrated in the drawing or text, and includes other than the connection relationship illustrated in the drawing or text.

For example, when A and B are electrically connected, an element (for example, a switch, a transistor, a capacitor, an inductor, a resistance element, a diode, or the like) that enables electrical connection between A and B is provided. 1 or more may be arranged between A and B. Alternatively, when A and B are functionally connected, a circuit (for example, a logic circuit (an inverter, a NAND circuit, a NOR circuit, etc.), a signal conversion circuit that enables functional connection between A and B (DA conversion circuit, AD conversion circuit, gamma correction circuit, etc.), potential level conversion circuit (power supply circuit (boost circuit,
Step-down circuit), level shifter circuit that changes signal potential level), voltage source, current source,
Switching circuit, amplifier circuit (circuit that can increase signal amplitude or current, etc., operational amplifier,
One or more differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation circuits, memory circuits, control circuits, etc.) may be arranged between A and B. Alternatively, when A and B are directly connected, A and B without interposing other elements or other circuits between A and B.
And may be directly connected.

When it is explicitly described that “A and B are directly connected”, when A and B are directly connected (that is, another element or other circuit is connected between A and B). And A and B are electrically connected (that is, A and B are connected with another element or circuit sandwiched between them). Case).

When it is explicitly described that “A and B are electrically connected”, when A and B are electrically connected (that is, another element or When connected with another circuit) and when A and B are functionally connected (that is, functionally connected with another circuit between A and B) Case) and a case where A and B are directly connected (that is, a case where another element or another circuit is not connected between A and B). That is, when it is explicitly described that it is electrically connected, it is the same as when it is explicitly only described that it is connected.

A display element, a display device that includes a display element, a light-emitting element, and a light-emitting device that includes a light-emitting element can have various modes or have various elements. For example, as a display element, a display device, a light-emitting element, or a light-emitting device, an EL element (an organic EL element or an inorganic EL element) can be used.
Element or EL element including organic and inorganic substances), electron emission element, liquid crystal element, electronic ink, electrophoretic element, grating light valve (GLV), plasma display (PDP)
In addition, a display medium whose contrast, luminance, reflectance, transmittance, or the like is changed by an electromagnetic action, such as a digital micromirror device (DMD), a piezoelectric ceramic display, or a carbon nanotube, can be used. As a display device using an EL element, E
As a display device using an L display or an electron-emitting device, a field emission display (FED) or a SED type flat display (SED: Surface-cond)
Liquid crystal displays (transmission type liquid crystal display, transflective type liquid crystal display, reflective type liquid crystal display, direct view type liquid crystal display, projection type liquid crystal display), electronic ink and electrophoresis as display devices using liquid crystal elements such as action Electron-emitter Display There is electronic paper as a display device using an element.

Various types of transistors can be used as the transistor described in this specification. Thus, there is no limitation on the type of transistor used. For example, a thin film transistor (TFT) including a non-single-crystal semiconductor film typified by amorphous silicon, polycrystalline silicon, microcrystalline (also referred to as semi-amorphous) silicon, or the like can be used. When using TFT, there are various advantages. For example, since it can be manufactured at a temperature lower than that of single crystal silicon, the manufacturing cost can be reduced and the manufacturing apparatus can be enlarged. Since the manufacturing apparatus can be enlarged, it can be manufactured on a large substrate. Therefore, since a large number of display devices can be manufactured at the same time, it can be manufactured at low cost. Furthermore, since the manufacturing temperature is low, a substrate with low heat resistance can be used. Therefore, a transistor can be manufactured on a transparent substrate. Then, light transmission through the display element can be controlled using a transistor over a transparent substrate. Alternatively, since the thickness of the transistor is small, part of the film included in the transistor can transmit light. Therefore, the aperture ratio can be improved.

By using a catalyst (such as nickel) when manufacturing polycrystalline silicon, it is possible to further improve crystallinity and to manufacture a transistor with good electrical characteristics. as a result,
A gate driver circuit (scanning line driving circuit), a source driver circuit (signal line driving circuit), and a signal processing circuit (signal generation circuit, gamma correction circuit, DA conversion circuit, etc.) can be integrally formed on the substrate.

By using a catalyst (such as nickel) when manufacturing microcrystalline silicon, it is possible to further improve crystallinity and to manufacture a transistor with good electrical characteristics. At this time,
Crystallinity can be improved simply by applying heat treatment without using a laser. As a result, a part of the gate driver circuit (scanning line driver circuit) and the source driver circuit (analog switch or the like) can be integrally formed on the substrate. Further, when a laser is not used for crystallization, unevenness in crystallinity of silicon can be suppressed. Therefore, a beautiful image can be displayed.

However, it is possible to produce polycrystalline silicon or microcrystalline silicon without using a catalyst (such as nickel).

Alternatively, a transistor can be formed using a semiconductor substrate, an SOI substrate, or the like. In that case, a MOS transistor, a junction transistor, a bipolar transistor, or the like can be used as the transistor described in this specification. Accordingly, a transistor with small variations in characteristics, size, shape, and the like, high current supply capability, and small size can be manufactured. When these transistors are used, a circuit with low power consumption can be formed, or high integration can be achieved.

Alternatively, a transistor having a compound semiconductor or an oxide semiconductor such as ZnO, a-InGaZnO, SiGe, GaAs, IZO, ITO, or SnO, or a thin film transistor in which these compound semiconductor or oxide semiconductor is thinned can be used. I can do it. Accordingly, the manufacturing temperature can be lowered, and for example, the transistor can be manufactured at room temperature. As a result, the transistor can be formed directly on a substrate having low heat resistance, such as a plastic substrate or a film substrate. These compound semiconductors or oxide semiconductors are
It can be used not only for the channel portion of the transistor but also for other purposes. For example, these compound semiconductors or oxide semiconductors can be used as resistance elements, pixel electrodes, and transparent electrodes. Further, they can be formed or formed at the same time as the transistor, so that cost can be reduced.

Alternatively, a transistor formed using an inkjet method or a printing method can be used. By these, manufacture at room temperature, manufacture at a low vacuum degree, or manufacture on a large substrate can be performed. Moreover, since it becomes possible to manufacture without using a mask (reticle),
The transistor layout can be easily changed. Furthermore, since it is not necessary to use a resist, the material cost is reduced and the number of processes can be reduced. Further, since a film is formed only on a necessary portion, the material is not wasted and cost can be reduced as compared with a manufacturing method in which etching is performed after film formation on the entire surface.

Alternatively, a transistor including an organic semiconductor or a carbon nanotube can be used. Thus, a transistor can be formed over a substrate that can be bent.
Therefore, it can be strong against impact.

In addition, various transistors can be used.

Various types of substrates can be used for forming the transistor, and the substrate is not limited to a specific type. As a substrate on which a transistor is formed, for example, a single crystal substrate, an SOI substrate, a glass substrate, a quartz substrate, a plastic substrate, a paper substrate, a cellophane substrate,
Stone substrate, wood substrate, cloth substrate (including natural fiber (silk, cotton, hemp), synthetic fiber (nylon, polyurethane, polyester) or recycled fiber (acetate, cupra, rayon, recycled polyester)), leather substrate, rubber A substrate, a stainless steel / still substrate, a substrate having stainless steel / still / foil, or the like can be used. Or the skin of animals such as humans (
(Skin surface, dermis) or subcutaneous tissue may be used as the substrate. Alternatively, a transistor may be formed over a certain substrate, and then the transistor may be transferred to another substrate, and the transistor may be disposed over another substrate. As a substrate to which the transistor is transferred, a single crystal substrate, an SOI substrate, a glass substrate, a quartz substrate, a plastic substrate, a paper substrate, a cellophane substrate, a stone substrate, a wood substrate,
Fabric substrate (natural fibers (silk, cotton, hemp), synthetic fibers (nylon, polyurethane, polyester)
Or recycled fibers (including acetate, cupra, rayon, recycled polyester)
Leather substrates, rubber substrates, stainless steel / still substrates, substrates having stainless steel / still foils, and the like can be used. Alternatively, the skin (skin surface, dermis) or subcutaneous tissue of an animal such as a human may be used as the substrate. By using these substrates, it is possible to form a transistor with good characteristics, a transistor with low power consumption, manufacture a device that is not easily broken, impart heat resistance, or reduce weight.

The structure of the transistor can take various forms. It is not limited to a specific configuration. For example, a multi-gate structure having two or more gate electrodes may be used. When the multi-gate structure is employed, the channel regions are connected in series, so that a plurality of transistors are connected in series. With the multi-gate structure, the off-state current can be reduced and the reliability can be improved by improving the withstand voltage of the transistor. Alternatively, when operating in the saturation region, even if the drain-source voltage changes, the current between the drain and source does not change so much, and the slope of the voltage / current characteristic can be made flat. By using a characteristic in which the slope of the voltage-current characteristic is flat, an ideal current source circuit and an active load having a very high resistance value can be realized. As a result, a differential circuit or a current mirror circuit with good characteristics can be realized.
Alternatively, a structure in which gate electrodes are arranged above and below the channel may be employed. By employing a structure in which gate electrodes are arranged above and below the channel, the channel region increases, so that the current value can be increased. Alternatively, a depletion layer can be easily formed and the S value can be reduced. When gate electrodes are provided above and below a channel, a structure in which a plurality of transistors are connected in parallel is obtained.

Alternatively, a structure in which a gate electrode is disposed over a channel region may be employed, or a structure in which a gate electrode is disposed under a channel region may be employed. Alternatively, a normal stagger structure or an inverted stagger structure may be used, the channel region may be divided into a plurality of regions, the channel regions may be connected in parallel, or the channel regions may be connected in series. Good. Also,
A source electrode or a drain electrode may overlap with the channel region (or a part thereof).
With the structure in which the source electrode or the drain electrode overlaps with the channel region (or part thereof), it is possible to prevent electric charges from being accumulated in part of the channel region and unstable operation. Further, an LDD region may be provided. By providing the LDD region, the off-state current can be reduced and the reliability can be improved by improving the withstand voltage of the transistor. Alternatively, when operating in the saturation region, even if the voltage between the drain and the source changes, the current between the drain and the source does not change so much, and the slope of the voltage-current characteristic can be made flat.

In this specification, one pixel represents the minimum unit of an image. Therefore, R (red) G
In the case of a full-color display device composed of (green) B (blue) color elements, one pixel is composed of R color element dots, G color element dots, and B color element dots. And Note that the color elements are not limited to three colors, and three or more colors may be used, or colors other than RGB may be used. For example, RGBW (W is white) may be added by adding white. Further, one or more colors such as yellow, cyan, magenta, emerald green, vermilion, and the like may be added to RGB. Alternatively, for example, a color similar to at least one of RGB may be added to RGB. For example, R, G, B1, and B2 may be used. B1 and B2 are both blue, but have slightly different frequencies. Similarly, R1, R2, G, and B may be used. By using such color elements, it is possible to perform display closer to the real thing or to reduce power consumption. A single pixel may have a plurality of dots of the same color element.
At that time, the plurality of color elements may have different sizes of regions contributing to display. Further, gradation may be expressed by controlling a plurality of dots of the same color element. This is called an area gradation method. Alternatively, the viewing angle may be widened by using a plurality of dots of the same color and using slightly different signals to be supplied to the dots. That is, a plurality of pixel electrodes having the same color element may have different potentials. As a result, the voltage applied to the liquid crystal molecules is different for each pixel electrode. Therefore, the viewing angle can be widened.

In this specification, one pixel represents one element whose brightness can be controlled. Therefore, as an example, one pixel represents one color element, and brightness is expressed by one color element. Therefore, at that time, in the case of a color display device composed of R (red), G (green), and B (blue) color elements, the minimum unit of an image is an R pixel, a G pixel, and a B pixel. It is assumed to be composed of three pixels. Note that the color elements are not limited to three colors, and three or more colors may be used, or colors other than RGB may be used. For example, RGBW (W is white) may be added by adding white. Further, one or more colors such as yellow, cyan, magenta, emerald green, vermilion, and the like may be added to RGB. Further, for example, a color similar to at least one of RGB may be added to RGB. For example, R, G, B1, and B2 may be used. B1 and B
Both are blue, but have slightly different frequencies. Similarly, R1, R2, G,
B may be used. By using such color elements, it is possible to perform display closer to the real thing or to reduce power consumption. As another example, when brightness is controlled using a plurality of areas for one color element, one area may be used as one pixel. Therefore, as an example, when area gradation is performed or when sub-pixels (sub-pixels) are provided, there are a plurality of brightness control areas for one color element, and the gradation is expressed as a whole. However, one pixel for controlling the brightness may be one pixel. Therefore, in that case, one color element is composed of a plurality of pixels. Alternatively, even if there are a plurality of areas for controlling the brightness in one color element, they may be combined into one pixel. Therefore, in that case, one color element is composed of one pixel. When brightness is controlled using a plurality of areas for one color element, the size of the area contributing to display may be different depending on the pixel. In addition, in a plurality of brightness control areas for one color element, a signal supplied to each may be slightly different to widen the viewing angle. That is, for one color element, the potentials of the pixel electrodes in each of a plurality of regions may be different from each other. As a result, the voltage applied to the liquid crystal molecules is different for each pixel electrode. Therefore, the viewing angle can be widened.

When it is explicitly described as one pixel (for three colors), it is assumed that three pixels of R, G, and B are considered as one pixel. When it is explicitly described as one pixel (for one color), it is assumed that when there are a plurality of areas for one color element, they are considered as one pixel.

In this specification, pixels may be arranged (arranged) in a matrix. Here, the pixel being arranged (arranged) in the matrix includes a case where the pixels are arranged in a straight line or a jagged line in the vertical direction or the horizontal direction. For example, when full color display is performed with three color elements (for example, RGB), the case where stripes are arranged and the case where dots of three color elements are arranged in a delta are included. further,
Including cases where Bayer is arranged. Note that the color elements are not limited to three colors, and may be more than that, for example, RGBW (W is white) or RGB in which one or more colors of yellow, cyan, magenta, etc. are added. Further, the size of the display area may be different for each dot of the color element. Thereby, power consumption can be reduced. Alternatively, the lifetime of the display element can be extended.

In this specification, an active matrix method in which an active element is included in a pixel or a passive matrix method in which an active element is not included in a pixel can be used.

In the active matrix system, not only transistors but also various active elements (active elements and nonlinear elements) can be used as active elements (active elements and nonlinear elements). For example, MIM (Metal Insulator Metal) or TFD (Th
inFilmDiode) or the like can also be used. These elements can be manufactured at low cost because they have few manufacturing processes. Alternatively, the yield can be increased. Furthermore, since the size of the element is small, the aperture ratio can be improved, and low power consumption and high luminance can be achieved.

Active elements (active elements, non-linear elements) other than active matrix systems
It is also possible to use a passive matrix type that does not use. Since no active element (active element or nonlinear element) is used, the number of manufacturing steps is small, and the manufacturing can be performed at low cost.
Alternatively, the yield can be increased. In addition, since an active element (an active element or a non-linear element) is not used, the aperture ratio can be improved, and low power consumption and high luminance can be achieved.

A transistor is an element having at least three terminals including a gate, a drain, and a source, has a channel region between the drain region and the source region, and includes the drain region, the channel region, and the source region. Current can be passed through. Here, since the source and the drain vary depending on the structure and operating conditions of the transistor, it is difficult to limit which is the source or the drain. Therefore, in this specification, a region functioning as a source and a drain may not be referred to as a source or a drain. In that case, as an example, there are cases where they are referred to as a first electrode and a second electrode, respectively.

The transistor may be an element having at least three terminals including a base, an emitter, and a collector. Similarly in this case, the emitter and the collector may be referred to as a first terminal and a second terminal.

A gate refers to the whole or part of a gate electrode and a gate wiring (also referred to as a gate line, a gate signal line, a scanning line, a scanning signal line, or the like). A gate electrode refers to a portion of a conductive film that overlaps with a semiconductor forming a channel region with a gate insulating film interposed therebetween. Note that a part of the gate electrode is an LDD (Lightly Doped Dr.
ain) region or a source region and a drain region may overlap with a gate insulating film. A gate wiring refers to a wiring for connecting a gate electrode of each transistor or a connection between the gate electrode and another wiring.

However, there are portions (regions, conductive films, wirings, etc.) that also function as gate electrodes and function as gate wirings. Such a portion (region, conductive film, wiring, or the like) may be called a gate electrode or a gate wiring. That is, there is a region where the gate electrode and the gate wiring cannot be clearly distinguished. For example, when a part of the gate wiring extended and the channel region overlaps, the portion (region, conductive film, wiring, etc.) functions as a gate wiring, but also as a gate electrode It is functioning. Therefore, such a portion (region, conductive film, wiring, or the like) may be called a gate electrode or a gate wiring.

A portion (region, conductive film, wiring, or the like) that is formed using the same material as the gate electrode and is connected by forming the same island as the gate electrode may also be referred to as a gate electrode. Similarly, a portion (a region, a conductive film, a wiring, or the like) formed using the same material as the gate wiring and connected by forming the same island (island) as the gate wiring may be referred to as a gate wiring. Such a part (
(Region, conductive film, wiring, etc.) do not overlap with the channel region in the strict sense,
In some cases, it does not have a function of connecting to another gate electrode. However, it is made of the same material as the gate electrode or gate wiring, and is the same island (island) as the gate electrode or gate wiring.
There are portions (regions, conductive films, wirings, etc.) that are connected by forming. Such a portion (region, conductive film, wiring, or the like) may also be called a gate electrode or a gate wiring.

For example, in a multi-gate transistor, one gate electrode and another gate electrode are often connected by a conductive film formed using the same material as the gate electrode. Such a portion (region, conductive film, wiring, or the like) is a portion (region, conductive film, wiring, or the like) for connecting the gate electrode to the gate electrode, and may be called a gate wiring. These transistors can be regarded as a single transistor, and may be referred to as a gate electrode.
That is, a portion (region, conductive film, wiring, or the like) that is formed using the same material as the gate electrode or gate wiring and is connected to form the same island (island) as the gate electrode or gate wiring is connected to the gate electrode or gate wiring. You can call it. Further, for example, a conductive film in a portion where the gate electrode and the gate wiring are connected and formed of a material different from the gate electrode or the gate wiring may be referred to as a gate electrode. You may call it.

The gate terminal refers to a part of a portion of the gate electrode (region, conductive film, wiring, or the like) or a portion electrically connected to the gate electrode (region, conductive film, wiring, or the like).

In the case of calling a gate wiring, a gate line, a gate signal line, a scanning line, a scanning signal line, or the like, the gate of the transistor may not be connected to the wiring. In this case, the gate wiring, the gate line, the gate signal line, the scanning line, and the scanning signal line are formed using the same layer as the gate of the transistor,
It may mean a wiring formed of the same material as the gate of the transistor or a wiring formed at the same time as the gate of the transistor. Examples include a storage capacitor wiring, a power supply line, a reference potential supply wiring, and the like.

A source refers to the whole or a part of a source region, a source electrode, and a source wiring (also referred to as a source line, a source signal line, a data line, a data signal line, or the like). The source region refers to a semiconductor region containing a large amount of P-type impurities (such as boron and gallium) and N-type impurities (such as phosphorus and arsenic). Therefore, a region containing a little P-type impurity or N-type impurity, that is, a so-called LDD (Lightly Doped Drain) region is not included in the source region. A source electrode refers to a portion of a conductive layer which is formed using a material different from that of a source region and is electrically connected to the source region. However, the source electrode
The source region may be referred to as a source electrode. The source wiring is a wiring for connecting between the source electrodes of each pixel or connecting the source electrode to another wiring.

However, there are portions (regions, conductive films, wirings, and the like) that also function as source electrodes and function as source wirings. Such a portion (region, conductive film, wiring, or the like) may be called a source electrode or a source wiring. That is, there is a region where the source electrode and the source wiring cannot be clearly distinguished. For example, in the case where a part of a source wiring that is extended and the source region overlap with each other, the portion (region, conductive film, wiring, etc.) functions as a source wiring, but as a source electrode Will also work. Thus, such a portion (region, conductive film, wiring, or the like) may be called a source electrode or a source wiring.

A portion (region, conductive film, wiring, etc.) that is formed of the same material as the source electrode and forms the same island (island) as the source electrode, or a portion that connects the source electrode and the source electrode (region, conductive) Films, wirings, etc.) may also be called source electrodes. Further, a portion overlapping with the source region may be called a source electrode. Similarly, a region formed of the same material as the source wiring and connected by forming the same island as the source wiring may be called a source wiring. Such a portion (region, conductive film, wiring, or the like) may not have a function of connecting to another source electrode in a strict sense. But,
There is a portion (a region, a conductive film, a wiring, or the like) formed of the same material as the source electrode or the source wiring and connected to the source electrode or the source wiring. Therefore, such a portion (region, conductive film, wiring, or the like) may also be referred to as a source electrode or a source wiring.

For example, a conductive film in a portion where the source electrode and the source wiring are connected and formed of a material different from that of the source electrode or the source wiring may be called a source electrode.
You may call it source wiring.

A source terminal refers to a part of a source region, a source electrode, or a portion (region, conductive film, wiring, or the like) electrically connected to the source electrode.

In the case of calling a source wiring, a source line, a source signal line, a data line, a data signal line, or the like, the source (drain) of the transistor may not be connected to the wiring. In this case, the source wiring, the source line, the source signal line, the data line, and the data signal line are a wiring formed of the same layer as the source (drain) of the transistor and a wiring formed of the same material as the source (drain) of the transistor. Alternatively, it may mean a wiring formed simultaneously with the source (drain) of the transistor. Examples include a storage capacitor wiring, a power supply line, a reference potential supply wiring, and the like.

The drain is the same as the source.

A semiconductor device refers to a device having a circuit including a semiconductor element (a transistor, a diode, a thyristor, or the like). Furthermore, a device that can function by utilizing semiconductor characteristics may be called a semiconductor device.

Display elements include optical modulation elements, liquid crystal elements, light emitting elements, EL elements (organic EL elements, inorganic EL elements)
Element or EL element including organic and inorganic substances), electron-emitting device, electrophoretic device, discharge device,
It refers to a light reflection element, a light diffraction element, a digital micromirror device (DMD), and the like. However, it is not limited to this.

A display device refers to a device having a display element. Note that the display device may be a display panel body in which a plurality of pixels including display elements or a peripheral drive circuit for driving the pixels is formed over the same substrate. Note that the display device includes a peripheral drive circuit arranged on the substrate by wire bonding or bumps, an IC chip connected by so-called chip on glass (COG), or an IC chip connected by TAB or the like. May be. Note that the display device may include a flexible wiring board (FPC) to which an IC chip, a resistor element, a capacitor element, an inductor, a transistor, and the like are attached. Note that the display device may include a printed wiring board (PWB) connected via a flexible wiring board (FPC) or the like, to which an IC chip, a resistance element, a capacitor element, an inductor, a transistor, or the like is attached. Note that the display device may include an optical sheet such as a polarizing plate or a retardation plate. Note that the display device may include a lighting device, a housing, a voice input / output device, an optical sensor, and the like. Here, the illumination device such as the backlight unit may include a light guide plate, a prism sheet, a diffusion sheet, a reflection sheet, a light source (LED, cold cathode tube, etc.), a cooling device (water cooling type, air cooling type) and the like. good.

The lighting device refers to a device having a backlight unit, a light guide plate, a prism sheet, a diffusion sheet, a reflection sheet, a light source (LED, cold cathode tube, hot cathode tube, etc.), a cooling device, and the like.

Note that a light-emitting device refers to a device having a light-emitting element or the like.

The reflection device refers to a device having a light reflection element, a light diffraction element, a light reflection electrode, and the like.

A liquid crystal display device refers to a display device having a liquid crystal element. The liquid crystal display device has a direct view type,
There are a projection type, a transmission type, a reflection type, and a semi-transmission type.

A driving device refers to a device having a semiconductor element, an electric circuit, and an electronic circuit. For example, a transistor that controls input of a signal from a source signal line into a pixel (sometimes referred to as a selection transistor or a switching transistor), a transistor that supplies voltage or current to a pixel electrode, or a voltage or current to a light-emitting element A transistor that supplies the voltage is an example of a driving device. Further, a circuit for supplying a signal to the gate signal line (sometimes referred to as a gate driver or a gate line driver circuit), a circuit for supplying a signal to the source signal line (source driver,
(Sometimes referred to as a source line driver circuit) is an example of a driver.

In some cases, a display device, a semiconductor device, a lighting device, a cooling device, a light-emitting device, a reflecting device, a driving device, and the like overlap each other. For example, the display device may include a semiconductor device and a light-emitting device, or the semiconductor device may include a display device and a driving device.

In this specification, when B is formed on A or B is formed explicitly on A, B is formed on A in direct contact. It is not limited to that. The case where it is not in direct contact, that is, the case where another object is interposed between A and B is also included. Here, A and B are objects (for example, devices, elements, circuits, wirings, electrodes, terminals,
A conductive film, a layer, and the like.

Therefore, for example, when it is explicitly described that the layer B is formed on the layer A (or on the layer A), the layer B is formed in direct contact with the layer A. And the case where another layer (for example, layer C or layer D) is formed in direct contact with the layer A, and the layer B is formed in direct contact therewith. Note that another layer (for example, the layer C or the layer D) may be a single layer or a multilayer.

Furthermore, the same applies to the case where B is explicitly described as being formed above A, and is not limited to the direct contact of B on A. This includes the case where another object is interposed in. Therefore, for example, when the layer B is formed above the layer A, the case where the layer B is formed in direct contact with the layer A and the case where another layer is formed in direct contact with the layer A. (For example, the layer C, the layer D, etc.) are formed, and the layer B is formed in direct contact therewith. Note that another layer (for example, the layer C or the layer D) may be a single layer or a multilayer.

When it is explicitly stated that B is formed on A directly in contact with B, it includes a case where B is formed on A directly in contact with another object between A and B. It shall not be included in the case of intervening.

The same applies to the case where B is below A or B is below A.

Degradation of characteristics of all transistors included in the shift register can be suppressed. Therefore, malfunction of a semiconductor device to which the shift register such as a liquid crystal display device is applied can be suppressed.

3A and 3B illustrate a structure of a flip-flop described in Embodiment 1. 2 is a timing chart illustrating the operation of the flip-flop illustrated in FIG. 1. 3A and 3B illustrate operation of the flip-flop illustrated in FIG. 1. 3A and 3B illustrate a structure of a flip-flop described in Embodiment 1. 3A and 3B illustrate a structure of a flip-flop described in Embodiment 1. 3 is a timing chart illustrating operation of the flip-flop described in Embodiment 1; 3A and 3B illustrate a structure of a flip-flop described in Embodiment 1. 3A and 3B each illustrate a structure of a display device shown in Embodiment 1; 9 is a timing chart illustrating a writing operation of the display device illustrated in FIG. FIG. 5 illustrates a structure of a shift register shown in Embodiment 1; 11 is a timing chart illustrating operation of the shift register illustrated in FIG. 11 is a timing chart illustrating operation of the shift register illustrated in FIG. FIG. 5 illustrates a structure of a shift register shown in Embodiment 1; FIG. 5 illustrates a structure of a shift register shown in Embodiment 1; FIG. 5 illustrates a structure of a shift register shown in Embodiment 1; FIG. 6 illustrates a structure of a display device described in Embodiment 2; FIG. 5 illustrates a structure of a shift register shown in Embodiment 1; 3A and 3B each illustrate a structure of a display device shown in Embodiment 1; FIG. 19 is a timing chart illustrating a writing operation of the display device illustrated in FIG. 18. 3A and 3B each illustrate a structure of a display device shown in Embodiment 1; 3A and 3B illustrate a structure of a flip-flop described in Embodiment 1. FIG. 5 illustrates a structure of a flip-flop shown in Embodiment 2; FIG. 5 illustrates a structure of a flip-flop shown in Embodiment 4; 24 is a timing chart illustrating operation of the flip-flop illustrated in FIG. FIG. 2 is a top view of the flip-flop shown in FIG. 1. FIG. 14 is a diagram illustrating a configuration of a buffer illustrated in FIG. 13. 4A and 4B illustrate a structure of a flip-flop shown in Embodiment 3. 28 is a timing chart illustrating the operation of the flip-flop illustrated in FIG. FIG. 5 illustrates a structure of a shift register shown in Embodiment 3; 30 is a timing chart illustrating operation of the shift register illustrated in FIG. 6 is a timing chart illustrating operation of the flip-flop described in Embodiment 2. 6 is a timing chart illustrating operation of the flip-flop described in Embodiment 2. FIG. 5 illustrates a structure of a shift register described in Embodiment 2; FIG. 5 illustrates a structure of a shift register described in Embodiment 2; 34 is a timing chart illustrating operation of the shift register illustrated in FIG. 34 is a timing chart illustrating operation of the shift register illustrated in FIG. 7A and 7B illustrate a structure of a signal line driver circuit described in Embodiment 5. 38 is a timing chart illustrating operation of the signal line driver circuit illustrated in FIG. 7A and 7B illustrate a structure of a signal line driver circuit described in Embodiment 5. 40 is a timing chart illustrating operation of the signal line driver circuit illustrated in FIG. 7A and 7B illustrate a structure of a signal line driver circuit described in Embodiment 5. 7A and 7B illustrate a structure of a protection diode described in Embodiment 6. 7A and 7B illustrate a structure of a protection diode described in Embodiment 6. 7A and 7B illustrate a structure of a protection diode described in Embodiment 6. 8A and 8B illustrate a structure of a display device described in Embodiment 7. 2A and 2B are a pixel layout example and a cross-sectional view of a semiconductor device. 2A and 2B are a pixel layout example and a cross-sectional view of a semiconductor device. 2A and 2B are a pixel layout example and a cross-sectional view of a semiconductor device. 2A and 2B are a pixel layout example and a cross-sectional view of a semiconductor device. 2A and 2B are a pixel layout example and a cross-sectional view of a semiconductor device. Sectional drawing of the display element of a semiconductor device. Sectional drawing of the display element of a semiconductor device. Sectional drawing of the display element of a semiconductor device. FIG. 6 is a top view of a display element of a semiconductor device. FIG. 6 is a top view of a display element of a semiconductor device. FIG. 6 is a top view of a display element of a semiconductor device. FIG. 6 illustrates a peripheral circuit configuration of a semiconductor device. FIG. 6 illustrates a peripheral circuit configuration of a semiconductor device. 3A and 3B illustrate a panel circuit configuration of a semiconductor device. 3A and 3B illustrate a panel circuit configuration of a semiconductor device. FIG. 14 is a cross-sectional view of a semiconductor device. FIG. 6 illustrates a peripheral circuit configuration of a semiconductor device. FIG. 14 is a cross-sectional view of a semiconductor device. FIG. 14 is a cross-sectional view of a semiconductor device. FIG. 14 is a cross-sectional view of a semiconductor device. FIG. 14 is a cross-sectional view of a semiconductor device. FIG. 14 is a cross-sectional view of a semiconductor device. FIG. 14 is a cross-sectional view of a semiconductor device. FIG. 14 is a cross-sectional view of a semiconductor device. FIG. 14 is a cross-sectional view of a semiconductor device. FIG. 14 is a cross-sectional view of a semiconductor device. FIG. 14 is a cross-sectional view of a semiconductor device. FIG. 14 is a cross-sectional view of a semiconductor device. FIG. 14 is a cross-sectional view of a semiconductor device. FIG. 14 is a cross-sectional view of a semiconductor device. FIG. 14 is a cross-sectional view of a semiconductor device. FIG. 14 is a cross-sectional view of a semiconductor device. FIG. 14 is a cross-sectional view of a semiconductor device. FIG. 14 is a cross-sectional view of a semiconductor device. FIG. 14 is a cross-sectional view of a semiconductor device. FIG. 14 is a cross-sectional view of a semiconductor device. 10A and 10B illustrate a peripheral component member of a semiconductor device. FIG. 6 illustrates a peripheral circuit configuration of a semiconductor device. 10A and 10B illustrate a peripheral component member of a semiconductor device. 10A and 10B illustrate a peripheral component member of a semiconductor device. 10A and 10B illustrate a peripheral component member of a semiconductor device. 6A and 6B illustrate a semiconductor device. 8A and 8B illustrate one method for driving a semiconductor device. 8A and 8B illustrate one method for driving a semiconductor device. 8A and 8B illustrate one method for driving a semiconductor device. 8A and 8B illustrate one method for driving a semiconductor device. 2A and 2B are a pixel layout example and a cross-sectional view of a semiconductor device. 2A and 2B are a pixel layout example and a cross-sectional view of a semiconductor device. 2A and 2B are a pixel layout example and a cross-sectional view of a semiconductor device. Sectional drawing of the display element of a semiconductor device. 4A and 4B illustrate a device for forming a display element of a semiconductor device. 4A and 4B illustrate a device for forming a display element of a semiconductor device. 8A and 8B illustrate one method for driving a semiconductor device. 8A and 8B illustrate one method for driving a semiconductor device. FIG. 6 illustrates one pixel circuit of a semiconductor device. FIG. 6 illustrates one pixel circuit of a semiconductor device. 10A and 10B illustrate a process for manufacturing a semiconductor device. 4A and 4B illustrate a display element of a semiconductor device. 4A and 4B illustrate a display element of a semiconductor device. 6A and 6B illustrate a structure of a semiconductor device. 6A and 6B illustrate a structure of a semiconductor device. 6A and 6B illustrate a structure of a semiconductor device. 6A and 6B illustrate a structure of a semiconductor device. 6A and 6B illustrate a structure of a semiconductor device. 6A and 6B illustrate a structure of a semiconductor device. 6A and 6B illustrate a structure of a semiconductor device. 6A and 6B illustrate a structure of a semiconductor device. 6A and 6B illustrate a structure of a semiconductor device. 6A and 6B illustrate a structure of a semiconductor device. 6A and 6B illustrate a structure of a semiconductor device. 10A and 10B each illustrate an electronic device including a semiconductor device. 10A and 10B each illustrate an electronic device including a semiconductor device. 10A and 10B each illustrate an electronic device including a semiconductor device. 10A and 10B each illustrate an electronic device including a semiconductor device. 10A and 10B each illustrate an electronic device including a semiconductor device. 10A and 10B each illustrate an electronic device including a semiconductor device. 10A and 10B each illustrate an electronic device including a semiconductor device. FIG. 14 is a diagram illustrating a configuration of a buffer illustrated in FIG. 13. The figure explaining the structure and timing chart of the flip-flop of a prior art.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the present invention can be implemented in many different modes, and those skilled in the art can easily understand that the modes and details can be variously changed without departing from the spirit and scope of the present invention. Is done. Therefore, the present invention is not construed as being limited to the description of this embodiment mode.

(Embodiment 1)
In this embodiment, a structure and a driving method of a flip-flop, a driver circuit including the flip-flop, and a display device including the driver circuit are described.

A basic structure of the flip-flop of this embodiment is described with reference to FIG. 1 includes a first transistor 101, a second transistor 102, and a third transistor.
The transistor 103, the fourth transistor 104, the fifth transistor 105, the sixth transistor 106, and the seventh transistor 107 are included. In this embodiment, the first transistor 101, the second transistor 102, the third transistor 103, the fourth transistor
Transistor 104, fifth transistor 105, sixth transistor 106 and seventh transistor
The transistor 107 is an N-channel transistor and has a gate-source voltage (V
When gs) exceeds the threshold voltage (Vth), the conductive state is assumed.

A connection relation of the flip-flop of FIG. 1 will be described. First of the first transistor 101
Of the first transistor 101 is connected to the fifth wiring 125, and the second electrode of the first transistor 101 (the other of the source electrode and the drain electrode) is connected to the third wiring 12.
3 is connected. The first electrode of the second transistor 102 is connected to the fourth wiring 124, and the second electrode of the second transistor 102 is connected to the third wiring 123. The first electrode of the third transistor 103 is connected to the sixth wiring 126, the second electrode of the third transistor 103 is connected to the gate electrode of the second transistor 102, and the third transistor 1
The gate electrode 03 is connected to the seventh wiring 127. The first electrode of the fourth transistor 104 is connected to the ninth wiring 129, the second electrode of the fourth transistor 104 is connected to the gate electrode of the second transistor 102, and the gate of the fourth transistor 104 The electrode is connected to the gate electrode of the first transistor 101. The first electrode of the fifth transistor 105 is connected to the eighth wiring 128, the second electrode of the fifth transistor 105 is connected to the gate electrode of the first transistor 101, and the gate of the fifth transistor 105 The electrode is connected to the first wiring 121. The first electrode of the sixth transistor 106 is the tenth wiring 1
30, the second electrode of the sixth transistor 106 is connected to the gate electrode of the first transistor 101, and the gate electrode of the sixth transistor 106 is connected to the second transistor 1.
02 is connected to the gate electrode. The first electrode of the seventh transistor 107 is connected to the eleventh wiring 131, and the second electrode of the seventh transistor 107 is connected to the first transistor 101.
The gate electrode of the seventh transistor 107 is connected to the second wiring 122.

Note that the gate electrode of the first transistor 101, the gate electrode of the fourth transistor 104, the second electrode of the fifth transistor 105, the second electrode of the sixth transistor 106, and the second electrode of the seventh transistor 107 The electrode 141 is connected to a node 141. In addition, the second
A connection portion of the gate electrode of the transistor 102, the second electrode of the third transistor 103, the second electrode of the fourth transistor 104, and the gate electrode of the sixth transistor 106 is a node 142.

Note that the fourth wiring 124, the ninth wiring 129, the tenth wiring 130, and the eleventh wiring 13 are used.
1 may be connected to each other or the same wiring. Further, the seventh wiring 127 and the eighth wiring 128 may be connected to each other or the same wiring.

Note that the first wiring 121, the second wiring 122, the third wiring 123, the fifth wiring 125, and the sixth wiring 126 are respectively connected to the first signal line, the second signal, and the third signal line. , A fourth signal line and a fifth signal line. Further, the fourth wiring 124, the seventh wiring 127, the eighth wiring 128, the ninth wiring 129, the tenth wiring 130, and the eleventh wiring 131 are respectively connected to the first power supply line and the second power supply. May be called a line, a third power line, a fourth power line, a fifth power line, and a sixth power line.

Note that the seventh wiring 127 and the eighth wiring 128 are supplied with the potential of V1, respectively.
The wiring 124, the ninth wiring 129, the tenth wiring 130, and the eleventh wiring 131 are supplied with the potential of V2. Furthermore, V1> V2.

Note that signals are input to the first wiring 121, the second wiring 122, the fifth wiring 125, and the sixth wiring 126, respectively. The signal input to the first wiring 121 is a start signal, the signal input to the second wiring 122 is a reset signal, and the signal input to the fifth wiring 125 is a first clock signal. The signal input to the sixth wiring 126 is the second clock signal. Further, the signal inputted to each of the first wiring 121, the second wiring 122, the fifth wiring 125, and the sixth wiring 126 has an H signal potential of V1 (hereinafter also referred to as an H level), and an L signal. Is a digital signal whose potential is V2 (hereinafter also referred to as L level).

Note that various signals, potentials, and currents may be input to the first wiring 121, the second wiring 122, and the second wiring 122 to the eleventh wiring 131, respectively.

Note that a signal is output from the third wiring 123. A signal output from the third wiring 123 is an output signal of the flip-flop of each stage, and is also a start signal (hereinafter also referred to as a transfer signal) of the flip-flop of the next stage. Further, the signal output from the third wiring 123 has an H signal potential of V1 (hereinafter also referred to as H level) and an L signal potential of V2.
It is a digital signal (hereinafter also referred to as L level).

Next, the operation of the flip-flop shown in FIG. 1 will be described with reference to the timing chart of FIG. 2 and FIG. Further, the timing chart of FIG. 2 will be described by being divided into a selection period and a non-selection period. Further, the non-selection period will be described by being divided into a first non-selection period, a second non-selection period, a set period, and a reset period. Furthermore, in the non-selection period, the set period,
In the operation period excluding the selection period and the reset period, the first non-selection period and the second non-selection period are sequentially repeated.

Note that in FIG. 2, a signal 221, a signal 225, a signal 226, a potential 241, a potential 242,
The signals 222 and 223 are a signal input to the first wiring 121, a signal input to the fifth wiring 125, a signal input to the sixth wiring 126, the potential of the node 141, and the potential of the node 142, respectively. , A signal input to the second wiring 122 and a signal output from the third wiring 123 are shown.

First, in the set period shown in FIGS. 2A and 3A, since the signal 221 is H level, the fifth transistor 105 is turned on, and since the signal 222 is L level, the seventh transistor 107 is turned off. At this time, the potential of the node 141 is the second potential of the fifth transistor 105.
Since the source electrode becomes the source electrode and becomes the value obtained by subtracting the threshold voltage of the fifth transistor 105 from the potential of the eighth wiring 128, V1-Vth (105) (Vth (105): fifth transistor 105 threshold voltage). Accordingly, the first transistor 101 and the fourth transistor 104 are turned on, and the fifth transistor 105 is turned off. At this time, the potential of the node 142 (the potential 242) is the same as that of the third transistor 103 and the fourth transistor 1.
It is determined by the resistance ratio (L / W and applied voltage) to 04, and becomes V2 + β (β: any positive number). Further, β <Vth (102) (Vth (102): second transistor 10
2) and β <Vth (106) (threshold voltage of the sixth transistor 106). That is, the potential (V2) of the ninth wiring 129 and the potential (V1) of the sixth wiring 126
) (V1−V2) from the third transistor 103 and the fourth transistor 104.
Is divided by. Therefore, the second transistor 102 and the sixth transistor 106
Turns off. In this manner, in the set period, the third wiring 123 is electrically connected to the fifth wiring 125 to which the L signal is input, and thus the potential of the third wiring 123 is V2. Therefore,
The L signal is output from the third wiring 123. Further, the node 141 has a potential of V1-Vt.
The floating state is maintained while maintaining h (105).

In the selection period shown in FIGS. 2B and 3B, since the signal 221 becomes L level and the fifth transistor 105 is turned off and the signal 222 remains L level, the seventh transistor 10
7 remains off. At this time, the potential of the node 141 is maintained at V1-Vth (105). Therefore, the first transistor 101 and the fourth transistor 104 remain on. The potential of the node 142 at this time is V since the sixth wiring 126 is at the L level.
2 Accordingly, the second transistor 102 and the sixth transistor 106 remain off. Here, since the H signal is input to the fifth wiring 125, the potential of the third wiring 123 starts to increase. At this time, the potential of the node 141 is changed to V by the bootstrap operation.
The voltage rises from 1−Vth (105) and becomes V1 + Vth (101) + α (Vth (101): threshold voltage of the first transistor 101, α: any positive number). Therefore, the third
Since the potential of the wiring 123 is equal to the potential of the fifth wiring 125, it becomes V1. Note that this bootstrap operation is performed by capacitive coupling of parasitic capacitance between the gate electrode and the second electrode of the first transistor 101. Thus, in the selection period, the third wiring 123
Is electrically connected to the fifth wiring 125 to which the H signal is input, so that the potential of the third wiring 123 becomes V1. Therefore, the H signal is output from the third wiring 123.

In the reset period illustrated in FIGS. 2C and 3C, since the signal 221 remains at the L level, the fifth transistor 105 remains off, and the signal 222 becomes the H level. Turns on. At this time, the potential of the node 141 is the potential of the eleventh wiring (
Since V2) is supplied through the seventh transistor 107, it becomes V2. Accordingly, the first transistor 101 and the fourth transistor 104 are turned off. Node 142 at this time
, The second electrode of the third transistor 103 serves as a source electrode, and the sixth wiring 1
Therefore, V1−Vth (103) (Vth (103): threshold voltage of the third transistor 103) is obtained by subtracting the threshold voltage of the third transistor 103 from the potential 26 (V1). Accordingly, the second transistor 102 and the sixth transistor 106 are turned on. Thus, in the reset period, the third wiring 123 is electrically connected to the fourth wiring 124 to which V2 is supplied, so that the potential of the third wiring 123 becomes V2. Therefore, the L signal is output from the third wiring 123.

In the first non-selection period shown in FIGS. 2D and 3D, since the signal 221 remains at the L level, the fifth transistor 105 remains off, and the signal 222 becomes the L level. 7
The transistor 107 is turned off. At this time, the potential of the node 142 is the sixth wiring 126.
Since the L signal is input to V2, it becomes V2. Accordingly, the second transistor 102 and the sixth transistor 106 are turned off. Since the node 141 at this time is in a floating state, the potential is V
2 is maintained. Accordingly, the first transistor 101 and the fourth transistor 104 remain off. Thus, in the first non-selection period, the third wiring 123 is in a floating state, so that the potential of the third wiring 123 maintains V2.

In the second non-selection period shown in FIGS. 2E and 3E, since the signal 221 remains at the L level, the fifth transistor 105 remains off and the signal 222 remains at the L level. 7 transistor 107 remains off. The potential of the node 142 at this time is the sixth
Since the H signal is input to the wiring 126 and the transistor 104 is off, V1-Vth
(103). Accordingly, the second transistor 102 and the sixth transistor 106 are turned on. At this time, the potential of the node 141 is the same as that of the tenth wiring 130 (V2).
Since it is supplied via the transistor 106, it remains at V2. Accordingly, the first transistor 101 and the fourth transistor 104 remain off. In this manner, in the second non-selection period, the third wiring 123 is electrically connected to the fourth wiring 124 to which V2 is supplied, so that the potential of the third wiring 123 remains V2. Therefore, the L signal is output from the third wiring 12.
3 is output.

From the above, in the flip-flop in FIG. 1, the potential of the third wiring 123 is set to V1 by setting the potential of the node 141 higher than V1 + Vth (101) by using the bootstrap operation in the selection period. be able to. Further, in the flip-flop of FIG. 1, the bootstrap operation is performed using the capacitive coupling of the parasitic capacitance between the second electrode and the gate electrode of the first transistor 101, thereby reducing the layout area and the element. Advantages such as reduction of the number can be obtained.

Further, since the second transistor 102 and the sixth transistor 106 are turned on only in the second non-selection period, the flip-flop in FIG. 1 has the threshold voltage of the second transistor 102 and the sixth transistor 106. Shift can be suppressed.

Note that the flip-flop in FIG. 1 supplies V1 to the gate electrode of the third transistor 103 and inputs the second clock signal to the first electrode, whereby the threshold voltage of the third transistor 103 is increased. Shifts can also be suppressed.

Further, the flip-flop in FIG. 1 includes a first transistor 101 and a fourth transistor 1.
04, since the fifth transistor 105 and the seventh transistor 107 are not turned on in the first non-selection period and the second non-selection period, the first transistor 101, the fourth transistor 104, the fifth transistor 105, and A shift in threshold voltage of the seventh transistor 107 can be suppressed.

Further, in the flip-flop in FIG. 1, even if the potential of the node 141 and the potential of the third wiring 123 fluctuate in the first non-selection period, the node 141 and the third wiring in the next second non-selection period. By supplying V2 to 123, the potential of the node 141 and the potential of the third wiring 123 can be reset to V2. Accordingly, the flip-flop in FIG. 1 can suppress malfunction caused by the fluctuation of the potential of the node 141 and the third wiring 123 due to the floating state of the node 141 and the wiring 123.

Furthermore, since the flip-flop in FIG. 1 can suppress the threshold shift of the transistor,
A malfunction caused by a threshold voltage shift of the transistor can be suppressed.

Further, in the flip-flop in FIG. 1, the first transistor 101 to the seventh transistor 107 are all N-channel transistors. Accordingly, the flip-flop in FIG. 1 can use amorphous silicon as a semiconductor layer of a transistor, so that the manufacturing process can be simplified, and manufacturing cost can be reduced and yield can be improved. Further, a large display device can be manufactured. However, the manufacturing process can be simplified even if polysilicon or polycrystalline silicon is used for the semiconductor layer of the transistor.

Note that the flip-flop in FIG. 1 can suppress deterioration in characteristics of a transistor even when amorphous silicon whose characteristics are deteriorated (shift in threshold voltage) is used as a semiconductor layer of the transistor. A display device can be manufactured.

Here, functions of the first transistor 101 to the eighth transistor 108 are described. The first transistor 101 has a function of selecting the timing at which the potential of the fifth wiring 125 is supplied to the third wiring 123 and increasing the potential of the node 141 by a bootstrap operation, and functions as a bootstrap transistor. To do. Second transistor 10
2 has a function of selecting timing for supplying the potential of the fourth wiring 124 to the third wiring 123 and functions as a switching transistor. The third transistor 103 is the sixth transistor
The potential of the first wiring and the potential of the ninth wiring 129 are divided and function as a resistor or a transistor having a resistance component. The fourth transistor 104 includes a ninth wiring 129.
Has a function of selecting the timing of supplying the potential to the node 142 and functions as a switching transistor. The fifth transistor has a function of selecting timing for supplying the potential of the eighth wiring to the node 141 and functions as an input transistor. The sixth transistor 106 has a function of selecting timing for supplying the potential of the tenth wiring 130 to the node 141 and functions as a switching transistor. Seventh transistor 10
7 has a function of selecting the timing at which the potential of the eleventh wiring 131 is supplied to the node 141, and functions as a switching transistor. Note that the first transistor 101 to the seventh transistor 107 are not limited to transistors as long as they have the functions described above. For example, the second transistor 102 functioning as a switching transistor
, Fourth transistor 104, sixth transistor 106, and seventh transistor 107
As long as the element has a switching function, a diode, a CMOS analog switch, or various logic circuits may be applied. Further, the fifth transistor 105 that functions as an input transistor only needs to have a function of selecting the timing of turning off by increasing the potential of the node 141. A PN junction diode or a diode-connected transistor is used as the fifth transistor 105. Also good.

Note that the third transistor 103 and the fourth transistor 104 form an AC pulse generation circuit. The AC pulse generation circuit outputs a signal input from the first electrode of the third transistor 103 to the node 142. However, when the gate electrode of the fourth transistor 104 is at the H level, the AC pulse generation circuit outputs an L signal to the node 142 regardless of a signal input from the first electrode of the third transistor 103.

Note that in the flip-flop of this embodiment, the W / L value of the first transistor 101 is maximized among the W / L values of the first transistor 101 to the seventh transistor 107. Then, the fall time and rise time of the signal 223 can be shortened. Accordingly, even when a large load is connected to the wiring 123, the flip-flop of this embodiment can output a signal with less rounding and delay.

Further, in the flip-flop of this embodiment, W / L of the first transistor 101
The value of is preferably 2 to 5 times, more preferably 3 to 4 times the value of W / L of the fifth transistor 105. Thus, even when a large load is connected to the wiring 123, the flip-flop in Embodiment 1 can output a signal with less rounding and delay.

Further, in the flip-flop of this embodiment, W / L of the fourth transistor 104
Is larger than the W / L value of the third transistor 103, the potential of the node 142 in the set period can be reduced. Accordingly, the flip-flop of this embodiment can surely turn off the sixth transistor 106 during the set period, so that malfunction can be suppressed.

Further, in the flip-flop of this embodiment, the value of L of the third transistor 103 is preferably larger than the value of L of the fourth transistor 104, more preferably 2
Times to 3 times. Accordingly, in the flip-flop of this embodiment, since the value of W / L of the third transistor 103 is reduced, the value of W of the fourth transistor 104 can be reduced, and the layout area can be reduced. be able to.

Note that the arrangement and the number of the transistors are not limited to those in FIG. 1 as long as the operation similar to that in FIG. 1 is performed. As can be seen from FIG. 3 illustrating the operation of the flip-flop of FIG. 1, in the present embodiment, the set period, the selection period, the reset period, the first non-selection period, and the second non-selection period are shown in FIG. It suffices that the continuity is taken as indicated by the solid lines shown in (A) to (E). Therefore, transistors, other elements (resistive elements, capacitive elements, etc.), diodes, switches, various logic circuits, etc. are newly arranged if the transistor can be arranged and operated to satisfy this requirement. Also good.

For example, in the flip-flop illustrated in FIG. 4A, the bootstrap operation in the selection period is further stabilized by disposing the capacitor 401 between the gate electrode and the second electrode of the first transistor 101. Can be done. Further, the flip-flop in FIG.
Since the parasitic capacitance between the gate electrode and the second electrode of the transistor 101 can be reduced,
Each transistor can be switched at high speed. Alternatively, as illustrated in FIG. 4B, a transistor 402 may be used as the capacitor 401. The transistor 402 can function as a capacitor having a large capacitance component by connecting the gate electrode to the node 141 and connecting the first electrode and the second electrode to the third wiring 123. Note that the transistor 402 can function as a capacitor even when one of the first electrode and the second electrode is floated. Note that portions common to the configuration in FIG. 1 are denoted by common reference numerals and description thereof is omitted.

Note that the capacitor 401 may use a gate insulating film as an insulating layer and a gate electrode layer and a wiring layer as a conductive layer, or use a gate insulating film as an insulating layer and a gate electrode layer and an impurity as a conductive layer. An added semiconductor layer may be used, or an interlayer film (insulating film) as an insulating layer
A wiring layer and a transparent electrode layer may be used as the conductive layer. Note that in the case where the capacitor 401 uses a gate electrode layer and a wiring layer as the conductive film, the gate electrode layer is connected to the gate electrode of the first transistor 101 and the wiring layer is connected to the second electrode of the first transistor 101. It is good to connect. More preferably, when a gate electrode layer and a wiring layer are used as the conductive film, the gate electrode layer is directly connected to the gate electrode of the first transistor 101, and the wiring layer is directly connected to the second electrode of the first transistor 101. Good. This is because the increase in the layout area of the flip-flop due to the arrangement of the capacitive element 401 is small.

As another example, the flip-flop illustrated in FIG.
By connecting the first electrode to the first wiring 121 (by connecting the first transistor 101 as a diode), the eighth wiring 128 is unnecessary, and the wiring and the power supply (V1) can be reduced by one. it can. Note that portions common to the configuration in FIG. 1 are denoted by common reference numerals and description thereof is omitted.

As another example, the flip-flop illustrated in FIG. 4D can reduce wiring and power by one by using the resistor 403 instead of the third transistor 103. further,
In the flip-flop in FIG. 4D, the potential of the node 142 is changed to the sixth potential in the second non-selection period.
Therefore, the driving capability can be improved.
Note that portions common to the configuration in FIG. 1 are denoted by common reference numerals and description thereof is omitted.

As another example, the flip-flop illustrated in FIG. 7A connects the gate electrode of the second transistor 102 to a wiring 711 to which an arbitrary signal is input, so that the second transistor 10
A reverse bias can be applied to the two gate electrodes. Further, Vgs of the second transistor 102
Can be reduced. Accordingly, the threshold shift of the second transistor 102 can be further suppressed. Note that portions common to the configuration in FIG. 1 are denoted by common reference numerals and description thereof is omitted.

As another example, the flip-flop illustrated in FIG. 7B can turn on the second transistor 102 even in the set period because the gate electrode of the second transistor 102 is connected to the sixth wiring 126. The driving ability can be improved. Further, the third wiring 1
23 noise can be reduced. Note that portions common to the configuration in FIG. 1 are denoted by common reference numerals and description thereof is omitted.

As another example, the flip-flop illustrated in FIG. 7C can reduce the wiring and the power supply by one by using the diode-connected transistor 701 and the diode-connected transistor 702 instead of the third transistor 103. . The first electrode of the transistor 701, the second electrode of the transistor 702, and the gate electrode of the transistor 701 are the sixth wiring 1
26, the second electrode of the transistor 701, the second electrode of the transistor 702, and the gate electrode of the transistor 702 are connected to the node 141. That is, the sixth wiring 1
Between the node 26 and the node 141, two reverse diodes are connected in parallel. In addition, FIG.
The parts common to the configuration of FIG.

As another example, as shown in FIG. 21A, the sixth transistor 106 is not necessarily required. This is because the sixth transistor 106 is not necessarily required as long as the potential of the node 141 can be maintained at the L level in the non-selection period. Thus, the flip-flop in FIG. 21A can reduce the number of transistors, and thus can provide advantages such as a reduction in layout area. Note that portions common to the configuration in FIG. 1 are denoted by common reference numerals and description thereof is omitted.

As another example, as shown in FIG. 21B, instead of the fourth transistor 104, the eighth transistor
Alternatively, the transistor 2108 may be used. The first electrode of the eighth transistor 2108 is connected to the twelfth wiring 2132, and the second electrode of the eighth transistor 2108 is connected to the node 14.
2 and the gate electrode of the eighth transistor 2108 is connected to the first wiring 121. Further, V2 is supplied to the twelfth wiring 2132. In this way, FIG.
In the flip-flop), on / off of the eighth transistor 2108 is controlled by the start signal, the fall time of the potential of the node 142 can be shortened in the set period, and the second transistor 102 and The time during which the sixth transistor 106 is turned off can be shortened. Further, in the flip-flop in FIG. 21B, the sixth transistor 106 is turned off earlier, so that the rise time of the potential of the node 141 can be shortened in the set period. In this manner, the flip-flop in FIG. 21B can improve the driving ability of the flip-flop. Note that portions common to the configuration in FIG. 1 are denoted by common reference numerals and description thereof is omitted.

Note that the eighth wiring 128 includes a fourth wiring 124, a ninth wiring 129, and a tenth wiring 130.
Alternatively, it may be connected to the eleventh wiring 131.

As another example, an eighth transistor 2108 may be added as illustrated in FIG. The eighth transistor 2108 can have a small transistor size because it is sufficient that the potential of the node 142 can be set to L level when the start signal is at H level. Further, FIG.
In the flip-flop in (C), on / off of the eighth transistor 2108 is controlled by the start signal, so that the driving ability of the flip-flop can be improved as in the flip-flop in FIG. 22B. . Note that portions common to the configurations in FIGS. 1 and 21B are denoted by common reference numerals and description thereof is omitted.

Note that the connection relationship of the wirings is not limited to that in FIG. 1 as long as the operation similar to that in FIG.
As can be seen from FIG. 3 illustrating the operation of the flip-flop of FIG. 1, in the present embodiment, the set period, the selection period, the reset period, the first non-selection period, and the second non-selection period are shown in FIG. It suffices that the continuity is taken as indicated by the solid lines shown in (A) to (E). Therefore, it is only necessary that each wiring is arranged or connected so as to satisfy this.

For example, as illustrated in FIG. 5A, the first electrode of the second transistor 102, the first electrode of the fourth transistor 104, the first electrode of the sixth transistor 106, and the seventh transistor 107 The first electrode may be connected to the sixth wiring 506. Further, the first electrode of the third transistor 103 and the first electrode of the fifth transistor 105 may be connected to the seventh wiring 507. Thus, the number of wirings in the flip-flop in FIG. 5A can be reduced from 11 to 7 as compared with the flip-flop in FIG. Further, the flip-flop in FIG. 5A can improve the yield of the shift register by reducing the number of wirings. Further, the flip-flop in FIG. 5A can reduce the wiring area and the layout area of the shift register. Further, the flip-flop in FIG. 5A can increase the width of each wiring, so that a voltage drop can be reduced and the drive capability of the shift register can be improved. Note that portions common to the configuration in FIG. 1 are denoted by common reference numerals and description thereof is omitted.

Note that the sixth wiring 506 illustrated in FIG. 5A corresponds to the fourth wiring 124, the ninth wiring 129, the tenth wiring 130, and the eleventh wiring 131 illustrated in FIG. Further, FIG.
7 corresponds to the seventh wiring 127 and the eighth wiring 128 illustrated in FIG. 1. Further, the first wiring 501, the second wiring 502, and the third wiring 50 illustrated in FIG.
3, the fourth wiring 504, and the fifth wiring 505 are respectively the first wiring 121 shown in FIG.
, The second wiring 122, the third wiring 123, the fifth wiring 125, and the sixth wiring 126.

Note that the sixth wiring 506 and the seventh wiring 507 may be referred to as a first power supply line and a second power supply line, respectively. Further, the first wiring 501, the second wiring 502, the third wiring 503, the fourth wiring 504, and the fifth wiring 505 are respectively connected to the first signal line, the second signal line, and the third signal. May be referred to as a line, a fourth signal line, or a fifth signal line.

As another example, as illustrated in FIG. 5B, the first electrode of the fourth transistor 104 is an eighth electrode.
The wiring 508 may be connected. The flip-flop in FIG. 5B can suppress malfunction due to a voltage drop in the sixth wiring 506 by flowing an instantaneous current generated in the fourth transistor 104 through the eighth wiring 508 in the set period. 1 and 5A.
The parts common to the configuration of FIG.

As another example, as shown in FIG. 5C, the first electrode of the second transistor 102 is the ninth electrode.
The wiring 509 may be connected. The flip-flop in FIG. 5B allows the sixth current to flow through the ninth wiring 509 by passing an instantaneous current generated in the second transistor 102 in the reset period.
Malfunction due to a voltage drop in the wiring 506 can be suppressed. 1 and 5 (A
The same reference numerals are used for portions common to the configuration of), and the description thereof is omitted.

As another example, as shown in FIG. 5D, the gate electrode of the third transistor 103 is a first transistor.
0 wiring 510 may be connected. The flip-flop in FIG. 5D has the tenth wiring 5
10 is supplied with a potential lower than V1, the potential of the gate electrode of the second transistor 102 and the potential of the gate electrode of the sixth transistor 106 are decreased in the second non-selection period. Deterioration of characteristics of the sixth transistor 106 can be suppressed. Note that portions common to those in FIGS. 1 and 5A are denoted by the same reference numerals, and description thereof is omitted.

Note that the power supply potential, the signal amplitude, and the signal timing are not limited to the timing chart in FIG. 2 as long as the operation similar to that in FIG. 1 is performed. As can be seen from FIG. 3 illustrating the operation of the flip-flop of FIG. 1, in the present embodiment, the set period, the selection period, the reset period, the first non-selection period, and the second non-selection period are shown in FIG. It suffices that the continuity is taken as indicated by the solid lines shown in (A) to (E). Therefore, the power supply potential, the signal amplitude, and the signal timing may be changed to satisfy this.

For example, as shown in the timing chart of FIG. 6, the first wiring 121 and the fifth wiring 125 are used.
The period for inputting the H signal to the sixth wiring 126 may be shortened. Compared with the timing chart of FIG. 2, FIG.
The timing at which the signal is delayed by 1 and the signal is switched from the H level to the L level is advanced by the period Ta2. That is, FIG. 6 shows a period (period Tb) during which the signal is at an H level, as compared with FIG.
) Is shortened by the period Ta1 + the period Ta2. Therefore, in the flip-flop to which the timing chart of FIG. 6 is applied, the instantaneous current of each wiring is small, so that power saving, malfunction prevention, and drive capability can be improved. Further, the flip-flop to which the timing chart of FIG. 6 is applied can shorten the fall time of the signal output from the third wiring 123 in the reset period. . This is because the timing at which the potential of the node 141 becomes the L level is delayed by the period Ta1 + the period Ta2, so that the L signal input to the fifth wiring 125 has a large current capability (a channel width is large). This is because the voltage is supplied to the third wiring 123 via the. Note that portions common to the timing chart of FIG. 2 are denoted by common reference numerals, and description thereof is omitted.

Note that the relationship between the period Ta1, the period Ta2, and the period Tb is ((Ta1 + Tb) / (Ta1 +
Ta2 + Tb)) × 100 <10 [%] is desirable. More preferably, ((T
a1 + Tb) / (Ta1 + Ta2 + Tb)) × 100 <5 [%] is desirable.
Further, it is desirable that the period Ta1≈the period Ta2.

As another example, when Va (V2 <Va <V1) is supplied to the seventh wiring 127, the potential of the node 142 becomes Va−Vth (103) in the reset period and the second non-selection period. The threshold voltage shift of the transistor 102 and the sixth transistor 106 can be suppressed.

As another example, when Vb (V1 + Vth (103) <Vb) is supplied to the seventh wiring 127, the potential of the node 142 becomes V1 in the reset period and the second non-selection period. The sixth transistor 106 can be easily turned on.

As another example, the potential of the L signal input to the sixth wiring 126 is Vc (Vc <V2), and the potential of the H signal is Vd (V1>Vd> V2). 6th
The threshold voltage shift of the transistor 106 can be suppressed. This is because the potential of the node 142 becomes Vc in the set period and the first non-selection period, and a reverse bias is applied to the second transistor 102 and the sixth transistor 106. Further, the potential of the node 142 becomes Vd in the reset period and the second non-selection period, and the second
This is because Vgs of the first transistor 102 and the sixth transistor 106 becomes smaller.

FIG. 25 shows an example of a top view of the flip-flop shown in FIG. The conductive layer 2501 includes portions functioning as the gate electrode of the second transistor 102 and the gate electrode of the sixth transistor 106, and is connected to the conductive layer 2502 through a wiring 2547. Conductive layer 25
02 includes a portion functioning as the second electrode of the third transistor 103 and the second electrode of the fourth transistor 104. The conductive layer 2503 includes portions functioning as a first electrode of the second transistor 102, a first electrode of the sixth transistor 106, and a first electrode of the fourth transistor 104, and the sixth wiring 506 Connected. The conductive layer 2504 includes a portion functioning as the second electrode of the second transistor 102 and is connected to the third wiring 503 through the wiring 2548. The conductive layer 2505 includes the second electrode of the fifth transistor 105,
It includes a portion functioning as the second electrode of the seventh transistor 107 and is connected to the conductive layer 2510 through a wiring 2549. The conductive layer 2506 includes a portion functioning as the first electrode of the seventh transistor 107 and is connected to the sixth wiring 506. The conductive layer 2507 includes a portion functioning as the first electrode of the first transistor 101 and is connected to the fourth wiring 504 through the wiring 2541. The conductive layer 2508 includes a portion functioning as the second electrode of the first transistor 101 and is connected to the third wiring 503 through the wiring 2548.
The conductive layer 2510 includes the gate electrode of the first transistor 101 and the fourth transistor 104.
A portion functioning as a gate electrode. The conductive layer 2511 includes the seventh transistor 107
Including a portion functioning as a gate electrode of the second wiring 502 and connected to the second wiring 502 through the wiring 2546. The conductive layer 2512 includes a portion functioning as the gate electrode of the third transistor 103 and is connected to the seventh wiring 507 through the wiring 2544. The conductive layer 2513 is a third layer
The transistor 103 includes a portion functioning as the first electrode and is connected to the fifth wiring 505 through the wiring 2543. The conductive layer 2514 includes a portion functioning as the gate electrode of the fifth transistor 105 and is connected to the first wiring 501 through the wiring 2545. The conductive layer 2515 includes a portion functioning as the second electrode of the sixth transistor 106 and is connected to the conductive layer 2510 through the wiring 2547.

Note that portions functioning as the gate electrode, the first electrode, and the second electrode of the first transistor 101 are portions where a conductive layer including each of them overlaps with the semiconductor layer 2581. The portions functioning as the gate electrode, the first electrode, and the second electrode of the second transistor 102 are portions where a conductive layer including each of them overlaps with the semiconductor layer 2582. The portions functioning as the gate electrode, the first electrode, and the second electrode of the third transistor 103 are portions where a conductive layer including each of them overlaps with the semiconductor layer 2583. The portions functioning as the gate electrode, the first electrode, and the second electrode of the fourth transistor 104 are portions where a conductive layer including each of them overlaps with the semiconductor layer 2584. The portions functioning as the gate electrode, the first electrode, and the second electrode of the fifth transistor 105 are portions where a conductive layer including each of them overlaps with the semiconductor layer 2585. The portions functioning as the gate electrode, the first electrode, and the second electrode of the sixth transistor 106 are portions where a conductive layer including each of them overlaps with the semiconductor layer 2586. The portions functioning as the gate electrode, the first electrode, and the second electrode of the seventh transistor 107 are portions where a conductive layer including each of them overlaps with the semiconductor layer 2587.

A structure and a driving method of the shift register including the flip-flop of this embodiment described above will be described.

A structure of the shift register of this embodiment is described with reference to FIG. The shift register in FIG. 10 includes n flip-flops (flip-flops 1001_1 to 1001_n).

Connection relations of the shift register in FIG. 10 are described. In the shift register in FIG. 10, the i-th flip-flop 1001_i (any one of the flip-flops 1001_1 to 1001_n) includes a second wiring 1012, a third wiring 1013, a fourth wiring 1014, and a fifth wiring. 1015, the sixth wiring 1016, the eighth wiring 1018_i-1, the eighth wiring 10
18_i and the eighth wiring 1018_i + 1. However, the flip-flop 1001_1 in the first stage includes a first wiring 1011, a second wiring 1012, a third wiring 1013,
4th wiring 1014, 5th wiring 1015, 6th wiring 1016, 8th wiring 1018_
The first and eighth wirings 1018_2 are connected. Furthermore, the nth flip-flop 100
1_n denotes the second wiring 1012, the third wiring 1013, the fourth wiring 1014, the fifth wiring 1015, the sixth wiring 1016, the seventh wiring 1017, the eighth wiring 1018_n-1, and the eighth wiring It is connected to the wiring 1018_n.

The first wiring 1011 is connected to the first wiring 121 illustrated in FIG. 1 of the flip-flop 1001_1. The second wiring 1012 is connected to the fifth wiring 125 illustrated in FIG. 1 in the odd-numbered flip-flops, and is connected to the sixth wiring 126 illustrated in FIG. 1 in the even-numbered flip-flops. The third wiring 1013 is connected to the sixth wiring 126 illustrated in FIG. 1 in the odd-numbered flip-flops, and is connected to the fifth wiring 125 illustrated in FIG. 1 in the even-numbered flip-flops. The fourth wiring 1014 is a flip-flop at all stages, and the seventh wiring 1 shown in FIG.
27. The fifth wiring 1015 is connected to the eighth wiring 128 illustrated in FIG. 1 by flip-flops at all stages. The sixth wiring 1016 is connected to the fourth wiring 124, the ninth wiring 129, the tenth wiring 130, and the eleventh wiring 131 shown in FIG. The eighth wiring 1018_i includes the second wiring 122 illustrated in FIG. 1 of the flip-flop 1001_i−1, the third wiring 123 illustrated in FIG. 1 of the flip-flop 1001_i, and the first wiring 121 illustrated in FIG. 1 of the flip-flop 1001_i + 1. Connected to. However,
The eighth wiring 1018_1 is the third wiring 12 illustrated in FIG. 1 of the flip-flop 1001_1.
3 and the flip-flop 1001_2 are connected to the first wiring 121 shown in FIG. Further, the eighth wiring 1018_n is connected to the second wiring 122 illustrated in FIG. 1 of the flip-flop 1001_n−1 and the third wiring 123 illustrated in FIG. 1 of the flip-flop 1001_n.

Note that the potential of V1 is supplied to each of the fourth wiring 1014 and the fifth wiring 1015, and
The sixth wiring 1016 is supplied with the potential V2.

The first wiring 1011, the second wiring 1012, the third wiring 1013, and the seventh wiring 1
A signal is input to 017 respectively. A signal input to the first wiring 1011 is a start signal, a signal input to the second wiring 1012 is a first clock signal, and a signal input to the third wiring 1013 is a second clock. A signal that is input to the seventh wiring 1017 is a reset signal. Further, the first wiring 1011, the second wiring 1012,
Signals input to the third wiring 1013 and the seventh wiring 1017 are digital signals in which the potential of the H signal is V1 and the potential of the L signal is V2.

Note that various signals, power supply potentials, or currents may be input to the first wiring 1011 to the seventh wiring 1017.

Note that signals are output from the eighth wiring 1018_1 to the eighth wiring 1018_n. For example, a signal output from the eighth wiring 1018 — i is an output signal of the flip-flop 1001 — i. Further, signals output from the eighth wiring 1018 — i are also a start signal for the flip-flop 1001 — i + 1 and a reset signal for the flip-flop 1001 — i−1.

Note that in the case where signals or voltages supplied to the first wiring 1011 to the seventh wiring 1017 are the same, the first wiring 1011 to the seventh wiring 1017 may be connected or the same. It is good also as wiring of this.

Next, operation of the shift register illustrated in FIG. 10 is described with reference to a timing chart in FIG. 11 and a timing chart in FIG. Here, the timing chart of FIG. 11 is divided into a scanning period and a blanking period. The scanning period is a period from when the selection signal is output from the eighth wiring 1018_1 to when the selection signal is output from the eighth wiring 1018_n. The blanking period is a period from when the output of the selection signal from the eighth wiring 1018_n is finished to when the selection signal is output from the eighth wiring 1018_1.

In FIG. 11, the signal 1111 input to the first wiring 1011, the second wiring 10
12, a signal 1113 input to the third wiring 1013, a signal 1117 input to the seventh wiring 1017, and a signal eighth output to the eighth wiring 1018_1.
The signal 1118_n output to the wiring 1018_2 and the eighth wiring 1018_n is shown. Further, in FIG. 12, the signal 1211 input to the first wiring 1011, the signal 1218_1 output to the eighth wiring 1018_1, the signal 1218_i output to the eighth wiring 1018_i, and the eighth wiring 1018_i + 1 are output. The signal 1218_i + 1 and the signal 1218_n output to the eighth wiring 1018_n are shown.

As illustrated in FIG. 12, for example, when the flip-flop 1001_i is in the selection period (the H signal is output from the eighth wiring 1018_i. At this time, the flip-flop 1001_
i + 1 is a set period. After that, the flip-flop 1001_i enters a reset period, and an L signal is output from the eighth wiring 1018_i. At this time, flip-flop 1
001_i + 1 is a selection period. After that, the flip-flop 1001_i enters the first non-selection period, and the eighth wiring 1018_i is in a floating state to maintain the potential at the L level. At this time, the flip-flop 1001_i + 1 is in the reset period. After that, the flip-flop 1001_i enters the second non-selection period, and the L signal is output from the eighth wiring 1018_i. At this time, the flip-flop 1001_i + 1 is in the first non-selection period. Thus, the flip-flop 1001_i repeats the first non-selection period and the second non-selection period until the next set period.

From the above, the shift register in FIG. 10 can output a selection signal from the eighth wiring 1018_1 to the eighth wiring 1018_n in order. That is, the shift register in FIG. 10 can scan the eighth wiring 1018_1 to the eighth wiring 1018_n. Therefore, the shift register in FIG. 10 can sufficiently function as a shift register.

Further, the reset signal input to the final flip-flop 1001 — n is input through the seventh wiring 1017. By doing so, the shift register of FIG. 10 does not require a dummy flip-flop, and thus the layout area can be reduced. However, a dummy flip-flop may be arranged.

Further, the shift register in FIG. 10 can freely determine a blanking period depending on the timing of a signal input to the first wiring 1011.

Further, the shift register in FIG. 10 can suppress the threshold shift of the transistor by applying the flip-flop described in this embodiment. Further, the shift register in FIG. 10 can have a long lifetime. Further, the shift register in FIG. 10 can improve driving capability. Further, malfunction can be suppressed. further,
The shift register in FIG. 10 can simplify the process.

Note that the configuration is not limited to the configuration in FIG. 10 as long as the same operation as that in FIG. 10 is performed.

For example, as shown in FIG. 13, the output signal of each flip-flop may be output via a buffer. In the shift register in FIG. 13, since the flip-flops 1001_1 to 1001_n are connected to the eighth wiring 1018_1 to the eighth wiring 1018_n through the buffers 1301_1 to 1301_n, respectively, wide driving ability can be obtained. This is because when a large load is connected to each of the eighth wiring 1018_1 to the eighth wiring 1018_n, delay and rounding occur in signals output from the eighth wiring 1018_1 to the eighth wiring 1018_n. That is, the eighth wiring 1018_1˜
This is because delay and rounding of a signal output from each of the eighth wirings 1018_n do not affect the operation of the shift register. Note that portions common to the configuration in FIG. 10 are denoted by common reference numerals, and description thereof is omitted.

Note that each of the buffers 1301_1 to 1301_n can be a logic circuit such as NAND or NOR, an operational amplifier, or a circuit combining these. That is, an inverter or an analog buffer can be used. In addition, buffer 1
Each of 301_1 to buffer 1301_n is preferably formed of an N-channel transistor when the flip-flop is formed of an N-channel transistor.
Further, each of the buffers 1301_1 to 1301_n is preferably configured to perform a bootstrap operation. Further, the driving voltage (potential difference between the negative power supply and the positive power supply) of each of the buffers 1301_1 to 1301_n is the flip-flop 1
The driving voltage is preferably larger than the driving voltages of 001_1 to flip-flop 1001_n.

Here, the buffers 1301_1 to 1301 included in the shift register illustrated in FIG.
An example of _n will be described with reference to FIGS. 123 (A) and 123 (B). FIG.
A buffer 8000 shown in A) includes an inverter 8001 between the wiring 8011 and the wiring 8012.
a, the inverter 8001b and the inverter 8001c are connected, so that an inverted signal of the signal input to the wiring 8011 is output from the wiring 8012. However, the number of inverters connected between the wiring 8011 and the wiring 8012 is not limited. For example, the wiring 8011 and the wiring 80
12, an even number of inverters are connected to the wiring 8011, and a signal having the same polarity as the signal input to the wiring 8011 is output from the wiring 8012. Further, the buffer 810 in FIG.
0, inverters 8002a, 8002b and 8002c connected in series, and inverters 8003a and 8003b arranged in series
And the inverter 8003c may be connected in parallel. Buffer 81 in FIG. 123 (B)
00 can average variations in characteristics of the transistors, so that delay and rounding of a signal output from the wiring 8012 can be reduced. Further, inverter 8002a and inverter 8
The output of 002a and the outputs of the inverter 8002b and the inverter 8002b may be connected to each other.

Note that in FIG. 123A, it is preferable that W of the transistor included in the inverter 8001a <W of the transistor included in the inverter 8001b <W of the transistor included in the inverter 8001c. This is because the drive capacity of the flip-flop (specifically, the value of W / L of the transistor 101 in FIG. 1) can be reduced because the W of the inverter 8001a is small, so that the shift register of this embodiment has a layout area. Can be small. Similarly, in FIG. 123B, it is preferable that W of the transistor included in the inverter 8002a <W of the transistor included in the inverter 8002b <W of the transistor included in the inverter 8002c. Similarly, in FIG. 123B, it is preferable that W of the transistor included in the inverter 8003a <W of the transistor included in the inverter 8003b <W of the transistor included in the inverter 8003c. Furthermore, the inverter 800
W2 of the transistor included in the inverter 8003a, W of the transistor included in the inverter 8002b = W of the transistor included in the inverter 8003b, W of the transistor included in the inverter 8002c = W of the transistor included in the inverter 8003c. preferable.

Note that there is no particular limitation on the inverter illustrated in FIGS. 123A and 123B as long as it can output an inverted signal. For example, as illustrated in FIG. 123C, an inverter may be formed using the first transistor 8201 and the second transistor 8202. Further, a signal is input to the first wiring, a signal is output from the second wiring 8212, V 1 is supplied to the third wiring 8213, and V 2 is supplied to the fourth wiring 8214. 123C, when an H signal is input to the first wiring 8211, the potential obtained by dividing V1-V2 by the first transistor 8201 and the second transistor 8202 (W / L of the first transistor 8201) <W / L of the second transistor 8202)
Output from the second wiring 8212. Further, in the inverter in FIG. 123C, when an L signal is input to the first wiring 8211, V1−Vth (8201) (Vth (8201): First
The threshold voltage of the transistor 8201 is output from the second wiring 8212. further,
The first transistor 8201 may be a PN junction diode as long as it is an element having a resistance component, or may simply be a resistance element.

Further, as illustrated in FIG. 123D, an inverter may be formed using the first transistor 8301, the second transistor 8302, the third transistor 8303, and the fourth transistor 8304. Further, a signal is input to the first wiring 8311, a signal is output from the second wiring 8312, V1 is supplied to the third wiring 8313 and the fifth wiring 8315, and the fourth wiring 8314 and V2 is supplied to the sixth wiring 8316. FIG.
When an H signal is input to the first wiring 8311, the inverter (D) converts V2 to the second wiring 8.
312 is output. At this time, since the potential of the node 8341 is set to the L level, the first transistor 8301 is turned off. Further, the inverter in FIG. 123D includes the first wiring 83.
When an L signal is input to 11, V 1 is output from the second wiring 8312. At this time, when the potential of the node 8341 becomes V1−Vth (8303) (Vth (8303): threshold voltage of the third transistor 8303), the node 8341 is in a floating state, and the node 8341
Of V1 + Vth (8301) (Vth (8301)) by the bootstrap operation.
: Threshold voltage of the first transistor 8301), the first transistor 8301 is turned on. Further, since the first transistor 8301 functions as a bootstrap transistor, a capacitor may be provided between the second electrode and the gate electrode.

Further, as illustrated in FIG. 26A, an inverter may be formed using the first transistor 8401, the second transistor 8402, the third transistor 8403, and the fourth transistor 8404. The inverter in FIG. 26A is a two-input inverter and can perform a bootstrap operation. Further, a signal is input to the first wiring 8411, an inverted signal is input to the second wiring 8412, and a signal is output from the third wiring 8413.
V1 is supplied to the fourth wiring 8414 and the sixth wiring 8416, and V2 is supplied to the fifth wiring 8415 and the seventh wiring 8417. In the inverter in FIG. 26A, when an L signal is input to the first wiring 8411 and an H signal is input to the second wiring 8412, V2 is converted to the third wiring 841.
3 is output. At this time, since the potential of the node 8441 is V2, the first transistor 8401 is turned off. Further, the inverter in FIG. 26A is connected to the first wiring 8411 with H
When an L signal is input to the signal and the second wiring 8412, V 1 is output from the third wiring 8413. At this time, the potential of the node 8441 is V1−Vth (8403) (Vth (8403)).
: The threshold voltage of the third transistor 8403), the node 8441 is in a floating state, and the potential of the node 8441 becomes V1 + Vth (8401) by the bootstrap operation.
Since it becomes higher than (Vth (8401): threshold voltage of the first transistor 8401), the first transistor 8401 is turned on. Further, since the first transistor 8401 functions as a bootstrap transistor, a capacitor may be provided between the second electrode and the gate electrode. Further, the third wiring 123 illustrated in FIG. 1 may be connected to one of the first wiring 8411 and the second wiring 8412, and the node 142 illustrated in FIG. 1 may be connected to the other.

Further, as illustrated in FIG. 26B, an inverter may be formed using the first transistor 8501, the second transistor 8502, and the third transistor 8503. FIG.
The inverter 6 (B) is a two-input inverter and can perform a bootstrap operation. Further, a signal is input to the first wiring 8511, an inverted signal is input to the second wiring 8512, a signal is output from the third wiring 8513, and the fourth wiring 8514 and the sixth wiring
The second wiring 8516 is supplied with V2, and the fifth wiring 8515 is supplied with V2. FIG.
When an L signal is input to the first wiring 8511 and an H signal is input to the second wiring 8512, the inverter of FIG. 5B outputs V2 from the third wiring 8513. At this time, since the potential of the node 8541 is V2, the first transistor 8501 is turned off. Further, when the inverter in FIG. 26B inputs an H signal to the first wiring 8511 and an L signal to the second wiring 8512, the inverter
1 is output from the third wiring 8513. At this time, the potential of the node 8541 is V1−Vth.
(8503) (Vth (8503): threshold voltage of the third transistor 8503), the node 8541 is in a floating state, and the potential of the node 8541 is changed to V1 + Vth (8501) (Vth (8501): the first) by the bootstrap operation. 1 transistor 8501
The first transistor 8501 is turned on. Further, since the first transistor 8501 functions as a bootstrap transistor,
A capacitor may be disposed between the second electrode and the gate electrode. Further, the first wiring 85
One of the eleventh and second wirings 8512 may be connected to the third wiring 123 shown in FIG. 1, and the other may be connected to the node 142 shown in FIG.

Further, as illustrated in FIG. 26C, an inverter may be formed using the first transistor 8601, the second transistor 8602, the third transistor 8603, and the fourth transistor 8604. The inverter in FIG. 26C is a two-input inverter and can perform a bootstrap operation. Further, a signal is input to the first wiring 8611, an inverted signal is input to the second wiring 8612, and a signal is output from the third wiring 8613.
V1 is supplied to the fourth wiring 8614 and V2 is supplied to the fifth wiring 8615 and the sixth wiring 8616. In the inverter in FIG. 26A, an L signal is supplied to the first wiring 8611, the second
When an H signal is input to the second wiring 8612, V 2 is output from the third wiring 8613. At this time, since the potential of the node 8641 becomes V2, the first transistor 8601 is turned off.
Further, in the inverter in FIG. 26C, the first wiring 8611 has an H signal and the second wiring 861.
When an L signal is input to 2, V 1 is output from the third wiring 8613. At this time, the node 8
641 is V1-Vth (8603) (Vth (8603): the third transistor 8
(The threshold voltage of 603), the node 8641 enters a floating state, and the potential of the node 8641 becomes V1 + Vth (8601) (Vth (8601):
The threshold voltage of the first transistor 8601 is higher than that of the first transistor 8601, so that the first transistor 8601 is turned on. Further, since the first transistor 8601 functions as a bootstrap transistor, a capacitor may be provided between the second electrode and the gate electrode. Further, the third wiring 123 illustrated in FIG. 1 may be connected to one of the first wiring 8611 and the second wiring 8612, and the node 142 illustrated in FIG. 1 may be connected to the other.

As another example, another input signal or output signal of the shift register can be used as the reset signal input to the flip-flop 1001_n. That is, flip-flop 100
By generating a reset signal input to 1_n inside the shift register, one wiring and one signal can be reduced. For example, in the case where the flip-flop 1001_n is an even-numbered stage, as illustrated in FIG. 14, the flip-flop 1001_n may be connected to the eighth wiring 1018_1. . As another example, when the flip-flop 1001_n is an even-numbered stage, as shown in FIG.
The wiring 1011 may be connected. As another example, a reset signal to be input to the flip-flop 1001_n may be generated using a dummy flip-flop 1001_d as illustrated in FIG. The dummy flip-flop 1001_d can be the same as the flip-flop 1001_n-1. Note that the second wiring 122 illustrated in FIG. 1 of the dummy flip-flop 1001_d is connected to the sixth wiring 1016 in FIG. Note that portions common to the configuration in FIG. 10 are denoted by common reference numerals, and description thereof is omitted.

Next, a structure and driving method of the display device including the shift register of this embodiment described above will be described. Note that the display device of this embodiment mode includes at least the flip-flop of this embodiment mode.

A structure of the display device of this embodiment will be described with reference to FIG. The display device in FIG. 18 includes a signal line driver circuit 1801, a scan line driver circuit 1802, and a pixel portion 1804, and the pixel portion 1804 has a plurality of signals that extend from the signal line driver circuit 1801 in the column direction. Line S
1 to Sm, a plurality of scanning lines G1 to G1 arranged extending from the scanning line driving circuit 1802 in the row direction.
A plurality of pixels 1803 are arranged in a matrix corresponding to Gn, signal lines S1 to Sm, and scanning lines G1 to Gn. Each pixel 1803 includes a signal line Sj (signal lines S1 to S1).
any one of m) and the scanning line Gi (any one of the scanning lines G1 to Gn). Further, the scan line driver circuit 1802 may be referred to as a driver circuit.

Note that the shift register of this embodiment can be used as the scan line driver circuit 1802. Needless to say, the shift register of this embodiment may also be used for the signal line driver circuit 1801.

Note that the scan lines G1 to Gn are connected to the eighth wiring 1808_1 to the eighth wiring 1808_n illustrated in FIGS. 10, 12, 13, 14, 15, and 17.

Note that the signal line and the scanning line may be simply referred to as wiring. Further, a signal line driver circuit 1801
The scan line driver circuit 1802 may be referred to as a driver circuit.

Note that the pixel 1803 includes at least one switching element, one capacitor, and a pixel electrode. Note that the pixel 1803 may include a plurality of switching elements or a plurality of capacitor elements. Furthermore, a capacitive element is not always necessary. Further, the pixel 1803
May further include a transistor operating in a saturation region. Further, the pixel 1803
May have a display element such as a liquid crystal element or an EL element. Here, a transistor and a PN junction diode can be used as the switching element. However, when a transistor is used as the switching element, it is preferable that the transistor operates in a linear region. Further, in the case where the scan line driver circuit 1802 includes only N-channel transistors, it is preferable to use N-channel transistors as switching elements. Further, in the case where the scan line driver circuit 1802 includes only P-channel transistors, it is preferable to use P-channel transistors as switching elements.

Note that the scan line driver circuit 1802 and the pixel portion 1804 are formed over the insulating substrate 1805, and the signal line driver circuit 1801 is not formed over the insulating substrate 1805. The signal line driver circuit 1801 is formed over a single crystal substrate, an SOI substrate, or an insulating substrate different from the insulating substrate 1805. The signal line driver circuit 1801 is connected to the signal lines S1 to Sm via a printed board such as an FPC. Note that the signal line driver circuit 1801 may be formed over the insulating substrate 1805, or a circuit that constitutes part of the function of the signal line driver circuit 1801 may be formed over the insulating substrate 1805.

Note that wiring, electrodes, conductive layers, conductive films, terminals, etc. are made of aluminum (Al), tantalum (T
a), titanium (Ti), molybdenum (Mo), tungsten (W), neodymium (Nd)
, Chromium (Cr), nickel (Ni), platinum (Pt), gold (Au), silver (Ag), copper (C
u), magnesium (Mg), scandium (Sc), cobalt (Co), zinc (Zn)
, Niobium (Nb), Silicon (Si), Phosphorus (P), Boron (B), Arsenic (As), Gallium (Ga), Indium (In), Tin (Sn), Oxygen (O) Or one or more elements selected from the above, or a compound or alloy material (for example, indium tin oxide (ITO), indium zinc oxide (IZO) containing one or more elements selected from the above group as a component) ), Indium tin oxide containing silicon oxide (ITSO), zinc oxide (ZnO),
Aluminum neodymium (Al-Nd), magnesium silver (Mg-Ag), molybdenum niobium (
Mo—Nb) and the like. Alternatively, the wiring, the electrode, the conductive layer, the conductive film, the terminal, and the like are preferably formed using a substance in which these compounds are combined. Or one or more elements selected from the group and a silicon compound (silicide) (for example, aluminum silicon, molybdenum silicon, nickel silicide, etc.), one or more elements selected from the group and nitrogen It is desirable to form with a compound (eg, titanium nitride, tantalum nitride, molybdenum nitride, or the like).

Note that silicon (Si) includes n-type impurities (such as phosphorus) or p-type impurities (such as boron).
May be included. When silicon contains impurities, conductivity can be improved. Or it becomes possible to behave like a normal conductor. Therefore, it becomes easy to use as wiring, electrodes, and the like.

Note that silicon having various crystallinity such as single crystal, polycrystal (polysilicon), and microcrystal (microcrystal silicon) can be used. Or amorphous (
Amorphous silicon) can also be used. By using single crystal silicon or polycrystalline silicon, resistance of a wiring, an electrode, a conductive layer, a conductive film, a terminal, or the like can be reduced. By using amorphous silicon or microcrystalline silicon, a wiring or the like can be formed by a simple process.

Note that since aluminum or silver has high conductivity, signal delay can be reduced.
Further, since etching is easy, patterning is easy and fine processing can be performed.

Note that since copper has high conductivity, signal delay can be reduced. When using copper,
In order to improve adhesion, it is desirable to have a laminated structure.

Molybdenum or titanium is preferable because it has advantages such as no defects, easy etching, and high heat resistance even when in contact with an oxide semiconductor (ITO, IZO, or the like) or silicon.

Tungsten is desirable because it has advantages such as high heat resistance.

Neodymium is desirable because it has advantages such as high heat resistance. In particular, when an alloy of neodymium and aluminum is used, the heat resistance is improved, and aluminum does not easily cause hillocks.

Silicon is preferable because it can be formed at the same time as a semiconductor layer included in a transistor and has high heat resistance.

In addition, ITO, IZO, ITSO, zinc oxide (ZnO), silicon (Si), tin oxide (S
Since nO) has translucency, it can be used in a portion that transmits light. For example, it can be used as a pixel electrode or a common electrode.

Note that a wiring, an electrode, a conductive layer, a conductive film, a terminal, or the like may have a single-layer structure or a multilayer structure. With a single-layer structure, a manufacturing process of wiring, electrodes, conductive layers, conductive films, terminals, and the like can be simplified, the number of process days can be reduced, and cost can be reduced. Alternatively, by using a multilayer structure, it is possible to reduce the demerits while making use of the merits of each material, and to form wirings, electrodes, and the like with good performance. For example, by including a low resistance material (such as aluminum) in the multilayer structure, the resistance of the wiring can be reduced. In addition, by using a laminated structure in which a low heat resistant material is sandwiched between high heat resistant materials, the heat resistance of a wiring, an electrode, or the like can be increased while taking advantage of the low heat resistant material. For example, a layered structure in which a layer containing aluminum is sandwiched between layers containing molybdenum, titanium, neodymium, or the like is preferable.

In addition, when wires, electrodes, etc. are in direct contact with each other, they may adversely affect each other. For example, one wiring, an electrode, or the like may enter a material such as the other wiring, an electrode, etc., changing its properties and failing to fulfill its original purpose. Alternatively, a high resistance portion may be formed. Or when manufacturing, a problem may arise and it may become unable to manufacture normally. In such a case, it is preferable to sandwich or cover a material that reacts more easily by a laminated structure with a material that does not react easily. For example, when ITO and aluminum are connected, ITO
It is desirable to sandwich titanium, molybdenum, or neodymium alloy between aluminum and aluminum.
Moreover, when connecting silicon and aluminum, between ITO and aluminum,
It is desirable to sandwich titanium, molybdenum, or neodymium alloy.

In addition, wiring means what the conductor is arrange | positioned. It may extend linearly or may be arranged short without extending. Therefore, the electrode is included in the wiring.

Note that the wirings and electrodes described above can also be applied to other display devices, shift registers, and pixels.

Note that the signal line driver circuit 1801 inputs voltage or current as video signals to the signal lines S1 to Sm. However, the video signal may be a digital signal or an analog signal. Further, the positive / negative polarity of the video signal may be inverted every frame (frame inversion driving), or the positive / negative polarity may be inverted every row (gate line inversion driving). Positive electrode
The negative electrode may be inverted (source line inversion driving), and the positive electrode and the negative electrode may be inverted for each row and column (dot line inversion driving). Further, the video signal may be input to the signal lines S1 to Sm by dot sequential driving or may be input by line sequential driving. Further, the signal line driver circuit 1801 applies not only a video signal but also a constant voltage such as a precharge voltage to the signal lines S1 to Sm.
May be entered. It is desirable to input a constant voltage such as a precharge voltage for each gate selection period and for each frame.

Note that the scan line driver circuit 1802 inputs signals to the scan lines G1 to Gn, and scan lines G1 to Gn.
Are selected in order from the first line (hereinafter also referred to as scanning). Then, the scanning line driving circuit 180
2 selects a plurality of pixels 1803 connected to the selected scanning line. Here, a period in which one scanning line is selected is referred to as one gate selection period, and a period in which the scanning line is not selected is referred to as a non-selection period. Further, a signal output from the scan line driver circuit 1802 to the scan line is referred to as a scan signal. Further, the maximum value of the scanning signal is larger than the maximum value of the video signal or the maximum voltage of the signal line, and the minimum value of the scanning signal is smaller than the minimum value of the video signal or the minimum voltage of the signal line.

Note that when the pixel 1803 is selected, a video signal is input from the signal line driver circuit 1801 to the pixel 1803 through the signal line. Further, when the pixel 1803 is not selected, the pixel 1803 receives the video signal (potential corresponding to the video signal) input during the selection period.
Holding.

Note that although not illustrated, the signal line driver circuit 1801 and the scan line driver circuit 1802 are supplied with a plurality of potentials and a plurality of signals.

Next, operation of the display device illustrated in FIG. 18 will be described with reference to a timing chart of FIG. Further, FIG. 19 shows one frame period corresponding to a period for displaying an image for one screen. However, the period of one frame is not particularly limited, but is preferably set to at least 1/60 second or less so that a person viewing the image does not feel flicker.

In the timing chart of FIG. 19, the first scanning line G1, the i-th scanning line Gi, i
The timing at which the + 1st scanning line Gi + 1 and the nth scanning line Gn are selected is shown.

In FIG. 19, for example, the i-th scanning line Gi is selected, and a plurality of pixels 1803 connected to the scanning line Gi are selected. Each of the plurality of pixels 1803 connected to the scanning line Gi receives a video signal and holds a potential corresponding to the video signal. Thereafter, the i-th scanning line Gi is deselected, the i + 1-th scanning line Gi + 1 is selected, and the plurality of pixels 1803 connected to the scanning line Gi + 1 are selected. The plurality of pixels 1803 connected to the scanning line Gi + 1 each input a video signal and hold a potential corresponding to the video signal. Thus, in one frame period, the scanning lines G1 to Gn are sequentially selected, and the pixels 1803 connected to the respective scanning lines are also selected in order. A plurality of pixels 1803 connected to each scanning line each input a video signal and hold a potential corresponding to the video signal.

From the above, the display device in FIG. 18 can input video signals to all the pixels independently, so that the function as an active matrix display device can be sufficiently obtained.

Further, since the display device in FIG. 18 uses the shift register of this embodiment as the scan line driver circuit 1802, the threshold shift of the transistor can be suppressed. The display device in FIG. 18 can have a long lifetime. The display device in FIG. 18 can improve driving capability. The display device in FIG. 18 can suppress malfunction. The display device in FIG. 18 can simplify the process.

Further, in the display device in FIG. 18, the signal line driver circuit 1801 that requires high-speed operation, the scan line driver circuit 1802, and the pixel 1803 are formed over different substrates;
As the semiconductor layer of the transistor included in 2 and the semiconductor layer of the transistor included in the pixel 1803, amorphous silicon can be used. Therefore, the manufacturing process can be simplified and the manufacturing cost can be reduced. Further, the display device in FIG. 18 can improve yield. Further, the display device of this embodiment can be increased in size. Alternatively, the manufacturing process can be simplified by using polysilicon or polycrystalline silicon as the semiconductor layer of the transistor.

Note that in the case where the signal line driver circuit 1801, the scan line driver circuit 1802, and the pixel 1803 are formed over the same substrate, a transistor semiconductor layer included in the scan line driver circuit 1802 and a semiconductor layer of the transistor included in the pixel 1803 Silicon or polycrystalline silicon may be used.

Note that as shown in FIG. 18, the number and arrangement of the driver circuits are not limited to those in FIG. 18 as long as a pixel can be selected and a video signal can be written to the pixel independently.

For example, as shown in FIG. 20, the scanning lines G1 to Gn are converted into the first scanning line driving circuit 2002.
Scanning may be performed by a and the second scanning line driving circuit 2002b. The first scanning line driving circuit 2002a and the second scanning line driving circuit 2002b are the scanning line driving circuit 1 shown in FIG.
The configuration is the same as that of 802, and the scanning lines G1 to Gn are scanned at the same timing. Further, the first scan line driver circuit 2002a and the second scan line driver circuit 2002b may be referred to as a first driver circuit and a second driver circuit, respectively.

The display device in FIG. 20 includes a first scan line driver circuit 2002a and a second scan line driver circuit 200.
Even if a defect occurs in one of 2b, the other of the scanning line driving circuit 2002a and the second scanning line driving circuit 2002b can scan the scanning lines G1 to Gn, so that redundancy can be provided. Further, in the display device of FIG. 20, the load of the first scan line driver circuit 2002a (the wiring resistance of the scan line and the parasitic capacitance of the scan line) and the load of the second scan line driver circuit 2002b are shown in FIG.
Therefore, the delay and rounding of signals input to the scanning lines G1 to Gn (output signals of the first scanning line driver circuit 2002a and the second scanning line driver circuit 2002b) can be reduced. Furthermore, since the load on the first scan line driver circuit 2002a and the load on the second scan line driver circuit 2002b are reduced, the display device in FIG. 20 can scan the scan lines G1 to Gn at high speed. it can. Furthermore, since the scanning lines G1 to Gn can be scanned at high speed, the panel can be enlarged or the panel can be made high definition. 20 is more effective when amorphous silicon is used for the semiconductor layers of the transistors included in the first scan line driver circuit 2002a and the second scan line driver circuit 2002b. Note that portions common to the configuration in FIG. 18 are denoted by common reference numerals, and description thereof is omitted.

As another example, FIG. 8 illustrates a display device in which a video signal can be written to pixels at high speed. In the display device in FIG. 8, a video signal is input to the odd-numbered pixel 1803 from the odd-numbered signal line, and a video signal is input to the even-numbered pixel 1803 from the even-numbered signal line. Further, in the display device of FIG. 8, the odd-numbered scanning lines among the scanning lines G1 to Gn are scanned by the first scanning line driving circuit 802a, and the even-numbered scanning lines among the scanning lines G1 to Gn. The scan line is scanned by the second scan line driver circuit 802b. Further, the first scan line driver circuit 802
The start signal input to b is input with a delay of ¼ period of the clock signal from the start signal input to the first scan line driver circuit 802a.

Note that the display device in FIG. 8 can perform dot inversion driving only by inputting a positive video signal and a negative video signal for each column to each signal line in one frame period. further,
The display device of FIG. 8 can perform frame inversion driving by inverting the polarity of the video signal input to each signal line for each frame period.

The operation of the display device in FIG. 8 will be described with reference to the timing chart in FIG. In the timing chart of FIG. 9, the first scanning line G1, the i-1th scanning line Gi-1, the ith scanning line Gi, the i + 1th scanning line Gi + 1, and the nth scanning line Gn. Indicates the timing of selection. Furthermore, in the timing chart of FIG. 9, one selection period is divided into a selection period a and a selection period b. Further, in the timing chart of FIG.
A case where the display device performs dot inversion driving and frame inversion driving will be described.

In FIG. 9, for example, the selection period a of the i-th scanning line Gi is the (i−1) -th scanning line Gi−1.
The selection period Tb of the i-th scanning line Gi overlaps the selection period a of the i + 1-th scanning line Gi + 1. Therefore, in the selection period a, i-1
The video signal input to the pixel 1803 in the (j + 1) th column is the pixel 1 in the ith row and jth column.
803 is input. Further, in the selection period b, the same video signal input to the pixel 1803 of the i row and j column is input to the pixel 1803 of the i + 1 row and j + 1 column. Note that a video signal input to the pixel 1803 in the selection period b is an original video signal, and a video signal input to the pixel 1803 in the selection period a is a video signal for precharging the pixel 1803. Therefore, each pixel 1803 is i in the selection period a.
After precharging with the video signal input to the pixel 1803 in the −1 row and j + 1 column, the original video signal (i row and j column) is input in the selection period b.

From the above, the display device in FIG. 8 can write a video signal to the pixel 1803 at high speed, and thus can be easily increased in size or increased in definition. Further, in the display device of FIG. 8, video signals having the same polarity are input to the signal lines in one frame period.
There is little charge / discharge of each signal line, and low power consumption can be realized. Further, in the display device of FIG. 8, the load on the IC for supplying the video signal is greatly reduced, so that the heat generation of the IC and the power consumption of the IC can be reduced. Further, in the display device in FIG. 8, the driving frequency of the first scan line driver circuit 802a and the second scan line driver circuit 802b can be halved.

Note that the display device of this embodiment can perform various driving methods depending on the structure and driving method of the pixel 1803. For example, in one frame period, the scan line driver circuit may scan the scan line a plurality of times.

8, 18, and 20, another wiring or the like may be added depending on the configuration of the pixel 1803. For example, a power supply line, a capacitor line, a new scanning line, or the like maintained at a constant potential may be added. However, when a scan line is newly added, a scan line driver circuit to which the shift register of this embodiment is applied may be newly added. As another example, dummy scanning lines, signal lines, power supply lines, or capacitor lines may be arranged in the pixel portion.

Note that although various drawings are used in this embodiment mode, the contents or part of the contents described in each figure can be applied to the contents or part of the contents described in another figure. Or they can be combined. Furthermore, in the figures described so far, for each part,
More figures can be constructed by combining different parts.

Similarly, the contents or part of the contents described in each drawing in this embodiment mode can be applied to the contents or a part of the contents described in the drawing in another embodiment mode. Or they can be combined.
Further, in the drawings of this embodiment mode, more drawings can be formed by combining each portion with a portion of another embodiment.

Note that this embodiment is an example in which the content described in the other embodiments is embodied, an example in which the content is slightly modified, an example in which a part is changed, an example in which the content is improved, and a detailed description An example of the case described, an example of application, an example of a related part, and the like are shown. Therefore, the contents described in other embodiments can be applied to this embodiment. Or they can be combined.

(Embodiment 2)
In this embodiment, a structure and a driving method of a flip-flop different from that in Embodiment 1, a driver circuit including the flip-flop, and a display device including the driver circuit will be described. Note that components similar to those in Embodiment 1 are denoted by common reference numerals, and detailed description of the same portions or portions having similar functions is omitted.

As the structure of the flip-flop in this embodiment, the same flip-flop structure as in Embodiment 1 can be used. However, the timing for driving the flip-flop is the first embodiment.
Is different. Therefore, in this embodiment mode, description of the structure of the flip-flop is omitted.

Note that the case where the driving timing of this embodiment is applied to the flip-flop of FIG. 1 will be described; however, the driving timing of this embodiment is shown in FIGS. 4A, 4B, 4C, and 4C. 4 (D), FIG. 5 (A), FIG. 5 (B), FIG. 5 (C), FIG. 5 (D), FIG. 7 (A), FIG.
It can be implemented by freely combining with the flip-flop of FIG. 7C, FIG. 21A, FIG. 21B, or FIG. Furthermore, the driving timing of the present embodiment can be implemented by freely combining with the driving timing described in the first embodiment.

Next, the operation of the flip-flop of this embodiment will be described with reference to the flip-flop of FIG. 1 and the timing chart of FIG. Further, the timing chart of FIG. 31 will be described by being divided into a selection period and a non-selection period. Further, the non-selection period is a first non-selection period,
The description will be divided into a second non-selection period, a set period a, a set period b, and a reset period.
Further, the selection period will be described by being divided into a selection period a and a selection period b. Further, in the non-selection period, the first non-selection period and the second non-selection period are repeated in the operation period excluding the set period a, the set period b, the selection period a, the selection period b, and the reset period.

In FIG. 31, a signal 3121, a signal 3125, a signal 3126, a potential 3141, a potential 3142, a signal 3122, and a signal 3123 are a signal input to the first wiring 121 and a signal input to the fifth wiring 125, respectively. , A signal input to the sixth wiring 126, a potential of the node 141, a potential of the node 142, a signal input to the second wiring 122, the third wiring 1
The signal output from 23 is shown.

Note that the signal 3121, the signal 3125, the signal 3126, the potential 3141, the potential 3142, the signal 3122, and the signal 3123 are changed to the signal 221, the signal 225, the signal 226, the potential 241, the potential 242, the signal 222, and the signal 223 shown in FIG. Corresponding and has similar characteristics.

Note that the flip-flop of this embodiment basically performs the same operation as the flip-flop described in Embodiment 1. However, the flip-flop of this embodiment is different from the flip-flop of Embodiment 1 in that the timing at which the H signal is input to the first wiring 121 is delayed by ¼ period of the clock signal.

Note that the flip-flop of this embodiment includes the first non-selection period and the second non-selection period of the flip-flop described in Embodiment 1 in the first non-selection period and the second non-selection period. The same operation is performed. Furthermore, the flip-flop of this embodiment performs the same operation as in the second non-selection period in the set period a. Further, in the reset period, the flip-flop of this embodiment performs the same operation as that of the reset period of the flip-flop described in Embodiment 1. Further, the flip-flop of this embodiment performs the same operation as that of the selection period of the flip-flop described in Embodiment 1 in the selection period a and the selection period b. However, the flip-flop of this embodiment is different from the flip-flop of Embodiment 1 in that an H signal is input to the first wiring 121 in the selection period a. However, even when an H signal is input to the first wiring 121 in the selection period a, the fifth transistor 105 is off, so that the operation of this embodiment is hardly affected. Therefore, the set period a, the set period b, the selection period a, the selection period b, the reset period, the first non-selection period, and the second
A detailed description of the flip-flop of this embodiment in the non-selection period is omitted.

Note that the layout area of the flip-flop of this embodiment can be reduced as in the flip-flop described in Embodiment 1. Further, the flip-flop of this embodiment can suppress a threshold shift of the transistor. Further, the flip-flop of this embodiment can simplify the process.

Note that by applying the timing chart illustrated in FIG. 32 to the flip-flop of this embodiment, the flip-flop of this embodiment can significantly shorten the fall time of the output signal. This is because the L signal can be input to the third wiring 123 through the first transistor 101 by shifting the timing at which the signal 3122 (reset signal) becomes H level.

Next, a structure and driving method of the shift register including the flip-flop of this embodiment described above will be described.

A structure of the shift register of this embodiment is described with reference to FIG. The shift register in FIG. 33 includes n flip-flops (flip-flops 3301_1 to flip-flop 3301_n).

A connection relation of the shift register in FIG. 33 is described. The shift register in FIG. 33 includes a 4N-3 (N is a natural number of 1 or more) stage flip-flop 330 in the i-th stage flip-flop 3301_i (any one of the flip-flops 3301_1 to 3011_n).
The 1_4N-3 and 4N-1 stage flip-flops 3301_4N-1 include the second wiring 3312, the fourth wiring 3314, the sixth wiring 3316, the seventh wiring 3317, the eighth wiring 3318, and the eleventh wiring. Wiring 3321 — i−1, eleventh wiring 3321 — i, eleventh wiring 3
321_i + 2. Furthermore, 4N-2 stage flip-flop 3301_4N
−2 and 4N stage flip-flops 3301_4N include a third wiring 3313, a fifth wiring 3315, a sixth wiring 3316, a seventh wiring 3317, an eighth wiring 3318, and an eleventh wiring.
Are connected to the first wiring 3321 — i−1, the eleventh wiring 3321 — i, and the eleventh wiring 3321 — i + 2. However, the first-stage flip-flop 3301_1 includes the first wiring 3111,
A second wiring 3312, a fourth wiring 3314, a sixth wiring 3316, a seventh wiring 3317,
The eighth wiring 3318, the eleventh wiring 3321_1, and the eleventh wiring 3321_3 are connected. Further, the (n−1) th stage flip-flop 3101 — n−1 includes the second wiring 3312,
A fourth wiring 3314, a sixth wiring 3316, a seventh wiring 3317, an eighth wiring 3318,
Tenth wiring 3320, eleventh wiring 3321_n-2, and eleventh wiring 3321_n-1
Connected to. Further, the n-th flip-flop 3301_n includes the third wiring 3313.
, Fifth wiring 3315, sixth wiring 3316, seventh wiring 3317, and eighth wiring 3318.
, To the ninth wiring 3319, the eleventh wiring 3321_n-1, and the eleventh wiring 3321_n.

The first wiring 3311 is connected to the first wiring 121 illustrated in FIG. 1 of the flip-flop 3301_1. The second wiring 3312 is connected to the fifth wiring 125 illustrated in FIG. 1 in the flip-flop 3301_4N-3, and is connected to the sixth wiring 126 illustrated in FIG. 1 in the flip-flop 3301_4N-1. The third wiring 3313 is formed using a flip-flop 3301_4N.
-2 is connected to the fifth wiring 125 shown in FIG. 1, and the flip-flop 3301_4N is connected to the sixth wiring 126 shown in FIG. The fourth wiring 3314 is connected to the flip-flop 3
301_4N-3 is connected to the sixth wiring 126 shown in FIG.
1_4N-1 is connected to the fifth wiring 125 shown in FIG. The fifth wiring 3315 is connected to the sixth wiring 126 illustrated in FIG. 1 in the flip-flop 3301_4N-2 and is connected to the fifth wiring 125 illustrated in FIG. 1 in the flip-flop 3301_4N. Sixth wiring 3
Reference numeral 306 denotes a flip-flop at all stages and is connected to the seventh wiring 127 shown in FIG. The seventh wiring 3317 is connected to the eighth wiring 128 illustrated in FIG. 1 by flip-flops at all stages.
The eighth wiring 3318 and all stages of flip-flops are connected to the fourth wiring 124, the ninth wiring 129, the tenth wiring 130, and the eleventh wiring 131 shown in FIG. Ninth wiring 331
9 is connected to the second wiring 122 illustrated in FIG. 1 of the flip-flop 3301 — n. First
The 0 wiring 3120 is the second wiring 122 illustrated in FIG. 1 of the flip-flop 3301_n−1.
Connected to. The eleventh wiring 3321_i corresponds to the flip-flop 3301_i-2 in FIG.
2 and the third wiring 123 illustrated in FIG. 1 of the flip-flop 3301_i.
And the first wiring 121 shown in FIG. 1 of the flip-flop 3301_i + 1.
Note that the eleventh wiring 3321_1 is the third wiring of the flip-flop 3301_1 illustrated in FIG.
1 and the first wiring 121 shown in FIG. 1 of the flip-flop 3301_2. Furthermore, the eleventh wiring 3321_2 includes the third wiring 123 illustrated in FIG. 1 of the flip-flop 3301_2 and the first wiring 12 illustrated in FIG. 1 of the flip-flop 3301_3.
1 is connected. Further, the eleventh wiring 3321 — n is a flip-flop 3301 — n.
Are connected to the third wiring 123 shown in FIG.

Note that the sixth wiring 3316 and the seventh wiring 3317 are each supplied with the potential of V1.
The eighth wiring 3318 is supplied with a potential of V2.

Note that the first wiring 3311, the second wiring 3312, the third wiring 3314, and the fifth wiring 33 are used.
15, signals are input to the ninth wiring 3319 and the tenth wiring 3320, respectively. A signal input to the first wiring 3311 is a start signal, a signal input to the second wiring 3312 is a first clock signal, and a signal input to the third wiring 3313 is a second clock. A signal that is input to the fourth wiring 3314 is a third clock signal,
A signal input to the fifth wiring 3315 is a fourth clock signal, and the ninth wiring 3319 is used.
A signal input to the first wiring is a first reset signal, and a signal input to the tenth wiring 3320 is a second reset signal. Further, the first wiring 3311, the second wiring 3312, the third wiring
Signals input to the first wiring 3314, the fifth wiring 3315, the ninth wiring 3319, and the tenth wiring 3320 are digital signals having an H signal potential of V1 and an L signal potential of V2.

Note that various signals, currents, or voltages may be input to the first wiring 3311 to the tenth wiring 3320, respectively.

Note that a signal is output from the eleventh wiring 3321_1 to the eleventh wiring 3321_n.
For example, a signal output from the eleventh wiring 3321 — i is a flip-flop 3301 —
The output signal of i. Further, signals output from the eleventh wiring 3321 — i are also an input signal of the flip-flop 3301 — i + 1 and a reset signal of the flip-flop 3301 — i-2.

Next, operation of the shift register illustrated in FIG. 33 is described with reference to a timing chart in FIG. 35 and a timing chart in FIG. Here, the timing chart of FIG. 35 is divided into a scanning period and a blanking period. The scan period is a period from when the selection signal is output from the eleventh wiring 3311_1 to when the selection signal is output from the eleventh wiring 3311_n. The blanking period is a period from when the selection signal is output from the eleventh wiring 3311_n to when the selection signal is output from the eleventh wiring 3311_1.

In FIG. 35, the signal 3511 input to the first wiring 3311 and the second wiring 33
12, a signal 3513 input to the third wiring 3313, a signal 3514 input to the fourth wiring 3314, and a signal 3515 input to the fifth wiring 3315.
, A signal 3519 input to the ninth wiring 3319, a signal 3520 input to the tenth wiring 3320, a signal 3521_1 output to the eleventh wiring 3321_1, and a signal 3521_n output to the eleventh wiring 3321_n are shown. ing. Further, in FIG. 36, a signal 3611 input to the first wiring 3311, a signal 3621_1 output to the eleventh wiring 3321_1, a signal 3621_i-1 output to the eleventh wiring 3321_i-1, an eleventh wiring The signal 3621_i output to 3321_i and the eleventh wiring 3321_i + 1
And the signal 3621_i + 1 output to the 11th wiring 3321_n.
21_n.

As illustrated in FIG. 36, for example, when the flip-flop 3301_i-1 is in the selection period a, an H signal is output from the eleventh wiring 3321_i-1. At this time, flip-flop 3
301_i is the set period a. After that, the flip-flop 3301_i-1 enters the selection period b, and the H signal is output from the eleventh wiring 3321_i-1. At this time, the flip-flop 3301_i is in the selection period a. Then flip-flop 33
01_i-1 is a reset period, and an H signal is output from the eleventh wiring 3321_i-1. At this time, the flip-flop 3301_i is in the selection period b. That is, in the shift register of this embodiment, H signals are sequentially output from the flip-flop 3301_i-1, but the selection period b of the flip-flop 3301_i-1 and the flip-flop 3301_
i has a period in which the selection period a overlaps.

Note that in the case where the timing chart in FIG. 32 is applied to the flip-flop in this specification, the structure of the shift register may be as illustrated in FIG. In the shift register in FIG. 34, for example, the wiring 122 illustrated in FIG. 1 of the i-th flip-flop 3301_i is the eleventh wiring 33.
21_i + 3. Further, the second wiring 122 illustrated in FIG. 1 of the flip-flop 3301_n-2 is connected to the twelfth wiring 3322 to which the third reset signal is input.
Note that portions common to FIG. 33 are denoted by common reference numerals and description thereof is omitted.

Note that since the flip-flop of this embodiment is applied to the shift register of this embodiment, the threshold shift of the transistor is suppressed, the lifetime is increased, the driving ability is improved, the malfunction is suppressed, the process Simplification can be achieved.

Note that the shift register of this embodiment can be freely combined with the shift register described in Embodiment 1. For example, the shift register of the present embodiment is shown in FIGS.
It can be implemented by freely combining with the shift register of FIGS. Specifically, in the shift register of this embodiment, a buffer may be connected to the eleventh wiring 3321_1 to the eleventh wiring 3321_n, a reset signal may be generated internally, or a dummy flip-flop May be placed. As already described, the same reference numerals are used for portions common to the first embodiment, and description thereof is omitted.

Next, a structure and driving method of the display device including the shift register of this embodiment described above will be described. Note that the display device of this embodiment mode includes at least the flip-flop of this embodiment mode.

The structure of the display device of this embodiment will be described with reference to FIG. In the display device in FIG. 16, the scanning lines G <b> 1 to Gn are scanned by the scanning line driving circuit 1602. In addition, FIG.
In the display device 6, a video signal is input to the odd-numbered pixel 1803 from the odd-numbered signal line, and a video signal is input to the even-numbered pixel 1803 from the even-numbered signal line. In addition, FIG.
The parts common to the configuration of FIG.

Note that the display device in FIG. 16 can perform the same operation as the display device in FIG. 8 with one scan line driver circuit by applying the shift register of this embodiment to the scan line driver circuit 1602. Therefore, the display device in FIG. 16 can write a video signal to a pixel at high speed. Further, the display device in FIG. 16 can be increased in size or increased in definition. Further, the display device in FIG. 16 can further reduce power consumption in the display device in FIG. Further, the display device of FIG. 16 can suppress heat generation of the IC. Further, the display device in FIG. 16 can save power in the IC.

Note that as shown in FIG. 22, the scanning lines G1 to Gn are connected to the first scanning line driving circuit 2202a.
Further, scanning may be performed by the second scan line driver circuit 2202b. The first scanning line driving circuit 2002a and the second scanning line driving circuit 2002b are the same as the scanning line driving circuit 16 shown in FIG.
The scanning line G1 to the scanning line Gn are scanned at the same timing. Further, the first scan line driver circuit 2202a and the second scan line driver circuit 2202b may be referred to as a first driver circuit and a second driver circuit, respectively.

The display device in FIG. 22 includes a first scan line driver circuit 2202a and a second scan line driver circuit 220.
Even if a defect occurs in one of 2b, the other of the scanning line driver circuit 2202a and the second scanning line driver circuit 2202b can scan the scanning lines G1 to Gn, so that redundancy can be provided. Further, in the display device in FIG. 22, since the first scan line driver circuit 2202a and the second scan line driver circuit 2202b scan the scan lines G1 to Gn, the load on the first scan line driver circuit 2202a ( The wiring resistance of the scan line and the parasitic capacitance of the scan line) and the load of the second scan line driver circuit 2202b can be halved compared to FIG. Accordingly, in the display device in FIG. 22, since the load on the first scan line driver circuit 2202a and the load on the second scan line driver circuit 2202b are reduced, signals (first signals) input to the scan lines G1 to Gn. Delay and rounding of output signals of the first scan line driver circuit 2202a and the second scan line driver circuit 2202b can be reduced. Further, in the display device in FIG. 22, the load on the first scan line driver circuit 2202a and the load on the second scan line driver circuit 2202b are reduced, so that the scan lines G1 to Gn are reduced.
Can be scanned at high speed. Furthermore, since the scanning lines G1 to Gn can be scanned at high speed, the panel can be enlarged or the panel can be made high definition. Further, the display device in FIG. 22 has a merit when amorphous silicon is used for a semiconductor layer of a transistor included in the first scan line driver circuit 2202a and the second scan line driver circuit 2202b.
It is even more effective. Note that portions common to the configuration in FIG. 16 are denoted by common reference numerals and description thereof is omitted.

Note that although various drawings are used in this embodiment mode, the contents or part of the contents described in each figure can be applied to the contents or part of the contents described in another figure. Or they can be combined. Furthermore, in the figures described so far, for each part,
More figures can be constructed by combining different parts.

Similarly, the contents or part of the contents described in each drawing in this embodiment mode can be applied to the contents or a part of the contents described in the drawing in another embodiment mode. Or they can be combined.
Further, in the drawings of this embodiment mode, more drawings can be formed by combining each portion with a portion of another embodiment.

Note that this embodiment is an example in which the content described in the other embodiments is embodied, an example in which the content is slightly modified, an example in which a part is changed, an example in which the content is improved, and a detailed description An example of the case described, an example of application, an example of a related part, and the like are shown. Therefore, the contents described in other embodiments can be applied to this embodiment. Or they can be combined.

(Embodiment 3)
In this embodiment, a structure and a driving method of a flip-flop different from those in Embodiments 1 and 2, a driving circuit including the flip-flop, and a display device including the driving circuit will be described. The flip-flop of this embodiment is characterized in that the output signal of the flip-flop and the transfer signal of the flip-flop are output from different wirings by different transistors. Note that components similar to those in Embodiments 1 and 2 are denoted by common reference numerals, and detailed description of the same portions or portions having similar functions is omitted.

A basic structure of the flip-flop of this embodiment is described with reference to FIG. FIG.
7 includes a first transistor 101, a second transistor 102,
The third transistor 103, the fourth transistor 104, the fifth transistor 105, the sixth transistor 106, the seventh transistor 107, the eighth transistor 108, and the ninth transistor 109 are included. In this embodiment, the eighth transistor 108 and the ninth transistor 109 are N-channel transistors and are turned on when a gate-source voltage (Vgs) exceeds a threshold voltage (Vth). And

Note that the flip-flop in FIG. 27 is similar to the flip-flop in FIG.
This is the same as that in which the eighth and ninth transistors 109 are added. Therefore, the first transistor 101, the second transistor 102, the third transistor 103, the fourth transistor 104, the fifth transistor 105, the sixth transistor 106, and the seventh transistor 107 are the same as those in FIG. Things can be used.

A connection relation of the flip-flop of FIG. 27 will be described. The first electrode (one of the source electrode and the drain electrode) of the first transistor 101 is connected to the fifth wiring 125, and the second electrode (the other of the source electrode and the drain electrode) of the first transistor 101 is the first electrode. 3 wiring 1
23. The first electrode of the second transistor 102 is connected to the fourth wiring 124, and the second electrode of the second transistor 102 is connected to the third wiring 123. The first electrode of the third transistor 103 is connected to the sixth wiring 126, and the third transistor 103
The second electrode is connected to the gate electrode of the second transistor 102, and the gate electrode of the third transistor 103 is connected to the seventh wiring 127. The first of the fourth transistor 104
Is connected to the ninth wiring 129, the second electrode of the fourth transistor 104 is connected to the gate electrode of the second transistor 102, and the gate electrode of the fourth transistor 104 is connected to the first transistor 101. Connected to the gate electrode. First of the fifth transistor 105
Are connected to the eighth wiring 128, the second electrode of the fifth transistor 105 is connected to the gate electrode of the first transistor 101, and the gate electrode of the fifth transistor 105 is connected to the first wiring 121. Connected. The first electrode of the sixth transistor 106 is connected to the tenth wiring 130, and the second electrode of the sixth transistor 106 is connected to the first transistor 101.
The gate electrode of the sixth transistor 106 is connected to the gate electrode of the second transistor 102. The first electrode of the seventh transistor 107 is connected to the eleventh wiring 131, and the second electrode of the seventh transistor 107 is connected to the first transistor 10.
1 and the gate electrode of the seventh transistor 107 is connected to the second wiring 122.
Connected to. The first electrode of the eighth transistor 108 is connected to the thirteenth wiring 133, the second electrode of the eighth transistor 108 is connected to the twelfth wiring, and the gate electrode of the eighth transistor 108 is connected to the first wiring The transistor 101 is connected to the gate electrode. The first electrode of the ninth transistor 109 is connected to the fourteenth wiring 134, and the ninth transistor 1
The second electrode of 09 is connected to the twelfth wiring 132, and the gate electrode of the ninth transistor 109 is connected to the gate electrode of the second transistor 102.

Note that the twelfth wiring 132 and the third wiring 133 may be referred to as a sixth signal line and a seventh signal line, respectively. Further, the fourteenth wiring may be referred to as a seventh power supply line.

Note that V2 is supplied to the fourteenth wiring 134.

Note that a signal is input to the thirteenth wiring 133. The signal input to the third wiring is the fifth
A signal similar to that input to the wiring 125 can be used.

Note that a signal is output from the twelfth wiring 132. Further, as described in Embodiment Mode 1, a signal is also output from the third wiring 123.

Note that the first wiring 121, the second wiring 122, the fourth wiring 124, the fifth wiring 125, the sixth wiring 126, the seventh wiring 127, the eighth wiring 128, the ninth wiring 129, A signal input to or a potential supplied to each of the tenth wiring 130 and the eleventh wiring 131 is as shown in FIG.
It is the same.

Note that the flip-flop in FIG. 27 is similar to the flip-flop in FIG.
Although the case where the eighth and ninth transistors 109 are added is shown, FIG.
B), FIG. 4C, FIG. 4D, FIG. 5A, FIG. 5B, FIG. 5C, FIG. 5D, FIG. 7A, and FIG. The eighth transistor 108 and the ninth transistor 109 may be added to the flip-flops illustrated in FIGS. 7C, 21A, 21B, and 21C.

Next, the operation of the flip-flop shown in FIG. 1 will be described with reference to the timing chart of FIG. Furthermore, common parts with the timing chart of FIG.

Note that the signal 232 indicates a signal output from the twelfth wiring 132. Further, the signal 221, the signal 225, the signal 226, the potential 241, the potential 242, the signal 222, and the signal 22 are displayed.
3 is the same as FIG. However, the signal 221, the signal 225, the signal 226, the potential 241,
As the potential 242, the signal 222, and the signal 223, the same one as in FIG. 6, FIG. 31, or FIG. 32 can be used.

In this embodiment mode, as described above, the output signal of the flip-flop and the transfer signal of the flip-flop are output from different wirings by different transistors. That is, the flip-flop in FIG. 27 outputs a signal from the third wiring 123 by the first transistor 101 and the second transistor 102, and the eighth transistor 108.
A signal is output from the twelfth wiring 132 by the ninth transistor. In addition, the eighth
The transistor 108 and the ninth transistor are connected in the same manner as the first transistor 101 and the second transistor 102. Therefore, as shown in FIG.
The signal output from the third wiring 123 (signal 232) is the signal output from the third wiring 123 (signal 223).
The waveform is almost the same as). Here, the signal 232 is the output signal of the flip-flop, and the signal 223 is the transfer signal of the flip-flop. However, the signal 223 may be the output signal of the flip-flop, and the signal 232 may be the transfer signal of the flip-flop.

Note that the eighth transistor 108 and the ninth transistor 109 have functions similar to those of the first transistor 101 and the second transistor 102, respectively. Further, the eighth transistor 108 and the ninth transistor 109 may be referred to as a buffer portion.

From the above, the flip-flop in FIG. 27 can prevent malfunction even when a large load is connected to the third wiring 132 and a delay or a rounding occurs in the signal 232. This is because the flip-flop of FIG. 27 outputs the output signal of the flip-flop and the transfer signal of the flip-flop from different wirings by different transistors, so that the delay of the output signal, the rounding, etc. are the operations of the flip-flop. This is because it has no effect.

In addition, the flip-flop of FIG. 27 is similar to the flip-flops described in Embodiments 1 and 2, the layout area is reduced, the threshold shift of the transistor is suppressed, the process is simplified, a large display device, and the like. Advantages such as the manufacture of the semiconductor device and the manufacture of a semiconductor device such as a long-life display panel can be obtained.

Note that the operation timing described in Embodiment 2 can also be applied to the flip-flop in this embodiment.

A structure and a driving method of the shift register including the flip-flop of this embodiment described above will be described.

A structure of the shift register of this embodiment is described with reference to FIG. The shift register in FIG. 29 includes n flip-flops (flip-flops 2901_1 to 2901_n).

Connection relations of the flip-flop in FIG. 29 will be described. The flip-flop in FIG.
i-th flip-flop 2901_i (flip-flops 2901_1 to 2901_n
Any one of the second wiring 2912, the third wiring 2913, and the fourth wiring 2914.
To the fifth wiring 2915, the sixth wiring 2916, the eighth wiring 2918_i-1, the eighth wiring 2918_i, the eighth wiring 2918_i + 1, and the ninth wiring 2919_i.
However, the first-stage flip-flop 2901_1 includes a first wiring 2911 and a second wiring 2
912, the third wiring 2913, the fourth wiring 2914, the fifth wiring 2915, and the sixth wiring 2
916, the eighth wiring 2918_1, the eighth wiring 2918_2, and the ninth wiring 2919_1 are connected. Further, the n-th flip-flop 2901_n includes the second wiring 2912,
A third wiring 2913, a fourth wiring 2914, a fifth wiring 2915, a sixth wiring 2916,
The seventh wiring 2917, the eighth wiring 2918_n-1, the eighth wiring 2918_n, and the ninth wiring 2919_n are connected.

The first wiring 2911 is the first wiring 121 illustrated in FIG. 27 of the flip-flop 2901_1.
Connected to. The second wiring 2912 is connected to the fifth wiring 125 and the third wiring 133 shown in FIG. 27 in the odd-numbered flip-flops, and is connected to the second wiring 2912 in FIG.
7 to the sixth wiring 126 shown in FIG. The third wiring 2913 is connected to the sixth wiring 126 illustrated in FIG. 27 in the odd-numbered flip-flops, and is connected to the fifth wiring 125 and the third wiring 133 illustrated in FIG. 27 in the even-numbered flip-flops. Is done. The fourth wiring 2914 is
The flip-flops at all stages are connected to the seventh wiring 127 shown in FIG. Fifth wiring 29
Reference numeral 15 denotes a flip-flop at all stages, which is connected to the eighth wiring 128 shown in FIG. The sixth wiring 2916 is connected to the fourth wiring 124, the ninth wiring 129, the 29th wiring 130, and the eleventh wiring 131 shown in FIG. Eighth wiring 2918
_I is the second wiring 122 of the flip-flop 2901_i-1 shown in FIG. 27, the third wiring 123 of the flip-flop 2901_i shown in FIG. 27, and the flip-flop 2901i.
+1 is connected to the first wiring 121 shown in FIG. Note that the eighth wiring 2918_1 is connected to the third wiring 123 illustrated in FIG. 27 of the flip-flop 2901_1 and the first wiring 121 illustrated in FIG. 27 of the flip-flop 2901_2. Further, an eighth wiring 291
8_n is connected to the second wiring 122 illustrated in FIG. 27 of the flip-flop 2901_n−1 and the third wiring 123 illustrated in FIG. 27 of the flip-flop 2901_n. 9th wiring 2
The 919_1 to ninth wiring 2919_n are connected to the twelfth wiring 132 illustrated in FIG. 27 of the flip-flops 2901_1 to 2901_n, respectively.

Note that the flip-flops 2901_1 to 2901_n and the first wiring 29
11, second wiring 2912, third wiring 2913, fourth wiring 2914, and fifth wiring 29.
15, the fifth wiring 2916, and the seventh wiring 2907 are the flip-flops 1001_1 to 1001_n, the first wiring 1011, the second wiring 1012, the third wiring 1013, and the fourth wiring shown in FIG. It corresponds to the wiring 1014, the fifth wiring 1015, the fifth wiring 1016, and the seventh wiring 1007, and a similar signal or potential is supplied.

Next, operation of the shift register illustrated in FIG. 29 is described with reference to a timing chart of FIG.

In FIG. 30, the signal 3011 input to the first wiring 2911, the eighth wiring 2918 —
1 is output to the first wiring 3018_1, and the signal 3018_ is output to the eighth wiring 2918_i.
i, the signal 3018_i + 1 output to the eighth wiring 2918_i + 1, the eighth wiring 291
The signal 3018_n output to 8_n and the signal 301 output to the ninth wiring 2919_1
9_1, a signal 3019_i output to the ninth wiring 2918_i, and a ninth wiring 2918_
A signal 3019_i + 1 output to i + 1 and a signal 3018_n output to the ninth wiring 2919_n are illustrated.

As shown in FIG. 30, for example, when the flip-flop 2901_i enters the selection period,
H signal is output from the second wiring 2918 — i and the ninth wiring 2919 — i. At this time, the flip-flop 2901_i + 1 is in the set period. Then flip-flop 290
1_i is a reset period, and an L signal is output from the eighth wiring 2918_i and the ninth wiring 2919_i. At this time, the flip-flop 2901_i + 1 is in a selection period. After that, the flip-flop 2901_i enters the first non-selection period, and the eighth wiring 29
The 18_i and the ninth wiring 2919_i are in a floating state, and the potential is maintained at the L level. At this time, the flip-flop 2901_i + 1 is in the reset period. After that, the flip-flop 2901_i enters the second non-selection period, and an L signal is output from the eighth wiring 2918_i and the ninth wiring 2919_i. At this time, the flip-flop 2901_i + 1
Is the first non-selection period. Thus, the flip-flop 2901_i repeats the first non-selection period and the second non-selection period until the next set period.

From the above, the shift register in FIG. 29 can output a transfer signal from the eighth wiring 2918_1 to the eighth wiring 2918_n in order. Further, the shift register in FIG. 29 can output a selection signal from the ninth wiring 2919_1 to the ninth wiring 2919_n in order. That is, the shift register in FIG. 29 can scan the ninth wiring 2919_1 to the ninth wiring 2919_n. Therefore, the shift register in FIG. 29 can sufficiently function as a shift register.

Further, the shift register in FIG. 29 includes a ninth wiring 2919_1 to a ninth wiring 2919_n.
Even when a large load (such as a resistor and a capacitor) is connected to the power supply, it can operate without being affected by the load. Further, the shift register in FIG. 29 includes a ninth wiring 2919_1 to a ninth wiring 29.
Even if any of 19_n is short-circuited with the power supply line or the signal line, the normal operation can be continued. Therefore, the shift register in FIG. 29 can improve driving capability. This is because the shift register in FIG. 29 divides the transfer signal of each flip-flop and the output signal of each flip-flop.

Further, the shift register in FIG. 29 is applied with the flip-flop described in this embodiment, so that the layout area can be reduced, the threshold shift of the transistor can be suppressed, the process can be simplified,
Advantages such as manufacture of a semiconductor device such as a large display device and manufacture of a semiconductor device such as a long-life display panel can be obtained.

Note that the configuration is not limited to the configuration in FIG. 29 as long as the same operation as that in FIG. 29 is performed. For example,
By implementing in combination with the shift register of FIG. 13, FIG. 14, FIG. 15, and FIG. 17, the same merit as FIG. 13, FIG. 14, FIG. 15, and FIG.

A structure and a driving method of the display device including the shift register of this embodiment described above are described. Note that the display device of this embodiment mode includes at least the flip-flop of this embodiment mode.

As the display device in this embodiment, the display devices in FIGS. 8, 18, 16, 20, and 22 can be used. Therefore, in the display device of this embodiment, when the shift register of this embodiment is applied as a scan line driver circuit, the layout area can be reduced. Further, the display device in this embodiment can suppress threshold shift of the transistor. Further, the display device of this embodiment can simplify the process. Further, the display device of this embodiment can be increased in size or definition. Furthermore, the display device of this embodiment can have a long lifetime. In particular, when the shift register of this embodiment is used as a scan line driver circuit in the display devices in FIGS. 8, 16, and 22, enlargement or high definition can be achieved. Further, the display device in FIG. 8, FIG. 16, or FIG. 22 to which the shift register of this embodiment is applied can achieve power saving. Furthermore, the display device in FIG. 8, FIG. 16, or FIG. 22 to which the shift register of this embodiment is applied can suppress the heat generation of the IC. Furthermore, the display device of FIG. 8, FIG. 16, or FIG. 22 to which the shift register of this embodiment is applied is I
C power saving can be achieved.

Note that although various drawings are used in this embodiment mode, the contents or part of the contents described in each figure can be applied to the contents or part of the contents described in another figure. Or it can be combined and combined. Further, in the drawings described so far, more parts can be formed by combining each part with another part.

Similarly, the contents or part of the contents described in each drawing in this embodiment mode can be applied to the contents or a part of the contents described in the drawing in another embodiment mode. Or they can be combined.
Further, in the drawings of this embodiment mode, more drawings can be formed by combining each portion with a portion of another embodiment.

Note that this embodiment is an example in which the content described in the other embodiments is embodied, an example in which the content is slightly modified, an example in which a part is changed, an example in which the content is improved, and a detailed description An example of the case described, an example of application, an example of a related part, and the like are shown. Therefore, the contents described in other embodiments can be applied to or combined with this embodiment.

(Embodiment 4)
In this embodiment, the case where a p-channel transistor is used as a transistor included in the flip-flop in this specification will be described. Further, a structure and a driving method of a driver circuit including the flip-flop and a display device including the driver circuit are described.

In the flip-flop of this embodiment, the case where the polarity of the transistor included in the flip-flop in FIG. 1 is a P-channel type will be described. However, FIG. 4 (A), FIG. 4 (B), FIG.
(C), FIG. 4 (D), FIG. 5 (A), FIG. 5 (B), FIG. 5 (C), FIG. 5 (D), FIG.
The polarity of the transistor included in the flip-flop illustrated in FIG. 7B, FIG. 7C, FIG. 21A, FIG. 21B, FIG. 21C, or FIG. it can. Further, the flip-flop of this embodiment can be implemented by being freely combined with the description in Embodiments 1 to 3.

A basic structure of the flip-flop of this embodiment is described with reference to FIG. FIG.
3 includes a first transistor 2301 and a second transistor 230.
2, third transistor 2303, fourth transistor 2304, fifth transistor 2
305, a sixth transistor 2306, and a seventh transistor 2307 are included. In this embodiment, the first transistor 2301, the second transistor 2302, the third transistor 2303, the fourth transistor 2304, the fifth transistor 2305, and the sixth transistor
The transistor 2306 and the seventh transistor 2307 are P-channel transistors, and the absolute value of the gate-source voltage (| Vgs |) is the absolute value of the threshold voltage (| Vt
When h |) is exceeded (when Vgs is less than Vth), a conductive state is assumed.

A connection relation of the flip-flop of FIG. 23 will be described. The first electrode (one of the source electrode and the drain electrode) of the first transistor 2301 is connected to the fifth wiring 2325, and the second electrode (the other of the source electrode and the drain electrode) of the first transistor 2301 is the first electrode. 3 wiring 2323. The first electrode of the second transistor 2302 is connected to the fourth wiring 23.
24, and the second electrode of the second transistor 2302 is connected to the third wiring 2323. The first electrode of the third transistor 2303 is connected to the sixth wiring 2326, the second electrode of the third transistor 2303 is connected to the gate electrode of the second transistor 2302, and the gate of the third transistor 2303 The electrode is connected to the seventh wiring 2327.
The first electrode of the fourth transistor 2304 is connected to the ninth wiring 2329, the second electrode of the fourth transistor 2304 is connected to the gate electrode of the second transistor 2302,
The gate electrode of the fourth transistor 2304 is connected to the gate electrode of the first transistor 2301. The first electrode of the fifth transistor 2305 is connected to the eighth wiring 2328, the second electrode of the fifth transistor 2305 is connected to the gate electrode of the first transistor 2301, and the gate of the fifth transistor 2305 The electrode is connected to the first wiring 2321. The first electrode of the sixth transistor 2306 is connected to the tenth wiring 2330,
The second electrode of the transistor 2306 is connected to the gate electrode of the first transistor 2301, and the gate electrode of the sixth transistor 2306 is connected to the gate electrode of the second transistor 2302. The first electrode of the seventh transistor 2307 is connected to the eleventh wiring 2331, the second electrode of the seventh transistor 2307 is connected to the gate electrode of the first transistor 2301, and the gate of the seventh transistor 2307 The electrode is connected to the second wiring 2322.

Note that the gate electrode of the first transistor 2301, the gate electrode of the fourth transistor 2304, the second electrode of the fifth transistor 2305, the second electrode of the sixth transistor 2306, and the second electrode of the seventh transistor 2307 A connection portion of the electrodes is referred to as a node 2341.
Further, the gate electrode of the second transistor 2302 and the second electrode of the third transistor 2303
A connection portion of the second electrode, the second electrode of the fourth transistor 2304, and the gate electrode of the sixth transistor 2306 is a node 2342.

Fourth wiring 2324, ninth wiring 2329, tenth wiring 2330, and eleventh wiring 23
31 may be connected to each other or the same wiring. Further, the seventh wiring 23
27 and the eighth wiring 2328 may be connected to each other or the same wiring.

Note that the first transistor 2301 to the seventh transistor 2307 correspond to the first transistor 101 to the seventh transistor 107 in FIG. 1, respectively, and have similar functions.

Note that each of the first wiring 2321 to the eleventh wiring 2331 is the first wiring 121 in FIG.
Corresponds to the eleventh wiring 131. However, the first wiring 2321 to the eleventh wiring 23.
A signal input to 31, a potential to be supplied, or a signal to be output is the first wiring 121 in FIG.
The H level and L level are inverted compared to the signal input to the eleventh wiring 131, the supplied potential, or the output signal.

Note that a potential of V2 is supplied to each of the seventh wiring 2327 and the eighth wiring 2328,
Fourth wiring 2324, ninth wiring 2329, tenth wiring 2330, and eleventh wiring 23
31 is supplied with the potential V1.

Note that the first wiring 2321, the second wiring 2322, the fifth wiring 2325, and the sixth wiring 2 are used.
Each signal is input to 326. A signal input to the first wiring 2321 is a start signal, a signal input to the second wiring 2322 is a reset signal, and a signal input to the fifth wiring 2325 is a first clock signal. The signal input to the sixth wiring 2326 is a second clock signal. Further, the first wiring 2321 and the second wiring 2322 are used.
The signals inputted to the fifth wiring 2325 and the sixth wiring 2326 have an H signal potential of V1 (hereinafter also referred to as H level) and an L signal potential of V2 (hereinafter also referred to as L level).
It is a digital signal.

Note that the first wiring 2321, the second wiring 2322, the second wiring 2322 to the eleventh wiring 2 are used.
Various signals, currents, or voltages may be input to 331, respectively.

Note that a signal is output from the third wiring 2323. A signal output from the third wiring 2323 is an output signal of the flip-flop of each stage, and is also a start signal (hereinafter also referred to as a transfer signal) of the flip-flop of the next stage. Further, the third wiring 2323
The signal output from is a digital signal with the potential of the H signal being V1 (hereinafter also referred to as H level) and the potential of the L signal being V2 (hereinafter also referred to as L level).

Next, the operation of the flip-flop shown in FIG. 23 will be described with reference to the timing chart of FIG. Further, the timing chart of FIG. 24 will be described by being divided into a selection period and a non-selection period. Further, the non-selection period will be described by being divided into a first non-selection period, a second non-selection period, a set period, and a reset period. Here, as shown in the timing chart of FIG. 24, each period includes a set period, a selection period, a reset period, a first non-selection period, a second non-selection period, a first non-selection period, and a second period. They are arranged in the order of the non-selection period. In other words, the set period,
In the operation period excluding the selection period and the reset period, the first non-selection period and the second non-selection period are sequentially repeated. Furthermore, the period before the set period is the second non-selection period.

Note that the timing chart of FIG. 24 is the same as that obtained by inverting the H level / L level of the timing chart of FIG.

It should be noted that the flip-flop of this embodiment is not only the flip-flop of the H level / L level of FIG. 2 but also the flip of the H level / L level of the timing charts of FIGS. 6, 28, 31 and 32. You may use what you did.

In FIG. 24, a signal 2421, a signal 2425, a signal 2426, a potential 2441, a potential 2442, a signal 2422, and a signal 2423 are a signal input to the first wiring 2321 and a signal input to the fifth wiring 2325, respectively. , A signal input to the sixth wiring 2326,
A potential of the node 2341, a potential of the node 2342, a signal input to the second wiring 2322,
A signal output from the third wiring 2323 is illustrated.

Note that the signal 2421, the signal 2425, the signal 2426, the potential 2441, the potential 2442, the signal 2422, and the signal 223 correspond to the signal 221, the signal 225, the signal 226, the potential 241, the potential 242, the signal 222, and the signal 223 in FIG. 2, respectively. doing. However, as already described, the H level and the L level are inverted.

First, in the set period shown in FIG. 24A, since the signal 2421 is L level, the fifth transistor 2305 is turned on, and since the signal 2422 is H level, the seventh transistor 230 is turned on.
7 turns off. At this time, the potential of the node 2341 is the second potential of the fifth transistor 2305.
, The potential of the eighth wiring 2328 and the fifth transistor 2305
V2 + | Vth (2305) | (Vth (23
05): threshold voltage of the fifth transistor 2305). Accordingly, the first transistor 2301 and the fourth transistor 2304 are turned on, and the fifth transistor 2305 is turned off. At this time, the potential of the node 2342 (the potential 2442) is equal to the third transistor 2
It is determined by the resistance ratio (L / W and applied voltage) between the transistor 303 and the fourth transistor 2304, and becomes V1−θ (θ: an arbitrary positive number). Further, θ <| Vth (2302) | (Vt
h (2302): threshold voltage of the second transistor 2302) and θ <| Vth (23
06) | (the threshold voltage of the sixth transistor 2306). That is, the ninth wiring 2
A potential difference (V 1 −V 2) between the potential (V 1) of 329 and the potential (V 2) of the sixth wiring 2326 is divided by the third transistor 2303 and the fourth transistor 2304. Accordingly, the second transistor 2302 and the sixth transistor 2306 are turned off. In this manner, in the set period, the third wiring 2323 has the fifth wiring 2325 to which the H signal is input.
And the potential of the third wiring 2323 becomes V1. Accordingly, the H signal is output from the third wiring 2323. Further, the node 2341 has a potential of V2 + | Vth (23
05) Floating state while maintaining |.

In the selection period shown in FIG. 24B), the signal 2421 becomes H level and the fifth transistor 2
Since 305 is turned off and the signal 2422 remains at the H level, the seventh transistor 2307 remains off. At this time, the potential of the node 2341 is maintained at V2 + | Vth (2305) |. Accordingly, the first transistor 2301 and the fourth transistor 2304 remain on. The potential of the node 2342 at this time is V1 because the sixth wiring 2326 is at an H level. Therefore, the second transistor 2302 and the sixth transistor 23
06 remains off. Here, since the L signal is input to the fifth wiring 2325, the third wiring 2325
The potential of the wiring 2323 starts to decrease. Then, the potential of the node 2341 decreases from V2 + | Vth (2305) | by the bootstrap operation, and V2- | Vth (230
1) | −γ (Vth (2301): threshold voltage of the first transistor 2301, γ: any positive number). Accordingly, the potential of the third wiring 2323 is equal to that of the fifth wiring 2325 and thus becomes V2. Note that this bootstrap operation is performed by capacitive coupling of parasitic capacitance between the gate electrode and the second electrode of the first transistor 2301.
In this manner, in the selection period, the third wiring 2323 is the fifth wiring 2 to which the L signal is input.
Since it is electrically connected to 325, the potential of the third wiring 2323 becomes V2. Accordingly, the L signal is output from the third wiring 2323.

In the reset period illustrated in FIG. 24C, since the signal 2421 remains at the H level, the fifth transistor 2305 remains off, the signal 2422 becomes the L level, and the seventh transistor 2307 is turned on. At this time, the potential of the node 2341 is the potential of the eleventh wiring (V
Since 1) is supplied via the seventh transistor 2307, it becomes V1. Accordingly, the first transistor 2301 and the fourth transistor 2304 are turned off. Node 2 at this time
The potential of 342 is the same as that of the sixth transistor 2303 because the second electrode of the third transistor 2303 serves as a source electrode.
Therefore, V2 + | Vth (2303) | (Vth (2303): threshold voltage of the third transistor 2303) is obtained by subtracting the threshold voltage of the third transistor 2303 from the potential (V2) of the second wiring 2326. It becomes. Accordingly, the second transistor 2302 and the sixth transistor 2306 are turned on. Thus, in the reset period, the third wiring 2323 is V
1 is electrically connected to the fourth wiring 2324 to which 1 is supplied, so that the potential of the third wiring 2323 is V
1 Accordingly, the H signal is output from the third wiring 2323.

In the first non-selection period illustrated in FIG. 24D, since the signal 2421 remains at the H level, the fifth transistor 2305 remains off, and the signal 2422 becomes the H level so that the seventh transistor 2307 is off. To do. At this time, the potential of the node 2342 is the sixth wiring 2326.
Since the H signal is input to V1, it becomes V1. Accordingly, the second transistor 2302 and the sixth transistor 2306 are turned off. Since the node 2341 at this time is in a floating state, the potential is maintained at V1. Therefore, the first transistor 2301 and the fourth transistor 23
04 remains off. In this manner, in the first non-selection period, the third wiring 2323 is in a floating state, so that the potential of the third wiring 2323 maintains V1.

In the second non-selection period illustrated in FIG. 24E, since the signal 2421 remains at the H level, the fifth transistor 2305 remains off, and since the signal 2422 remains at the H level, the seventh transistor 2307 is off. Remains. At this time, the potential of the node 2342 is V2 + | V because the L signal is input to the sixth wiring 2326 and the transistor 2304 is off.
th (2303) | Accordingly, the second transistor 2302 and the sixth transistor 2306 are turned on. At this time, the potential of the node 2341 remains V 1 because the potential (V 1) of the tenth wiring 2330 is supplied through the sixth transistor 2306. Accordingly, the first transistor 2301 and the fourth transistor 2304 remain off. In this way, in the second non-selection period, the third wiring 2323 is supplied with V1.
Since the second wiring 2324 is electrically connected to the second wiring 2324, the potential of the third wiring 2323 remains V 1. Accordingly, the H signal is output from the third wiring 2323.

From the above, the flip-flop in FIG. 23 uses the bootstrap operation in the selection period to make the potential of the node 2341 lower than V2− | Vth (2301) | Can be set to V2. Further, in the flip-flop of FIG. 23, the bootstrap operation is performed using the capacitive coupling of the parasitic capacitance between the second electrode and the gate electrode of the first transistor 2301, thereby reducing the layout area and the element. Advantages such as a reduction in the number can be obtained.

Further, since the second transistor 2302 and the sixth transistor 2306 are turned on only in the second non-selection period, the flip-flop in FIG.
A shift in threshold voltage of the second and sixth transistors 2306 can be suppressed.

Note that the flip-flop in FIG. 23 supplies V2 to the gate electrode of the third transistor 2303 and inputs the second clock signal to the first electrode, whereby the third transistor 230 is input.
The threshold voltage shift of 3 can also be suppressed.

Further, in the flip-flop in FIG. 23, the first transistor 2301, the fourth transistor 2304, the fifth transistor 2305, and the seventh transistor 2307 are not turned on in the first non-selection period and the second non-selection period. , First transistor 2301, fourth transistor 2304, fifth transistor 2305, and seventh transistor 230
7 threshold voltage shift can be suppressed.

Further, in the flip-flop in FIG. 23, even when the potential of the node 2341 and the potential of the third wiring 2323 are changed in the first non-selection period, the node 23 in the next second non-selection period.
41 and the third wiring 2323 are supplied, whereby the potential of the node 2341 and the potential of the third wiring 2323 can be reset to V1. Therefore, the flip-flop in FIG. 23 can suppress a malfunction that is caused by the potential of the node 2341 and the third wiring 2323 changing because the node 2341 and the wiring 2323 are in a floating state.

Further, since the flip-flop in FIG. 23 can suppress a threshold shift of the transistor, malfunction caused by the threshold voltage shift of the transistor can be suppressed.

Further, the flip-flop in FIG. 23 is characterized in that all of the first transistor 2301 to the seventh transistor 2307 are P-channel transistors. Therefore, the flip-flop in FIG. 23 can simplify the manufacturing process, reduce manufacturing costs, and improve yield.

If the same operation as that in FIG. 24 is performed, the arrangement and number of transistors are as shown in FIG.
It is not limited to four. Therefore, a transistor, other elements (such as a resistance element and a capacitor element), a diode, a switch, and various logic circuits may be newly placed in the flip-flop in FIG.

Note that the shift register of this embodiment can be implemented by freely combining the flip-flop of this embodiment with the shift register described in any of Embodiments 1 to 3. For example, the shift register of this embodiment includes the flip-flop of this embodiment as illustrated in FIG.
13, FIG. 14, FIG. 15, FIG. 17, FIG. 29, FIG. 33, and FIG. 34 can be implemented in any combination. However, in the shift register of this embodiment, the H level and the L level are inverted as compared with the shift register described in any of Embodiments 1 to 3.

Note that the display device of this embodiment can be implemented by freely combining the shift register of this embodiment with the display device described in any of Embodiments 1 to 3. For example, the display device of this embodiment mode can be implemented by being freely combined with the display devices of FIGS. 8, 18, 16, 20, and 22. However, in the display device of this embodiment, the H level and the L level are inverted as compared with the display devices described in Embodiments 1 to 3.

Note that although various drawings are used in this embodiment mode, the contents or part of the contents described in each figure can be applied to the contents or part of the contents described in another figure. Or they can be combined. Furthermore, in the figures described so far, for each part,
More figures can be constructed by combining different parts.

Similarly, the contents or part of the contents described in each drawing in this embodiment mode can be applied to the contents or a part of the contents described in the drawing in another embodiment mode. Or they can be combined.
Further, in the drawings of this embodiment mode, more drawings can be formed by combining each portion with a portion of another embodiment.

Note that this embodiment is an example in which the content described in the other embodiments is embodied, an example in which the content is slightly modified, an example in which a part is changed, an example in which the content is improved, and a detailed description An example of the case described, an example of application, an example of a related part, and the like are shown. Therefore, the contents described in other embodiments can be applied to this embodiment. Or they can be combined.

(Embodiment 5)
In this embodiment, a signal line driver circuit included in the display device described in any of Embodiments 1 to 4 is described.

The signal line driver circuit in FIG. 37 will be described. The signal line driver circuit shown in FIG.
C5601, switch groups 5602_1 to 5602_M, a first wiring 5611, a second wiring 5612, a third wiring 5613, and wirings 5621_1 to 5621_M. Each of the switch groups 5602_1 to 5602_M includes a first switch 5603a, a second switch 5603b, and a third switch 5603c.

The driver IC 5601 includes a first wiring 5611, a second wiring 5612, and a third wiring 5613.
And the wirings 5621_1 to 5621_M. And switch group 5602_1-
Each of 5602_M includes a first wiring 5611, a second wiring 5612, and a third wiring 561.
3 and switches 5621_1 to 5602_1 to 5602_1 to 5602_M respectively.
Connected to one of 621_M. Each of the wirings 5621_1 to 5621_M includes a first switch 5603a, a second switch 5603b, and a third switch 56.
It is connected to three signal lines via 03c. For example, the wiring 5621_J (any one of the wirings 5621_1 to 5621_M) in the J column includes a first switch 5603a, a second switch 5603b, and a third switch 5603c included in the switch group 5602_J.
To the signal line Sj-1, the signal line Sj, and the signal line Sj + 1.

Note that a signal is input to each of the first wiring 5611, the second wiring 5612, and the third wiring 5613.

Note that the driver IC 5601 is preferably formed over a single crystal substrate or a glass substrate using a polycrystalline semiconductor. Further, the switch group 5602 is preferably formed over the same substrate as the pixel portion described in Embodiments 1 to 4. Therefore,
The driver IC 5601 and the switch group 5602 are preferably connected via an FPC or the like.

Next, operation of the signal line driver circuit illustrated in FIG. 37 is described with reference to a timing chart in FIG. Note that the timing chart in FIG. 38 is a timing chart when the i-th scanning line Gi is selected. Further, the selection period of the i-th scanning line Gi is divided into a first sub-selection period T1, a second sub-selection period T2, and a third sub-selection period T3. Further, the signal line driver circuit in FIG. 37 operates in the same manner as in FIG. 38 even when a scan line in another row is selected.

Note that in the timing chart of FIG. 38, the wiring 5621_J in the J-th column is the first switch 56.
03a, the signal line Sj through the second switch 5603b and the third switch 5603c.
-1, signal line Sj, and signal line Sj + 1 are connected.

Note that the timing chart in FIG. 38 illustrates the timing at which the i-th scanning line Gi is selected, the on / off timing 5703a of the first switch 5603a, and the second switch 5603.
The ON / OFF timing 5703b of b, the ON / OFF timing 5703c of the third switch 5603c, and the signal 5721_J input to the wiring 5621_J in the J-th column are shown.

Note that different video signals are input to the wirings 5621_1 to 5621_M in the first sub-selection period T1, the second sub-selection period T2, and the third sub-selection period T3. For example, a video signal input to the wiring 5621_J in the first sub-selection period T1 is input to the signal line Sj-1, and a video signal input to the wiring 5621_J in the second sub-selection period T2 is input to the signal line Sj. In the third sub-selection period T3, the wiring 5621
The video signal input to _J is input to the signal line Sj + 1. Further, in the selection period T1, the second sub-selection period T2, and the third sub-selection period T3, video signals input to the wiring 5621_J are Dataj-1, Dataj, and Dataj + 1, respectively.

As shown in FIG. 38, in the first sub-selection period T1, the first switch 5603a is turned on, and the second switch 5603b and the third switch 5603c are turned off. At this time, Dataj-1 input to the wiring 5621_J is input to the signal line Sj-1 through the first switch 5603a. In the second sub-selection period T2, the second switch 5603b is turned on, and the first switch 5603a and the third switch 5603c are turned off. At this time,
Dataj input to the wiring 5621_J is input to the signal line Sj through the second switch 5603b. In the third sub-selection period T3, the third switch 5603c is turned on,
The first switch 5603a and the second switch 5603b are turned off. At this time, the wiring 5
Dataj + 1 input to 621_J is connected to the signal line S via the third switch 5603c.
j + 1.

From the above, the signal line driver circuit in FIG. 37 can divide one gate selection period into three to input video signals from one wiring 5621 to three signal lines during one gate selection period. it can. Therefore, in the signal line driver circuit in FIG. 37, the number of connections between the substrate on which the driver IC 5601 is formed and the substrate on which the pixel portion is formed can be reduced to about 1/3 of the number of signal lines. When the number of connections is about 約, the signal line driver circuit in FIG. 37 can improve reliability, yield, and the like.

Note that the number of connections between the substrate on which the pixel portion is formed and the external substrate can be further reduced by applying the signal line driver circuit of this embodiment to the display device described in Embodiments 1 to 4. . Therefore, the display device of this embodiment can improve reliability. Further, the display device in this embodiment can increase yield.

Next, the first switch 5603a, the second switch 5603b, and the third switch 560
A case where an N-channel transistor is applied to 3c will be described with reference to FIG.
Note that components similar to those in FIG. 37 are denoted by common reference numerals, and detailed description of the same portions or portions having similar functions is omitted.

The first transistor 5903a corresponds to the first switch 5603a, the second transistor 5903b corresponds to the second switch 5603b, and the third transistor 5903c corresponds to the third switch 5603c.

For example, in the case of the switch group 5602_J, the first transistor 5903a includes a first electrode connected to the wiring 5621_J, a second electrode connected to the signal line Sj-1, and a gate electrode connected to the first wiring 5611. Is done. In the second transistor 5903b, the first electrode is connected to the wiring 5621_J, the second electrode is connected to the signal line Sj, and the gate electrode is connected to the second wiring 5612. The third transistor 5903c has a first electrode whose wiring is 5621_
J, the second electrode is connected to the signal line Sj + 1, and the gate electrode is the third wiring 561.
3 is connected.

Note that the first transistor 5903a, the second transistor 5903b, and the third transistor 5903c each function as a switching transistor. Further, the first transistor 5903a, the second transistor 5903b, and the third transistor 5903
c is turned on when the signal input to the gate electrode is at the H level, and is turned off when the signal input to the gate electrode is at the L level.

Note that the first switch 5603a, the second switch 5603b, and the third switch 560 are provided.
By using an N-channel transistor as 3c, amorphous silicon can be used as the semiconductor layer of the transistor. Therefore, the manufacturing process can be simplified, and the manufacturing cost can be reduced and the yield can be improved. Because it can. Further, it is possible to manufacture a semiconductor device such as a large display panel. Alternatively, the manufacturing process can be simplified by using polysilicon or polycrystalline silicon as the semiconductor layer of the transistor.

In the signal line driver circuit in FIG. 39, the first transistor 5903a and the second transistor 59 are provided.
03b and the case where an N-channel transistor is used as the third transistor 5903c has been described, the first transistor 5903a, the second transistor 5903b,
A P-channel transistor may be used as the third transistor 5903c. At this time, the transistor is turned on when the signal input to the gate electrode is at L level, and is turned off when the signal input to the gate electrode is at H level.

As shown in FIG. 37, if one gate selection period is divided into a plurality of sub-selection periods and a video signal can be input to each of a plurality of signal lines from one wiring in each of the plurality of sub-selection periods, There are no restrictions on the arrangement, number, or driving method.

For example, when a video signal is input from one wiring to each of three or more signal lines in each of three or more sub-selection periods, a switch and a wiring for controlling the switch may be added. However, if one gate selection period is divided into four or more sub selection periods, one sub selection period is shortened. Therefore, it is desirable that one gate selection period is divided into two or three sub selection periods.

As another example, as shown in the timing chart of FIG. 40, one selection period is divided into a precharge period Tp, a first sub selection period T1, a second sub selection period T2, and a third selection period T3. May be. Further, in the timing chart of FIG. 40, the timing at which the i-th scanning line Gi is selected, the on / off timing 5803a of the first switch 5603a, and the second
ON / OFF timing 5803b of the third switch 5603b, ON / OFF timing 5803c of the third switch 5603c, and a signal 58 input to the wiring 5621_J of the J-th column
21_J is shown. As shown in FIG. 40, the first switch 5603a, the second switch 5603b, and the third switch 5603c are turned on in the precharge period Tp.
At this time, the precharge voltage Vp input to the wiring 5621_J is changed to the first switch 560.
3a, the second switch 5603b, and the third switch 5603c to be input to the signal line Sj-1, the signal line Sj, and the signal line Sj + 1, respectively. In the first sub-selection period T1, the first switch 5603a is turned on, and the second switch 5603b and the third switch 56
03c turns off. At this time, Dataj-1 input to the wiring 5621_J is input to the signal line Sj-1 through the first switch 5603a. In the second sub-selection period T2, the second switch 5603b is turned on, and the first switch 5603a and the third switch 5
603c turns off. At this time, Dataj input to the wiring 5621_J is input to the signal line Sj through the second switch 5603b. In the third sub-selection period T3, the third sub-selection period T3
The switch 5603c of the first switch 5603c is turned on, the first switch 5603a and the second switch 5603
b turns off. At this time, Dataj + 1 input to the wiring 5621_J is input to the signal line Sj + 1 through the third switch 5603c.

From the above, the signal line driver circuit in FIG. 37 to which the timing chart in FIG. 40 is applied can precharge the signal line by providing the precharge selection period before the sub selection period. Can be written at high speed. Note that components similar to those in FIG. 38 are denoted by common reference numerals, and detailed description of the same portions or portions having similar functions is omitted.

Also in FIG. 41, as shown in FIG. 37, one gate selection period is divided into a plurality of sub-selection periods,
A video signal can be input to each of a plurality of signal lines from one wiring in each of a plurality of sub-selection periods. Note that FIG. 41 illustrates only the switch group 6022_J in the J column in the signal line driver circuit. The switch group 6022_J includes the first transistor 60.
01, a second transistor 6002, a third transistor 6003, a fourth transistor 6004, a fifth transistor 6005, and a sixth transistor 6006. First transistor 6001, second transistor 6002, third transistor 6003
, Fourth transistor 6004, fifth transistor 6005, sixth transistor 60.
06 is an N-channel transistor. The switch group 6022_J includes the first wiring 60
11, second wiring 6012, third wiring 6013, fourth wiring 6014, and fifth wiring 60.
15, sixth wiring 6016, wiring 5621_J, signal line Sj-1, signal line Sj, signal line S
connected to j + 1.

The first electrode of the first transistor 6001 is connected to the wiring 5621_J, the second electrode is connected to the signal line Sj-1, and the gate electrode is connected to the first wiring 6011. The first electrode of the second transistor 6002 is connected to the wiring 5621_J, and the second electrode is connected to the signal line Sj.
−1 and the gate electrode is connected to the second wiring 6012. Third transistor 6
The first electrode of 003 is connected to the wiring 5621_J, the second electrode is connected to the signal line Sj, and the gate electrode is connected to the third wiring 6013. A first electrode of the fourth transistor 6004 is connected to the wiring 5621_J, a second electrode is connected to the signal line Sj, and a gate electrode is connected to the fourth wiring 6014. The first electrode of the fifth transistor 6005 is connected to the wiring 56.
21_J, the second electrode is connected to the signal line Sj + 1, and the gate electrode is connected to the fifth wiring 6015. A first electrode of the sixth transistor 6006 is connected to the wiring 5621_J, a second electrode is connected to the signal line Sj + 1, and a gate electrode is connected to the sixth wiring 6016.

Note that the first transistor 6001, the second transistor 6002, the third transistor 6003, the fourth transistor 6004, the fifth transistor 6005, and the sixth transistor 6006 each function as a switching transistor. Further, the first transistor 6001, the second transistor 6002, the third transistor 6003, the fourth transistor
The transistor 6004, the fifth transistor 6005, and the sixth transistor 6006 are turned on when the signal input to the gate electrode is at the H level, and turned off when the signal input to the gate electrode is at the L level. .

Note that the first wiring 6011 and the second wiring 6012 correspond to the first wiring 5911 in FIG. The third wiring 6013 and the fourth wiring 6014 correspond to the second wiring 5912 in FIG. The fifth wiring 6015 and the sixth wiring 6016 are the third wiring 5913 in FIG.
It corresponds to. Note that the first transistor 6001 and the second transistor 6002 correspond to the first transistor 5903a in FIG. Third transistor 6003 and fourth transistor
The transistor 6004 corresponds to the second transistor 5903b in FIG. The fifth transistor 6005 and the sixth transistor 6006 correspond to the third transistor 5903c in FIG.

41, the first transistor 600 in the first sub-selection period T1 shown in FIG.
Either the first or second transistor 6002 is turned on. In the second sub-selection period T2, either the third transistor 6003 or the fourth transistor 6004 is turned on. In the third sub-selection period T3, either the fifth transistor 6005 or the sixth transistor 6006 is turned on. Further, the first transistor 6001, the third transistor 6003, and the fifth transistor 60 are used in the precharge period Tp shown in FIG.
05, or any one of the second transistor 6002, the fourth transistor 6004, and the sixth transistor 6006 is turned on.

Accordingly, in FIG. 41, since the on-time of each transistor can be shortened, deterioration of characteristics of each transistor can be suppressed. This is because, for example, in the first sub-selection period T1 shown in FIG. 38, the first transistor 6001 or the second transistor 60
This is because a video signal can be input to the signal line Sj-1 if either one of 02 is on. Note that, for example, in the first sub-selection period T1 illustrated in FIG. 38, the first transistor 6001 and the second transistor 6002 are simultaneously turned on, so that a video signal can be input to the signal line Sj-1 at high speed. it can.

Note that FIG. 41 illustrates the case where two transistors are connected in parallel between the wiring 5621 and the signal line. However, the present invention is not limited to this, and three or more transistors are connected to the wiring 56.
You may connect in parallel between 21 and a signal line. By doing so, it is possible to further suppress the characteristic deterioration of each transistor.

Note that although various drawings are used in this embodiment mode, the contents or part of the contents described in each figure can be applied to the contents or part of the contents described in another figure. Or they can be combined. Furthermore, in the figures described so far, for each part,
More figures can be constructed by combining different parts.

Similarly, the contents or part of the contents described in each drawing in this embodiment mode can be applied to the contents or a part of the contents described in the drawing in another embodiment mode. Or they can be combined.
Further, in the drawings of this embodiment mode, more drawings can be formed by combining each portion with a portion of another embodiment.

Note that this embodiment is an example in which the content described in the other embodiments is embodied, an example in which the content is slightly modified, an example in which a part is changed, an example in which the content is improved, and a detailed description An example of the case described, an example of application, an example of a related part, and the like are shown. Therefore, the contents described in other embodiments can be applied to this embodiment. Or they can be combined.

(Embodiment 6)
In this embodiment, a structure for preventing a defect due to electrostatic breakdown of the display device described in any of Embodiments 1 to 4 will be described.

Note that electrostatic breakdown means that when a positive or negative charge accumulated in a human body or object is instantaneously discharged through the input / output terminals of the device when a semiconductor device is touched, a large current is generated inside the device. It is the destruction that occurs by flowing.

FIG. 42A shows a structure for preventing electrostatic breakdown generated in the scanning line by the protective diode. FIG. 42A illustrates a structure in which the protective diode is provided between the wiring 6111 and the scan line. Although not shown, a plurality of pixels are connected to the i-th scanning line Gi. Note that a transistor 6101 is used as the protective diode. Note that the transistor 61
01 is an N-channel transistor. Note that a p-channel transistor may be used, and the transistor 6101 may have a polarity similar to that of the transistor included in the scan line driver circuit or the pixel.

Although only one protective diode is arranged, a plurality of protective diodes may be arranged in series, may be arranged in parallel, or may be arranged in series-parallel.

The transistor 6101 has a first electrode connected to the i-th scanning line Gi, a second electrode connected to the wiring 6111, and a gate electrode connected to the i-th scanning line Gi.

The operation of FIG. 42A will be described. A certain potential is input to the wiring 6111, and the potential is lower than the L level of the signal input to the i-th scanning line Gi. When positive or negative charges are not discharged to the i-th scanning line Gi, the transistor 6101 is off because the potential of the i-th scanning line Gi is at the H level or the L level. On the other hand, when negative charges are discharged to the i-th scanning line Gi, the potential of the i-th scanning line Gi drops instantaneously. At this time, the potential of the i-th scanning line Gi is changed from the potential of the wiring 6111 to the transistor 61.
When lower than the value obtained by subtracting the threshold voltage of 01, the transistor 6101 is turned on, and a current flows to the wiring 6111 through the transistor 6101. Therefore, with the structure illustrated in FIG. 42A, a large current can be prevented from flowing into the pixel, so that electrostatic breakdown of the pixel can be prevented.

Note that FIG. 42B illustrates a structure for preventing electrostatic breakdown when positive charges are discharged to the i-th scanning line Gi. A transistor 6102 functioning as a protective diode is provided between the scan line and the wiring 6112. Although only one protective diode is arranged, a plurality of protective diodes may be arranged in series, may be arranged in parallel, or may be arranged in series-parallel. Note that the transistor 6102 is an N-channel transistor. Note that a p-channel transistor may be used, and the transistor 6102 may have a polarity similar to that of the transistor included in the scan line driver circuit or the pixel. The transistor 6102 has a first electrode connected to the i-th scanning line Gi, and a second
The electrode is connected to the wiring 6112 and the gate electrode is connected to the wiring 6112. Note that a potential higher than the H level of the signal input to the i-th scanning line Gi is input to the wiring 6112. Accordingly, the transistor 6102 is off when the electric charge is not discharged to the i-th scanning line Gi. On the other hand, when positive charges are discharged to the i-th scanning line Gi, the potential of the i-th scanning line Gi rises instantaneously. At this time, the i-th scanning line Gi
Is higher than the sum of the potential of the wiring 6112 and the threshold voltage of the transistor 6102, the transistor 6102 is turned on, and current flows through the transistor 6102.
12 flows. Therefore, the structure illustrated in FIG. 42B can prevent a large current from flowing into the pixel, so that electrostatic breakdown of the pixel can be prevented.

Note that as shown in FIG. 42C, by combining FIG. 42A and FIG. 42B, even when positive charges are discharged to the i-th scanning line Gi. Even when negative charges are discharged to the i-th scanning line Gi, electrostatic breakdown of the pixels can be prevented. Note that FIG.
2 (A) and (B) are denoted by the same reference numerals, and detailed description of the same portion or a portion having a similar function is omitted.

FIG. 43A illustrates a structure in the case where a transistor 6201 functioning as a protection diode is connected between a scan line and a storage capacitor line. Although only one protective diode is arranged, a plurality of protective diodes may be arranged in series, may be arranged in parallel, or may be arranged in series-parallel. Note that the transistor 6201 is an N-channel transistor. Note that a p-channel transistor may be used, and the transistor 6201 may have a polarity similar to that of the transistor included in the scan line driver circuit or the pixel. Note that the wiring 6211 functions as a storage capacitor line. Transistor 6201
The first electrode is connected to the i-th scanning line Gi, the second electrode is connected to the wiring 6211,
The gate electrode is connected to the i-th scanning line Gi. Note that a potential lower than an L level of a signal input to the i-th scanning line Gi is input to the wiring 6211. Accordingly, the transistor 6201 is turned off when the electric charge is not discharged to the i-th scanning line Gi. On the other hand, when negative charges are discharged to the i-th scanning line Gi, the i-th scanning line Gi.
The potential drops instantaneously. At this time, when the potential of the i-th scanning line Gi is lower than the potential of the wiring 6211 minus the threshold voltage of the transistor 6201, the transistor 62
01 is turned on and current flows to the wiring 6211 through the transistor 6201. Therefore, the structure illustrated in FIG. 43A can prevent a large current from flowing into the pixel, so that electrostatic breakdown of the pixel can be prevented. Further, in the structure illustrated in FIG. 43A, since the storage capacitor line is used as a wiring for releasing charge, it is not necessary to add a new wiring.

Note that FIG. 43B illustrates a structure for preventing electrostatic breakdown when positive charges are discharged to the i-th scanning line Gi. Here, a potential higher than the H level of the signal input to the i-th scanning line Gi is input to the wiring 6211. Thus, transistor 6201
Is turned off when the electric charge is not discharged to the i-th scanning line Gi. On the other hand, when positive charges are discharged to the i-th scanning line Gi, the potential of the i-th scanning line Gi rises instantaneously. At this time, the potential of the i-th scanning line Gi is equal to the potential of the wiring 6211 and the transistor 62.
When higher than the sum of the threshold voltage of 01, the transistor 6201 is turned on, and a current flows to the wiring 6211 through the transistor 6201. Therefore, the structure illustrated in FIG. 43B can prevent a large current from flowing into the pixel, so that electrostatic breakdown of the pixel can be prevented. Further, in the structure illustrated in FIG. 43B, since the storage capacitor line is used as a wiring for releasing charge, it is not necessary to add a new wiring. Note that FIG.
Components similar to those in B) are denoted by common reference numerals, and detailed description of the same portions or portions having similar functions is omitted.

Next, FIG. 44 shows a configuration for preventing electrostatic breakdown generated in the signal line by the protection diode.
Shown in (A). FIG. 44A illustrates a structure in the case where a protective diode is provided between the wiring 6411 and the signal line. Although not shown, a plurality of pixels are connected to the signal line Sj in the j-th column. Note that a transistor 6401 is used as the protective diode. Note that the transistor 6401 is an N-channel transistor. Note that a p-channel transistor may be used, and the transistor 6401 may have a polarity similar to that of the signal line driver circuit or the transistor included in the pixel.

Although only one protective diode is arranged, a plurality of protective diodes may be arranged in series, may be arranged in parallel, or may be arranged in series-parallel.

The transistor 6401 has a first electrode connected to the j-th signal line Sj, a second electrode connected to the wiring 6411, and a gate electrode connected to the j-th signal line Sj.

The operation of FIG. 44A will be described. A certain potential is input to the wiring 6411, and the potential is also a potential where the minimum value of the video signal input to the signal line Sj in the j-th row is low. When positive or negative charges are not discharged to the j-th signal line Sj, the potential of the j-th signal line Sj is the same as that of the video signal, so that the transistor 6401 is off. On the other hand, when negative charges are discharged to the j-th signal line Sj, the potential of the j-th signal line Sj drops instantaneously.
At this time, when the potential of the signal line Sj in the j-th row is lower than a value obtained by subtracting the threshold voltage of the transistor 6401 from the potential of the wiring 6411, the transistor 6401 is turned on and current flows through the transistor 6401. Flowing into. Therefore, the structure illustrated in FIG. 44A can prevent a large current from flowing into the pixel, so that electrostatic breakdown of the pixel can be prevented.

Note that FIG. 44B illustrates a structure for preventing electrostatic breakdown when positive charges are discharged to the signal line Sj in the j-th row. A transistor 6402 functioning as a protective diode is provided between the scan line and the wiring 6412. Although only one protective diode is arranged, a plurality of protective diodes may be arranged in series, may be arranged in parallel, or may be arranged in series-parallel. Note that the transistor 6402 is an N-channel transistor. Note that a p-channel transistor may be used, and the transistor 6402 may have a polarity similar to that of the transistor included in the scan line driver circuit or the pixel. The transistor 6402 has a first electrode connected to the signal line Sj in the j-th row,
The electrode is connected to the wiring 6412 and the gate electrode is connected to the wiring 6412. Note that a potential higher than the maximum value of the video signal input to the j-th signal line Sj is input to the wiring 6412. Accordingly, the transistor 6402 is off when the electric charge is not discharged to the signal line Sj in the j-th row. On the other hand, when positive charges are discharged to the j-th signal line Sj, the potential of the j-th signal line Sj rises instantaneously. At this time, when the potential of the signal line Sj in the j-th row becomes higher than the sum of the potential of the wiring 6412 and the threshold voltage of the transistor 6402, the transistor 6402 is turned on and current flows to the wiring 6412 through the transistor 6402. Flowing. Therefore, the structure illustrated in FIG. 44B can prevent a large current from flowing into the pixel, so that electrostatic breakdown of the pixel can be prevented.

Note that as shown in FIG. 44C, by combining FIG. 44A and FIG. 44B, even when positive charges are discharged to the signal line Sj in the j-th row. Even when negative charges are discharged to the signal line Sj in the j-th row, the electrostatic breakdown of the pixel can be prevented. Note that FIG.
4 (A) and (B) are denoted by common reference numerals, and detailed description of the same portion or a portion having a similar function is omitted.

In this embodiment mode, a configuration for preventing electrostatic breakdown of pixels connected to a scan line and a signal line has been described. However, the configuration of this embodiment is not applied only to prevention of electrostatic breakdown of pixels connected to the scanning line and the signal line. For example, in the case where this embodiment is applied to the scan line driver circuit described in Embodiments 1 to 4 and a wiring to which a signal or a potential connected to the signal line driver circuit is input, the scan line driver circuit In addition, electrostatic breakdown of the signal line driver circuit can be prevented.

Note that although various drawings are used in this embodiment mode, the contents or part of the contents described in each figure can be applied to the contents or part of the contents described in another figure. Or they can be combined. Furthermore, in the figures described so far, for each part,
More figures can be constructed by combining different parts.

Similarly, the contents or part of the contents described in each drawing in this embodiment mode can be applied to the contents or a part of the contents described in the drawing in another embodiment mode. Or they can be combined.
Further, in the drawings of this embodiment mode, more drawings can be formed by combining each portion with a portion of another embodiment.

Note that this embodiment is an example in which the content described in the other embodiments is embodied, an example in which the content is slightly modified, an example in which a part is changed, an example in which the content is improved, and a detailed description An example of the case described, an example of application, an example of a related part, and the like are shown. Therefore, the contents described in other embodiments can be applied to this embodiment. Or they can be combined.

(Embodiment 7)
In this embodiment, a new structure of a display device that can be applied to the display devices described in Embodiments 1 to 4 will be described.

FIG. 45A illustrates a structure in which a diode-connected transistor is provided between one scan line and another scan line. In FIG. 45A, a diode-connected transistor 6301a is arranged between the (i-1) th scanning line Gi-1 and the ith scanning line Gi, and the ith scanning line Gi and the (i + 1) th row are arranged. Transistor 63 which is diode-connected between the scanning line Gi + 1 of the eye
The configuration when 01b is arranged is shown. Note that the transistors 6301a and 6301b are N-channel transistors. Note that a p-channel transistor may be used, and the transistors 6301a and 6301b may have the same polarity as that of the transistor included in the scan line driver circuit or the pixel.

In FIG. 45A, the i-1th scanning line Gi-1, the ith scanning line Gi, and the i + 1th scanning line Gi + 1 are representatively shown, but other scanning lines are also shown. Similarly, diode-connected transistors are arranged.

The first electrode of the transistor 6301a is connected to the i-th scanning line Gi, and the second electrode is i
The gate electrode is connected to the (Gi-1) th scanning line Gi-1 and connected to the (-1th) th scanning line Gi-1. The first electrode of the transistor 6301b is connected to the (i + 1) th scanning line Gi + 1, the second electrode is connected to the ith scanning line Gi, and the gate electrode is connected to the ith scanning line Gi.

The operation of FIG. 45A will be described. In the scanning line driver circuit described in any of Embodiments 1 to 4, in the non-selection period, the i−1th scanning line Gi−1, the ith scanning line Gi, and the i + 1th scanning line Gi + 1. Keeps the L level. Therefore, transistor 6
301a and transistor 6301b are off. However, for example, when the potential of the i-th scanning line Gi increases due to noise or the like, the i-th scanning line Gi selects a pixel, and an invalid video signal is written to the pixel. Thus, by arranging a diode-connected transistor between scan lines as shown in FIG. 45A, an illegal video signal can be prevented from being written to a pixel. This is because when the potential of the i-th scanning line Gi rises to the sum of the potential of the (i-1) -th scanning line Gi-1 and the threshold voltage of the transistor 6301a, the transistor 6301a is turned on. The potential of the scanning line Gi of the eye is lowered. Therefore, no pixel is selected by the i-th scanning line Gi.

Note that the structure in FIG. 45A is particularly advantageous when the scan line driver circuit and the pixel portion are formed over the same substrate. This is because in a scan line driver circuit including only an N-channel transistor or a P-channel transistor, the scan line may be in a floating state, and noise is easily generated in the scan line.

Note that FIG. 45B illustrates a structure in the case where the direction of the diode-connected transistor provided between the scan lines is reversed. Note that the transistor 6302a and the transistor 6302b
Is an N-channel transistor. Note that a p-channel transistor may be used, and the transistors 6302a and 6302b may have the same polarity as that of the transistor included in the scan line driver circuit or the pixel. In FIG. 45B, the first electrode of the transistor 6302a is connected to the i-th scanning line Gi, the second electrode is connected to the (i-1) th scanning line Gi-1, and the gate electrode is i. Connected to the scanning line Gi of the row. The first electrode of the transistor 6302b is connected to the (i + 1) th scanning line Gi + 1, the second electrode is connected to the ith scanning line Gi, and the gate electrode is connected to the i + 1th scanning line Gi + 1. In FIG. 45B, as in FIG. 44A, the potential of the i-th scanning line Gi is equal to or higher than the sum of the potential of the i−1th scanning line Gi + 1 and the threshold voltage of the transistor 6302b. When it rises,
The transistor 6302b is turned on, and the potential of the i-th scanning line Gi is lowered. Therefore,
The pixel is not selected by the i-th scanning line Gi, and an illegal video signal can be prevented from being written to the pixel.

Note that as illustrated in FIG. 45C, by combining FIGS. 45A and 45B, the transistor 6301a can be used even when the potential of the i-th scanning line Gi rises. Since the transistor 6302b is turned on, the potential of the i-th scanning line Gi is lowered. Note that FIG.
In (C), since the current flows through the two transistors, larger noise can be removed. Note that components similar to those in FIGS. 45A and 45B are denoted by common reference numerals, and detailed description of the same portions or portions having similar functions is omitted.

Note that as shown in FIGS. 43A and 43B, a diode-connected transistor is arranged between the scanning line and the storage capacitor line as in FIGS. 45A, 45B, and 45C. The effect of can be obtained.

Note that although various drawings are used in this embodiment mode, the contents or part of the contents described in each figure can be applied to the contents or part of the contents described in another figure. Or they can be combined. Furthermore, in the figures described so far, for each part,
More figures can be constructed by combining different parts.

Similarly, the contents or part of the contents described in each drawing in this embodiment mode can be applied to the contents or a part of the contents described in the drawing in another embodiment mode. Or they can be combined.
Further, in the drawings of this embodiment mode, more drawings can be formed by combining each portion with a portion of another embodiment.

Note that this embodiment is an example in which the content described in the other embodiments is embodied, an example in which the content is slightly modified, an example in which a part is changed, an example in which the content is improved, and a detailed description An example of the case described, an example of application, an example of a related part, and the like are shown. Therefore, the contents described in other embodiments can be applied to this embodiment. Or they can be combined.

(Embodiment 8)
In this embodiment, a pixel structure of a display device will be described. In particular, a pixel structure of a liquid crystal display device will be described.

FIG. 46 is a cross-sectional view and a top view of a pixel in the case where a thin film transistor (TFT) is combined with a so-called TN mode of a pixel structure of a liquid crystal display device. 46A is a cross-sectional view of a pixel, and FIG. 46B is a top view of the pixel. A cross-sectional view of the pixel shown in FIG. 46A corresponds to a line segment aa ′ in the top view of the pixel shown in FIG. By applying this embodiment to the liquid crystal display device having the pixel structure shown in FIG. 46, the liquid crystal display device can be manufactured at low cost.

A pixel structure of a TN liquid crystal display device is described with reference to FIG. The liquid crystal display device has a basic part that displays an image, called a liquid crystal panel. LCD panel
Two processed substrates are bonded together with a gap of several micrometers, and a liquid crystal material is injected between the two substrates. In FIG. 46A, the two substrates are a first substrate 10101 and a second substrate 10116. TFT on the first substrate
And a pixel electrode, and a second substrate includes a light-shielding film 10114 and a color filter 1011.
5, the fourth conductive layer 10113, the spacer 10117, and the second alignment film 10112 may be manufactured.

Note that this can be achieved without manufacturing TFTs on the first substrate 10101. In the case where this embodiment is performed without manufacturing a TFT, the number of steps is reduced, so that manufacturing cost can be reduced. Furthermore, since the structure is simple, the yield can be improved. on the other hand,
When a TFT is manufactured and this embodiment mode is implemented, a larger display device can be obtained.

Note that the TFT illustrated in FIG. 46 is a bottom-gate TFT using an amorphous semiconductor. A liquid crystal panel to which a TFT using an amorphous semiconductor is applied has an advantage that it can be manufactured at low cost using a large-area substrate. However, the present embodiment is not limited to this. The TFT structure that can be used includes a channel etch type, a channel protection type, and the like in a bottom gate type TFT. A top gate type may also be used. Furthermore, not only an amorphous semiconductor but also a polycrystalline semiconductor can be used.

Note that this embodiment mode can be implemented without forming the light-blocking film 10114 on the second substrate 10116. In the case where this embodiment mode is implemented without forming the light-blocking film 10114, the number of steps is reduced, so that manufacturing cost can be reduced. In addition, since the structure is simple, the yield can be improved. On the other hand, in the case where the light-blocking film 10114 is formed and this embodiment is performed, a display device with little light leakage at the time of black display can be obtained.

Note that this embodiment mode can be implemented without forming the color filter 10115 over the second substrate 10116. In the case where this embodiment is performed without manufacturing the color filter 10115, the number of steps is reduced, so that the manufacturing cost can be reduced. In addition, since the structure is simple, the yield can be improved. However, even when this embodiment is performed without manufacturing the color filter 10115, a display device capable of color display by field sequential driving can be obtained. On the other hand, when the color filter 10115 is manufactured and this embodiment is performed, a display device capable of color display can be obtained.

Note that this embodiment mode can also be implemented by spraying spherical spacers without forming the spacers 10117 on the second substrate 10116. In the case of carrying out the present embodiment by spraying spherical spacers, the number of steps is reduced, so that the manufacturing cost can be reduced. In addition, since the structure is simple, the yield can be improved. Meanwhile, the spacer 101
17 is manufactured and this embodiment is carried out, the position of the spacer does not vary.
The distance between the substrates can be made uniform, and a display device with little display unevenness can be obtained.

Next, processing performed on the first substrate 10101 will be described. The first substrate 10101 is preferably a light-transmitting substrate, and may be a quartz substrate, a glass substrate, or a plastic substrate, for example. Note that the first substrate 10101 may be a light-blocking substrate, and may be a semiconductor substrate or SOI (S
An silicon on Insulator board may be used.

First, the first insulating film 10102 may be formed over the first substrate 10101. The first insulating film 10102 is formed using a silicon oxide film, a silicon nitride film, or a silicon oxynitride film (SiOxN
An insulating film such as y) may be used. Alternatively, the first insulating film 10102 may be an insulating film having a stacked structure in which two or more films of a silicon oxide film, a silicon nitride film, a silicon oxynitride film (SiOxNy), and the like are combined. In the case where this embodiment is performed with the first insulating film 10102 formed, impurities from the substrate can be prevented from affecting the semiconductor layer and the properties of the TFT from being changed. Moreover, since the change of the property of TFT can be suppressed,
A display device with high reliability can be obtained. Note that in the case where this embodiment is performed without forming the first insulating film 10102, the number of steps is reduced, so that manufacturing cost can be reduced. In addition, since the structure is simple, the yield can be improved.

Next, the first conductive layer 1010 is formed over the first substrate 10101 or the first insulating film 10102.
3 is formed. Note that the first conductive layer 10103 may be formed by processing a shape. The step of processing the shape is preferably as follows. First, the first conductive layer 101
03 is formed on the entire surface. At this time, the first conductive layer 10103 is formed using a sputtering apparatus or C
The film may be formed using a film forming apparatus such as a VD apparatus. Next, a photosensitive resist material is formed over the entire surface over the first conductive layer formed over the entire surface. Next, the resist material is exposed according to the shape to be formed by a photolithography method, a laser direct drawing method, or the like. Next, either one of the resist material that has been exposed or the resist material that has not been exposed is removed by etching, whereby a mask for processing the shape of the first conductive layer 10103 can be obtained. After that, according to the formed mask pattern, the first conductive layer 10103
Is removed by etching, the first conductive layer 10103 can be processed into a desired pattern. Note that there are a chemical method (wet etching) and a physical method (dry etching) as a method for etching the first conductive layer 10103. The material of the first conductive layer 10103, the first conductive layer 10103, The material is selected as appropriate in consideration of the properties of the material under the conductive layer 10103 and the like. Note that materials used for the first conductive layer 10103 are Mo, Ti, and Al.
Nd, Cr and the like are preferable. Or the laminated structure which combined 2 or more of Mo, Ti, Al, Nd, Cr etc. may be sufficient.

Next, a second insulating film 10104 is formed. At this time, the second insulating film 10104 may be formed using a film formation apparatus such as a sputtering apparatus or a CVD apparatus. Note that a material used for the second insulating film 10104 is preferably a thermal oxide film, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or the like. Alternatively, a stacked structure in which two or more of a thermal oxide film, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and the like are combined may be used.
Note that the second insulating film 10104 in contact with the first semiconductor layer 10105 is particularly preferably a silicon oxide film. This is because when a silicon oxide film is used, the semiconductor layer 10
This is because the trap level at the interface with 105 is reduced. The first conductive layer 10
When 103 is formed of Mo, a portion of the second insulating film 1 in contact with the first conductive layer 10103 is formed.
0104 is preferably a silicon nitride film. This is because the silicon nitride film does not oxidize Mo.

Next, a first semiconductor layer 10105 is formed. After that, the second semiconductor layer 10106 is preferably formed continuously. Note that the first semiconductor layer 10105 and the second semiconductor layer 1
0106 may be formed by processing the shape. The step of processing the shape is preferably a method such as the photolithography method described above. Note that a material used for the first semiconductor layer 10105 is preferably silicon, silicon germanium (SiGe), or the like. The material used for the second semiconductor layer 10106 is preferably silicon containing phosphorus or the like.

Next, a second conductive layer 10107 is formed. At this time, as a formation method of the second conductive layer 10107, it is preferable to use a sputtering method or a printing method. The second conductive layer 10
The material used for 107 may be transparent or reflective. In the case of having transparency, for example, indium tin oxide in which tin oxide is mixed with indium oxide (IT
O) film, indium tin oxide (ITSO) film in which silicon oxide is mixed with indium tin oxide (ITO), indium zinc oxide (IZO) film in which zinc oxide is mixed in zinc oxide, zinc oxide film or tin oxide A membrane can be used. In addition, IZO is 2 to ITO.
It is a transparent conductive material formed by sputtering using a target mixed with 20 wt% zinc oxide (ZnO). On the other hand, when it has reflectivity, Ti, Mo, Ta, Cr
, W, Al, or the like can be used. Alternatively, a two-layer structure in which Ti, Mo, Ta, Cr, W and Al are stacked, or a three-layer structure in which Al is sandwiched between metals such as Ti, Mo, Ta, Cr, and W may be used. Note that the second conductive layer 10107 may be formed by processing a shape. The method of processing the shape is preferably a method such as the photolithography method described above. Note that the etching method is preferably dry etching. Dry etching is performed by ECR (Electron Cyclotron Resonance) or ICP (In
It may be carried out by a dry etching apparatus using a high-density plasma source such as a ductile coupled plasma).

Next, a channel region of the TFT is formed. At this time, as a mask for etching the second semiconductor layer 10106, the second conductive layer 10107 may be used, or a mask (resist) for etching the second conductive layer 10107 may be used. Good. By doing so, the number of masks can be reduced, so that the manufacturing cost can be reduced. By etching the second semiconductor layer 10106 having conductivity, the removed portion becomes a TFT.
Channel region. Note that without forming the first semiconductor layer 10105 and the second semiconductor layer 10106 in succession, after the formation of the first semiconductor layer 10105, a film serving as a stopper is formed in a portion to be a channel region of the TFT. After patterning, the second semiconductor layer 10
106 may be formed. Note that the first semiconductor layer 10105 and the second semiconductor layer 10106 are used.
Are etched using the same mask when the shape of the second conductive layer 10107 is processed by the above-described photolithography method or the like. In this way, the second conductive layer 1010
Since the TFT channel region can be formed without using 7 as a mask, there is an advantage that the degree of freedom of the layout pattern is increased. In addition, since the first semiconductor layer 10105 is not etched when the second semiconductor layer 10106 is etched, there is an advantage that the channel region of the TFT can be surely formed without causing etching failure.

Next, a third insulating film 10108 is formed. It is preferable that the third insulating film has transparency. Note that a material used for the third insulating film 10108 is an inorganic material (silicon oxide,
Silicon nitride, silicon oxynitride, or the like) or an organic compound material having a low dielectric constant (photosensitive or non-photosensitive organic resin material) is preferable. Further, a material containing siloxane may be used. Siloxane is a material in which a skeleton structure is formed by a bond of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (for example, an alkyl group or an aromatic hydrocarbon) is used. Alternatively, a fluoro group may be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as a substituent. Note that a contact hole is selectively formed in the third insulating film 10108 by etching. The contact hole is formed at least over the second conductive layer 10107. In addition,
By etching the second insulating film 10104 at the same time as etching the third insulating film 10108, a contact hole can be formed not only with the second conductive layer 10107 but also with the first conductive layer 10103. Note that the surface of the third insulating film 10108 is preferably as flat as possible. This is because the alignment of liquid crystal molecules is affected by the unevenness of the surface in contact with the liquid crystal.

Next, a third conductive layer 10109 is formed. At this time, as a formation method of the third conductive layer 10109, a sputtering method or a printing method is preferably used. The third conductive layer 10
The material used for 109 may have transparency or reflectivity as in the second conductive layer 10107. Note that a material that can be used for the third conductive layer 10109 is a second material.
The conductive layer 10107 may be the same. Further, the third conductive layer 10109 may be formed by processing a shape. A method for processing the shape may be the same as that of the second conductive layer 10107.

Next, a first alignment film 10110 is formed. As the alignment film 10110, a polymer film such as polyimide can be used. Note that after the first alignment film 10110 is formed, rubbing may be performed in order to control alignment of liquid crystal molecules. The rubbing is a process of streaking the alignment film by rubbing the alignment film with a cloth. By performing rubbing, the alignment film can be provided with orientation.

The first substrate 10101 manufactured as described above, the light-shielding film 10114, and the color filter 10
115, the fourth conductive layer 10113, the spacer 10117, and the second substrate 10116 on which the second alignment film 10112 is manufactured are bonded to each other with a gap of several μm by a sealant. A liquid crystal panel can be manufactured by injecting a liquid crystal material between two substrates. Note that in the TN liquid crystal panel as shown in FIG. 46, the fourth conductive layer 101 is used.
13 may be formed on the entire surface of the second substrate 10116.

Next, features of the pixel structure of the TN liquid crystal panel shown in FIG. 46 will be described. Figure 46
The liquid crystal molecules 10118 shown in (A) are elongated molecules having a major axis and a minor axis. In order to show the direction of the liquid crystal molecules 10118, the length is expressed in FIG. That is, the longer expressed liquid crystal molecules 10118 are parallel to the paper surface, and the shorter expressed liquid crystal molecules 10118 are closer to the normal direction of the paper surface. . That is, the liquid crystal molecules 10118 shown in FIG. 46A have a major axis orientation of 9 for those close to the first substrate 10101 and those close to the second substrate 10116.
The direction of the major axis of the liquid crystal molecules 10118 located in the middle is 0 degrees, and the orientation is such that they are smoothly connected. That is, the liquid crystal molecules 101 shown in FIG.
18 is in an orientation state in which it is twisted 90 degrees between the first substrate 10101 and the second substrate 10116.

Next, an example of a pixel layout in the case where this embodiment is applied to a TN liquid crystal display device will be described with reference to FIG. A pixel of a TN liquid crystal display device to which this embodiment mode is applied includes a scan line 10121, a video signal line 10122, and a capacitor line 10123.
And a TFT 10124, a pixel electrode 10125, and a pixel capacitor 10126.

The scan line 10121 is preferably formed using the first conductive layer 10103 because it is electrically connected to the gate electrode of the TFT 10124.

The video signal line 10122 is preferably formed of the second conductive layer 10107 because it is electrically connected to the source electrode or the drain electrode of the TFT 10124. Since the scanning lines 10121 and the video signal lines 10122 are arranged in a matrix, at least
It is preferable that the conductive layers are formed of different layers.

The capacitor line 10123 is arranged in parallel with the pixel electrode 10125 so that the pixel capacitor 1012
6 is preferably formed of the first conductive layer 10103. Note that as illustrated in FIG. 46B, the capacitor line 10123 may extend along the video signal line 10122 so as to surround the video signal line 10122. By doing so, it is possible to reduce a phenomenon in which the potential of the electrode that should hold the potential changes, so-called crosstalk, in accordance with the potential change of the video signal line 10122. Note that in order to reduce cross capacitance with the video signal line 10122, as shown in FIG. 46B, the first semiconductor layer 10105 is used.
May be provided in an intersection region between the capacitor line 10123 and the video signal line 10122.

The TFT 10124 operates as a switch for electrically connecting the video signal line 10122 and the pixel electrode 10125. Note that as illustrated in FIG. 46B, either the source region or the drain region of the TFT 10124 may be disposed so as to surround the other of the source region or the drain region. By doing so, a large channel width can be obtained with a small area, and the switching capability can be increased. As shown in FIG. 46B, the TFT
The gate electrode 10124 may be disposed so as to surround the first semiconductor layer 10105.

The pixel electrode 10125 is electrically connected to one of the source electrode and the drain electrode of the TFT 10124. The pixel electrode 10125 is an electrode for applying a signal voltage transmitted through the video signal line 10122 to the liquid crystal element. In addition, by arranging the capacitor line 10123,
A pixel capacitor 10126 may be formed. Thus, the pixel electrode 10125 can easily hold the signal voltage transmitted through the video signal line 10122. The pixel electrode 101
25 may be a rectangle as shown in FIG. By doing so, the aperture ratio of the pixel can be increased, so that the efficiency of the liquid crystal display device is improved. Also, the pixel electrode 1
When 0125 is manufactured using a material having transparency, a transmissive liquid crystal display device can be obtained. A transmissive liquid crystal display device has high color reproducibility and can display an image with high image quality. In the case where the pixel electrode 10125 is formed using a reflective material, a reflective liquid crystal display device can be obtained. The reflective liquid crystal display device has high visibility in a bright environment such as outdoors and does not require a backlight, so that power consumption can be extremely reduced. Note that in the case where the pixel electrode 10125 is formed using both a transparent material and a reflective material, a transflective liquid crystal display device having both advantages can be obtained. Note that in the case where the pixel electrode 10125 is formed using a reflective material, the surface of the pixel electrode 10125 may be uneven. Alternatively, the surface of the third insulating film 10108 can be uneven so that the pixel electrode 10125 can be uneven. By doing so, since the reflected light is irregularly reflected, there is an advantage that the angle dependence of the intensity distribution of the reflected light is reduced. That is, it is possible to obtain a reflective liquid crystal display device having a certain brightness at any angle.

Next, with reference to FIG. 47, a case where the present embodiment is applied to a VA (Vertical Alignment) mode liquid crystal display device will be described. FIG. 47 shows a so-called MVA (Multi-domain) in which liquid crystal molecules are controlled to have various orientations by using alignment control protrusions in the pixel structure of the VA mode liquid crystal display device, and the viewing angle is increased. Ver
6A and 6B are a cross-sectional view and a top view of a pixel in the case where the present embodiment is applied to a (tial alignment) method. 47A is a cross-sectional view of a pixel, and FIG. 47B is a top view of the pixel. A cross-sectional view of the pixel shown in FIG. 47A corresponds to a line segment aa ′ in the top view of the pixel shown in FIG. By applying this embodiment to the liquid crystal display device having the pixel structure shown in FIG. 47, a liquid crystal display device with a wide viewing angle, a high response speed, and a high contrast can be obtained.

The pixel structure of the MVA liquid crystal display device is described with reference to FIG. The liquid crystal display device has a basic part that displays an image, called a liquid crystal panel. A liquid crystal panel is made by bonding two processed substrates together with a gap of several micrometers.
It is manufactured by injecting a liquid crystal material between a plurality of substrates. In FIG. 47A, the two substrates are a first substrate 10201 and a second substrate 10216. The first substrate has TF
T and a pixel electrode are manufactured, and a light-shielding film 10214, a color filter 102 are formed on the second substrate.
15, a fourth conductive layer 10213, a spacer 10217, a second alignment film 10212, and an alignment control protrusion 10219 may be formed.

Note that this embodiment mode can be implemented without manufacturing a TFT on the first substrate 10201. In the case where this embodiment is performed without manufacturing a TFT, the number of steps is reduced, so that manufacturing cost can be reduced. Furthermore, since the structure is simple, the yield can be improved. On the other hand, when a TFT is manufactured and this embodiment is performed, a larger display device can be obtained.

Note that the TFT illustrated in FIG. 47 is a bottom-gate TFT using an amorphous semiconductor. A liquid crystal panel to which a TFT using an amorphous semiconductor is applied has an advantage that it can be manufactured at low cost using a large-area substrate. However, the present embodiment is not limited to this. The TFT structure that can be used includes a channel etch type, a channel protection type, and the like in a bottom gate type TFT. A top gate type may also be used. Furthermore, not only an amorphous semiconductor but also a polycrystalline semiconductor can be used.

Note that this embodiment mode can be implemented without forming the light-blocking film 10214 over the second substrate 10216. When this embodiment mode is implemented without forming the light-blocking film 10214, the number of steps is reduced, so that manufacturing cost can be reduced. In addition, since the structure is simple, the yield can be improved. On the other hand, in the case where the light-blocking film 10214 is formed and this embodiment is performed, a display device with little light leakage during black display can be obtained.

Note that this embodiment mode can be implemented without forming the color filter 10215 over the second substrate 10216. In the case where this embodiment is performed without manufacturing the color filter 10215, the number of steps is reduced, so that the manufacturing cost can be reduced. In addition, since the structure is simple, the yield can be improved. Note that a display device capable of color display by field sequential driving can be obtained even when this embodiment is performed without manufacturing the color filter 10215. On the other hand, in the case where the color filter 10215 is manufactured and this embodiment is performed, a display device capable of color display can be obtained.

Note that this embodiment mode can also be implemented by spraying spherical spacers without forming the spacers 10217 on the second substrate 10216. In the case of carrying out the present embodiment by spraying spherical spacers, the number of steps is reduced, so that the manufacturing cost can be reduced. In addition, since the structure is simple, the yield can be improved. Meanwhile, the spacer 102
17 is manufactured and this embodiment is carried out, the position of the spacer does not vary.
The distance between the substrates can be made uniform, and a display device with little display unevenness can be obtained.

Next, processing performed on the first substrate 10201 may be omitted because the method described in FIG. 46 may be used. Here, the first substrate 10201, the first insulating film 10202, the first conductive layer 10203, the second insulating film 10204, the first semiconductor layer 10205, the second semiconductor layer 10206, and the second conductive layer 10207 are used. , Third insulating film 10208, third conductive layer 1020
9 and the first alignment film 10210 are the first substrate 10101 and the first alignment film in FIG.
Insulating film 10102, first conductive layer 10103, second insulating film 10104, first semiconductor layer 10105, second semiconductor layer 10106, second conductive layer 10107, third insulating film 10
108, the third conductive layer 10109, and the first alignment film 10110. Although not shown, an alignment control protrusion may be provided also on the first substrate side. By doing so, the orientation of the liquid crystal molecules can be controlled more reliably. In addition, the first alignment film 10210 and the second alignment film
The alignment film 10212 may be a vertical alignment film. By doing so, the liquid crystal molecules 10218 can be vertically aligned.

The first substrate 10201 manufactured as described above, the light shielding film 10214, and the color filter 10
215, a fourth conductive layer 10213, a spacer 10217, and a second alignment film 10212
A liquid crystal panel can be manufactured by bonding the second substrate 10216 manufactured by attaching a gap of several micrometers with a sealing material and injecting a liquid crystal material between the two substrates. Note that in the MVA mode liquid crystal panel as shown in FIG. 47, the fourth conductive layer 102 is used.
13 may be formed on the entire surface of the second substrate 10216. The fourth conductive layer 10
An alignment control protrusion 10219 may be formed in contact with 213. In addition, the alignment control protrusion 1
The shape of 0219 is not limited, but a shape having a smooth curved surface is preferable. By doing so, the alignment of the adjacent liquid crystal molecules 10218 becomes very close, and alignment defects are reduced. In addition, defects in the alignment film due to the second alignment film 10212 being stepped by the alignment control protrusion 10219 can be reduced.

Next, features of the pixel structure of the MVA liquid crystal panel illustrated in FIG. 47 will be described. FIG.
A liquid crystal molecule 10218 shown in (A) of FIG. 7 is an elongated molecule having a major axis and a minor axis. In order to show the direction of the liquid crystal molecules 10218, the length is expressed in FIG. That is, the longer expressed liquid crystal molecules 10218 are parallel to the paper surface, and the shorter expressed liquid crystal molecules 10218 are closer to the normal direction of the paper surface. . That is, the liquid crystal molecules 10218 shown in FIG. 47A are aligned so that the direction of the major axis is in the normal direction of the alignment film. Therefore, the alignment control projection 1021
The liquid crystal molecules 10218 in the portion with 9 are aligned radially around the alignment control protrusion 10219. In this state, a liquid crystal display device with a large viewing angle can be obtained.

Next, an example of a pixel layout in the case where this embodiment is applied to an MVA liquid crystal display device will be described with reference to FIG. A pixel of an MVA liquid crystal display device to which this embodiment is applied includes a scan line 10221, a video signal line 10222, and a capacitor line 102.
23, a TFT 10224, a pixel electrode 10225, a pixel capacitor 10226, and an alignment control projection 10219 may be provided.

The scan line 10221 is preferably formed using the first conductive layer 10203 because it is electrically connected to the gate electrode of the TFT 10224.

The video signal line 10222 is preferably formed using the second conductive layer 10207 because it is electrically connected to the source electrode or the drain electrode of the TFT 10224. Further, since the scanning lines 10221 and the video signal lines 10222 are arranged in a matrix, at least
It is preferable that the conductive layers are formed of different layers.

The capacitor line 10223 is arranged in parallel with the pixel electrode 10225 so that the pixel capacitor 1022
6 is preferably formed of the first conductive layer 10203. Note that as illustrated in FIG. 47B, the capacitor line 10223 may extend along the video signal line 10222 so as to surround the video signal line 10222. By doing so, it is possible to reduce a phenomenon in which the potential of the electrode that should hold the potential changes, that is, so-called crosstalk, with the change in the potential of the video signal line 10222. Note that in order to reduce cross capacitance with the video signal line 10222, as shown in FIG. 47B, the first semiconductor layer 10205 is used.
May be provided in an intersection region between the capacitor line 10223 and the video signal line 10222.

The TFT 10224 operates as a switch for electrically connecting the video signal line 10222 and the pixel electrode 10225. Note that as shown in FIG. 47B, either the source region or the drain region of the TFT 10224 may be arranged so as to surround the other of the source region or the drain region. By doing so, a large channel width can be obtained with a small area, and the switching capability can be increased. As shown in FIG. 47B, the TFT
The gate electrode 10224 may be disposed so as to surround the first semiconductor layer 10205.

The pixel electrode 10225 is electrically connected to one of a source electrode and a drain electrode of the TFT 10224. The pixel electrode 10225 is an electrode for applying a signal voltage transmitted through the video signal line 10222 to the liquid crystal element. In addition, by arranging the capacitor line 10223,
A pixel capacitor 10226 may be formed. Thus, the pixel electrode 10225 can easily hold the signal voltage transmitted through the video signal line 10222. The pixel electrode 102
25 may be a rectangle as shown in FIG. By doing so, the aperture ratio of the pixel can be increased, so that the efficiency of the liquid crystal display device is improved. Also, the pixel electrode 1
When 0225 is formed using a material having transparency, a transmissive liquid crystal display device can be obtained. A transmissive liquid crystal display device has high color reproducibility and can display an image with high image quality. In the case where the pixel electrode 10225 is formed using a reflective material, a reflective liquid crystal display device can be obtained. The reflective liquid crystal display device has high visibility in a bright environment such as outdoors and does not require a backlight, so that power consumption can be extremely reduced. Note that in the case where the pixel electrode 10225 is formed using both a transparent material and a reflective material, a transflective liquid crystal display device having both advantages can be obtained. Note that in the case where the pixel electrode 10225 is formed using a reflective material, the surface of the pixel electrode 10225 may have unevenness. Alternatively, when the surface of the third insulating film 10208 is uneven, the pixel electrode 10225 can be uneven. By doing so, since the reflected light is irregularly reflected, there is an advantage that the angle dependence of the intensity distribution of the reflected light is reduced. That is, it is possible to obtain a reflective liquid crystal display device having a certain brightness at any angle.

Next, another example in the case where the present embodiment is applied to a VA (Vertical Alignment) mode liquid crystal display device will be described with reference to FIG. FIG. 48 illustrates a so-called pixel structure of a VA mode liquid crystal display device in which the fourth conductive layer 10313 is patterned so that liquid crystal molecules are controlled in various directions to increase the viewing angle. PVA (P
FIG. 6 is a cross-sectional view and a top view of a pixel when this embodiment is applied to an attenuated vertical alignment) method. 48A is a cross-sectional view of a pixel, and FIG. 48B is a top view of the pixel. Further, the cross-sectional view of the pixel shown in FIG. 48A corresponds to a line segment aa ′ in the top view of the pixel shown in FIG. By applying this embodiment to the liquid crystal display device having the pixel structure shown in FIG. 48, a liquid crystal display device with a large viewing angle, a high response speed, and a high contrast can be obtained.

A pixel structure of a PVA liquid crystal display device will be described with reference to FIG. The liquid crystal display device has a basic part that displays an image, called a liquid crystal panel. A liquid crystal panel is made by bonding two processed substrates together with a gap of several micrometers.
It is manufactured by injecting a liquid crystal material between a plurality of substrates. In FIG. 48A, the two substrates are a first substrate 10301 and a second substrate 10316. The first substrate has T
An FT and a pixel electrode are manufactured, and a light shielding film 10314, a color filter 10315, a fourth conductive layer 10313, a spacer 10317, and a second alignment film 10 are formed on the second substrate.
312 may be manufactured.

Note that this embodiment mode can be implemented without manufacturing a TFT over the first substrate 10301. In the case where this embodiment is performed without manufacturing a TFT, the number of steps is reduced, so that manufacturing cost can be reduced. Furthermore, since the structure is simple, the yield can be improved. On the other hand, when a TFT is manufactured and this embodiment is performed, a larger display device can be obtained.

Note that the TFT illustrated in FIG. 48 is a bottom-gate TFT using an amorphous semiconductor. A liquid crystal panel to which a TFT using an amorphous semiconductor is applied has an advantage that it can be manufactured at low cost using a large-area substrate. However, the present embodiment is not limited to this. The TFT structure that can be used includes a channel etch type, a channel protection type, and the like in a bottom gate type TFT. A top gate type may also be used. Furthermore, not only an amorphous semiconductor but also a polycrystalline semiconductor can be used.

Note that this embodiment mode can be implemented without forming the light-blocking film 10314 over the second substrate 10316. When this embodiment mode is implemented without forming the light-blocking film 10314, the number of steps is reduced, so that manufacturing cost can be reduced. In addition, since the structure is simple, the yield can be improved. On the other hand, in the case where the light-blocking film 10314 is formed and this embodiment is performed, a display device with little light leakage at the time of black display can be obtained.

Note that this embodiment mode can be implemented without forming the color filter 10315 over the second substrate 10316. In the case where this embodiment is performed without manufacturing the color filter 10315, the number of steps is reduced, so that manufacturing cost can be reduced. In addition, since the structure is simple, the yield can be improved. However, even when this embodiment mode is implemented without manufacturing the color filter 10315, a display device capable of color display by field sequential driving can be obtained. On the other hand, in the case where the color filter 10315 is manufactured and this embodiment is performed, a display device capable of color display can be obtained.

Note that this embodiment mode can also be implemented by spraying spherical spacers without forming the spacers 10317 on the second substrate 10316. In the case of carrying out the present embodiment by spraying spherical spacers, the number of steps is reduced, so that the manufacturing cost can be reduced. In addition, since the structure is simple, the yield can be improved. Meanwhile, the spacer 103
17 is manufactured and this embodiment is carried out, the position of the spacer does not vary.
The distance between the substrates can be made uniform, and a display device with little display unevenness can be obtained.

Next, processing performed on the first substrate 10301 may be omitted because the method described in FIG. 46 may be used. Here, the first substrate 10301, the first insulating film 10302, the first conductive layer 10303, the second insulating film 10304, the first semiconductor layer 10305, the second semiconductor layer 10306, and the second conductive layer 10307 , Third insulating film 10308, third conductive layer 1030
9 and the first alignment film 10310 are the first substrate 10101 and the first alignment film in FIG.
Insulating film 10102, first conductive layer 10103, second insulating film 10104, first semiconductor layer 10105, second semiconductor layer 10106, second conductive layer 10107, third insulating film 10
108, the third conductive layer 10109, and the first alignment film 10110. Note that an electrode notch portion may be provided in the third conductive layer 10309 on the first substrate 10301 side. By doing so, the orientation of the liquid crystal molecules can be controlled more reliably. Also, the first alignment film 10
310 and the second alignment film 10312 may be vertical alignment films. By doing so, the liquid crystal molecules 10318 can be vertically aligned.

The first substrate 10301 manufactured as described above, the light shielding film 10314, and the color filter 10
315, a fourth conductive layer 10313, a spacer 10317, and a second alignment film 10312
A liquid crystal panel can be manufactured by bonding the second substrate 10316 manufactured by attaching a gap of several μm with a sealing material and injecting a liquid crystal material between the two substrates. Note that in the PVA liquid crystal panel as illustrated in FIG. 48, the fourth conductive layer 10313 may be subjected to patterning to form the electrode notch portion 10319. Note that the shape of the electrode notch 10319 is not limited, but a shape in which a plurality of rectangles having different directions are combined is preferable. By doing so, a plurality of regions having different orientations can be formed, so that a liquid crystal display device with a large viewing angle can be obtained. In addition, the shape of the fourth conductive layer 10313 at the boundary between the electrode notch 10319 and the fourth conductive layer 10313 is preferably a smooth curve. By doing so, the alignment of the liquid crystal molecules 10318 that are close to each other becomes extremely close, so that alignment defects are reduced. In addition, the second alignment film 10312 includes the electrode notch 10.
Defects in the alignment film due to the disconnection caused by 319 can also be reduced.

Next, characteristics of the pixel structure of the PVA liquid crystal panel shown in FIG. 48 will be described. FIG.
A liquid crystal molecule 10318 shown in FIG. 8A is an elongated molecule having a major axis and a minor axis. In order to show the direction of the liquid crystal molecules 10318, the length is expressed in FIG. That is, the longer expressed liquid crystal molecules 10318 are parallel to the paper surface, and the shorter expressed liquid crystal molecules 10318 are closer to the normal direction of the paper surface. . That is, the liquid crystal molecules 10318 shown in FIG. 48A are aligned so that the direction of the long axis is in the normal direction of the alignment film. Therefore, the electrode notch 1031
The liquid crystal molecules 10318 in the portion with 9 are formed by the electrode notch 10319 and the fourth conductive layer 103.
It is oriented radially around 13 boundaries. In this state, a liquid crystal display device with a large viewing angle can be obtained.

Next, an example of a pixel layout in the case where this embodiment is applied to a PVA liquid crystal display device will be described with reference to FIG. A pixel of a PVA liquid crystal display device to which this embodiment mode is applied includes a scan line 10321, a video signal line 10322, and a capacitor line 103.
23, a TFT 10324, a pixel electrode 10325, a pixel capacitor 10326, and an electrode notch 10319 may be provided.

Since the scan line 10321 is electrically connected to the gate electrode of the TFT 10324, the scan line 10321 is preferably formed using the first conductive layer 10303.

Since the video signal line 10322 is electrically connected to the source electrode or the drain electrode of the TFT 10324, the video signal line 10322 is preferably formed using the second conductive layer 10307. Further, since the scanning lines 10321 and the video signal lines 10322 are arranged in a matrix, at least
It is preferable that the conductive layers are formed of different layers.

The capacitor line 10323 is arranged in parallel with the pixel electrode 10325 so that the pixel capacitor 1032 is formed.
6 is preferably formed of the first conductive layer 10303. Note that as illustrated in FIG. 48B, the capacitor line 10323 may be extended along the video signal line 10322 so as to surround the video signal line 10322. By doing so, it is possible to reduce a phenomenon in which the potential of the electrode that should hold the potential changes, so-called crosstalk, in accordance with the potential change of the video signal line 10322. Note that in order to reduce cross capacitance with the video signal line 10322, as shown in FIG. 48B, the first semiconductor layer 10305 is used.
May be provided in an intersection region between the capacitor line 10323 and the video signal line 10322.

The TFT 10324 operates as a switch for electrically connecting the video signal line 10322 and the pixel electrode 10325. Note that as shown in FIG. 48B, either the source region or the drain region of the TFT 10324 may be disposed so as to surround the other of the source region or the drain region. By doing so, a large channel width can be obtained with a small area, and the switching capability can be increased. As shown in FIG. 48B, the TFT
The gate electrode 10324 may be disposed so as to surround the first semiconductor layer 10305.

The pixel electrode 10325 is electrically connected to one of the source electrode and the drain electrode of the TFT 10324. The pixel electrode 10325 is an electrode for applying a signal voltage transmitted through the video signal line 10322 to the liquid crystal element. In addition, by arranging the capacitor line 10323,
A pixel capacitor 10326 may be formed. Thus, the pixel electrode 10325 can easily hold the signal voltage transmitted through the video signal line 10322. The pixel electrode 103
48B, as shown in FIG. 48B, in accordance with the shape of the electrode notch 10319 provided in the fourth conductive layer 10313, the pixel electrode 103
It is preferable to form a portion where 25 is cut out. In this way, liquid crystal molecules 10318 are obtained.
Since a plurality of regions having different orientations can be formed, a liquid crystal display device having a large viewing angle can be obtained. In the case where the pixel electrode 10325 is made of a material having transparency,
A transmissive liquid crystal display device can be obtained. A transmissive liquid crystal display device has high color reproducibility and can display an image with high image quality. In the case where the pixel electrode 10325 is formed using a reflective material, a reflective liquid crystal display device can be obtained. The reflective liquid crystal display device has high visibility in a bright environment such as outdoors and does not require a backlight, so that power consumption can be extremely reduced. Note that in the case where the pixel electrode 10325 is formed using both a transparent material and a reflective material, a transflective liquid crystal display device having both advantages can be obtained. Note that in the case where the pixel electrode 10325 is formed using a reflective material, the surface of the pixel electrode 10325 may have unevenness. Alternatively, when the surface of the third insulating film 10308 is uneven, the pixel electrode 10325 can be uneven. By doing so, since the reflected light is irregularly reflected, there is an advantage that the angle dependence of the intensity distribution of the reflected light is reduced. That is, it is possible to obtain a reflective liquid crystal display device having a certain brightness at any angle.

Next, a case where the present embodiment is applied to a horizontal electric field type liquid crystal display device will be described with reference to FIG. FIG. 49 shows the pixel electrode 10425 and the common electrode 10423 in the pixel structure of a liquid crystal display device in which an electric field is applied in the lateral direction in order to perform switching so that the alignment of liquid crystal molecules is always horizontal with respect to the substrate. FIG. 6 is a cross-sectional view and a top view of a pixel when this embodiment is applied to a method of applying an electric field in a lateral direction by performing comb-like pattern processing, that is, a so-called IPS (In-Plane-Switching) method. . 49A is a cross-sectional view of a pixel, and FIG. 49B is a top view of the pixel. A cross-sectional view of the pixel shown in FIG. 49A corresponds to a line segment aa ′ in the top view of the pixel shown in FIG. By applying this embodiment to a liquid crystal display device having a pixel structure shown in FIG. 49, a liquid crystal display device having a large viewing angle in principle and a small dependence of response speed on gray scale can be obtained.

A pixel structure of an IPS liquid crystal display device is described with reference to FIG. The liquid crystal display device has a basic part that displays an image, called a liquid crystal panel. A liquid crystal panel is manufactured by bonding two processed substrates together with a gap of several μm and injecting a liquid crystal material between the two substrates. In FIG. 49A, the two substrates are a first substrate 10401 and a second substrate 10416. A TFT and a pixel electrode are formed on the first substrate, and a light shielding film 10414 and a color filter 10415 are formed on the second substrate.
Alternatively, the spacer 10417 and the second alignment film 10412 may be manufactured.

Note that this embodiment mode can be implemented without manufacturing a TFT over the first substrate 10401. In the case where this embodiment is performed without manufacturing a TFT, the number of steps is reduced, so that manufacturing cost can be reduced. Furthermore, since the structure is simple, the yield can be improved. On the other hand, when a TFT is manufactured and this embodiment is performed, a larger display device can be obtained.

Note that the TFT illustrated in FIG. 49 is a bottom-gate TFT using an amorphous semiconductor. A liquid crystal panel to which a TFT using an amorphous semiconductor is applied has an advantage that it can be manufactured at low cost using a large-area substrate. However, the present embodiment is not limited to this. The TFT structure that can be used includes a channel etch type, a channel protection type, and the like in a bottom gate type TFT. A top gate type may also be used. Furthermore, not only an amorphous semiconductor but also a polycrystalline semiconductor can be used.

Note that this embodiment can be implemented without forming the light-blocking film 10414 over the second substrate 10416. In the case where this embodiment mode is implemented without forming the light-blocking film 10414, the number of steps is reduced, so that manufacturing cost can be reduced. In addition, since the structure is simple, the yield can be improved. On the other hand, in the case where the light-blocking film 10414 is formed and this embodiment is performed, a display device with little light leakage during black display can be obtained.

Note that this embodiment can be implemented without forming the color filter 10415 over the second substrate 10416. In the case where this embodiment is performed without manufacturing the color filter 10415, the number of steps is reduced, so that manufacturing cost can be reduced. However, even when this embodiment mode is implemented without manufacturing the color filter 10415, a display device capable of color display by field sequential driving can be obtained. In addition, since the structure is simple, the yield can be improved. On the other hand, in the case where the color filter 10415 is manufactured and this embodiment is performed, a display device capable of color display can be obtained.

Note that this embodiment mode can also be implemented by spraying spherical spacers without forming the spacers 10417 on the second substrate 10416. In the case of carrying out the present embodiment by spraying spherical spacers, the number of steps is reduced, so that the manufacturing cost can be reduced. In addition, since the structure is simple, the yield can be improved. Meanwhile, the spacer 104
17 is manufactured and this embodiment is carried out, the position of the spacer does not vary.
The distance between the substrates can be made uniform, and a display device with little display unevenness can be obtained.

Next, processing performed on the first substrate 10401 may be omitted because the method described in FIG. 46 may be used. Here, the first substrate 10401, the first insulating film 10402, the first conductive layer 10403, the second insulating film 10404, the first semiconductor layer 10405, the second semiconductor layer 10406, and the second conductive layer 10407 are used. , A third insulating film 10408, a third conductive layer 1040
9 and the first alignment film 10410 are the first substrate 10101 and the first alignment film in FIG.
Insulating film 10102, first conductive layer 10103, second insulating film 10104, first semiconductor layer 10105, second semiconductor layer 10106, second conductive layer 10107, third insulating film 10
108, the third conductive layer 10109, and the first alignment film 10110. Note that the third conductive layer 10409 on the first substrate 10401 side was subjected to patterning and meshed with each other.
You may form in the shape of two comb teeth. One comb-like electrode may be electrically connected to one of a source electrode or a drain electrode of the TFT 10424, and the other comb-like electrode may be electrically connected to the common electrode 10423. In this way, liquid crystal molecules 10418 are obtained.
Can effectively apply a lateral electric field.

The first substrate 10401 manufactured as described above, the light-shielding film 10414, and the color filter 10
415, the spacer 10417, and the second substrate 10 on which the second alignment film 10412 is manufactured.
A liquid crystal panel can be manufactured by bonding 416 with a sealant with a gap of several micrometers and injecting a liquid crystal material between two substrates. Although not shown,
A conductive layer may be formed on the second substrate 10416 side. By forming the conductive layer on the second substrate 10416 side, it is possible to reduce the influence of electromagnetic wave noise from the outside.

Next, features of the pixel structure of the IPS liquid crystal panel shown in FIG. 49 will be described. FIG.
A liquid crystal molecule 10418 shown in 9A is an elongated molecule having a major axis and a minor axis. In order to show the direction of the liquid crystal molecules 10418, the length is expressed in FIG. In other words, the liquid crystal molecule 10418 expressed in a long direction has a long axis direction parallel to the paper surface, and the liquid crystal molecule 10418 expressed in a short direction has a long axis direction closer to the normal direction of the paper surface. . That is, the liquid crystal molecules 10418 shown in FIG. 49A are aligned so that the major axis is always in the horizontal direction to the substrate. In FIG. 49A,
Although the orientation is shown in the absence of an electric field, when an electric field is applied to the liquid crystal molecules 10418, the orientation of the major axis always rotates in a horizontal plane while maintaining the horizontal direction. In this state, a liquid crystal display device with a large viewing angle can be obtained.

Next, an example of a pixel layout in the case where the present embodiment is applied to an IPS liquid crystal display device will be described with reference to FIG. A pixel of an IPS liquid crystal display device to which this embodiment mode is applied includes a scan line 10421, a video signal line 10422, and a common electrode 10.
423, a TFT 10424, and a pixel electrode 10425 may be provided.

Since the scan line 10421 is electrically connected to the gate electrode of the TFT 10424, the scan line 10421 is preferably formed using the first conductive layer 10403.

Since the video signal line 10422 is electrically connected to the source electrode or the drain electrode of the TFT 10424, the video signal line 10422 is preferably formed using the second conductive layer 10407. Further, since the scanning lines 10421 and the video signal lines 10422 are arranged in a matrix, at least
It is preferable that the conductive layers are formed of different layers. Note that as illustrated in FIG. 49B, the video signal line 10422 may be formed to be bent in the pixel so as to match the shape of the pixel electrode 10425 and the common electrode 10423. By doing so, the aperture ratio of the pixel can be increased, so that the efficiency of the liquid crystal display device can be improved.

The common electrode 10423 is an electrode for generating a horizontal electric field by being arranged in parallel with the pixel electrode 10425, and includes the first conductive layer 10403 and the third conductive layer 10409. Is preferred. As shown in FIG. 49B, the common electrode 1042
3 may extend along the video signal line 10422 so as to surround the video signal line 10422. By doing so, it is possible to reduce a phenomenon in which the potential of the electrode that should hold the potential changes, so-called crosstalk, in accordance with the potential change of the video signal line 10422.
Note that in order to reduce cross capacitance with the video signal line 10422, a first semiconductor layer 10405 may be provided in a cross region of the common electrode 10423 and the video signal line 10422 as illustrated in FIG.

The TFT 10424 operates as a switch for electrically connecting the video signal line 10422 and the pixel electrode 10425. Note that as illustrated in FIG. 49B, either the source region or the drain region of the TFT 10424 may be disposed so as to surround the other of the source region or the drain region. By doing so, a large channel width can be obtained with a small area, and the switching capability can be increased. As shown in FIG. 49B, the TFT
The gate electrode of 10424 may be disposed so as to surround the first semiconductor layer 10405.

The pixel electrode 10425 is electrically connected to one of a source electrode and a drain electrode of the TFT 10424. The pixel electrode 10425 is an electrode for applying a signal voltage transmitted through the video signal line 10422 to the liquid crystal element. Further, a pixel capacitor may be formed by providing the common electrode 10423. In this way, the pixel electrode 10325 is connected to the video signal line 10.
It becomes easy to hold the signal voltage transmitted by 422. Note that the pixel electrode 10425 and the comb-like common electrode 10423 are preferably formed in a bent comb-like shape as illustrated in FIG. Thus, a plurality of regions with different alignment of the liquid crystal molecules 10418 can be formed, so that a liquid crystal display device with a wide viewing angle can be obtained. In the case where the pixel electrode 10425 and the comb-like common electrode 10423 are formed using a transparent material, a transmissive liquid crystal display device can be obtained. The transmissive liquid crystal display device
High color reproducibility and high image quality can be displayed. Further, in the transmissive liquid crystal display device, the pixel has a high aperture ratio, and light efficiency can be improved. Note that a transmissive liquid crystal display device can be obtained even when the pixel electrode 10425 and the comb-like common electrode 10423 are formed using a material that is not transparent and does not have reflectivity. In the transmissive liquid crystal display device, light is transmitted through only the liquid crystal molecules 10418 in a portion where a lateral electric field exists, so that an image with high color reproducibility and high image quality can be displayed. In the case where the pixel electrode 10425 and the comb-like common electrode 10423 are formed using a reflective material,
A transflective liquid crystal display device can be obtained. The transflective liquid crystal display device has high visibility in a bright environment such as outdoors, and can greatly reduce power consumption. further,
A transflective liquid crystal display device has high color reproducibility and can display images with high image quality. Note that a transflective liquid crystal display device can be obtained even when the pixel electrode 10425 and the comb-like common electrode 10423 are formed using both a transparent material and a reflective material. Note that in the case where the pixel electrode 10425 and the comb-like common electrode 10423 are formed using a reflective material, the pixel electrode 10425 and the comb-like common electrode 10
The surface of 423 may be uneven. Alternatively, the surface of the third insulating film 10408 can be uneven so that the pixel electrode 10425 and the comb-shaped common electrode 10423 can be uneven. By doing so, since the reflected light is irregularly reflected, there is an advantage that the angle dependence of the intensity distribution of the reflected light is reduced. That is, it is possible to obtain a reflective liquid crystal display device having a certain brightness at any angle.

Note that the comb-like pixel electrode 10425 and the comb-like common electrode 10423 are both formed using the third conductive layer 10409; however, the pixel structure to which this embodiment can be applied is limited to this. However, it can be selected as appropriate. For example, both the comb-like pixel electrode 10425 and the comb-like common electrode 10423 may be formed using the second conductive layer 10407, or both may be formed using the first conductive layer 10403. Either one may be formed of the third conductive layer 10409 and the other may be formed of the second conductive layer 10407, or one of them may be formed of the third conductive layer 10409 and the other is formed of the first conductive layer 10409. The layer 10407 may be formed, or one of them may be formed using the second conductive layer 10409 and the other may be formed using the first conductive layer 10407.

Next, with reference to FIG. 50, a case where the present embodiment is applied to another horizontal electric field type liquid crystal display device will be described. FIG. 50 is a diagram showing another pixel structure of a liquid crystal display device in which an electric field is applied in the lateral direction in order to perform switching so that the alignment of liquid crystal molecules is always horizontal with respect to the substrate. More specifically, one of the pixel electrode 10525 and the common electrode 10523 is subjected to comb-like pattern processing, and the other is formed by uniformly forming an electrode in a region overlapping the comb-like shape. A method of applying an electric field in the direction, so-called FFS (Fringe Field S)
2A and 2B are a cross-sectional view and a top view of a pixel when this embodiment is applied to a (switching) method. 50A is a cross-sectional view of a pixel, and FIG. 50B is a top view of the pixel.
Further, the cross-sectional view of the pixel shown in FIG. 50A corresponds to a line segment aa ′ in the top view of the pixel shown in FIG. By applying this embodiment to the liquid crystal display device having the pixel structure shown in FIG. 50, a liquid crystal display device having a large viewing angle in principle and a small dependence of response speed on gray scale can be obtained.

A pixel structure of an FFS liquid crystal display device is described with reference to FIG. The liquid crystal display device has a basic part that displays an image, called a liquid crystal panel. A liquid crystal panel is manufactured by bonding two processed substrates together with a gap of several macrometers and injecting a liquid crystal material between the two substrates. In FIG. 50A, the two substrates are a first substrate 10501 and a second substrate 10516. TFT on the first substrate
And a pixel electrode, and a second substrate includes a light-shielding film 10514 and a color filter 1051.
5, the spacer 10517, and the second alignment film 10512 may be formed.

Note that this embodiment mode can be implemented without manufacturing a TFT over the first substrate 10501. In the case where this embodiment is performed without manufacturing a TFT, the number of steps is reduced, so that manufacturing cost can be reduced. In addition, since the structure is simple, the yield can be improved. On the other hand, when a TFT is manufactured and this embodiment is performed, a larger display device can be obtained.

Note that the TFT illustrated in FIG. 50 is a bottom-gate TFT using an amorphous semiconductor. A liquid crystal panel to which a TFT using an amorphous semiconductor is applied has an advantage that it can be manufactured at low cost using a large-area substrate. However, the present embodiment is not limited to this. The TFT structure that can be used includes a channel etch type, a channel protection type, and the like in a bottom gate type TFT. A top gate type may also be used. Furthermore, not only an amorphous semiconductor but also a polycrystalline semiconductor can be used.

Note that this embodiment mode can be implemented without forming the light-blocking film 10514 over the second substrate 10516. In the case where this embodiment mode is implemented without forming the light-blocking film 10514, the number of steps is reduced, so that manufacturing cost can be reduced. In addition, since the structure is simple, the yield can be improved. On the other hand, in the case where the light-blocking film 10514 is formed and this embodiment is performed, a display device with little light leakage during black display can be obtained.

Note that this embodiment mode can be implemented without forming the color filter 10515 over the second substrate 10516. In the case where this embodiment is performed without manufacturing the color filter 10515, the number of steps is reduced, so that manufacturing cost can be reduced. In addition, since the structure is simple, the yield can be improved. However, even when this embodiment is performed without manufacturing the color filter 10515, a display device capable of color display by field sequential driving can be obtained. On the other hand, in the case where the color filter 10515 is manufactured and this embodiment is performed, a display device capable of color display can be obtained.

Note that this embodiment mode can also be implemented by spraying spherical spacers without forming the spacers 10517 on the second substrate 10516. In the case of carrying out the present embodiment by spraying spherical spacers, the number of steps is reduced, so that the manufacturing cost can be reduced. In addition, since the structure is simple, the yield can be improved. Meanwhile, the spacer 105
17 is manufactured and this embodiment is carried out, the position of the spacer does not vary.
The distance between the substrates can be made uniform, and a display device with little display unevenness can be obtained.

Next, processing performed on the first substrate 10501 may be performed by using the method described with reference to FIG. Here, the first substrate 10501, the first insulating film 10502, the first conductive layer 10503, the second insulating film 10504, the first semiconductor layer 10505, the second semiconductor layer 10506, and the second conductive layer 10507 are used. , A third insulating film 10508, a third conductive layer 1050
9 and the first alignment film 10510 are respectively the first substrate 10101 and the first alignment film in FIG.
Insulating film 10102, first conductive layer 10103, second insulating film 10104, first semiconductor layer 10105, second semiconductor layer 10106, second conductive layer 10107, third insulating film 10
108, the third conductive layer 10109, and the first alignment film 10110.

46 differs from FIG. 46 in that a fourth insulating film 10519 and a fourth conductive layer 10513 may be formed on the first substrate 10501 side. More specifically, after pattern processing is performed on the third conductive layer 10509, a fourth insulating film 10519 is formed, and after pattern processing is performed to form a contact hole, the fourth conductive layer 10513 is formed. The first alignment film 10510 may be formed after film formation and patterning in the same manner. Note that materials and processing methods that can be used for the fourth insulating film 10519 and the fourth conductive layer 10513 can be the same as those used for the third insulating film 10508 and the third conductive layer 10509. One comb-like electrode may be electrically connected to one of a source electrode and a drain electrode of the TFT 10524, and the other uniform electrode may be electrically connected to the common electrode 10523. Thus, a horizontal electric field can be effectively applied to the liquid crystal molecules 10518.

The first substrate 10501 manufactured as described above, the light-shielding film 10514, and the color filter 10
515, spacer 10517, and second substrate 10 on which second alignment film 10512 is fabricated
A liquid crystal panel can be manufactured by bonding 516 with a sealant with a gap of several macrometers and injecting a liquid crystal material between two substrates. Note that although not illustrated, a conductive layer may be formed on the second substrate 10516 side. By forming the conductive layer on the second substrate 10516 side, the influence of electromagnetic noise from the outside can be reduced.

Next, features of the pixel structure of the FFS mode liquid crystal panel illustrated in FIG. 50 will be described. FIG.
A liquid crystal molecule 10518 shown in (A) of 0 is an elongated molecule having a major axis and a minor axis. In order to show the direction of the liquid crystal molecules 10518, the length is expressed in FIG. In other words, the longer expressed liquid crystal molecule 10518 has a major axis direction parallel to the paper surface, and the shorter expressed liquid crystal molecule 10518 has a longer axis direction closer to the normal direction of the paper surface. . That is, the liquid crystal molecules 10518 shown in FIG. 50A are aligned so that the major axis is always in the horizontal direction to the substrate. In FIG. 50A,
Although the orientation is shown in the absence of an electric field, when an electric field is applied to the liquid crystal molecules 10518, the orientation of the major axis always rotates in a horizontal plane while maintaining the horizontal direction. In this state, a liquid crystal display device with a large viewing angle can be obtained.

Next, an example of a pixel layout when this embodiment is applied to an FFS liquid crystal display device will be described with reference to FIG. A pixel of an FFS liquid crystal display device to which this embodiment is applied includes a scan line 10521, a video signal line 10522, and a common electrode 10.
523, a TFT 10524, and a pixel electrode 10525 may be provided.

Since the scan line 10521 is electrically connected to the gate electrode of the TFT 10524, the scan line 10521 is preferably formed using the first conductive layer 10503.

Since the video signal line 10522 is electrically connected to the source electrode or the drain electrode of the TFT 10524, the video signal line 10522 is preferably formed using the second conductive layer 10507. Further, since the scanning lines 10521 and the video signal lines 10522 are arranged in a matrix, at least
It is preferable that the conductive layers are formed of different layers. Note that as shown in FIG. 50B, the video signal line 10522 may be bent in the pixel so as to match the shape of the pixel electrode 10525. By doing this, the aperture ratio of the pixel can be increased,
The efficiency of the liquid crystal display device can be improved.

The common electrode 10523 is preferably formed using a first conductive layer 10503 and a third conductive layer 10509. In order to reduce the cross capacitance with the video signal line 10522,
As shown in FIG. 50B, the first semiconductor layer 10505 may be provided in an intersection region between the common electrode 10523 and the video signal line 10522.

The TFT 10524 operates as a switch for electrically connecting the video signal line 10522 and the pixel electrode 10525. Note that as illustrated in FIG. 50B, either the source region or the drain region of the TFT 10524 may be arranged so as to surround the other of the source region or the drain region. By doing so, a large channel width can be obtained with a small area, and the switching capability can be increased. As shown in FIG. 50B, the TFT
The gate electrode 10524 may be disposed so as to surround the first semiconductor layer 10505.

The pixel electrode 10525 is electrically connected to one of the source electrode and the drain electrode of the TFT 10524. The pixel electrode 10525 is an electrode for applying a signal voltage transmitted through the video signal line 10522 to the liquid crystal element. Further, a pixel capacitor may be formed by disposing the common electrode 10523. In this way, the pixel electrode 10525 is connected to the video signal line 10.
It becomes easier to hold the signal voltage transmitted by 522. Note that the pixel electrode 10525 includes
As shown in FIG. 50B, it is preferable to form a bent comb-like shape. Thus, a plurality of regions with different alignment of the liquid crystal molecules 10518 can be formed, so that a liquid crystal display device with a wide viewing angle can be obtained. In addition, the comb-like pixel electrode 1052
5 and the common electrode 10523 are made of a transparent material, a transmissive liquid crystal display device can be obtained. Note that a transmissive liquid crystal display device can be obtained even when the comb-like pixel electrode 10525 is formed using a non-reflective material and the common electrode 10523 is formed using a transparent material. A transmissive liquid crystal display device has high color reproducibility and can display an image with high image quality. In the case where the comb-like pixel electrode 10525 and the common electrode 10523 are formed using a reflective material, a reflective liquid crystal display device can be obtained. However, if at least the common electrode 10523 is made of a reflective material, a reflective liquid crystal display device can be obtained. The reflective liquid crystal display device has high visibility in a bright environment such as outdoors and does not require a backlight, so that power consumption can be extremely reduced. Note that in the case where the comb-like pixel electrode 10525 and the common electrode 10523 are formed using both a transparent material and a reflective material, a transflective liquid crystal display device having both advantages is obtained. Can be obtained. However, the comb-like pixel electrode 1
Even when 0525 is formed using a reflective material and the pixel electrode 10525 is formed using a transmissive material, a transflective liquid crystal display device can be obtained. Note that in the case where the pixel electrode 10525 and the comb-shaped common electrode 10523 are formed using a reflective material, the surfaces of the comb-shaped pixel electrode 10525 and the common electrode 10523 may be uneven. Alternatively, the surface of the third insulating film 10508 can be uneven so that the comb-like pixel electrode 10525 and the common electrode 10523 can be uneven. By doing so, since the reflected light is irregularly reflected, there is an advantage that the angle dependence of the intensity distribution of the reflected light is reduced. That is, it is possible to obtain a reflective liquid crystal display device having a certain brightness at any angle.

Note that the comb-like pixel electrode 10525 is formed of the fourth conductive layer 10513 and the uniform common electrode 10523 is formed of the third conductive layer 10509; however, this embodiment mode can be applied. The pixel configuration is not limited to this, and can be appropriately selected as long as a certain condition is satisfied. More specifically, it is only necessary that the comb-like electrode is positioned closer to the liquid crystal than the uniform electrode when viewed from the first substrate 10501. This is because the horizontal electric field is always generated in the opposite direction to the uniform electrode when viewed from the comb-like electrode. That is, in order to apply a lateral electric field to the liquid crystal, the comb-like electrode must be positioned closer to the liquid crystal than the uniform electrode.

In order to satisfy this condition, for example, a comb-like electrode may be formed of the fourth conductive layer 10513, a uniform electrode may be formed of the third conductive layer 10509, or a comb-like electrode may be formed. Fourth conductive layer 1
The uniform electrode may be formed of the second conductive layer 10507, the comb-like electrode may be formed of the fourth conductive layer 10513, and the uniform electrode may be formed of the first conductive layer. 10503, a comb-like electrode may be formed of the third conductive layer 10509, a uniform electrode may be formed of the second conductive layer 10507, or a comb-like electrode may be formed. The third conductive layer 10509 may be used, and a uniform electrode may be formed using the first conductive layer 10503, or a comb-like electrode may be formed using the second conductive layer 1
A uniform electrode may be formed using the first conductive layer 10503. Note that the comb-like electrode is electrically connected to one of the source region and the drain region of the TFT 10524, and the uniform electrode is electrically connected to the common electrode 10523, but this connection is reversed. But you can. In that case, a uniform electrode may be formed independently for each pixel.

Next, various liquid crystal modes applicable to the liquid crystal display device of this embodiment will be described.

First, FIGS. 51A1 and 51A2 are schematic views of a TN mode liquid crystal display device.

As in the above embodiment mode, the liquid crystal layer 10600 is sandwiched between the first substrate 10601 and the second substrate 10602 which are arranged to face each other. Then, the first substrate 106
A layer 10603 including a first polarizer is stacked on the 01 side, and a layer 10604 including a second polarizer is disposed on the second substrate 10602 side. Note that the layer 10 containing the first polarizer
603 and the layer 10604 including the second polarizer are arranged so as to be crossed Nicols.

Although not shown, the backlight or the like is disposed outside the layer including the second polarizer. A first electrode 10605 is formed over the first substrate 10601 and the second substrate 10602, respectively.
A second electrode 10606 is provided. The first electrode 10605 which is the electrode on the side opposite to the backlight, that is, the viewing side is formed so as to have at least translucency.

In the liquid crystal display device having the structure as illustrated in FIGS. 51A1 and 51A, in the normally white mode, voltage is applied to the first electrode 10605 and the second electrode 10606 (referred to as a vertical electric field mode). Then, black display is performed as shown in FIG. At this time, the liquid crystal molecules are aligned vertically. As a result, the light from the backlight cannot pass through the substrate, resulting in a black display.

Then, as shown in FIG. 51A2, the first electrode 10605 and the second electrode 10606 are used.
When no voltage is applied during this period, the display is white. At this time, the liquid crystal molecules are aligned horizontally,
It will be in the state rotated in the plane. As a result, light from the backlight passes through a layer including a pair of polarizers (a layer including a first polarizer 10603 and a layer 10604 including a second polarizer) arranged to be crossed Nicols. And a predetermined video display is performed.

A liquid crystal display device having a structure illustrated in FIGS. 51A1 and 51A2 can perform full-color display by being provided with a color filter. The color filter is formed on the first substrate 10.
It can be provided on either the 601 side or the second substrate 10602 side. However, FIG.
A liquid crystal display device having a configuration such as 1 (A1) or (A2) can perform full-color display by field sequential driving if light from a backlight changes with time without providing a color filter.

A known liquid crystal material may be used for the TN mode.

FIG. 51B1 is a schematic view of a VA mode liquid crystal display device. The VA mode is a mode in which liquid crystal molecules are aligned so as to be perpendicular to the substrate when there is no electric field.

Similarly to FIGS. 51A1 and 51A2, a first electrode 10605 and a second electrode 10606 are provided over the first substrate 10601 and the second substrate 10602, respectively. The first electrode 10605 which is the electrode on the side opposite to the backlight, that is, the viewing side is formed so as to have at least translucency. A layer 10603 including a first polarizer is stacked on the first substrate 10601 side, and a layer 1 including a second polarizer is stacked on the second substrate 10602 side.
0604 is arranged. Note that the layer 10603 including the first polarizer and the layer 10604 including the second polarizer are arranged so as to be crossed Nicols.

In the liquid crystal display device having the structure illustrated in FIGS. 51A1 and 51A1, the first electrode 106 is used.
05 and when a voltage is applied to the second electrode 10606 (vertical electric field method), FIG. 51 (B1)
As shown in FIG. 2, the white display is performed. At this time, the liquid crystal molecules are arranged side by side. Then, light from the backlight is a layer including a pair of polarizers (layer 10603 including a first polarizer and layer 10604 including a second polarizer) which are arranged so as to be crossed Nicols.
), And a predetermined video display is performed. At this time, a full color display can be performed by providing a color filter. The color filter is formed on the first substrate 10.
It can be provided on either the 601 side or the second substrate 10602 side.

Then, as illustrated in FIG. 51B2, the first electrode 10605 and the second electrode 10606 are used.
When no voltage is applied during this period, the display is black, that is, an off state. At this time, the liquid crystal molecules are aligned vertically. As a result, the light from the backlight cannot pass through the substrate, resulting in a black display.

In the off state, the liquid crystal molecules rise perpendicularly to the substrate and display black, and in the on state, the liquid crystal molecules tilt horizontally with respect to the substrate and display white. Since the liquid crystal molecules are standing up in the off state, the light from the polarized backlight passes through the cell without being affected by the birefringence of the liquid crystal molecules and is blocked by the layer containing the polarizer on the counter substrate side. be able to.

Here, FIGS. 51C1 and 51C2 illustrate examples in which the layer including the stacked polarizers of this embodiment is applied to the MVA mode in which the alignment of the liquid crystal is divided. The MVA mode is a method for mutually compensating the viewing angle dependency of each part. As shown in FIG. 51C1, in the MVA mode, protrusions 10607 and 10608 having a triangular cross section are provided on the first electrode 10605 and the second electrode 10606 for alignment control. First electrode 10605 and second electrode
When a voltage is applied to the electrode 10606 (vertical electric field method), a white display is performed as shown in FIG. 51C1. At this time, the liquid crystal molecules are projected from 10607 and 1060.
It will be in a state of being lined up against 8. Then, light from the backlight passes through a layer including a pair of polarizers (a layer 10603 including a first polarizer and a layer 10604 including a second polarizer) which are arranged to be crossed Nicols. And a predetermined video display is performed. Note that a liquid crystal display device having a structure illustrated in FIGS. 51C1 and 51C2 can perform full-color display by being provided with a color filter. The color filter can be provided on either the first substrate 10601 side or the second substrate 10602 side. Needless to say, the liquid crystal display device having the structure shown in FIGS. 51C1 and 51C2 can perform full-color display by field sequential driving without providing a color filter.

Then, as illustrated in FIG. 51C2, the first electrode 10605 and the second electrode 1060 are used.
When no voltage is applied during 6, the display is black, that is, an off state. At this time, the liquid crystal molecules are aligned vertically. As a result, the light from the backlight cannot pass through the substrate, resulting in a black display.

FIG. 54 shows a top view and a cross-sectional view of another example of the MVA mode. As shown in FIG. 54A, the second electrodes 10606a, 10606b, and 10606c may be formed in a bent pattern like a dogleg shape. In addition, insulating layers 10901 and 10902 are formed in the vicinity of the liquid crystal layer 10600. Note that the insulating layers 10901 and 10902 may be alignment films. As shown in FIG. 54B, in the vicinity of the first electrode 10605, the protrusion 1
0607 may be formed corresponding to the second electrodes 10606a, 10606b, and 10606c. The protrusion 10607 is connected to the second electrode 10606a, 10606b, 10606c.
To form the second electrodes 10606a, 10606b, 10606.
The opening of c functions like a protrusion and can effectively align liquid crystal molecules. Note that the order in which the first electrode 10605 and the protrusion 10607 are formed may be opposite to that in FIG.

52A1 and 52A2 are schematic views of an OCB mode liquid crystal display device. In the OCB mode, the alignment of liquid crystal molecules forms an optically compensated state in the liquid crystal layer, which is called bend alignment.

As in FIG. 51, a first electrode 10605 and a second electrode 10606 are provided over the first substrate 10601 and the second substrate 10602, respectively. Although not illustrated, the backlight or the like is disposed outside the layer 10604 including the second polarizer. The first electrode 10605 which is the electrode on the side opposite to the backlight, that is, the viewing side is formed so as to have at least translucency. Then, on the first substrate 10601 side, the layer 1 including the first polarizer
0603 is stacked, and a layer 10604 including a second polarizer is provided on the second substrate 10602 side. Note that the layer 10603 containing the first polarizer and the layer 10 containing the second polarizer.
604 is arranged to be crossed Nicols.

In the liquid crystal display device having the structure shown in FIGS. 52A1 and 52A1, the first electrode 106 is used.
05 and when a constant on-voltage is applied to the second electrode 10606 (vertical electric field method), FIG.
2 (A1), black display is performed. At this time, the liquid crystal molecules are aligned vertically. Then, the light from the backlight cannot pass through the substrate, and a black display is obtained.

Then, as shown in FIG. 52A2, the first electrode 10605 and the second electrode 1060 are used.
When a constant off voltage is applied during 6, the white display is obtained. At this time, the liquid crystal molecules are in a bend alignment state. As a result, light from the backlight passes through a layer including a pair of polarizers (a layer including a first polarizer 10603 and a layer 10604 including a second polarizer) arranged to be crossed Nicols. And a predetermined video display is performed. Note that FIG.
A liquid crystal display device having a configuration such as A1) and (A2) can perform full-color display by providing a color filter. The color filter can be provided on either the first substrate 10601 side or the second substrate 10602 side. Of course, FIG.
1) The liquid crystal display device having the configuration as in (A2) can perform full color display by field sequential driving without providing a color filter.

In the OCB mode as shown in FIGS. 52A1 and 52A, the alignment of the liquid crystal molecules can be optically compensated in the liquid crystal layer, so that the viewing angle dependency is small, and the contrast is increased by the layer including a pair of stacked polarizers. The ratio can be increased.

52B1 and 52B are schematic views of liquid crystals in the FLC mode and the AFLC mode.

As in FIG. 51, a first electrode 10605 and a second electrode 10606 are provided over the first substrate 10601 and the second substrate 10602, respectively. The first electrode 10605 which is the electrode on the side opposite to the backlight, that is, the viewing side is formed so as to have at least translucency. A layer 10603 including a first polarizer is provided on the first substrate 10601 side.
Are stacked, and a layer 10604 including a second polarizer is provided on the second substrate 10602 side. Note that the layer 10603 including the first polarizer and the layer 10604 including the second polarizer are arranged so as to be crossed Nicols.

In the liquid crystal display device having the structure shown in FIGS. 52B1 and 52B1, the first electrode 106 is used.
When a voltage is applied to 05 and the second electrode 10606 (referred to as a vertical electric field method), FIG.
As shown in 1), the display is white. At this time, the liquid crystal molecules are arranged side by side in a direction shifted from the rubbing direction. Therefore, light from the backlight passes through a layer including a pair of polarizers (a layer 10603 including a first polarizer and a layer 10604 including a second polarizer) which are arranged to be crossed Nicols. And a predetermined video display is performed.

Then, as illustrated in FIG. 52B2, the first electrode 10605 and the second electrode 1060 are used.
When no voltage is applied during 6, black display is performed. At this time, the liquid crystal molecules are arranged side by side along the rubbing direction. As a result, the light from the backlight cannot pass through the substrate, resulting in a black display.

Note that a liquid crystal display device having a structure illustrated in FIGS. 52B1 and 52B2 can perform full-color display by being provided with a color filter. The color filter can be provided on either the first substrate 10601 side or the second substrate 10602 side. Needless to say, a liquid crystal display device having a structure as shown in FIGS. 52B1 and 52B2 can perform full-color display by field sequential driving without providing a color filter.

As the liquid crystal material used in the FLC mode and the AFLC mode, a known material may be used.

53A1 and 53A2 are schematic views of an IPS mode liquid crystal display device. The IPS mode is a mode in which liquid crystal molecules are always rotated in a plane with respect to a substrate, and an electrode adopts a horizontal electric field method provided only on one substrate side.

The IPS mode is characterized in that the liquid crystal is controlled by a pair of electrodes provided on one substrate. Therefore, a pair of electrodes 10801 and 10802 is provided over the second substrate 10602. The pair of electrodes 10801 and 10802 may each have a light shielding property. A layer 10603 including a first polarizer is stacked on the first substrate 10601 side, and a layer 10604 including a second polarizer is disposed on the second substrate 10602 side. Note that the layer 10603 including the first polarizer and the layer 10604 including the second polarizer may be arranged so as to be crossed Nicols.

In the liquid crystal display device having the configuration as shown in FIGS. 53A1 and 53A2, the pair of electrodes 10
When a voltage is applied to 801 and 10802, as shown in FIG. 53A1, the liquid crystal molecules are aligned along the lines of electric force deviated from the rubbing direction and turned on so that white display is performed. Then, light from the backlight passes through a layer including a pair of polarizers (a layer 10603 including a first polarizer and a layer 10604 including a second polarizer) which are arranged to be crossed Nicols. And a predetermined video display is performed.

Note that a liquid crystal display device having a structure illustrated in FIGS. 53A1 and 53A2 can perform full-color display by being provided with a color filter. The color filter can be provided on either the first substrate 10601 side or the second substrate 10602 side. Needless to say, the liquid crystal display device having the structure illustrated in FIGS. 53A1 and 53A2 can perform full-color display by field sequential driving without a color filter.

Then, as shown in FIG. 53A2, when no voltage is applied between the pair of electrodes 10801 and 10802, black display, that is, an off state is obtained. At this time, the liquid crystal molecules are arranged side by side along the rubbing direction. As a result, the light from the backlight cannot pass through the substrate, resulting in a black display.

An example of a pair of electrodes 10801 and 10802 that can be used in the IPS mode is shown in FIG. In FIGS. 55A to 55D, the electrode 10801 includes the electrode 10801a and the electrode 10.
Corresponds to 801b, electrode 10801c and electrode 10801d. In addition, the electrode 10802
Corresponds to the electrode 10802a, the electrode 10802b, the electrode 10802c, and the electrode 10802d. In FIG. 55A, the electrode 10801a and the electrode 10802a are wavy shapes having waviness, and in FIG. 55B, the electrode 10801b and the electrode 10802b are shapes having concentric openings, and FIG. Then, electrode 10801c and electrode 10802c
Is a comb-like shape and is partially overlapped. In FIG. 55D, the electrode 10801d and the electrode 10802d are comb-like and have a shape in which the electrodes are engaged with each other.

In addition to the IPS mode, an FFS mode can also be used. In the IPS mode, the pair of electrodes are formed on the same insulating film, whereas in the FFS mode, the electrodes in FIGS.
As shown in 2), the pair of electrodes 10803 and 10804 may be formed on different layers of insulating films.

When a voltage is applied to the pair of electrodes 10803 and 10804 in the liquid crystal display device having the structure illustrated in FIGS. 53B1 and 53B, white display is performed as illustrated in FIG. 53B1. Turns on. Then, light from the backlight passes through a layer including a pair of polarizers (a layer 10603 including a first polarizer and a layer 10604 including a second polarizer) which are arranged to be crossed Nicols. And a predetermined video display is performed.

Note that a liquid crystal display device having a structure illustrated in FIGS. 53B1 and 53B2 can perform full-color display by being provided with a color filter. The color filter can be provided on either the first substrate 10601 side or the second substrate 10602 side. Needless to say, the liquid crystal display device having the structure shown in FIGS. 53B1 and 53B2 can perform full-color display by field sequential driving without providing a color filter.

Then, as shown in FIG. 53B2, when no voltage is applied between the pair of electrodes 10803 and 10804, black display, that is, an off state is obtained. At this time, the liquid crystal molecules are arranged side by side and rotated in a plane. As a result, the light from the backlight cannot pass through the substrate, resulting in a black display.

An example of a pair of electrodes 10803 and 10804 that can be used in the FFS mode is shown in FIG. In FIGS. 56A to 56D, the electrode 10803 includes the electrode 10803a and the electrode 10.
803b corresponds to the electrode 10803c and the electrode 10803d. In addition, the electrode 10804
Corresponds to the electrode 10804a, the electrode 10804b, the electrode 10804c, and the electrode 10804d. In FIG. 56 (A), the electrode 10803a is bent and shaped like an electrode 1080.
4a may not be patterned in the pixel region. In FIG. 56B, the electrode 108
03b has a concentric shape, and the electrode 10804b may not be patterned in the pixel region. In FIG. 56C, the electrode 10803c has a comb-like shape and the electrodes are engaged with each other, and the electrode 10804c is not necessarily patterned in the pixel region.
In FIG. 56D, the electrode 10803d has a comb-like shape, and the electrode 10804d may not be patterned in the pixel region.

Note that the electrode 10803 (10803a, 10803b, 10803c, 10803d) and the electrode 10804 (10804a, 10804b, 10804c, 10804d)
It may have translucency. With the light-transmitting property, a transmissive display device with a high aperture ratio can be obtained.

Note that the electrode 10803 (10803a, 10803b, 10803c, 10803d) and the electrode 10804 (10804a, 10804b, 10804c, 10804d)
You may have light-shielding property or reflectivity. With the light-shielding property or the reflective property, a reflective display device with low power consumption and no backlight can be obtained.

Note that the electrode 10803 (10803a, 10803b, 10803c, 10803d) and the electrode 10804 (10804a, 10804b, 10804c, 10804d)
You may have both the area | region which has translucency, the area | region which has light-shielding property or reflectivity, and both. By having both areas, a transmissive display with high display quality is displayed in a dark environment such as indoors, and a reflective display with low power consumption is unnecessary in a bright environment such as outdoors. Thus, a transflective display device can be obtained.

As the liquid crystal material used for the IPS mode and the FFS mode, a known material may be used.

Note that as a liquid crystal mode applicable to the liquid crystal display device of this embodiment mode, in addition to the above-described liquid crystal mode, ASM (Axial Symmetric Aligned Micro-
cell) mode, PDLC (Polymer Dispersed Liquid C)
mode).

Note that this embodiment can be freely combined with any of the other embodiments.

In addition, the content of each figure in this embodiment can be implemented in combination freely with the content of other figures.

(Embodiment 9)
In the present embodiment, a display panel configuration and a peripheral configuration of a display device that can implement the present embodiment will be described. In particular, a display panel (also referred to as a liquid crystal panel) configuration and a peripheral configuration of a liquid crystal display device will be described.

First, a simple structure of the liquid crystal panel will be described with reference to FIG. Also, FIG.
FIG. 7A is a top view of the liquid crystal panel.

In a liquid crystal panel illustrated in FIG. 57A, a pixel portion 20101, a scan line input terminal 20103, and a signal line input terminal 20104 are formed over a substrate 20100. Scan line input terminal 201
The scanning line extends in the row direction from 03 and is formed on the substrate 20100, and the signal line input terminal 201
A signal line is formed on the substrate 20100 from 04 to extend in the column direction. In addition, the pixel unit 2
In 0101, the pixel 20102 is arranged on the matrix where the scanning line and the signal line intersect. In addition, in the pixel 20102, a switching element and a pixel electrode layer are arranged.

As shown in the liquid crystal panel of FIG.
It is formed on both sides in the row direction. The signal line input terminal 20104 is formed on one side in the column direction of the substrate 20100. In addition, scanning lines extending from one scanning line input terminal 20103 and scanning lines extending from the other scanning line input terminal 20103 are alternately formed.

In each pixel 20102 in the pixel portion 20101, the first terminal of the switching element is connected to the signal line, and the second terminal is connected to the pixel electrode layer.
02 can be independently controlled by a signal input from the outside. Note that on / off of the switching element is controlled by a signal supplied to the scanning line.

Note that the pixels 20102 can be arranged with high density by arranging the scan line input terminals 20103 in both of the row directions of the substrate 20100. Also, the signal line side input terminal 20103
Is arranged in one of the column directions of the substrate 20100 to reduce the frame of the liquid crystal panel,
The area of the pixel portion 20101 can be increased.

Note that as described above, the substrate 20100 includes a single crystal substrate, an SOI substrate, a glass substrate, a quartz substrate, a plastic substrate, a paper substrate, a cellophane substrate, a stone substrate, a stainless steel substrate, a substrate having stainless steel foil, or the like. Can be used.

Note that as described above, a transistor, a diode (for example, a PN diode, a PIN diode, a Schottky diode, a diode-connected transistor, or the like), a thyristor, or a logic circuit combining them can be used as the switching element. .

Note that in the case where a TFT is used as the switching element, the gate of the TFT is connected to the scanning line, the first terminal is connected to the signal line, and the second terminal is connected to the pixel electrode layer. Can be controlled independently by an externally input signal.

Note that the scan line input terminal 20103 may be arranged in one of the row directions of the substrate 20100. By disposing the scan line input terminal 20103 in one of the row directions of the substrate 20100, the frame of the liquid crystal panel can be reduced and the area of the pixel portion 20101 can be increased.

Note that the scanning line extending from one scanning line input terminal 20103 and the other scanning line input terminal 2
The scanning line extending from 0103 may be shared.

Note that the scan line input terminals 20103 may be arranged in both of the column directions of the substrate 20100. By arranging the scan line input terminals 20103 in both the column directions of the substrate 20100, the pixels 20102 can be arranged with high density.

Note that a capacitor may be further formed in the pixel 20102. In the case where a capacitor is provided in the pixel 20102, a capacitor line may be formed over the substrate 20100. In the case where a capacitor line is formed over the substrate 20100, the first electrode of the capacitor is connected to the capacitor line and the second terminal is connected to the pixel electrode layer. In the case where a capacitor line is not formed over the substrate 20100, the first electrode of the capacitor is connected to a different scan line from the pixel 20102 in which the capacitor is arranged, and the second terminal is connected to the pixel electrode layer. To be.

Here, the liquid crystal panel illustrated in FIG. 57A has a structure in which signals supplied to the scan lines and the signal lines are controlled by an external driver circuit. As illustrated in FIG. COG (
The driver IC 20201 may be mounted on the substrate 20100 by a Chip on Glass method. As another structure, as shown in FIG. 58B, TAB (Tape
The driver IC 20201 is connected to the FPC2 by the Automated Bonding method.
It may be mounted on 0200 (Flexible Printed Circuit).
In FIG. 58, the driver IC 20201 is connected to the FPC 20200.

Note that the driver IC 20201 may be formed over a single crystal semiconductor substrate or a circuit formed with TFTs over a glass substrate.

Note that in the liquid crystal panel illustrated in FIG. 57A, the scan line driver circuit 20105 may be formed over the substrate 20100 as illustrated in FIG. In addition, as illustrated in FIG. 57C, the scan line driver circuit 20105 and the signal line driver circuit 20106 may be formed over the substrate 20100.

Note that each of the scan line driver circuit 20105 and the scan line driver circuit 20105 includes a large number of N-channel transistors and a large number of P-channel transistors. However, it may be composed of only a large number of N-channel transistors or only a large number of P-channel transistors.

Next, details of the pixel 20102 will be described with reference to circuit diagrams of FIGS.

A pixel 20102 in FIG. 59A includes a transistor 20301, a liquid crystal element 20302, and a capacitor 20303. A gate of the transistor 20301 is connected to the wiring 20305 and a first terminal is connected to the wiring 20304. A first electrode of the liquid crystal element 20302 is connected to the counter electrode 20307, and a second electrode is connected to the second terminal of the transistor 20301. A first electrode of the capacitor 20303 is connected to the capacitor line 20306, and a second electrode is connected to the second terminal of the transistor 20301.

Note that the wiring 20304 is a signal line, the wiring 20305 is a scanning line, and the capacitor line 2030.
6 is a capacity line. The transistor 20301 is a switching transistor and may be a P-channel transistor or an N-channel transistor. Liquid crystal element 2
0302 is a TN (twisted nematic) mode as an operation mode, IPS
(In-Plane-Switching) mode, FFS (Fringe Field)
Switching mode, MVA (Multi-domain Vertical)
Alignment mode, PVA (Patterned Vertical Al)
ignition), ASM (Axial Symmetric aligned M)
micro-cell) mode, OCB (Optical Compensated Bi)
refrenceence) mode, FLC (Ferroelectric Liquid)
Crystal) mode, AFLC (Antiferroelectric Liquid)
id Crystal) or the like can be used.

A video signal and a scanning signal are input to the wiring 20304 and the wiring 20305, respectively. The video signal is an analog voltage signal, and the scanning signal is an H level or L level digital voltage signal. However, the video signal may be a current signal or a digital signal. The H level and the L level of the scanning signal may be any potential that can control the on / off of the transistor 20301.

A constant power supply voltage is supplied to the capacitor line 20306. However, a pulsed signal may be supplied.

An operation of the pixel 20102 in FIG. 59A is described. First, when the wiring 20305 is at an H level, the transistor 20301 is turned on, and the second electrode of the liquid crystal element 20302 and the capacitor 2030 are connected through the transistor 20301 in which the video signal is turned on from the wiring 20304.
3 to the second electrode. The capacitor 20303 holds a potential difference between the potential of the wiring 203076 and the potential of the video signal.

Next, when the wiring 20305 is at an L level, the transistor 20301 is turned off and the wiring 20
304 is electrically disconnected from the second electrode of the liquid crystal element 20302 and the second electrode of the capacitor 20303. However, since the capacitor 20303 holds a potential difference between the potential of the wiring 203076 and the potential of the video signal, the potential of the second electrode of the capacitor 20303 can be maintained at the same potential as the video signal.

In this manner, the pixel 20102 in FIG. 59A can maintain the potential of the second electrode of the liquid crystal element 20302 at the same potential as the video signal, and can maintain the transmittance of the liquid crystal element 20302 according to the video signal.

Note that although not illustrated, the capacitor 20303 is not necessarily required as long as the liquid crystal element 20302 has a capacitance component that can hold a video signal.

Note that as illustrated in FIG. 59B, the first electrode of the liquid crystal element 20302 may be connected to the capacitor line 20306. For example, when the liquid crystal mode of the liquid crystal element 20302 is the FFS mode, the liquid crystal element 20302 uses the structure in FIG.

Note that as illustrated in FIG. 60, the first electrode of the capacitor 20303 may be connected to the wiring 20305a in the previous row. Note that when the wiring 20305a is an n-th scanning line (n is a positive integer), the wiring 20305b is an n + 1-th scanning line. Similarly, transistor 20301a
When the pixel 20102a and the capacitor 20303a are elements in the n-th row, the transistor 2
0301b, the pixel 20102b, and the capacitor 20303b are elements in the (n + 1) th row. In this manner, the number of wirings can be reduced by connecting the first electrode of the capacitor 20303b to the wiring 20305a in the previous row. Therefore, the pixels 2010a and 20102 in FIG.
b can increase the aperture ratio.

Next, a more detailed configuration of the liquid crystal panel than the configuration of the liquid crystal panel described with reference to FIGS. 57 and 58 will be described with reference to FIG. Specifically, a TFT substrate, a counter substrate,
A configuration of a liquid crystal panel having a liquid crystal layer sandwiched between a counter substrate and a TFT substrate will be described. FIG. 61A is a top view of the liquid crystal panel. FIG. 61 (B) is similar to FIG.
It is sectional drawing in line CD of A). FIG. 61B is a cross-sectional view in the case where a top-gate transistor in which a crystalline semiconductor film (polysilicon film) is used as a semiconductor film over a substrate 20100 is formed.

In a liquid crystal panel illustrated in FIG. 61A, a pixel portion 20101, a scan line driver circuit 20105a, a scan line driver circuit 20105b, and a signal line driver circuit 2010 are formed over a substrate 20100. Pixel portion 20101, scan line driver circuit 20105a, scan line driver circuit 20105
b and the signal line driver circuit 20106 are sealed between the substrate 20100 and the counter substrate 20515 by a sealant 20516. In addition, by the TAB method, FPC2051
8 and the IC chip 20530 are arranged on the substrate 20100.

A cross-sectional structure taken along line CD in FIG. 61A is described with reference to FIG.
A pixel portion 20101 and its peripheral driver circuit portion (scanning line circuit 20105) are formed over a substrate 20100.
a and a scanning line driver circuit 20105b and a signal line driver circuit 20106 are formed. Here, a driver circuit region 20525 (a scanning line driver circuit 20105a and a scanning line driver circuit 20105b) and a pixel region 20526 (a pixel portion 20101) are formed. ) And is shown.

First, an insulating film 20501 is formed over the substrate 20100 as a base film. As the insulating film 20501, a silicon oxide film, a silicon nitride film, or a silicon oxynitride film (Si
A single layer of an insulating film such as OxNy) or a stacked structure including at least two of these films may be used.

Note that a silicon oxide film is preferably used in a portion in contact with the semiconductor. As a result, electron trapping in the base film and hysteresis of transistor characteristics can be suppressed. Also,
It is desirable to dispose at least one film containing a large amount of nitrogen as the base film. Thereby, impurities from the glass can be reduced.

Next, a semiconductor layer 20502 is formed over the insulating film 20501 by a photolithography method, an inkjet method, a printing method, or the like.

Next, the insulating layer 2501 is formed over the insulating film 20501 and the semiconductor layer 20502 as a gate insulating film.
0503 is formed.

Note that as the insulating layer 20503, a single layer or a stacked structure such as a thermal oxide film, a silicon oxide film, a silicon nitride film, or a silicon oxynitride film can be used. Semiconductor layer 20502
The insulating layer 20503 in contact with the gate electrode is preferably a silicon oxide film. This is because a trap level at the interface with the semiconductor layer 20502 is reduced when a silicon oxide film is used. When the gate electrode is made of Mo, the gate insulating film in contact with the gate electrode is preferably a silicon nitride film. This is because the silicon nitride film does not oxidize Mo. Here, the insulating layer 20503
A silicon oxynitride film having a thickness of 115 nm (composition ratio Si = 3) by plasma CVD
2%, O = 59%, N = 7%, H = 2%).

Next, a conductive layer 20504 is formed over the insulating layer 20503 as a gate electrode by a photolithography method, an inkjet method, a printing method, or the like.

Note that the conductive layer 20504 includes Ti, Mo, Ta, Cr, W, Al, Nd, Cu, and A.
g, Au, Pt, Nb, Si, Zn, Fe, Ba, Ge, etc., and alloys of these elements. Or you may comprise by lamination | stacking of these elements or the alloy of these elements. Here, the gate electrode is formed of Mo. Mo is suitable because it is easy to etch and is resistant to heat.

Note that in the semiconductor layer 20502, an impurity element is doped into the semiconductor layer 20502 using the conductive layer 20504 or the resist as a mask, and a channel formation region and impurity regions to be a source region and a drain region are formed.

The impurity region may be formed as a high concentration region and a low concentration region by controlling the impurity concentration.

Note that the conductive layer 20504 of the transistor 20521 has a dual gate structure.
The transistor 20521 has a dual gate structure, so that the transistor 20521
The off current can be reduced. Note that the dual gate structure is a structure having two gate electrodes. Note that a plurality of gate electrodes may be provided over the channel region of the transistor.

Next, an insulating layer 20505 is formed over the insulating layer 20503 and the conductive layer 20504 as an interlayer film.
Is formed.

Note that as the insulating layer 20505, an organic material, an inorganic material, or a stacked structure thereof can be used. For example, silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide or aluminum oxide whose nitrogen content is higher than oxygen content, diamond like carbon (DLC), polysilazane, nitrogen content It can be formed of a material selected from carbon (CN), PSG (phosphorus glass), BPSG (phosphorus boron glass), alumina, and other inorganic insulating materials. An organic insulating material may be used, and the organic material may be either photosensitive or non-photosensitive, and polyimide, acrylic, polyamide, polyimide amide, resist, benzocyclobutene, siloxane resin, or the like can be used. . Siloxane resin is Si-
It corresponds to a resin containing an O—Si bond. Siloxane has a skeleton structure formed of a bond of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (for example, an alkyl group or an aromatic hydrocarbon) is used. A fluoro group may be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as a substituent.

Note that a contact hole is selectively formed in the insulating layer 20503 and the insulating layer 20505. For example, the contact hole is formed on the upper surface of the impurity region of each transistor.

Next, a conductive film 20506 is formed over the insulating layer 20505 as a drain electrode, a source electrode, and a wiring by a photolithography method, an inkjet method, a printing method, or the like.

Note that the conductive film 20506 includes Ti, Mo, Ta, Cr, W, Al, and N as materials.
d, Cu, Ag, Au, Pt, Nb, Si, Zn, Fe, Ba, Ge, and alloys of these elements. Alternatively, a stacked structure of these elements or an alloy of these elements can be used.

Note that the conductive film 20506 and the impurity region of the semiconductor layer 20502 of the transistor are connected to each other in a portion where the contact hole of the insulating layer 20503 and the conductive layer 20504 is formed.

Next, an insulating layer 20507 is formed as a planarization film over the insulating layer 20505 and the conductive film 20506 formed over the insulating layer 20505.

Note that the insulating layer 20507 is preferably formed using an organic material because it is preferable to have flatness and covering properties. Note that the insulating layer 20507 may have a multilayer structure, and an organic material may be formed over an inorganic material (silicon oxide, silicon nitride, or silicon oxynitride).

Note that a contact hole is selectively formed in the insulating layer 20507. For example, the contact hole is formed on the upper surface of the drain electrode of the transistor 20521.

Next, a conductive layer 20508 is formed as a pixel electrode over the insulating layer 20507 by a photolithography method, an inkjet method, a printing method, or the like.

Note that as the conductive layer 20508, a transparent electrode that transmits light and a reflective electrode that reflects light can be used.

In the case of a transparent electrode, for example, indium tin oxide in which tin oxide is mixed with indium oxide (
ITO) film, indium tin oxide (ITSO) film in which indium tin oxide (ITO) is mixed with silicon oxide, indium zinc oxide (IZO) in which indium oxide is mixed with zinc oxide
) A film, a zinc oxide film, a tin oxide film, or the like can be used. IZO means I
The transparent conductive material is formed by sputtering using a target in which 2 to 20 wt% zinc oxide (ZnO) is mixed with TO, but is not limited thereto.

In the case of a reflective electrode, for example, Ti, Mo, Ta, Cr, W, Al, Nd, Cu, Ag, A
u, Pt, Nb, Si, Zn, Fe, Ba, Ge, or an alloy thereof can be used. Also, a two-layer structure in which Ti, Mo, Ta, Cr, W and Al are laminated, Al is Ti,
A three-layer structure sandwiched between metals such as Mo, Ta, Cr, and W may also be used.

Next, over the insulating layer 20507 and the conductive layer 20508 formed over the insulating layer 20507,
An insulating layer 20509 is formed as the alignment film.

Next, a sealant 20516 is formed on the periphery of the pixel portion 20101, or the periphery of the pixel portion 20101 and the periphery of the peripheral driver circuit portion by an inkjet method or the like.

Next, the counter substrate 20515 over which the insulating film 20514, the insulating film 20513, the conductive film 20512, the insulating film 20511, and the like are formed is bonded to the substrate 20100 with the spacer 2053 interposed therebetween. Has been placed.

Note that the substrate 20115 may function as a counter substrate. The insulating film 20514 is formed of
It may function as a black matrix (light shielding film). The insulating film 20513 may function as a color filter. Alternatively, the spacer 20531 may be provided by dispersing particles of several μm, or may be formed by etching the resin film after forming the resin film on the entire surface of the substrate. Further, the conductive film 20512 may function as a counter electrode. The conductive film 20512 can be similar to the conductive layer 20508.
The insulating film 20511 may function as an alignment film.

Note that the insulating film 20532 may be formed between the insulating film 20513 and the insulating film 20514 and the conductive film 20512 as a planarization film. Note that the insulating film 20532 is not illustrated in FIG.

Note that a known liquid crystal can be used freely as the liquid crystal layer 20510. For example, a ferroelectric liquid crystal may be used as the liquid crystal layer 20510, or an antiferroelectric liquid crystal may be used. The driving method of the liquid crystal is TN (Twisted Nematic) mode, IPS (
In-Plane-Switching mode, FFS (Fringe Field)
Switching mode, MVA (Multi-domain Vertical)
Alignment mode, PVA (Patterned Vertical Ali)
gmnent), ASM (Axial Symmetric Aligned Mi)
cro-cell) mode, OCB (Optical Compensated Bir)
efficiency mode, FLC (Ferroelectric Liquid)
Crystal) mode, AFLC (Antiferroelectric Liquid)
d Crystal) etc. can be used freely.

Next, the conductive film 205 which is electrically connected to the pixel portion 20101 and its peripheral driver circuit portion.
An FPC 20200 is disposed on the layer 33 with an anisotropic conductive layer 20517 interposed therebetween. In addition, an IC chip is provided over the FPC 20200 with an anisotropic conductive layer 20517 interposed therebetween. That is, the FPC 20200, the conductive film 20533, and the IC chip 20530 are electrically connected.

Note that the conductive film 20533 has a function of transmitting a signal and a potential input from the FPC 20200 to a pixel or a peripheral circuit. The conductive film 20533 may be similar to the conductive film 20506, may be similar to the conductive layer 20504, or may be similar to the impurity region of the semiconductor layer 20502. A combination of at least two layers may be used.

Note that the IC chip 20530 can effectively use the substrate area by forming a functional circuit (memory or buffer).

61A and 61B includes a scan line driver circuit 20105a and a scan line driver circuit 2.
Although the structure in the case where the 0105b and the signal line driver circuit 20106 are formed over the substrate 20100 has been described, a driver circuit corresponding to the signal line driver circuit 20106 is formed in the driver IC 20601 as illustrated in the liquid crystal panel in FIG. And it is good also as a structure mounted in the liquid crystal panel by the COG system. By forming the signal line driver circuit 20106 in the driver IC 20601, power saving can be achieved. In addition, when the driver IC 20601 is a semiconductor chip such as a silicon wafer, the liquid crystal panel in FIG. 62A can achieve higher speed and lower power consumption.

Similarly, as illustrated in the liquid crystal panel in FIG. 62B, driver circuits corresponding to the scan line driver circuit 20105a, the scan line driver circuit 20105b, and the signal line driver circuit 2010 are assigned to a driver IC 20602a, a driver IC 20602b, and a driver IC 20601, respectively. It may be formed and mounted on a liquid crystal panel by a COG method or the like. In addition, by forming driver circuits corresponding to the scan line driver circuit 20105a, the scan line driver circuit 20105b, and the signal line driver circuit 2010 in the driver IC 20602a, the driver IC 20602b, and the driver IC 20601, cost reduction can be achieved.

Note that although the transistor 20521 has a dual gate structure, the pixel region 205 in FIG.
As shown in FIG. 26, the transistor 20521 may have a single gate structure. However, FIG. 63 shows only the pixel region 20526.

Next, a cross-sectional view in the case where a bottom-gate transistor is formed over the substrate 20100 is described with reference to FIGS. However, FIG. 64 shows only the pixel region 20526.

First, an insulating film 20501 is formed over the substrate 20100 as a base film. next,
A conductive layer 20504 is formed over the insulating film 20501 as a gate electrode by a photolithography method, an inkjet method, a printing method, or the like. Note that the transistor 2052
One conductive layer 20504 has a dual gate structure. This is because the transistor 20521 has a dual gate structure as described above, so that the transistor 2052
1 off-current can be reduced. Next, an insulating layer 20503 is formed as a gate insulating film over the insulating film 20501 and the conductive layer 20504. Next, over the insulating layer 20503,
The semiconductor layer 20502 is formed by a photolithography method, an inkjet method, a printing method, or the like. Note that the semiconductor layer 20502 is formed using the resist as a mask.
An impurity element is doped in 502, and a channel formation region and impurity regions to be a source region and a drain region are formed. The impurity region may be formed as a high concentration region and a low concentration region by controlling the impurity concentration. Next, an insulating layer 20505 is formed as an interlayer film over the insulating layer 20503 and the semiconductor layer 20502. Note that a contact hole is selectively formed in the insulating layer 20505. For example, the contact hole is formed on the upper surface of the impurity region of each transistor. Next, the insulating layer 2050
On 5, a conductive film 20506 is formed as a drain electrode, a source electrode, and a wiring by a photolithography method, an inkjet method, a printing method, or the like. Note that the insulating layer 205
In the portion where the contact hole 05 is formed, the conductive film 20506 and the impurity region of the semiconductor layer 20502 of the transistor are connected. Next, an insulating layer 20507 is formed over the insulating layer 20505 and the conductive film 20506 as a planarization film. Note that a contact hole is selectively formed in the insulating layer 20507. For example, the contact hole is formed on the upper surface of the drain electrode of the transistor 20521. Next, a conductive layer 20508 is formed as a pixel electrode over the insulating layer 20507 by a photolithography method, an inkjet method, a printing method, or the like. Next, an insulating layer 20509 is formed as an alignment film over the insulating layer 20507 and the conductive layer 20508. Next, the insulating film 20
A liquid crystal layer 20510 is provided in a gap between the substrate 20100 and the counter substrate 20515 on which the insulating film 20513, the conductive film 20512, the insulating film 20511, and the like are formed.

Note that in FIG. 64, the transistor 20521 has a dual gate structure. However,
As illustrated in the pixel region 20526 in FIG. 65, the transistor 20521 may have a single gate structure.

Next, a cross-sectional view in the case where a double-gate transistor is formed over the substrate 20100 is described with reference to FIGS. However, FIG. 66 shows only the pixel region 20526.

Note that a double-gate transistor refers to a structure in which gate electrodes are provided above and below a semiconductor film, respectively. In addition, a double-gate transistor has twice the current flowing if it has the same size and the same applied voltage as the top-gate transistor and the bottom-gate transistor. In other words, the double gate transistor can flow more current with a small transistor size.

First, an insulating film 20501 is formed over the substrate 20100 as a base film. next,
A conductive layer 20504a is formed as a first gate electrode over the insulating film 20501 by a photolithography method, an inkjet method, a printing method, or the like. Note that the conductive layer 205
04a can be formed using a material and a structure similar to those of the conductive layer 20504. next,
As the first gate insulating film, the insulating layer 2 is formed over the insulating film 20501 and the conductive layer 20504a.
0503a is formed. Note that the insulating layer 20503a can be formed using a material and a structure similar to those of the insulating layer 20503. Next, the semiconductor layer 20502 is formed over the insulating layer 20503a by a photolithography method, an inkjet method, a printing method, or the like. Next, an insulating layer 20503b is formed as a second gate insulating film over the insulating layer 20503a and the semiconductor layer 20502. Note that the insulating layer 20503b corresponds to the insulating layer 20
A material and a structure similar to those of 503 can be used. Next, a conductive layer 20504b is formed as a second gate electrode over the insulating layer 20503b by a photolithography method, an inkjet method, a printing method, or the like. Note that the conductive layer 20504b is formed of the conductive layer 2
A material and a structure similar to those of 0504 can be used. Note that the semiconductor layer 20502
The semiconductor layer 20502 is doped with an impurity element using the conductive layer 20504b or a resist as a mask to form a channel formation region and impurity regions to be a source region and a drain region. The impurity region may be formed as a high concentration region and a low concentration region by controlling the impurity concentration. Note that the semiconductor layer 20502 includes an insulating layer 20503.
b and the conductive layer 20504b, the semiconductor layer 2050 is formed using a resist as a mask.
2 may be doped with an impurity element to form a channel formation region and impurity regions to be a source region and a drain region. Next, the insulating layer 20503b and the conductive layer 20
An insulating layer 20505 is formed over the layer 504b as an interlayer film. Note that the insulating layer 205
03b and the insulating layer 20505 are selectively formed with contact holes. For example, the contact hole is formed on the upper surface of the impurity region of each transistor. Next, a conductive film 20506 is formed over the insulating layer 20505 as a drain electrode, a source electrode, and a wiring by a photolithography method, an inkjet method, a printing method, or the like. In addition,
In the part where the contact holes of the insulating layer 20503 and the insulating layer 20505 are formed,
The conductive film 20506 is connected to the impurity region of the semiconductor layer 20502 of the transistor. Next, over the insulating layer 20505 and the conductive film 20506, the insulating layer 205 is formed as a planarization film.
07 is formed. Note that a contact hole is selectively formed in the insulating layer 20507. For example, the contact hole is formed on the upper surface of the drain electrode of the transistor 20521. Next, a conductive layer 20508 is formed as a pixel electrode over the insulating layer 20507 by a photolithography method, an inkjet method, a printing method, or the like. Next, an insulating layer 20509 is formed as an alignment film over the insulating layer 20507 and the conductive layer 20508. Next, a liquid crystal layer 20510 is provided in a gap between the counter substrate 20515 provided with the insulating film 20514, the insulating film 20513, the conductive film 20512, the insulating film 20511, and the like and the substrate 20100.

Note that FIGS. 61 and 63 to 66 illustrate cross-sectional views in the case where the insulating layer 20507 is formed as a flat film over the insulating layer 20505 and the conductive film 20506 formed over the insulating layer 20505. . However, the insulating layer 20507 is not necessarily required as shown in FIG.

Note that the cross-sectional view in FIG. 67 illustrates the case of a top-gate transistor, but the same applies to the case of a bottom-gate transistor and a double-gate transistor.

Next, an amorphous semiconductor film (amorphous silicon film) is formed over the substrate 20100 as a semiconductor film.
A cross-sectional view in the case of forming a transistor using n is described with reference to FIGS. The cross-sectional view in FIG. 68 is a cross-sectional view of an inverted staggered channel-etched transistor.

First, an insulating film 20501 is formed over the substrate 20100 as a base film. next,
A conductive layer 20504 is formed over the insulating film 20501 as a gate electrode by a photolithography method, an inkjet method, a printing method, or the like. Next, an insulating layer 20503 is formed as a gate insulating film over the insulating film 20501 and the conductive layer 20504. Next, a semiconductor layer 20502 is formed over the insulating layer 20503 by a photolithography method, an inkjet method, a printing method, or the like. Note that the semiconductor layer 20502 includes a first semiconductor film and a second semiconductor film, and the second semiconductor film is formed over the first semiconductor film. In addition, the first semiconductor film and the second semiconductor film may be successively formed and simultaneously patterned by a photolithography method. The second semiconductor film contains an impurity element. Next, a conductive film 20506 is formed over the insulating layer 20503 and the semiconductor layer 20502 by a photolithography method, an inkjet method, a printing method, or the like. In addition,
The semiconductor layer 20502 is etched using the conductive film 20506 as a mask, so that a channel formation region and impurity regions to be a source region and a drain region are formed. That is, in the channel region, the second semiconductor film containing the impurity element is removed. Note that the semiconductor layer 20502 may be etched using a resist for etching the conductive film 20506 as a mask. Next, an insulating layer 20507 is formed as a planarization film over the insulating layer 20503, the semiconductor layer 20502, and the conductive film 20506. Note that a contact hole is selectively formed in the insulating layer 20507. For example, the contact hole is formed on the upper surface of the drain electrode of the transistor 20521. Next, a conductive layer 20508 is formed as a pixel electrode over the insulating layer 20507 by a photolithography method, an inkjet method, a printing method, or the like. Next, an insulating layer 20509 is formed as an alignment film over the insulating layer 20507 and the conductive layer 20508. Next, the insulating film 2
A liquid crystal layer 20510 is provided in a gap between the substrate 20100 and the counter substrate 20515 provided with 0514, the insulating film 20513, the conductive film 20512, the insulating film 20511, and the like.

Note that although a channel-etched transistor is described, an insulating film 21301 may be provided over the semiconductor layer 20502 as illustrated in FIG. The insulating film 21301 is formed between the first semiconductor film and the second semiconductor film. The semiconductor layer 20502 includes the conductive film 20
When forming 506, it is etched simultaneously.

Note that the transistor 20521 in FIG. 68 is referred to as a channel etch structure, and the transistor 20521 in FIG. 69 is referred to as a channel protection structure.

Next, a cross-sectional view in the case where a top-gate transistor using an amorphous semiconductor film as a semiconductor film is formed over the substrate 20100 is described with reference to FIGS.

First, an insulating film 20501 is formed over the substrate 20100 as a base film. next,
A conductive film 20506 is formed over the insulating film 20501 by a photolithography method, an inkjet method, a printing method, or the like. Next, a semiconductor layer 20502a is formed over the conductive film 20506 by a photolithography method, an inkjet method, a printing method, or the like. Note that the semiconductor layer 20502a can be formed using a material and a structure similar to those of the semiconductor layer 20502. The semiconductor layer 20502a contains an impurity element. Next, a semiconductor layer 20502b is formed over the insulating film 20501 and the semiconductor layer 20502a by a photolithography method, an inkjet method, a printing method, or the like. Semiconductor layer 2
For the 0502b, a material and a structure similar to those of the semiconductor layer 20502 can be used.
Next, an insulating layer 20503 is formed as a gate insulating film over the insulating film 20501, the semiconductor layer 20502b, and the conductive film 20506. Next, a conductive layer 20504 is formed over the insulating layer 20503 as a gate electrode by a photolithography method, an inkjet method, a printing method, or the like. Next, an insulating layer 20507 is formed as a planarization film over the insulating layer 20503 and the conductive layer 20504 formed over the insulating layer 20503. Note that a contact hole is selectively formed in the insulating layer 20507. For example, the contact hole is formed on the upper surface of the drain electrode of the transistor 20521. Next, a conductive layer 20508 is formed as a pixel electrode over the insulating layer 20507 by a photolithography method, an inkjet method, a printing method, or the like. Next, an insulating layer 20509 is formed as an alignment film over the insulating layer 20507 and the conductive layer 20508. Next, a liquid crystal layer 20510 is provided in a gap between the counter substrate 20515 provided with the insulating film 20514, the insulating film 20513, the conductive film 20512, the insulating film 20511, and the like and the substrate 20100.

69 and 70, the cross-sectional views in the case where the insulating layer 20507 is formed as a flat film over the insulating layer 20505 and the conductive film 20506 formed over the insulating layer 20505 are described. However, the insulating layer 20507 is not necessarily required as shown in FIG.

Note that the cross-sectional view in FIG. 71 illustrates the case of an inverted staggered channel etch transistor, but the same applies to an inverted staggered channel protection transistor. FIG. 71 shows the case of an inverted staggered transistor.
A top-gate transistor may be used. 72 and 73 are cross-sectional views in the case of a top-gate transistor.

Note that in the case of the cross-sectional view in FIG. 72, the conductive layer 2 is formed over the insulating film 20501 and the conductive film 20506 as a pixel electrode by a photolithography method, an inkjet method, a printing method, or the like.
0508 is formed. The conductive layer 20508 is formed from the formation of the conductive film 20506 to the formation of the insulating layer 20503.

Note that in the cross-sectional view in FIG. 73, a conductive layer 20508 is formed over the insulating film 20501 as a pixel electrode by a photolithography method, an inkjet method, a printing method, or the like. The conductive layer 20508 is formed after the insulating film 20501 is formed.

Next, a cross-sectional view of the transflective liquid crystal panel will be described with reference to FIG.

Note that the cross-sectional view of FIG. 74 is a cross-sectional view of a liquid crystal panel in which a transistor uses a polycrystalline semiconductor as a semiconductor film. However, the transistor may be a bottom gate type or a double gate type. In addition, the gate electrode of the transistor may have a single gate structure,
A dual gate structure may be used.

Note that FIG. 74 is similar to FIG. 63 until the conductive film 20506 is formed. Accordingly, a process and structure after the conductive film 20506 is formed will be described.

First, over the insulating layer 20505 and the conductive film 20506 formed over the insulating layer 20505, a film for reducing the thickness (a so-called cell gap) of the liquid crystal layer 20510 is a photolithography method, an inkjet method, a printing method, or the like. Thus, an insulating film 21801 is formed. Note that the insulating film 21801 is preferably formed using an organic material because it is desirable that the insulating film 21801 has good flatness and coverage. Note that an organic material may be formed over an inorganic material (silicon oxide, silicon nitride, silicon oxynitride) to have a multilayer structure. Note that a contact hole is selectively formed in the insulating film 21801. For example, the contact hole is formed on the upper surface of the drain electrode of the transistor 20521. Next, a conductive layer 20508a is formed as a first pixel electrode over the insulating layer 20505 and the insulating layer 20507 by a photolithography method, an inkjet method, a printing method, or the like. Note that as the conductive layer 20508a, a transparent electrode that transmits light similar to the conductive layer 20508 can be used. Next, a conductive layer 20508b is formed as a second pixel electrode over the conductive layer 20508a by a photolithography method, an inkjet method, a printing method, or the like. Note that as the conductive layer 20508b, a reflective electrode that reflects light similar to the conductive layer 20508 can be used. Note that a region where the conductive layer 20508b is formed is referred to as a reflective region. In addition, among regions where the conductive layer 20508a is formed, a region where the conductive layer 20508b is not formed over the conductive layer 20508a is referred to as a transmissive region. Next, an insulating layer 20509 is formed as an alignment film over the insulating film 21801 and over the conductive layers 20508a and 20508b. Next, a liquid crystal layer 20510 is provided in a gap between the counter substrate 20515 provided with the insulating film 20514, the insulating film 20513, the conductive film 20512, the insulating film 20511, and the like and the substrate 20100.

74, the conductive layer 20508b is formed after the conductive layer 20508a is formed. However, as shown in FIG. 75, the conductive layer 20508b is formed after the conductive layer 20508b is formed.
a may be formed.

74 and 75, an insulating film for adjusting the liquid crystal layer 20510 (cell gap) is formed under the conductive layer 20508a and the conductive layer 20508b. But,
As shown in FIG. 76, the insulating film 22001 may be formed on the counter substrate 20515 side. The insulating film 22001 is an insulating film for adjusting the liquid crystal layer 20510 (cell gap), like the insulating film 21801.

Note that FIG. 76 illustrates the case where the insulating layer 20507 is formed as the planarization film; however, as illustrated in FIG. 77, the insulating layer 20507 may not be formed. In the case of FIG. 77, a conductive film 20506 can be used as the reflective pixel electrode. Of course, another conductive film may be formed as the reflective pixel electrode.

Note that the insulating film 22001 may be formed between the conductive film 20512 and the insulating film 20511, or may be formed between the insulating film 20511 and the liquid crystal layer 20510.

Next, FIG. 78 shows a cross-sectional view of a liquid crystal panel in the case where a polycrystalline semiconductor is used as a semiconductor film of a transistor in a transflective liquid crystal panel.

Note that the cross-sectional view of FIG. 78 is a cross-sectional view of a liquid crystal panel including a transistor using an inverted staggered channel etch structure. However, the transistor may be a top gate type or an inverted stagger type channel protection structure.

Note that FIG. 78 is similar to FIG. 78 until the conductive film 20506 is formed. Accordingly, a process and structure after the conductive film 20506 is formed will be described.

First, over the semiconductor layer 20502, over the insulating layer 20503 and the conductive film 20506, the liquid crystal layer 20
As a layer for reducing the thickness 510 (so-called cell gap), an insulating film 22201 is formed by a photolithography method, an inkjet method, a printing method, or the like. Note that the insulating film 22201 is preferably formed using an organic material because the insulating film 22201 preferably has good flatness and coverage. Note that an organic material may be formed over an inorganic material (silicon oxide, silicon nitride, silicon oxynitride) to have a multilayer structure. The insulating film 22
A contact hole is selectively formed in 201. For example, the contact hole is formed on the upper surface of the drain electrode of the transistor 20521. Next, the insulating layer 205
A conductive layer 20508a is formed as a first pixel electrode on 03 and the insulating film 22201 by a photolithography method, an inkjet method, a printing method, or the like. Next, a conductive layer 20508b is formed as a second pixel electrode over the conductive layer 20508a by a photolithography method, an inkjet method, a printing method, or the like. Note that the conductive layer 20508
A region where b is formed is referred to as a reflective region. In addition, among regions where the conductive layer 20508a is formed, a region where the conductive layer 20508b is not formed over the conductive layer 20508a is referred to as a transmissive region. Next, over the insulating film 22201, the conductive layer 20508a, and the conductive layer 20508b,
An insulating layer 20509 is formed as the alignment film. Next, the insulating film 20514 and the insulating film 2
0513, a counter substrate 20515 provided with a conductive film 20512, an insulating film 20511, and the like
A liquid crystal layer 20510 is provided in a gap between the substrate 20100 and the substrate 20100.

78, the conductive layer 20508b is formed after the conductive layer 20508a is formed. However, as shown in FIG. 79, the conductive layer 20508b is formed after the conductive layer 20508b is formed.
a may be formed.

78 and 79, an insulating film for adjusting the liquid crystal layer 20510 (cell gap) is formed under the conductive layer 20508a and the conductive layer 20508b. But,
As shown in FIG. 80, an insulating film 22001 may be formed on the counter substrate 20515 side. The insulating film 22001 is an insulating film for adjusting the liquid crystal layer 20510 (cell gap) similarly to the insulating film 22201.

Note that FIGS. 79 and 80 illustrate the case where the insulating layer 20507 is formed as the planarization film; however, as illustrated in FIG. 81, the insulating layer 20507 may not be formed. In the case of FIG. 81, a conductive film 20506 can be used as the reflective pixel electrode. Of course, another conductive film may be formed as the reflective pixel electrode.

61 and FIGS. 63 to 81, a pair of electrodes for applying a voltage to the liquid crystal layer 20510 (
An example is shown in which the conductive layer 20508 and the conductive film 20512) are formed over different substrates. However, the conductive film 20512 may be provided over the substrate 20100. Thus, an IPS (In-Plane-Switching) mode can be used as a liquid crystal driving method. Further, depending on the liquid crystal layer 20510, one or both of the two alignment films (the insulating layer 20509 and the insulating film 20511) can be omitted.

In FIGS. 61 and 63 to 81, a conductive layer 20508 (conductive layer 20508b) is formed as a reflective pixel electrode, but the shape of the conductive layer 20508 is preferably uneven. This is because the reflective pixel electrode is used for display by reflecting external light. This is because in order to efficiently use the external light that has entered the reflective electrode and increase the display luminance, it can be diffusely reflected by the reflective electrode. Note that a film below the conductive layer 20508 (the insulating layer 20
505, the insulating layer 20507, the insulating film 21801, the insulating film 22201, and the like) is uneven, so that the shape of the conductive layer 20508 is uneven.

Subsequently, a liquid crystal display device having the liquid crystal panel described in FIGS. 61 to 81 will be described with reference to FIG.

First, the liquid crystal display device illustrated in FIG. 82 is provided with a backlight unit 22601, a liquid crystal panel 22607, a layer 22608 including a first polarizer, and a layer 22609 including a second polarizer.

Note that the liquid crystal panel 22607 can be the same as that described in this embodiment. In addition, although the liquid crystal panel of this embodiment has been described with respect to an active structure in which a switching element is provided in each pixel, the liquid crystal panel in FIG. 82 may have a passive structure.

The structure of the backlight unit 22601 will be described. Backlight unit 226
01 is a diffusion plate 22602, a light guide plate 22603, a reflection plate 22604, a lamp reflector 2
2605 and a light source 22606 are provided. As the light source 22606, a cold cathode tube, a hot cathode tube, a light emitting diode, an inorganic EL, an organic EL, or the like is used.
6 has a function of emitting light as necessary. The lamp reflector 22605 includes a light source 2260.
6 has a function of efficiently guiding the fluorescence from the light guide plate 22603. The light guide plate 22603 has a function of totally reflecting fluorescence and guiding light to the entire surface. The diffusion plate 22602 has a function of reducing brightness unevenness. The reflection plate 22604 is directed downward from the light guide plate 22603 (the liquid crystal panel 2
It has a function of reflecting and reusing light leaked in the direction opposite to 2607).

In addition, the liquid crystal display device of this embodiment can improve the brightness of the screen of a liquid crystal panel by arrange | positioning a prism sheet between the diffuser plate 22602 and the layer 22609 containing a 2nd polarizer.

A control circuit for adjusting the luminance of the light source 22606 is connected to the backlight unit 22601. The luminance of the light source 22606 can be adjusted by supplying a signal from the control circuit.

A layer 22609 including a second polarizer is provided between the liquid crystal panel 22607 and the backlight unit 22601, and the liquid crystal panel 2 in the direction opposite to the backlight unit 22601 is provided.
A layer 22608 including a first polarizer is also provided in 2607.

Note that the layer 22608 including the first polarizer and the layer 22609 including the second polarizer are arranged so as to be in a crossed Nicol state when the liquid crystal element of the liquid crystal panel 22607 is driven in the TN mode. In addition, the layer 22608 including the first polarizer and the layer 22609 including the second polarizer are arranged so as to be in a crossed Nicol state when the liquid crystal element of the liquid crystal panel 22607 is driven in the VA mode. In addition, the layer 22608 including the first polarizer and the layer 226 including the second polarizer
When the liquid crystal element of the liquid crystal panel 22607 is driven in the IPS mode and the FFS mode, 09 may be arranged so as to be crossed Nicols or arranged so as to be parallel Nicols.

A retardation plate may be provided between both or one of the layer 22608 including the first polarizer and the layer 22609 including the second polarizer and the liquid crystal panel 22607.

As shown in FIG. 85, the layer 22609 containing the second polarizer and the backlight unit 2
By disposing a slit (grating) 22610 between 2601 and the liquid crystal display device of this embodiment, three-dimensional display can be performed.

A slit 22610 having an opening disposed on the backlight unit side transmits light incident from the light source in a stripe shape and allows the light to enter the display device. This slit 2261
With 0, parallax can be created in both eyes of the viewer on the viewer side, and the viewer sees only the pixels for the right eye in the right eye and only the pixels for the left eye in the left eye. Therefore, the viewer can see the three-dimensional display. That is, the light given a specific viewing angle by the slit 22610 passes through pixels corresponding to the right-eye image and the left-eye image,
The right-eye image and the left-eye image are separated into different viewing angles, and three-dimensional display is performed.

If an electronic device such as a television device or a mobile phone is manufactured using the liquid crystal display device in FIG. 85, an electronic device with high functionality and high image quality capable of three-dimensional display can be provided.

Next, a detailed configuration of the backlight will be described with reference to FIG. The backlight is provided in a liquid crystal display device as a backlight unit having a light source, and the light source is surrounded by a reflector so that the backlight unit efficiently scatters light.

As shown in FIG. 84 (A), the backlight unit 22852 is a cold cathode tube 2 as a light source.
2801 can be used. In addition, a lamp reflector 22832 can be provided in order to efficiently reflect light from the cold cathode tube 22801. The cold cathode tube 22801 is often used for a large display device. This is due to the intensity of the luminance from the cold cathode tube. Therefore, a backlight unit having a cold cathode tube can be used for a display of a personal computer.

As shown in FIG. 84B, the backlight unit 22852 can use a light-emitting diode 22802 (LED) as a light source. For example, light emitting diodes 22802 (W) that emit white light are arranged at predetermined intervals. Further, the light emitting diode 22802 (W) 22
In order to efficiently reflect light from 802, a lamp reflector 22832 can be provided.

As shown in FIG. 84 (C), the backlight unit 22852 has each color R as a light source.
GB light emitting diodes 22803, 22804, 22805 can be used. By using the light emitting diodes 22803, 22804, and 22805 for each color RGB, color reproducibility can be enhanced as compared with only the light emitting diode 22802 (W) that emits white. Further, in order to efficiently reflect the light from the light emitting diode, the lamp reflector 22 is used.
832 can be provided.

Further, as shown in FIG. 84D, each color RGB light emitting diode 2280 is used as a light source.
In the case of using 3, 22,804, 22805, it is not necessary to make the number and arrangement thereof the same.
For example, a plurality of colors with low emission intensity (for example, green) may be arranged.

Furthermore, the light emitting diode 22802 which emits white, and the light emitting diode 2280 of each color RGB
3, 22804, and 22805 may be used in combination.

Note that in the case of having RGB light emitting diodes, when the field sequential mode is applied, color display can be performed by sequentially turning on the RGB light emitting diodes according to time.

When a light-emitting diode is used, it has high luminance and is suitable for a large display device. Further, since the color purity of each of the RGB colors is good, the color reproducibility is superior to that of the cold cathode fluorescent lamp, and the arrangement area can be reduced. Therefore, the frame can be narrowed when applied to a small display device.

Further, the light source is not necessarily arranged as the backlight unit shown in FIG. For example, when a backlight having a light emitting diode is mounted on a large display device, the light emitting diode can be disposed on the back surface of the substrate. At this time, the light emitting diodes can maintain predetermined intervals, and the light emitting diodes of the respective colors can be arranged in order. The color reproducibility can be improved by the arrangement of the light emitting diodes.

Next, an example of a layer including a polarizer (also referred to as a polarizing plate or a polarizing film) is described with reference to FIG.

86 includes a protective film 23001 and a substrate film 23002.
, A PVA polarizing film 23003, a substrate film 23004, an adhesive layer 23005, and a release film 23006.

The PVA polarizing film 23003 has a function of generating light only in a certain vibration direction (linearly polarized light). Specifically, the PVA polarizing film 23003 includes molecules (polarizers) in which the electron density differs greatly in the vertical and horizontal directions. The PVA polarizing film 23003 can produce linearly polarized light by aligning the directions of molecules in which the electron density is greatly different in the vertical and horizontal directions.

As an example, the PVA polarizing film 23003 is made of polyvinyl alcohol (Poly V).
Inyl Alcohol) is doped with an iodine compound, and the PVA film is pulled in a certain direction, whereby a film in which iodine molecules are arranged in a certain direction can be obtained. And the light parallel to the long axis of an iodine molecule is absorbed by the iodine molecule. In addition, a dichroic dye may be used in place of iodine for high durability use and high heat resistance use. The dye is preferably used in liquid crystal display devices that require durability and heat resistance, such as in-vehicle LCDs and projector LCDs.

The PVA polarizing film 23003 is a film (substrate film 23002 which is a base material on both sides).
And the substrate film 3604), the reliability can be increased. The PVA polarizing film 23003 may be sandwiched between highly transparent and highly durable triacetylrose (TAC) films. In addition, a board | substrate film and a TAC film function as a protective layer of the polarizer which PVA polarizing film 23003 has.

One substrate film (substrate film 23004) has an adhesive layer 23005 attached to a glass substrate of a liquid crystal panel. Note that the pressure-sensitive adhesive layer 23005 is formed by applying a pressure-sensitive adhesive to a substrate film (substrate film 23004) on one side. The pressure-sensitive adhesive layer 23005 is provided with a release film 23006 (separate film).

The other substrate film (substrate film 23002) is provided with a protective film.

A hard coat scattering layer (anti-glare layer) may be provided on the surface of the polarizing film 23000. Since the hard coat scattering layer has fine irregularities formed on the surface by AG treatment and has an antiglare function for scattering external light, reflection of external light on the liquid crystal panel and surface reflection can be prevented.

Further, a plurality of optical thin film layers having different refractive indexes may be formed on the surface of the polarizing film 23000 (also referred to as anti-reflection treatment or AR treatment). The multilayered optical thin film layer having a plurality of refractive indexes can reduce the reflectance of the surface due to the light interference effect.

Next, the operation of each circuit included in the liquid crystal display device will be described with reference to FIG.

FIG. 83 shows a system block diagram of the pixel portion 22705 and the driver circuit portion 22708 of the display device.

The pixel portion 22705 includes a plurality of pixels, a signal line 22712 serving as each pixel, and the scanning line 22.
A switching element is provided in a region intersecting with 710. Application of a voltage for controlling the tilt of liquid crystal molecules can be controlled by the switching element. A structure in which switching elements are provided in each intersection region in this way is called an active type. The pixel portion of this embodiment mode is not limited to such an active type and may have a passive configuration. Since the passive type has no switching element in each pixel, the process is simple.

The driver circuit portion 22708 includes a control circuit 22702, a signal line driver circuit 22703, and a scanning line driver circuit 22704. A control circuit 22702 to which the video signal 22701 is input has a function of performing gradation control in accordance with display contents of the pixel portion 22705. Therefore, the control circuit 2
Reference numeral 2702 denotes a signal line driver circuit 22703 and a scan line driver circuit 22704 which are generated signals.
To enter. When a switching element is selected via the scanning line 22710 based on the scanning line driver circuit 22704, a voltage is applied to the pixel electrode in the selected intersection region. The value of this voltage is determined based on a signal input from the signal line driver circuit 22703 via the signal line.

Further, the control circuit 22702 generates a signal for controlling the power supplied to the lighting unit 22706, and the signal is input to the power source 22707 of the lighting unit 22706. The backlight unit described in the above embodiment can be used as the illumination unit. The illumination means includes a front light in addition to the backlight. The front light is a plate-like light unit that is mounted on the front side of the pixel portion and is composed of a light emitter and a light guide that illuminate the whole. Such illumination means can illuminate the pixel portion evenly with low power consumption.

As illustrated in FIG. 83B, the scan line driver circuit 22704 includes circuits that function as a shift register 22741, a level shifter 22742, and a buffer 22743. Signals such as a gate start pulse (GSP) and a gate clock signal (GCK) are input to the shift register 22741. Note that the scan line driver circuit in this embodiment is not limited to the structure illustrated in FIG.

As shown in FIG. 83C, the signal line driver circuit 22703 includes a shift register 22731.
, A first latch 22732, a second latch 22733, a level shifter 22734, and a circuit functioning as a buffer 22735. A circuit functioning as the buffer 22735 is a circuit having a function of amplifying a weak signal and includes an operational amplifier and the like. A signal such as a start pulse (SSP) is input to the level shifter 22734, and data (DATA) such as a video signal is input to the first latch 22732. The second latch 22733 has a latch (L
(AT) signal can be temporarily held and input to the pixel portion 22705 all at once. This is called line sequential driving. Therefore, if the pixel performs dot sequential driving instead of line sequential driving, the second
This latch can be dispensed with. In this manner, the signal line driver circuit of this embodiment mode is as shown in FIG.
The configuration is not limited to 3 (C).

Such a signal line driver circuit 22703, a scan line driver circuit 22704, and a pixel portion 22705 can be formed using semiconductor elements provided over the same substrate. The semiconductor element can be formed using a thin film transistor provided over a glass substrate. In this case, a crystalline semiconductor film is preferably applied to the semiconductor element. Since the crystalline semiconductor film has high electrical characteristics, particularly mobility, a circuit included in the driver circuit portion can be formed. Further, the signal line driving circuit 2
2703 and the scanning line driving circuit 22704 are integrated circuits (ICs).
It can also be mounted on a substrate using a chip. In this case, an amorphous semiconductor film can be applied to the semiconductor element in the pixel portion.

Here, the liquid crystal display module of this embodiment will be described with reference to FIGS. 87 (A) and 87 (B).

FIG. 87A illustrates an example of a liquid crystal display module, which includes a TFT substrate 23100 and a counter substrate 23.
101 is fixed by a sealant 23102, and a pixel portion 23103 including a TFT or the like therebetween
A liquid crystal layer 23104 is provided to form a display region. The colored layer 23105 is necessary for color display. In the case of the RGB method, a colored layer corresponding to each color of red, green, and blue is provided corresponding to each pixel. On the outside of the TFT substrate 23100 and the counter substrate 23101, a layer 23106 including a first polarizer, a layer 23107 including a second polarizer, and a diffusion plate 23113
Is arranged. The light source is composed of a cold cathode tube 23110 and a reflection plate 23111. The circuit board 23112 is connected to the TFT substrate 23100 by a flexible wiring board 23109, and an external circuit such as a control circuit or a power supply circuit is incorporated.

A layer 2310 including a second polarizer is provided between the TFT substrate 23100 and the backlight as the light source.
7 is stacked, and the counter substrate 23101 is also provided with a layer 23106 including the first polarizer. On the other hand, the absorption axis of the layer 23107 including the second polarizer and the absorption axis of the layer 23106 including the first polarizer provided on the viewing side are arranged to be crossed Nicols.

A layer 23107 including a stacked second polarizer and a layer 2310 including a stacked first polarizer
6 is bonded to the TFT substrate 23100 and the counter substrate 23101. Moreover, you may laminate | stack in the state which had the phase difference plate between the layer containing the laminated | stacked polarizer, and a board | substrate. Further, if necessary, the layer 23106 including the first polarizer on the viewing side may be subjected to an antireflection treatment.

The liquid crystal display module has TN (Twisted Nematic) mode, IPS (I
n-Plane-Switching) mode, FFS (Fringe Field S)
switching) mode, MVA (Multi-domain Vertical A)
license) mode, PVA (Patterned Vertical Align)
nment), ASM (Axial Symmetrical Aligned Mic)
ro-cell) mode, OCB (Optical Compensated Wire)
fringe) mode, FLC (Ferroelectric Liquid C)
crystal) mode, AFLC (Antiferroelectric Liquid)
Crystal), PDLC (Polymer Dispersed Liquid)
Crystal) mode or the like can be used.

87B is an example in which the OCB mode is applied to the liquid crystal display module of FIG. 87A, and is an FS-LCD (Field sequential-LCD). FS-L
The CD emits red light, green light, and blue light in one frame period, and can display images by combining images using time division. Further, since each light emission is performed by a light emitting diode or a cold cathode tube, a color filter is unnecessary. Therefore, it is not necessary to arrange the color filters of the three primary colors and limit the display area of each color, and it is possible to display all three colors in any area. On the other hand, since the three colors emit light in one frame period, a high-speed response of the liquid crystal is required. By applying the FLC mode and the OCB mode using the FS method to the display device of this embodiment mode, a high-performance and high-quality display device or a liquid crystal television device can be completed.

The liquid crystal layer in the OCB mode has a so-called π cell structure. The π cell structure is a structure in which the pretilt angles of liquid crystal molecules are aligned in a plane-symmetric relationship with respect to the center plane between the active matrix substrate and the counter substrate. The alignment state of the π cell structure is splay alignment when no voltage is applied between the substrates, and shifts to bend alignment when a voltage is applied. This bend orientation is white. When a voltage is further applied, the bend-aligned liquid crystal molecules are aligned perpendicularly to both substrates, and light is not transmitted. In the OCB mode, high-speed response that is about 10 times faster than the conventional TN mode can be realized.

In addition, as a mode corresponding to the FS system, a ferroelectric liquid crystal (FLC: Fe
HV (Half V) using roelectric Liquid Crystal
) -FLC, SS (Surface Stabilized) -FLC, etc. can also be used.

Further, by narrowing the cell gap of the liquid crystal display module, the optical response speed of the liquid crystal display module can be increased. The speed can also be increased by reducing the viscosity of the liquid crystal material. The increase in speed is more effective when the pixel pitch of the pixel area of the TN mode liquid crystal display module is 30 μm or less. In addition, the speed may be increased by using an overdrive that increases (or lowers) the voltage applied to the liquid crystal layer for a moment from the original voltage.

The liquid crystal display module in FIG. 87B is a transmissive liquid crystal display module, and is provided with a red light source 23190a, a green light source 23190b, and a blue light source 23190c as light sources. The light source is provided with a control unit 23199 for controlling on / off of the red light source 23190a, the green light source 23190b, and the blue light source 23190c. Control unit 2319
9 controls the light emission of each color, the light is incident on the liquid crystal, the image is synthesized using time division, and color display is performed.

Note that this embodiment can be freely combined with any of the other embodiments.

In addition, the content of each figure in this embodiment can be implemented in combination freely with the content of other figures.

(Embodiment 10)
In this embodiment, a driving method of a display device that can implement this embodiment will be described. In particular, a method for driving a liquid crystal display device will be described.

First, overdrive driving will be described with reference to FIG. (A) in FIG.
It shows the time change of the output luminance with respect to the input voltage of the display element. The time change of the output luminance of the display element with respect to the input voltage 30121 represented by the broken line is the same as the output luminance 30123 similarly represented by the broken line. That is, the voltage for obtaining the target output luminance Lo is Vi, but when Vi is input as it is as the input voltage, it takes time corresponding to the response speed of the element to reach the target output luminance Lo. End up.

Overdrive drive is a technique for increasing the response speed. Specifically, first,
This is a method in which Vo, which is a voltage higher than Vi, is applied to the element for a certain period of time to increase the response speed of the output luminance, and after returning it to the target output luminance Lo, the input voltage is returned to Vi.
At this time, the input voltage is represented as an input voltage 30122, and the output luminance is represented as an output luminance 30124. In the graph of the output luminance 30124, the time to reach the target luminance Lo is shorter than that of the graph of the output luminance 30123.

In FIG. 88A, the case where the output luminance changes positively with respect to the input voltage has been described. However, the present embodiment includes the case where the output luminance changes negatively with respect to the input voltage. It is out.

A circuit for realizing such driving will be described with reference to FIGS. 88B and 88C. First, the case where the input video signal 30131 is an analog value (may be a discrete value) and the output video signal 30132 is an analog value signal will be described with reference to FIG. The overdrive circuit shown in FIG. 88B includes an encoding circuit 30101, a frame memory 30102, a correction circuit 30103, and a DA conversion circuit 30.
104.

The input video signal 30131 is first input to the encoding circuit 30101 and encoded. That is, the analog signal is converted into a digital signal having an appropriate number of bits. Thereafter, the converted digital signal is input to the frame memory 30102 and the correction circuit 30103, respectively. The video signal of the previous frame held in the frame memory 30102 is also input to the correction circuit 30103 at the same time. Then, the correction circuit 30103 outputs a corrected video signal according to a numerical table prepared in advance from the video signal of the frame and the video signal of the previous frame. At this time, an output switching signal 30133 may be input to the correction circuit 30103 so that the corrected video signal and the video signal of the frame can be switched and output. Next, the corrected video signal or the video signal of the frame is input to the DA conversion circuit 30104. Then, an output video signal 30132 which is an analog signal having a value according to the corrected video signal or the video signal of the frame is output. In this way, overdrive driving can be realized.

Next, a case where the input video signal 30131 takes a digital value and the output video signal 30132 also takes a digital value will be described with reference to FIG. FIG.
8C, the overdrive circuit includes a frame memory 30112 and a correction circuit 301.
13.

The input video signal 30131 is a digital signal. First, the frame memory 30112,
Input to the correction circuit 30113. The video signal of the previous frame held in the frame memory 30112 is also input to the correction circuit 30113 at the same time. Then, the correction circuit 30113 outputs a corrected video signal according to a numerical table prepared in advance from the video signal of the frame and the video signal of the previous frame. At this time, an output switching signal 30133 may be input to the correction circuit 30113 so that the corrected video signal and the video signal of the frame can be switched and output. In this way, overdrive driving can be realized.

Note that the overdrive circuit in this embodiment includes a case where the input video signal 30131 is an analog signal and the output video signal 30132 is a digital signal. At this time,
The DA converter circuit 30104 may be omitted from the circuit shown in FIG. The overdrive circuit in this embodiment includes a case where the input video signal 30131 is a digital signal and the output video signal 30132 is an analog signal. At this time, the encoding circuit 30101 may be omitted from the circuit shown in FIG.

Next, driving for manipulating the potential of the common line will be described with reference to FIG. In (
A) shows a plurality of pixel circuits when one common line is arranged for one scanning line in a display device using a capacitive display element such as a liquid crystal element. FIG. The pixel circuit illustrated in FIG. 89A includes a transistor 30201, an auxiliary capacitor 30202, a display element 30203, a video signal line 30204, a scanning line 30205, and a common line 30206.

The gate electrode of the transistor 30201 is electrically connected to the scan line 30205, one of the source electrode and the drain electrode of the transistor 30201 is electrically connected to the video signal line 30204, and the other of the source electrode and the drain electrode of the transistor 30201 Are electrically connected to one electrode of the auxiliary capacitor 30202 and one electrode of the display element 30203. The other electrode of the auxiliary capacitor 30202 is electrically connected to the common line 30206.

First, since the transistor 30201 is turned on in the pixel selected by the scanning line 30205, a voltage corresponding to the video signal is applied to the display element 30203 and the auxiliary capacitor 30202 through the video signal line 30204, respectively. At this time, the video signal is the common line 3.
If the lowest gradation is displayed for all the pixels connected to 0206, or if the highest gradation is displayed for all the pixels connected to the common line 30206, the pixel It is not necessary to write a video signal via the video signal line 30204 respectively.
Instead of writing a video signal through the video signal line 30204, the voltage applied to the display element 30203 can be changed by moving the potential of the common line 30206.

Next, FIG. 89B shows a display device using a display element having a capacitive property such as a liquid crystal element when two common lines are arranged for one scanning line. It is a figure showing a plurality of pixel circuits. The pixel circuit illustrated in FIG. 89B includes a transistor 30211, an auxiliary capacitor 30212, a display element 30213, a video signal line 30214, a scanning line 30215, a first common line 30216, and a second common line 30217. .

The gate electrode of the transistor 30211 is electrically connected to the scan line 30215, one of the source electrode and the drain electrode of the transistor 30211 is electrically connected to the video signal line 30214, and the other of the source electrode and the drain electrode of the transistor 30211 Is electrically connected to one electrode of the auxiliary capacitor 30212 and one electrode of the display element 30213. In addition, the other electrode of the auxiliary capacitor 30212 is electrically connected to the first common line 30216. In the pixel adjacent to the pixel, the auxiliary capacitor 30212 is used.
The other electrode is electrically connected to the second common line 30217.

The pixel circuit illustrated in FIG. 89B has a small number of pixels electrically connected to one common line; therefore, instead of writing a video signal through the video signal line 30214, the first common line 30216 is used. Alternatively, the display element 30213 is moved by moving the potential of the second common line 30217.
The frequency at which the voltage applied to can be changed is significantly increased. Further, source inversion driving or dot inversion driving is possible. By source inversion driving or dot inversion driving, flicker can be suppressed while improving the reliability of the element.

Next, the scanning backlight will be described with reference to FIG. FIG. 90A is a diagram showing a scanning backlight in which cold cathode fluorescent lamps are juxtaposed. The scanning backlight shown in FIG. 90A includes a diffusion plate 30301 and N cold cathode fluorescent lamps 30302-1 to 30302-N. N cold cathode tubes 30302-1 to 30302 -N are juxtaposed behind the diffuser plate 30301, so that the N cold cathode tubes 30302-1 to 30302 -N scan with varying luminance. Can do.

A change in luminance of each cold cathode tube during scanning will be described with reference to FIG. First, the luminance of the cold cathode fluorescent lamp 30302-1 is changed for a certain time. Then, after that, the cold cathode tube 30
The luminance of the cold cathode fluorescent lamp 30302-2 arranged next to 302-1 is changed for the same time. In this way, the luminance is changed in order from the cold cathode fluorescent lamps 30302-1 to 30302-N. In FIG. 90C, the luminance to be changed for a certain time is smaller than the original luminance, but may be larger than the original luminance. Also, cold cathode fluorescent lamps 30302-1 to 3030
Although scanning up to 2-N is performed, scanning from cold cathode fluorescent lamps 30302-N to 30302-1 may be performed in the reverse direction.

By driving as shown in FIG. 90, the average luminance of the backlight can be reduced. Therefore, the power consumption of the backlight, which accounts for most of the power consumption of the liquid crystal display device, can be reduced.

An LED may be used as the light source of the scanning backlight. The scanning backlight in that case is as shown in FIG. The scanning backlight shown in FIG. 90B includes a diffusion plate 30311 and light sources 30312-1 to 30312 -N in which LEDs are juxtaposed. When the LED is used as the light source of the scanning backlight, the backlight is thin,
There is an advantage that can be lightened. Further, there is an advantage that the color reproduction range can be expanded. Further, LEs juxtaposed on each of the light sources 30312-1 to 30312 -N juxtaposed with LEDs.
Since D can also be scanned in the same manner, it can also be a dot scanning backlight.
If the point scanning type is adopted, the image quality of the moving image can be further improved.

Note that even when an LED is used as the light source of the backlight, it can be driven with the luminance changed as shown in FIG.

Next, high frequency driving will be described with reference to FIG. 91A is a diagram when one image and one intermediate image are displayed in one frame period 30400. FIG. 3040
1 is an image of the frame, 30402 is an intermediate image of the frame, 30403 is an image of the next frame, and 30404 is an intermediate image of the next frame.

Note that the intermediate image 30402 of the frame may be an image created based on the video signals of the frame and the next frame. Further, the intermediate image 30402 of the frame may be an image created from the image 30401 of the frame. Further, the intermediate image 30402 of the frame may be a black image. By doing so, the image quality of the moving image of the hold type display device can be improved. In the case where one image and one intermediate image are displayed in one frame period 30400, there is an advantage that consistency with the frame rate of the video signal can be easily obtained and the image processing circuit is not complicated.

FIG. 91B is a diagram when one image and two intermediate images are displayed in a period in which two one-frame periods 30400 are continuous (two-frame periods). 30411 is an image of the frame, 30412 is an intermediate image of the frame, 30413 is an intermediate image of the next frame, 3
0414 is an image of the next frame.

Note that the intermediate image 30412 of the frame and the intermediate image 30413 of the next frame may be images created based on the video signals of the frame, the next frame, and the next frame. The intermediate image 30412 of the frame and the intermediate image 30413 of the next frame are
A black image may be used. When one image and two intermediate images are displayed in two frame periods, there is an advantage that the image quality of the moving image can be effectively improved without significantly increasing the operating frequency of the peripheral drive circuit.

Note that this embodiment can be freely combined with any of the other embodiments.

In addition, the content of each figure in this embodiment can be implemented in combination freely with the content of other figures.

(Embodiment 11)
In this embodiment mode, a pixel structure of a display device in which this embodiment mode can be implemented will be described. In particular, a pixel structure of a display device using an organic EL element will be described.

FIG. 92A shows a layout example of an element of a pixel having two TFTs in one pixel.
FIG. 92B shows a cross-sectional view of a portion indicated by XX ′ in FIG.

As shown in FIG. 92A, the pixel in this embodiment includes a first TFT 60105,
First wiring 60106, second wiring 60107, second TFT 60108, third wiring 6
0111, counter electrode 60112, capacitor 60113, pixel electrode 60115, partition wall 60
116, an organic conductor film 60117, an organic thin film 60118, and a substrate 60119 may be included. Note that the first TFT 60105 is a switching TFT, and the first wiring 601 is used.
06 is a gate signal line, and the second wiring 60107 is a source signal line.
60108 is preferably used as a driving TFT, and the third wiring 60111 is preferably used as a current supply line.

As shown in FIG. 92A, the gate electrode of the first TFT 60105 is the first wiring 60.
106, one of the source electrode and the drain electrode of the first TFT 60105 is electrically connected to the second wiring 60107, and the other of the source electrode and the drain electrode of the first TFT 60105 is the second electrode It is preferable that the gate electrode of the TFT 60108 and one electrode of the capacitor 60113 be electrically connected. The first TFT
The gate electrode 60105 may be composed of a plurality of gate electrodes as shown in FIG. Thus, leakage current in the off state of the first TFT 60105 can be reduced.

One of the source electrode and the drain electrode of the second TFT 60108 is connected to the third wiring 6
It is preferable that the other of the source electrode and the drain electrode of the second TFT 60108 be electrically connected to the pixel electrode 60115. Thus, the current flowing through the pixel electrode 60115 can be controlled by the second TFT 60108.

An organic conductor film 60117 is provided on the pixel electrode 60115, and the organic thin film 601 is further provided.
18 (organic compound layer) may be provided. A counter electrode 60112 may be provided over the organic thin film 60118 (organic compound layer). Note that the counter electrode 60112 may be formed in a solid form so as to be commonly connected to all the pixels, or may be formed in a pattern using a shadow mask or the like.

Light emitted from the organic thin film 60118 (organic compound layer) is transmitted through either the pixel electrode 60115 or the counter electrode 60112. At this time, in FIG. 92B, a case where light is emitted to the pixel electrode side, that is, a side where a TFT or the like is formed is called bottom emission, and a case where light is emitted to the counter electrode side is called top emission.

In the case of bottom emission, the pixel electrode 60115 is preferably formed using a transparent conductive film.
Conversely, in the case of top emission, the counter electrode 60112 is preferably formed using a transparent conductive film.

Further, in a color display light emitting device, EL elements having emission colors of R, G, and B may be applied separately, or a single color EL element may be applied in a solid form, and R may be applied by a color filter.
-G and B emission may be obtained.

Note that the configuration illustrated in FIG. 92 is merely an example, and various configurations other than the configuration illustrated in FIG. 92 can be taken with respect to the pixel layout, the cross-sectional configuration, the stacking order of the electrodes of the EL element, and the like. For the light emitting layer, various elements such as a crystalline element such as an LED and an element composed of an inorganic thin film can be used in addition to the element composed of the illustrated organic thin film.

Next, a layout example of a pixel element having three TFTs in one pixel will be described with reference to FIG. FIG. 93B shows a cross-sectional view of a portion indicated by XX ′ in FIG.

93A, the pixel in this embodiment includes a substrate 60200, a first wiring 60201, a second wiring 60202, a third wiring 60203, a fourth wiring 60204, a first TFT 60205, Second TFT 60206, third TFT 60207, pixel electrode 6
0208, partition wall 60211, organic conductor film 60212, organic thin film 60213, counter electrode 6
0214, may be included. Note that the first wiring 60201 is a source signal line, the second wiring 60202 is a writing gate signal line, the third wiring 60203 is an erasing gate signal line, and the fourth wiring 60204 is a current supply line. The first TFT 60205 is used as a switching TFT, the second TFT 60206 is used as an erasing TFT, and a third TF is used.
T60207 is preferably used as a driving TFT.

As shown in FIG. 93A, the gate electrode of the first TFT 60205 is the second wiring 602.
02, one of the source and drain electrodes of the first TFT 60205 is electrically connected to the first wiring 60201, and the other of the source and drain electrodes of the first TFT 60205 is third. It is preferable that the TFT 60207 is electrically connected to the gate electrode. Note that the gate electrode of the first TFT 60205 may include a plurality of gate electrodes as illustrated in FIG. Thus, leakage current in the off state of the first TFT 60205 can be reduced.

The gate electrode of the second TFT 60206 is electrically connected to the third wiring 60203, and one of the source electrode and the drain electrode of the second TFT 60206 is connected to the fourth wiring 60.
204, and the other of the source electrode and the drain electrode of the second TFT 60206 is preferably electrically connected to the gate electrode of the third TFT 60207. Note that the gate electrode of the second TFT 60206 may include a plurality of gate electrodes as illustrated in FIG. Thus, leakage current in the off state of the second TFT 60206 can be reduced.

One of the source electrode and the drain electrode of the third TFT 60207 is connected to the fourth wiring 6
[0204] The other of the source electrode and the drain electrode of the third TFT 60207 is preferably electrically connected to the pixel electrode 60208. Thus, the current flowing through the pixel electrode 60208 can be controlled by the third TFT 60207.

An organic conductor film 60212 is provided on the pixel electrode 60208, and an organic thin film 602 is further provided.
13 (organic compound layer) may be provided. A counter electrode 60214 may be provided over the organic thin film 60213 (organic compound layer). Note that the counter electrode 60214 may be formed in a solid form so as to be commonly connected to all pixels, or may be formed in a pattern using a shadow mask or the like.

Light emitted from the organic thin film 60213 (organic compound layer) is transmitted through either the pixel electrode 60208 or the counter electrode 60214. At this time, in FIG. 93B, a case where light is emitted to the pixel electrode side, that is, a side where a TFT or the like is formed is called bottom emission, and a case where light is emitted to the counter electrode side is called top emission.

In the case of bottom emission, the pixel electrode 60208 is preferably formed using a transparent conductive film.
Conversely, in the case of top emission, the counter electrode 60214 is preferably formed using a transparent conductive film.

Further, in a color display light emitting device, EL elements having emission colors of R, G, and B may be applied separately, or a single color EL element may be applied in a solid form, and R may be applied by a color filter.
, G and B light emission may be obtained.

Note that the configuration illustrated in FIG. 93 is merely an example, and various configurations other than the configuration illustrated in FIG. 93 can be employed with respect to the pixel layout, the cross-sectional configuration, the stacking order of the electrodes of the EL element, and the like. For the light emitting layer, various elements such as a crystalline element such as an LED and an element composed of an inorganic thin film can be used in addition to the element composed of the illustrated organic thin film.

Next, a layout example of a pixel element having four TFTs in one pixel will be described with reference to FIG. In addition, FIG. 94B shows a cross-sectional view of a portion indicated by XX ′ in FIG.

As shown in FIG. 94A, a pixel in this embodiment includes a substrate 60300, a first wiring 60301, a second wiring 60302, a third wiring 60303, a fourth wiring 60304, a first TFT 60305, 2nd TFT60306, 3rd TFT60307, 4th TF
T60308, a pixel electrode 60309, a fifth wiring 60311, a sixth wiring 60312, a partition wall 60321, an organic conductor film 60322, an organic thin film 60323, and a counter electrode 60324 may be included. Note that the first wiring 60301 serves as a source signal line, and the second wiring 60
302 is a writing gate signal line, the third wiring 60303 is an erasing gate signal line, the fourth wiring 60304 is a reverse bias signal line, the first TFT 60305 is a switching TFT, The TFT 60306 is a third TF as an erasing TFT.
T60307 is a driving TFT, and the fourth TFT 60308 is a reverse bias TFT.
The fifth wiring 60311 is preferably used as a current supply line, and the sixth wiring 60312 is preferably used as a reverse bias power supply line.

As shown in FIG. 94A, the gate electrode of the first TFT 60305 is the second wiring 603.
02, one of the source electrode and the drain electrode of the first TFT 60305 is electrically connected to the first wiring 60301, and the other of the source electrode and the drain electrode of the first TFT 60305 is the third electrode It is preferable that the TFT 60307 is electrically connected to the gate electrode. Note that the gate electrode of the first TFT 60305 may include a plurality of gate electrodes as illustrated in FIG. Thus, leakage current in the off state of the first TFT 60305 can be reduced.

The gate electrode of the second TFT 60306 is electrically connected to the third wiring 60303, and one of the source electrode and the drain electrode of the second TFT 60306 is connected to the fifth wiring 60311.
The other of the source electrode and the drain electrode of the second TFT 60306 is preferably electrically connected to the gate electrode of the third TFT 60307. Note that the gate electrode of the second TFT 60306 may include a plurality of gate electrodes as illustrated in FIG. Thus, leakage current in the off state of the second TFT 60306 can be reduced.

One of the source electrode and the drain electrode of the third TFT 60307 is connected to the fifth wiring 6031.
1, and the other of the source electrode and the drain electrode of the third TFT 60307 is preferably electrically connected to the pixel electrode 60309. Thus, the current flowing through the pixel electrode 60309 can be controlled by the third TFT 60307.

The gate electrode of the fourth TFT 60308 is electrically connected to the fourth wiring 60304, and one of the source electrode and the drain electrode of the fourth TFT 60308 is the sixth wiring 60312.
The other of the source electrode and the drain electrode of the fourth TFT 60308 is preferably electrically connected to the pixel electrode 60309. Thus, the potential of the pixel electrode 60309 can be controlled by the fourth TFT 60308.
A reverse bias can be applied to the organic conductor film 60322 and the organic thin film 60323. By applying a reverse bias to a light-emitting element including the organic conductor film 60322 and the organic thin film 60323, the reliability of the light-emitting element can be greatly improved.

For example, a light-emitting element whose luminance half-life is about 400 hours when driven by a DC voltage (3.65 V) is an AC voltage (forward bias: 3.7 V, reverse bias: 1.7 V, duty 50%, It is known that when driven at an AC frequency of 60 Hz, the luminance half-life is 700 hours or more.

An organic conductor film 60322 is provided on the pixel electrode 60309, and an organic thin film 603 is further provided.
23 (organic compound layer) may be provided. A counter electrode 60324 may be provided over the organic thin film 60323 (organic compound layer). Note that the counter electrode 60324 may be formed in a solid form so as to be commonly connected to all the pixels, or may be patterned using a shadow mask or the like.

Light emitted from the organic thin film 60323 (organic compound layer) is transmitted through either the pixel electrode 60309 or the counter electrode 60324. In this case, in FIG. 94B, a case where light is emitted to the pixel electrode side, that is, a side where a TFT or the like is formed is called bottom emission, and a case where light is emitted to the counter electrode side is called top emission.

In the case of bottom emission, the pixel electrode 60309 is preferably formed using a transparent conductive film.
On the other hand, in the case of top emission, the counter electrode 60324 is preferably formed using a transparent conductive film.

In a light emitting device for color display, EL elements having emission colors of R, G, and B may be separately applied, or a monochrome EL element is applied in a solid form, and R, G,
B light emission may be obtained.

The configuration illustrated in FIG. 94 is merely an example, and various configurations other than the configuration illustrated in FIG. 94 can be taken with respect to the pixel layout, the cross-sectional configuration, the stacking order of the electrodes of the EL element, and the like. For the light emitting layer, various elements such as a crystalline element such as an LED and an element composed of an inorganic thin film can be used in addition to the element composed of the illustrated organic thin film.

Next, a structure of an EL element that can be applied to this embodiment mode is described.

The EL element applicable to this embodiment includes a hole injection layer made of a hole injection material, a hole transport layer made of a hole transport material, a light emitting layer made of a light emitting material, an electron transport layer made of an electron transport material, an electron The electron injection layer made of an injection material is not a layered structure that is clearly distinguished, and a plurality of materials such as a hole injection material, a hole transport material, a light emitting material, an electron transport material, and an electron injection material are used. A structure having a layer in which materials are mixed (mixed layer) (hereinafter referred to as a mixed junction type EL element) may be used.

A schematic diagram showing the structure of a mixed junction type EL element is shown in FIG. In FIG. 95, 6040
Reference numeral 1 denotes an anode of the EL element. Reference numeral 60402 denotes a cathode of the EL element. A layer sandwiched between the anode 60401 and the cathode 60402 corresponds to an EL layer.

95A, the EL layer includes a hole transport region 60403 made of a hole transport material and an electron transport region 60404 made of an electron transport material, and the hole transport region 60403 is more anode than the electron transport region 60404. And a mixed region 60 including both the hole transport material and the electron transport material between the hole transport region 60403 and the electron transport region 60404.
405 may be provided.

Note that in the direction from the anode 60401 to the cathode 60402, the concentration of the hole transport material in the mixed region 60405 may decrease, and the concentration of the electron transport material in the mixed region 60405 may increase.

Note that in the above structure, the hole transport region 60403 made of only the hole transport material does not exist, and the concentration ratio of each functional material changes in the mixed region 60405 including both the hole transport material and the electron transport material. It may be configured (having a concentration gradient). Further, a hole transport region 60403 made of only a hole transport material and an electron transport region 60404 made of only an electron transport material.
The ratio of the concentration of each functional material may change (has a concentration gradient) inside the mixed region 60405 including both the hole transport material and the electron transport material. The concentration ratio may be changed depending on the distance from the anode or the cathode. Further, the change in the concentration ratio may be continuous. The method of setting the concentration gradient can be set freely.

In the mixed region 60405, a region 60406 to which a light emitting material is added is provided. The emission color of the EL element can be controlled by the light emitting material. Further, carriers can be trapped by the light emitting material. As the light emitting material, various fluorescent dyes can be used in addition to a metal complex including a quinoline skeleton, a metal complex including a benzoxador skeleton, a metal complex including a benzothiazol skeleton, and the like. By adding these light emitting materials, the light emission color of the EL element can be controlled.

As the anode 60401, an electrode material having a high work function is preferably used in order to inject holes efficiently. For example, a transparent electrode such as tin-doped indium oxide (ITO), zinc-doped indium oxide (IZO), ZnO, SnO ₂ , or In ₂ O ₃ can be used. Further, the anode 60401 may be an opaque metal material if it is not necessary to have translucency.

An aromatic amine compound or the like can be used as the hole transport material.

As an electron transport material, a quinoline derivative, a metal complex having 8-quinolinol or a derivative thereof as a ligand (particularly, tris (8-quinolinolite) aluminum (Alq ₃ )) or the like can be used.

As the cathode 60402, an electrode material having a low work function is preferably used in order to inject electrons efficiently. A single metal such as aluminum, indium, magnesium, silver, calcium, barium, or lithium can be used. Moreover, the alloy of these metals may be sufficient and the alloy of these metals and another metal may be sufficient.

FIG. 95B is a schematic diagram of an EL element having a structure different from that in FIG. Note that FIG.
The same parts as in A) are denoted by the same reference numerals, and description thereof is omitted.

In FIG. 95B, there is no region to which the light-emitting material is added. However, the electron transport region 604
As a material added to 04, a material using both electron transporting property and light emitting property (electron transporting light emitting material), for example, tris (8-quinolinolite) aluminum (Alq ₃ ) can be used for light emission.

Alternatively, as a material added to the hole-transport region 60403, a material having both hole-transport property and light-emitting property (hole-transport light-emitting material) may be used.

FIG. 95C is a schematic diagram of an EL element having a structure different from those in FIGS. 95A and 95B. Note that the same portions as those in FIGS. 95A and 95B are denoted by the same reference numerals, and description thereof is omitted.

In FIG. 95C, a hole blocking material having a large energy difference between the highest occupied molecular orbital and the lowest occupied molecular orbital compared to the hole transporting material has a region 60407 added in the mixed region 60405. . The region 60407 to which the hole blocking material is added is arranged closer to the cathode 60402 than the region 60406 to which the light emitting material is added in the mixed region 60405, so that the carrier recombination rate can be increased and the light emission efficiency can be increased. it can. The above-described structure in which the region 60407 to which a hole blocking material is added is provided is particularly effective in an EL element using light emission (phosphorescence) by triple photoexcitons.

FIG. 9 is a schematic diagram of an EL element having a structure different from those in FIGS. 95 (A), 95 (B), and 95 (C).
5 (D). Note that the same portions as those in FIGS. 95A, 95B, and 95C are denoted by the same reference numerals, and description thereof is omitted.

In FIG. 95D, an electron blocking material having a larger energy difference between the highest occupied molecular orbital and the lowest occupied molecular orbital than the electron transporting material has a region 60408 added in the mixed region 60405. By disposing the region 60408 to which the electron blocking material is added closer to the anode 60401 than the region 60406 to which the light emitting material is added in the mixed region 60405, the carrier recombination rate can be increased and the light emission efficiency can be increased. . The structure provided with the region 60408 to which the electron blocking material is added is particularly effective in an EL element using light emission (phosphorescence) by triple photoexcitons.

FIG. 95E is a schematic diagram illustrating a structure of a mixed-junction EL element different from those in FIGS. 95A, 95B, 95C, and 95D. FIG. 95E illustrates an example of a structure including a region 60409 to which a metal material is added in the portion of the EL layer in contact with the electrode of the EL element. In FIG. 95E, the same portions as those in FIGS. 95A to 95D are denoted by the same reference numerals and description thereof is omitted. The structure shown in FIG. 95E is, for example, MgA as the cathode 60402.
A configuration may be employed in which a region 60409 to which an Al (aluminum) alloy is added is used in a region in contact with the cathode 60402 of the electron transport region 60404 to which an electron transport material is added using g (Mg—Ag alloy). With the above structure, oxidation of the cathode can be prevented and the efficiency of electron injection from the cathode can be increased. Thus, the life of the mixed junction type EL element can be extended. Further, the drive voltage can be lowered.

As a method of manufacturing the mixed junction type EL element, a co-evaporation method or the like can be used.

In the mixed junction EL element as shown in FIGS. 95A to 95E, there is no clear layer interface, and charge accumulation can be reduced. In this way, the lifetime can be extended. Further, the drive voltage can be lowered.

The structures shown in FIGS. 95A to 95E can be implemented in any combination.

The structure of the mixed junction type EL element is not limited to this. A known configuration can be used freely.

The organic material constituting the EL layer of the EL element may be a low molecular material or a high molecular material. Moreover, you may use both of these materials. When a low molecular material is used as the organic compound material, the film can be formed by an evaporation method. On the other hand, in the case where a polymer material is used for the EL layer, the polymer material can be dissolved in a solvent and formed into a film by a spin coating method or an inkjet method.

The EL layer may be made of a medium molecular material. In the present specification, the medium molecular organic light-emitting material refers to an organic light-emitting material having no sublimation property and having a degree of polymerization of about 20 or less. In the case where a medium molecular material is used for the EL layer, it can be formed by an inkjet method or the like.

A low molecular material, a high molecular material, and a medium molecular material may be used in combination.

The EL element may be either one that uses light emission (fluorescence) from singlet excitons or one that uses light emission (phosphorescence) from triplet excitons.

Next, a vapor deposition apparatus for manufacturing a display device to which this embodiment can be applied will be described with reference to the drawings.

A display device to which this embodiment mode can be applied may be manufactured by forming an EL layer. The EL layer
It is formed including at least part of a material that exhibits electroluminescence. The EL layer may be composed of a plurality of layers having different functions. In that case, the EL layer may be configured by combining layers having different functions called a hole injecting and transporting layer, a light emitting layer, and an electron injecting and transporting layer.

FIG. 96 shows a configuration of a vapor deposition apparatus for forming an EL layer on an element substrate over which a transistor is formed.
Shown in In this vapor deposition apparatus, a plurality of processing chambers are connected to transfer chambers 60560 and 60561. The processing chamber includes a load chamber 60562 for supplying a substrate and an unload chamber 605 for recovering the substrate.
63, in addition, a heat treatment chamber 60568, a plasma treatment chamber 60572, a film formation treatment chamber 60569 to 60575 for depositing an EL material, and a film formation for forming a conductive film containing aluminum or aluminum as a main component as one electrode of the EL element. A processing chamber 60576 is included. In addition, gate valves 60577a to 60577m are provided between the transfer chamber and each processing chamber, and the pressure in each processing chamber can be independently controlled to prevent cross-contamination between the processing chambers.

The substrate introduced into the transfer chamber 60560 from the load chamber 60562 is carried into a predetermined processing chamber by an arm-type transfer means 60566 that is rotatably provided. Further, the substrate is transported from one processing chamber to another processing chamber by the transporting means 60566. The transfer chamber 60560 and the transfer chamber 60561 are connected to each other through a film formation treatment chamber 60570, and the substrate is transferred by the transfer unit 60566 and the transfer unit 60567.

Each processing chamber connected to the transfer chamber 60560 and the transfer chamber 60561 is kept in a reduced pressure state. Therefore, in this vapor deposition apparatus, the substrate is continuously subjected to film formation of the EL layer without being exposed to the atmosphere. Since the display panel after the EL layer deposition process may be deteriorated by water vapor or the like, in this vapor deposition apparatus, a sealing process for performing a sealing process before exposure to the atmosphere in order to maintain the quality. A chamber 60565 is connected to the transfer chamber 60561. Sealing chamber 605
Since 65 is under atmospheric pressure or a reduced pressure close thereto, an intermediate processing chamber 60564 is also provided between the transfer chamber 60561 and the sealing processing chamber 60565. Intermediate processing chamber 60564
Is provided for transferring the substrate and buffering the pressure between the chambers.

The load chamber, the unload chamber, the transfer chamber, and the film forming chamber are provided with exhaust means for maintaining the chamber at a reduced pressure. As the exhaust means, various vacuum pumps such as a dry pump, a turbo molecular pump, and a diffusion pump can be used.

In the vapor deposition apparatus in FIG. 96, the number of treatment chambers connected to the transfer chamber 60560 and the transfer chamber 60561 and the structure thereof can be combined as appropriate depending on the stacked structure of the EL elements. An example of the combination is shown below.

In the heat treatment chamber 60568, degassing treatment is performed by first heating the substrate on which the lower electrode, the insulating partition wall, and the like are formed. The plasma treatment chamber 60572 performs rare gas or oxygen plasma treatment on the surface of the base electrode. This plasma treatment is performed to clean the surface, stabilize the surface state, and stabilize the physical or chemical state (eg, work function) of the surface.

The film formation treatment chamber 60569 is a treatment chamber for forming an electrode buffer layer in contact with one electrode of the EL element. The electrode buffer layer has carrier injection properties (hole injection or electron injection), and E
It is a layer that suppresses the occurrence of short circuits and dark spot defects in the L element. Typically, the electrode buffer layer is an organic-inorganic mixed material, and has a resistivity of 5 × 10 ⁴ to 1 × 10 ⁶ Ωcm, and 30 to 300.
It is formed to a thickness of nm. A film formation chamber 60571 is a treatment chamber for forming a hole transport layer.

The structure of the light emitting layer in the EL element differs depending on whether the light emission is monochromatic or white. In the vapor deposition apparatus, it is preferable to arrange the film forming treatment chamber accordingly. For example,
When three types of EL elements having different emission colors are formed on the display panel, it is necessary to form a light emitting layer corresponding to each emission color. In this case, the film formation chamber 60570 is used for forming the first light-emitting layer, the film formation chamber 60573 is used for forming the second light-emitting layer, and the film formation chamber 60574 is used for forming the third light-emitting layer. It can be used for membranes. By separating the film formation chamber for each light emitting layer, mutual contamination by different light emitting materials can be prevented, and the throughput of the film formation process can be improved.

Three types of EL materials having different emission colors may be sequentially deposited in the film formation chamber 60570, the film formation chamber 60573, and the film formation chamber 60574. In this case, a shadow mask is used, and vapor deposition is performed by shifting the mask in accordance with the region to be vapor deposited.

In the case of forming an EL element that emits white light, light emitting layers having different light emission colors are stacked vertically. Also in that case, the element substrate can be sequentially moved through the film formation chamber to form a film for each light emitting layer. In addition, different light emitting layers can be successively formed in the same film formation chamber.

In the deposition treatment chamber 60576, an electrode is deposited over the EL layer. The electrode can be formed by electron beam evaporation or sputtering, but resistance heating evaporation is preferably used.

After the formation of the electrodes, the element substrate passes through the intermediate processing chamber 60564 and the sealing processing chamber 60565.
It is carried in. The sealing treatment chamber 60565 is filled with an inert gas such as helium, argon, neon, or nitrogen, and a sealing plate is attached to the element substrate on the side where the EL layer is formed in the atmosphere. Stop. In the sealed state, between the element substrate and the sealing plate,
It may be filled with an inert gas or may be filled with a resin material. Sealing chamber 6
The 0565 is provided with a dispenser for drawing a sealing material, a mechanical element such as a fixed stage and an arm for fixing a sealing plate facing the element substrate, a dispenser for filling a resin material, a spin coater, and the like.

FIG. 97 shows the internal configuration of the film forming chamber. The film formation chamber is kept under reduced pressure. In FIG. 97, the inside between the top plate 60691 and the bottom plate 60692 is a room, and the room is kept under a reduced pressure.

One or a plurality of evaporation sources are provided in the processing chamber. This is because it is preferable to provide a plurality of evaporation sources when a plurality of layers having different compositions are formed or when different materials are co-evaporated. In FIG. 97, the evaporation sources 60681a, 60681b, and 60681c are attached to the evaporation source holder 60680. The evaporation source holder 60680 is held by an articulated arm 60683. The multi-joint arm 60683 has an evaporation source holder 60 by expansion and contraction of the joint.
The position of 680 can be freely moved within the movable range. Also, the evaporation source holder 606
80, a distance sensor 60682 is provided, and evaporation sources 60681a to 60681c and a substrate 606 are provided.
It is also possible to monitor the interval with 89 and control the optimum interval during vapor deposition. In that case, it is good also as an articulated arm which displaces to an articulated arm also in the up-down direction (Z direction).

The substrate stage 60686 and the substrate chuck 60687 are paired to fix the substrate 60689. The substrate stage 60686 may be configured to heat the substrate 60689 by incorporating a heater. The substrate 60689 is fixed to the substrate stage 60686 and carried in / out by the forcible relaxation of the substrate chuck 60687. In vapor deposition, a shadow mask 60690 having an opening corresponding to a vapor deposition pattern can be used as necessary. In that case, the shadow mask 60690 includes a substrate 60689 and evaporation sources 60681a to 60681c.
To be placed between. The shadow mask 60690 is fixed to the substrate 60689 with a mask chuck 60688 in close contact with or at a constant interval. Shadow mask 6
When the 0690 alignment is necessary, the camera is arranged in the processing chamber, and the mask chuck 60688 is provided with positioning means that finely moves in the X-Y-θ direction, thereby performing the alignment.

The evaporation source 60681 is provided with a deposition material supply means for continuously supplying the deposition material to the evaporation source. The vapor deposition material supply means includes material supply sources 60685a, 60685b, and 60685c arranged at positions distant from the evaporation source 60681, and a material supply pipe 6068 connecting the two.
4. Typically, the material supply sources 60685a, 60685b, and 60685c are provided corresponding to the evaporation source 60681. In the case of FIG. 97, the material supply source 60685a.
606 evaporation source 81a corresponds. A material supply source 60685b and an evaporation source 60681b,
The same applies to the material supply source 60685c and the evaporation source 60681c.

As an evaporation material supply method, an air current conveyance method, an aerosol method, or the like can be applied. In the air current conveyance method, fine powder of vapor deposition material is carried on an air current and is conveyed to the evaporation source 60681 using an inert gas or the like. The aerosol method is vapor deposition performed by conveying a raw material solution in which a vapor deposition material is dissolved or dispersed in a solvent, aerosolizing it with a sprayer, and vaporizing the solvent in the aerosol. In any case, the evaporation source 60681 is provided with a heating unit, and the conveyed vapor deposition material is evaporated to form a film on the substrate 60689. In the case of FIG. 97, the material supply pipe 60684
Can be flexibly bent, and is composed of a thin tube having rigidity that does not deform even under reduced pressure.

In the case of applying an air current conveyance method or an aerosol method, the film formation may be performed under a reduced pressure of 133 Pa to 13300 Pa in the film formation treatment chamber at atmospheric pressure or lower. The film formation chamber can be filled with an inert gas such as helium, argon, neon, krypton, xenon, or nitrogen, or the pressure can be adjusted while supplying the gas (while exhausting the gas). Further, in the film formation treatment chamber in which an oxide film is formed, a gas such as oxygen or nitrous oxide may be introduced to form an oxidizing atmosphere. Alternatively, a reducing atmosphere may be formed by introducing a gas such as hydrogen into a film formation chamber in which an organic material is deposited.

As another vapor deposition material supply method, a screw may be provided in the material supply pipe 60684 to continuously extrude the vapor deposition material toward the evaporation source.

According to this vapor deposition apparatus, even a large-screen display panel can be continuously formed with good uniformity. Further, it is not necessary to replenish the vapor deposition material each time the vapor deposition material runs out of the evaporation source, so that the throughput can be improved.

Note that this embodiment can be freely combined with any of the other embodiments.

In addition, the content of each figure in this embodiment can be implemented in combination freely with the content of other figures.

(Embodiment 12)
In this embodiment, a pixel circuit and a driving method of a display device that can implement this embodiment will be described.

First, digital time grayscale driving applicable to this embodiment will be described. First, a driving method in the case where the signal writing period (address period) to the pixel and the light emission period (sustain period) are separated will be described with reference to FIG. Here, as an example, a case of 4-bit digital time gradation will be described.

Note that a period for completely displaying an image for one display area is referred to as one frame period. One frame period has a plurality of subframe periods, and one subframe period has an address period and a sustain period. The address periods Ta1 to Ta4 indicate the time required for signal writing to pixels for all rows, and the periods Tb1 to Tb4 indicate the time required for signal writing to pixels for one row (or for one pixel). Further, the sustain periods Ts1 to Ts4 indicate the time during which the lighting or non-lighting state is maintained in accordance with the video signal written to the pixel, and the ratio of the lengths is Ts1: Ts2: Ts3: Ts4 = 2 ³ : 2 ² : 2 ¹ : 2 ⁰ = 8: 4: 2: 1. The gradation is expressed by the sustain period during which light is emitted.

The operation will be described. First, in the address period Ta1, pixel selection signals are input to the scanning lines in order from the first row, and pixels are selected. When a pixel is selected, a video signal is input from the signal line to the pixel. When a video signal is written to the pixel, the pixel holds the signal until the signal is input again. Lighting and non-lighting of each pixel in the sustain period Ts1 are controlled by the written video signal. Similarly, video signals are input to the pixels in the address periods Ta2, Ta3, and Ta4, and lighting and non-lighting of each pixel in the sustain periods Ts2, Ts3, and Ts4 are controlled by the video signals. In each subframe period, the pixel is not lit during the address period, and after the address period ends, the sustain period starts, and the pixel in which a signal for lighting is written is lit.

Here, the i-th pixel row will be described with reference to FIG. First, in the address period Ta1, pixel selection signals are sequentially input to the scanning lines from the first row, and the address period T
The pixel in the i-th row is selected in the period Tb1 (i) among a1. Then, when the i-th row pixel is selected, a video signal is input from the signal line to the i-th row pixel. And
When a video signal is written to the i-th row pixel, the i-th row pixel holds the signal until the signal is input again. Lighting and non-lighting of the i-th row pixel in the sustain period Ts1 are controlled by the written video signal. Similarly, address periods Ta2, Ta3, T
In a4, a video signal is input to the pixel in the i-th row, and lighting and non-lighting of the pixel in the i-th row in the sustain periods Ts2, Ts3, and Ts4 are controlled by the video signal. In each subframe period, the pixel is not lit during the address period, and after the address period ends, the sustain period starts, and the pixel in which a signal for lighting is written is lit.

Although the case where a 4-bit gradation is expressed has been described here, the number of bits and the number of gradations are not limited thereto. Moreover, the order of lighting does not need to be Ts1, Ts2, Ts3, and Ts4, and may be random or may be divided into a plurality of portions to emit light. Ts1, Ts2
, Ts3 and Ts4 do not need to be a power of 2, but may be the same length of lighting time or may be slightly shifted from a power of 2.

Next, a driving method in the case where the signal writing period (address period) to the pixel and the light emission period (sustain period) are not separated will be described. That is, the pixel in the row where the video signal writing operation is completed holds the signal until the signal is written (or erased) to the pixel next time. A period from writing operation to next signal writing to this pixel is referred to as data holding time. During this data retention time, the pixel is turned on or off according to the video signal written to the pixel. The same operation is performed up to the last line, and the address period ends. Then, the signal writing operation in the next subframe period is started in order from the row where the data holding time has ended.

As described above, when the signal writing operation is completed and the data holding time is reached, in the driving method in which the pixel is turned on or off in accordance with the video signal written to the pixel immediately, the data holding time is attempted to be shorter than the address period. However, since signals cannot be input to two rows at the same time, it is necessary to prevent the address periods from overlapping, and therefore the data holding time cannot be shortened. As a result, it becomes difficult to perform high gradation display.

Therefore, a data holding time shorter than the address period is set by providing an erasing period. A driving method in the case where an erasing period is provided and a data holding time shorter than the address period is set will be described with reference to FIG.

First, in the address period Ta1, pixel scanning signals are input to the scanning lines in order from the first row,
A pixel is selected. When a pixel is selected, a video signal is input from the signal line to the pixel. When a video signal is written to the pixel, the pixel holds the signal until the signal is input again. The sustain period Ts1 is determined by the written video signal.
The lighting and non-lighting of each pixel in are controlled. In the row where the video signal writing operation is completed, the pixels are turned on or off in accordance with the video signal written immediately. The same operation is performed up to the last row, and the address period Ta1 ends. Then, the signal writing operation in the next subframe period is started in order from the row where the data holding time has ended. Similarly, video signals are input to the pixels in the address periods Ta2, Ta3, and Ta4, and lighting and non-lighting of each pixel in the sustain periods Ts2, Ts3, and Ts4 are controlled by the video signals. The end of the sustain period TS4 is set by the start of the erase operation. This is because if the signal written to the pixel is erased at the erase time Te of each row, the signal is forced regardless of the video signal written to the pixel in the address period until the signal is written to the next pixel. This is because the light is not turned on. That is, the data holding time ends from the pixel in the row where the erasing time Te has started.

Here, with reference to FIG. 99B, description will be given focusing on the i-th pixel row. In the i-th pixel row, in the address period Ta1, pixel scanning signals are sequentially input to the scanning lines from the first row, and pixels are selected. Then, when the i-th row pixel is selected in the period Tb1 (i), a video signal is input to the i-th row pixel. When a video signal is written to the i-th row pixel, the i-th row pixel holds the signal until the signal is input again. By the written video signal, lighting and non-lighting of the pixel in the i-th row in the sustain period Ts1 (i) are controlled. That is, when the video signal writing operation is completed in the i-th row,
In accordance with the video signal immediately written, the pixels in the i-th row are turned on or off. Similarly, a video signal is input to the i-th row pixel in the address periods Ta2, Ta3, and Ta4, and lighting and non-lighting of the i-th row pixel in the sustain periods Ts2, Ts3, and Ts4 are controlled by the video signal. The end of the sustain period Ts4 (i) is set by starting the erase operation. This is because the light is forcibly turned off regardless of the video signal written to the pixel in the i-th row during the erasing time Ts (i) in the i-th row. That is, when the erasing time Te (i) starts, the data holding time of the pixel in the i-th row ends.

Therefore, a display device with a high gradation and a high duty ratio (ratio of lighting period in one frame period) shorter than the address period can be provided without separating the address period and the sustain period. In addition, since the instantaneous luminance can be reduced, the reliability of the display element can be improved.

Although the case where a 4-bit gradation is expressed has been described here, the number of bits and the number of gradations are not limited thereto. Further, the lighting order need not be Ts1, Ts2, Ts3, and Ts4, and may be random or may be divided into a plurality of light emission. Ts1, Ts2,
The lighting times of Ts3 and Ts4 do not need to be a power of 2, but may be the same lighting time, or may be slightly shifted from the power of 2.

Here, FIGS. 100A, 100B, 100C, 100D, and 100E are used for the pixel structure capable of digital time gray scale driving described in FIGS. 98A and 99A. The description will be given with reference. Note that display elements shown in FIGS. 100A, 100B, 100C, 100D, and 100E are EL elements.
Elements (organic EL elements, inorganic EL elements or EL elements including organic and inorganic substances), electron emitting elements, liquid crystal elements, electronic ink, grating light valves (GLV), digital micromirror devices (DMD), carbon nanotubes, etc. A display medium whose contrast is changed by a magnetic action can be applied. Also, FIGS. 100 (A), (B), (
For the pixels shown in C), (D), and (E), a self-luminous element such as an EL element is suitable as a display element. Note that FIGS. 100A, 100B, 100C, 100D, and 100E illustrate only one pixel, but the pixel portion of the display device is arranged in a matrix in the row direction and the column direction. A plurality of pixels are arranged.

A pixel illustrated in FIG. 100A includes a switching transistor 80301a, a driving transistor 80302a, and a capacitor 80304a. The switching transistor 80301a has a gate terminal connected to the scan line 8031a, a first terminal (source terminal or drain terminal) connected to the signal line 80311a, and a second terminal (source terminal or drain terminal) connected to the driving transistor 80302a. Connected to the gate terminal. The second terminal of the switching transistor 80301a is connected to the power supply line 8 via the capacitor 80304a.
0313a. Further, the driving transistor 80302a has a first terminal connected to the power supply line 80313a and a second terminal connected to the first electrode of the display element 80320a. A low power supply potential is set to the second electrode 80321a of the display element 80320a. Note that the low power supply potential is a potential that satisfies the low power supply potential <high power supply potential with reference to the high power supply potential set in the power supply line 80313a. For example, GND, 0V, or the like is set as the low power supply potential. Also good. The potential difference between the high power supply potential and the low power supply potential is expressed as a display element 80320.
In order to cause the display element 80320a to emit light by applying a current to the display element 80320a, the potential difference between the high power supply potential and the low power supply potential is greater than or equal to the forward threshold voltage of the display element 80320a. Set the potential. Note that the capacitor 80304a can be omitted instead of the gate capacitance of the driving transistor 80302a. With respect to the gate capacitance of the driving transistor 80302a, the capacitance may be formed in a region where the source electrode, the drain region, the LDD region, and the like overlap with the gate electrode, or the channel region and the gate electrode. A capacitance may be formed between the two.

When a pixel is selected by the scanning line 8031a, that is, the switching transistor 8
When 0301a is on, a video signal is input from the signal line 80311a to the pixel. Then, a charge corresponding to the voltage corresponding to the video signal is accumulated in the capacitor 80304a,
The capacitor 80304a holds the voltage. This voltage is applied to the driving transistor 80302.
a is a voltage between the gate terminal and the first terminal of a, and corresponds to the gate-source voltage Vgs of the driving transistor 80302a.

In general, the operation region of a transistor can be divided into a linear region and a saturation region. The boundary is when (Vgs−Vth) = Vds, where Vds is the drain-source voltage, Vgs is the gate-source voltage, and Vth is the threshold voltage. (Vgs−Vth)> Vds
Is a linear region, and the current value is determined by the magnitudes of Vds and Vgs. on the other hand,(
When Vgs−Vth) <Vds, the saturation region is reached. Ideally, even if Vds changes,
The current value hardly changes. That is, the current value is determined only by the magnitude of Vgs.

Here, in the case of the voltage input voltage driving method, a video signal is input to the gate terminal of the driving transistor 80302a so that the driving transistor 80302a is sufficiently turned on or off. . That is, the driving transistor 80302a is operated in a linear region.

Therefore, when the driving transistor 80302a is turned on, ideally, the power supply potential VDD set to the power supply line 80313a is used as it is as the display element 80320.
Set to the first electrode of a.

That is, ideally, the voltage applied to the display element 80320a is constant, and the display element 8032
The luminance obtained from 0a is made constant. A plurality of subframe periods are provided within one frame period, video signals are written to the pixels for each subframe period, and lighting or non-lighting of the pixels is controlled for each subframe period. The gradation is expressed by the sum of the subframe periods.

Next, the pixel structure in FIG. 100B is described. A pixel illustrated in FIG. 100B includes a switching transistor 80301a, a driving transistor 80302a, and a rectifying element 80.
306a, a capacitor 80304a, and a display element 80320b. The switching transistor 80301b has a gate terminal connected to the first scan line 8031b,
A terminal (source terminal or drain terminal) is connected to the signal line 80311b, and a second terminal (source terminal or drain terminal) is connected to the gate terminal of the driving transistor 80302b. Further, the gate terminal of the driving transistor 80302 is connected to the second scanning line 80314b through the rectifying element 80306a. Further, the switching transistor 80
A second terminal 301b is connected to a power supply line 80313b through a capacitor 80304b. Further, the driving transistor 80302b has a first terminal connected to the power supply line 80313b and a second terminal connected to the first electrode of the display element 80320b. Display element 8032
A low power supply potential is set for the second electrode 80321b of 0b. Note that the low power supply potential is a potential that satisfies the low power supply potential <the high power supply potential with reference to the high power supply potential set in the power supply line 80313b. Also good.
The potential difference between the high power supply potential and the low power supply potential is applied to the display element 80320b, so that the display element 8
In order to cause the display element 80320b to emit light by flowing current through 0320b, each potential is set so that the potential difference between the high power supply potential and the low power supply potential is equal to or higher than the forward threshold voltage of the display element 80320b. Note that the capacitor 80304b can be omitted instead of the gate capacitor of the driving transistor 80302b. As for the gate capacitance of the driving transistor 80302b, the capacitance may be formed in a region where the source region, the drain region, the LDD region, and the like overlap with the gate electrode, or the channel region and the gate electrode. A capacitance may be formed between the two.

This pixel configuration includes a rectifier element 80306a and a second scan line 8031 in addition to the pixel in FIG.
4b is added. Therefore, the switching transistor 80301b, the driving transistor 80302b, the capacitor 80304b, the signal line 80311b, the first scan line 8031b, and the power supply line 80313b are respectively connected to the switching transistor 80301.
a, a driving transistor 80302a, a capacitor 80304a, a signal line 80311a, a scanning line 80312a, and a power supply line 80313a, and the writing operation and the light emitting operation are the same.

The erase operation will be described. At the time of erasing operation, an H level signal is input to the second scan line 80314b. Then, current flows through the rectifying element 80306a, and the gate potential of the driving transistor 80302b held by the capacitor 80304b can be set to a certain potential. That is, the potential of the gate terminal of the driving transistor 80302b is set to a certain potential, and the driving transistor 80302 regardless of the video signal written to the pixel.
b can be forcibly turned off.

Note that the L-level signal input to the second scan line 80314b is set to a potential such that no current flows through the rectifier element 80306a when a non-lighting video signal is written to the pixel. The H-level signal input to the second scan line 80314b is a potential at which the gate terminal can be set to a potential at which the driving transistor 80302b is turned off regardless of the video signal written to the pixel. And

Note that a diode-connected transistor can be used for the rectifying element 80306a. In addition to a diode-connected transistor, a PN junction or PIN junction diode, a Schottky diode, a diode formed of carbon nanotubes, or the like may be used. FIG. 100C illustrates the case where a diode-connected N-channel transistor is used. The first terminal (source terminal or drain terminal) of the diode-connected transistor 80303c is connected to the gate terminal of the driving transistor 80302c. Also,
A second terminal (a source terminal or a drain terminal) of the diode-connected transistor 80303c is connected to the gate terminal and is also connected to the second scanning line 80314c. Then, when the second scan line 80314c is at the L level, no current flows through the diode-connected transistor 80303c because the gate terminal and the source terminal are connected, but the second scan line 80314c does not flow.
When a signal at H level is input to c, the second terminal of the diode-connected transistor 80303c becomes the drain terminal, so that a current flows through the diode-connected transistor 80303c.
Therefore, the diode-connected transistor 80303c has a rectifying action.

Note that the switching transistor 80301c, the driving transistor 80302c, the capacitor 80304c, the signal line 80311c, the first scan line 8031c, and the power supply line 8031
Reference numeral 3c denotes a switching transistor 80301a, a driving transistor 80302a, a capacitor 80304a, a signal line 80311a, and a scanning line 8031 in FIG.
2a corresponds to the power supply line 80313a. In addition, the second scanning line 80314c corresponds to FIG.
This corresponds to the second scanning line 8031d of B).

FIG. 100D illustrates the case where a diode-connected P-channel transistor is used. A first terminal (source terminal or drain terminal) of the diode-connected transistor 80303d is connected to the second scanning line 80313d. Also, the diode-connected transistor 803
The second terminal (source terminal or drain terminal) of 03d is connected to the gate terminal and to the gate terminal of the driving transistor 80302d. Then, the second scanning line 8031
When 3d is at L level, no current flows through the diode-connected transistor 80303d because the gate terminal and the source terminal are connected. However, when an H-level signal is input to the second scanning line 80313d, the diode-connected transistor 80303d Since the two terminals serve as drain terminals, a current flows through the diode-connected transistor 80303d. Therefore, the diode-connected transistor 80303d has a rectifying action.

Note that the switching transistor 80301d, the driving transistor 80302d, the capacitor 80304d, the signal line 80311d, the first scanning line 8031d, and the power supply line 8031
3d are a switching transistor 80301a, a driving transistor 80302a, a capacitor 80304a, a signal line 80311a, and a scanning line 8031 in FIG.
2a corresponds to the power supply line 80313a. Further, the second scanning line 80314d corresponds to FIG.
This corresponds to the second scanning line 8031d of B).

Further, an erasing transistor may be provided in order to erase a signal written to the pixel.
A pixel illustrated in FIG. 100E is different from the pixel illustrated in FIG.
And a second scanning line 80312e. Therefore, the switching transistor 80301e, the driving transistor 80302e, the capacitor 80304e, and the signal line 80
311e, the first scan line 8031e, and the power supply line 80313e are shown in FIG.
The switching transistor 80301a, the driving transistor 80302a, the capacitor 80304a, the signal line 80311a, the scanning line 80312a, and the power supply line 80313a correspond to the writing operation and the light emitting operation, and thus the description thereof is omitted here.

The erase operation will be described. In the erasing operation, an H level signal is input to the second scan line 8031e. Then, the erasing transistor 80303e is turned on, and the gate terminal and the first terminal of the driving transistor 80302e can be set to the same potential. That is, the gate-source voltage of the driving transistor 80302e can be set to 0V. Note that the H-level potential of the second scan line 8031e is preferably higher than the potential of the power supply line 80313e by the threshold voltage Vth of the erasing transistor 80303e. Thus, the driving transistor 80302e can be forcibly turned off.

Next, an example of a threshold voltage correction pixel circuit and a driving method which can be applied to this embodiment mode will be described with reference to FIG.

A pixel illustrated in FIG. 101A includes a driving transistor 80400 and a first switch 80401.
, Second switch 80402, third switch 80403, first capacitor element 80404,
A second capacitor 80405 and a display element 80420 are included. Drive transistor 80
The gate terminal 400 is connected to the signal line 80411 through the first capacitor 80404 and the first switch 80401 in order, the first terminal is connected to the power supply line 80412, and the second terminal is the third switch 80403. Is connected to the first electrode of the display element 80420. Further, the gate terminal of the driving transistor 80400 is connected to the power supply line 80412 through the second capacitor element 80405. Further, the gate terminal of the driving transistor 80400 is connected to the second terminal of the driving transistor 80400 through the second switch 80402. In addition, a low power supply potential is set for the second electrode 80421 of the display element 80420. Note that the low power supply potential is a potential that satisfies the low power supply potential <the high power supply potential with reference to the high power supply potential set in the power supply line 80412. For example, GND, 0V, or the like is set as the low power supply potential. Also good. The potential difference between the high power supply potential and the low power supply potential is expressed as a display element 80420.
In order to cause the display element 80420 to emit light by causing a current to flow through the display element 80420.
Each potential is set so that the potential difference between the high power supply potential and the low power supply potential is equal to or higher than the forward threshold voltage of the display element 80420. Note that the second capacitor 80405 can be omitted by using the gate capacitor of the driving transistor 80400 instead. Drive transistor 80
Regarding the gate capacitance of 400, the capacitance may be formed in a region where the source region, the drain region, the LDD region, and the like overlap with the gate electrode, or between the channel region and the gate electrode. A capacitor may be formed. The first switch 8
On / off of the 0401, the second switch 80402, and the third switch 80403 is controlled by the first scanning line 80413, the second scanning line 80414, and the third scanning line 80415, respectively.

A driving method of the pixel illustrated in FIG. 101A can be divided into an initialization period, a data writing period, a threshold value acquisition period, and a light emission period.

In the initialization period, the second switch 80402 and the third switch 80403 are turned on,
The potential of the gate terminal of the driving transistor 80400 is at least lower than the potential of the power supply line 80412. At this time, the first switch 80401 may be turned on or off. Note that the initialization period is not necessarily required.

In the threshold acquisition period, a pixel is selected by the first scan line 80413. That is, the first switch 80401 is turned on and a certain voltage is input from the signal line 80411. At this time, the second switch 80402 is on and the driving transistor 80400 is diode-connected. Further, the third switch 80403 is off. Therefore, the potential of the gate terminal of the driving transistor 80400 is a value obtained by subtracting the threshold voltage of the driving transistor 80400 from the potential of the power supply line 80412. The first capacitor element 80404 holds the threshold voltage of the driving transistor 80400. In addition, the second capacitor element 80405
The potential difference between the potential of the gate terminal of the driving transistor 80400 and the constant voltage input from the signal line 80411 is held.

In the data writing period, a video signal (voltage) is input from the signal line 80411. At this time, the first switch 80401 remains on, the second switch 80402 is turned off, and the second switch 80402 remains off. Further, the driving transistor 80400
The gate terminal of is floating. Therefore, the potential of the gate terminal of the driving transistor 80400 changes in accordance with the potential difference between the constant voltage input to the signal line 80411 in the threshold acquisition period and the video signal input to the signal line 80411 in the data writing period. For example, if the capacitance value of the first capacitor element 80404 << the capacitance value of the second capacitor element 80405, the potential of the gate terminal of the driving transistor 80400 in the data writing period is input to the signal line 80411 in the threshold value acquisition period. The potential difference between the fixed voltage and the video signal input to the signal line 80411 in the data writing period is approximately equal to a value obtained by adding the threshold voltage of the driving transistor 80400 to the potential of the power supply line 80412. That is, the potential of the gate terminal of the driving transistor 80400 is a potential obtained by correcting the threshold voltage of the driving transistor 80400.

In the light emission period, a current corresponding to the potential difference (Vgs) between the gate terminal of the driving transistor 80400 and the power supply line 80412 flows to the display element 80420. At this time, the first switch 80401 is turned off, the second switch 80402 is kept off, and the third switch 80403 is turned on. Note that the current flowing through the display element 80420 is equal to the driving transistor 8.
It is constant regardless of the threshold voltage of 0400.

Note that the pixel structure illustrated in FIG. 101A is not limited to FIG. For example, FIG.
A switch, a resistor, a capacitor, a transistor, a logic circuit, or the like may be newly added to the pixel shown in 01 (A). For example, the second switch 80402 is a P-channel transistor or an N-channel transistor, the third switch 80403 is a transistor having a polarity different from that of the second switch 80402, and the second switch 80402 The third switch 80403 may be controlled by the same scanning line.

Next, an example of a current input pixel circuit and a driving method that can be applied to the present embodiment will be described.
This will be described with reference to FIG.

A pixel illustrated in FIG. 101B includes a driving transistor 80430 and a first switch 8043.
1, a second switch 80432, a third switch 80433, a capacitor element 80434, and a display element 80450 are included. The driving transistor 80430 has a gate terminal connected to the signal line 80441 through the second switch 80432 and the first switch 80431 in order, a first terminal connected to the power supply line 80442, and a second terminal connected to the third terminal. It is connected to the first electrode of the display element 80450 through the switch 80433. Further, the gate terminal of the driving transistor 80430 is connected to the power supply line 80442 through the capacitor 80434. The gate terminal of the driving transistor 80430 is connected to the second terminal of the driving transistor 80430 through the second switch 80432. In addition, the display element 804
A low power supply potential is set for the 50 second electrodes 80451. The low power supply potential is
The low power supply potential <the potential satisfying the high power supply potential with respect to the high power supply potential set for the power supply line 80442 as a reference. For example, GND, 0 V, or the like may be set as the low power supply potential. A potential difference between the high power supply potential and the low power supply potential is applied to the display element 80450 to display the display element 8045.
In order to cause the display element 80450 to emit light by supplying current to 0, each potential is set so that the potential difference between the high power supply potential and the low power supply potential is equal to or higher than the forward threshold voltage of the display element 80450. Note that the capacitor 80434 can be omitted by using the gate capacitor of the driving transistor 80430 instead. Regarding the gate capacitance of the driving transistor 80430,
The capacitance may be formed in a region where the gate electrode overlaps with the source region, the drain region, the LDD region, or the like, or the capacitance is formed between the channel region and the gate electrode. Also good. Note that the first switch 80431 and the second switch 804 are provided.
32 and the third switch 80433 are a first scanning line 80443 and a second scanning line 8 respectively.
On / off is controlled by 0444 and the third scanning line 80445.

The driving method of the pixel illustrated in FIG. 101B can be divided into a data writing period and a light emission period.

In the data writing period, a pixel is selected by the first scan line 80443. That means
The first switch 80431 is turned on, and a current is input as a video signal from the signal line 80441. At this time, the second switch 80432 is turned on and the third switch 80433 is turned off. Accordingly, the potential of the gate terminal of the driving transistor 80430 becomes a potential corresponding to the video signal. In other words, the capacitor 80434 includes the driving transistor 80430.
The voltage between the gate and the source of the driving transistor 80430 that holds the same current as the video signal is held.

Next, in the light emission period, the first switch 80431 and the second switch 80432 are turned off, and the third switch 80433 is turned on. Therefore, a current having the same value as the video signal flows through the display element 80450.

Note that the pixel structure illustrated in FIG. 101B is not limited to FIG. For example, FIG.
A switch, a resistor, a capacitor, a transistor, a logic circuit, or the like may be newly added to the pixel shown in 01 (B). In addition, for example, the first switch 80431 is formed of a P-channel transistor or an N-channel transistor, the second switch 80432 is formed of a transistor having the same polarity as the first switch 80431, and the first switch 80431 and the first switch 80431 Two switches 80432 may be controlled by the same scanning line. The second switch 8043
2 may be disposed between the gate terminal of the driving transistor 80430 and the signal line 80441.

Note that this embodiment can be freely combined with any of the other embodiments.

In addition, the content of each figure in this embodiment can be implemented in combination freely with the content of other figures.

(Embodiment 13)
In this embodiment, a semiconductor device to which this embodiment can be applied is a thin film transistor (TF).
A method for manufacturing a semiconductor device in the case where T) is included as an element will be described with reference to drawings.

FIG. 102 is a diagram illustrating an example of a structure and manufacturing process of a TFT that can be included in a semiconductor device to which this embodiment can be applied. FIG. 102A illustrates an example of a structure of a TFT that can be included in a semiconductor device to which this embodiment can be applied. In addition, FIG.
(G) to (G) are diagrams illustrating an example of a manufacturing process of a TFT that can be included in a semiconductor device to which this embodiment can be applied.

Note that the structure and manufacturing process of a TFT which can be included in a semiconductor device to which this embodiment can be applied are not limited to those illustrated in FIGS. 102A and 102B, and various structures and manufacturing processes can be used.

First, an example of a structure of a TFT that can be included in a semiconductor device to which this embodiment can be applied will be described with reference to FIG. FIG. 102A shows a T having a plurality of different structures.
It is sectional drawing of FT. Here, in FIG. 102A, Ts having a plurality of different structures.
Although the FTs are shown in juxtaposition, this is an expression for explaining the structure of the TFT that the semiconductor device to which the invention can be applied, and the TFT that the semiconductor device to which the invention can be applied has, Actually, they do not have to be juxtaposed as shown in FIG. 102 (A), and they can be created as needed.

Next, characteristics of each layer included in a TFT that can be included in a semiconductor device to which this embodiment can be applied will be described.

As the substrate 110111, a glass substrate such as barium borosilicate glass or alumino borosilicate glass, a quartz substrate, a ceramic substrate, a metal substrate including stainless steel, or the like can be used. In addition, polyethylene terephthalate (PET), polyethylene naphthalate (P
EN), a substrate made of a synthetic resin having flexibility such as plastic or acrylic represented by polyethersulfone (PES) can be used. By using a flexible substrate, a semiconductor device that can be bent can be manufactured. In addition, since there is no great limitation on the area of the substrate and the shape of the substrate as long as the substrate has flexibility, for example, if the substrate 110111 has a rectangular shape with one side being 1 meter or more, , Productivity can be significantly improved. Such an advantage is a great advantage compared to the case of using a circular silicon substrate.

The insulating film 110112 functions as a base film. An alkali metal or alkaline earth metal such as Na is provided from the substrate 110111 in order to prevent adverse effects on the characteristics of the semiconductor element. As the insulating film 110112, an insulating film containing oxygen or nitrogen, such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x> y), or silicon nitride oxide (SiNxOy) (x> y) It is possible to provide a single layer structure or a laminated structure thereof.
For example, in the case where the insulating film 110112 is provided with a two-layer structure, a silicon nitride oxide film may be provided as a first insulating film and a silicon oxynitride film may be provided as a second insulating film. Insulating film 110
When 112 is provided in a three-layer structure, a silicon oxynitride film is provided as a first insulating film, a silicon nitride oxide film is provided as a second insulating film, and a silicon oxynitride film is provided as a third insulating film Good.

The semiconductor films 110113, 110114, and 110115 can be formed using an amorphous semiconductor or a semi-amorphous semiconductor (SAS). Alternatively, a polycrystalline semiconductor film may be used. SAS is a semiconductor having an intermediate structure between amorphous and crystalline structures (including single crystal and polycrystal) and having a third state that is stable in terms of free energy and has a short-range order and a lattice. It includes a crystalline region with strain. A crystal region of 0.5 to 20 nm can be observed in at least a part of the film, and when silicon is a main component, the Raman spectrum is shifted to a lower wave number side than 520 cm ^−1. Yes. In X-ray diffraction, diffraction peaks of (111) and (220) that are derived from the silicon crystal lattice are observed. Unbound hand (
At least 1 atomic% or more of hydrogen or halogen is included as compensation for dangling bonds. The SAS is formed by glow discharge decomposition (plasma CVD) of a material gas. As the material gas, SiH ₄ , Si ₂ H ₆ , SiH ₂ Cl ₂ , S
It is possible to use iHCl ₃ , SiCl ₄ , SiF ₄ or the like. Alternatively, GeF ₄
May be mixed. This material gas may be diluted with H ₂ , or H ₂ and one or more kinds of rare gas elements selected from He, Ar, Kr, and Ne. The dilution rate is in the range of 2 to 1000 times. The pressure is in the range of approximately 0.1 Pa to 133 Pa, the power supply frequency is 1 MHz to 120 MHz,
Preferably 13 MHz to 60 MHz. The substrate heating temperature may be 300 ° C. or less. As an impurity element in the film, impurities of atmospheric components such as oxygen, nitrogen, and carbon are desirably 1 × 10 ²⁰ cm ⁻¹ or less, and in particular, the oxygen concentration is 5 × 10 ¹⁹ / cm ³ or less, preferably 1 × 10 ^1
9 / cm ³ or less. Here, known means (sputtering, LPCVD, plasma C
Material using silicon (Si) as a main component (for example, SixGe1-x) using the VD method)
An amorphous semiconductor film is formed by using a laser crystallization method, a thermal crystallization method using an RTA or a furnace annealing furnace, a thermal crystallization method using a metal element that promotes crystallization, and the like. Crystallization is performed by the following crystallization method.

The insulating film 110116 includes silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (
A single-layer structure of an insulating film containing oxygen or nitrogen, such as SiOxNy) (x> y) or silicon nitride oxide (SiNxOy) (x> y), or a stacked structure thereof can be used.

The gate electrode 110117 can have a single-layer conductive film or a stacked structure of two-layer or three-layer conductive films. As a material of the gate electrode 110117, a known conductive film can be used. For example, a simple film of an element such as tantalum (Ta), titanium (Ti), molybdenum (Mo), tungsten (W), chromium (Cr), silicon (Si), or a nitride film of the element (typically A tantalum nitride film, a tungsten nitride film, a titanium nitride film), an alloy film combining the above elements (typically, a Mo—W alloy or a Mo—Ta alloy), or a silicide film of the above elements (typically, (Tungsten silicide film, titanium silicide film) or the like can be used. Note that the single film, nitride film, alloy film, silicide film, and the like described above may be used as a single layer or may be stacked.

The insulating film 110118 is formed by known means (such as sputtering or plasma CVD) by using silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x> y),
An insulating film containing oxygen or nitrogen such as silicon nitride oxide (SiNxOy) (x> y) or DLC (
It can be provided in a single layer structure of a film containing carbon such as diamond-like carbon) or a laminated structure thereof.

The insulating film 110119 is formed of siloxane resin, silicon oxide (SiOx), or silicon nitride (S
iNx), silicon oxynitride (SiOxNy) (x> y), silicon nitride oxide (SiNxOy) (
x> y) such as an insulating film having oxygen or nitrogen such as DLC (diamond-like carbon), or a film containing carbon such as epoxy, polyimide, polyamide, polyvinylphenol,
It can be provided in a single layer or a laminated structure made of an organic material such as benzocyclobutene and acrylic. Note that a siloxane resin corresponds to a resin including a Si—O—Si bond. Siloxane has a skeleton structure formed of a bond of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (for example, an alkyl group or an aromatic hydrocarbon) is used. A fluoro group can also be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as a substituent. Note that in the semiconductor device in this embodiment, the insulating film 110119 can be provided directly so as to cover the gate electrode 110117 without providing the insulating film 110118.

The conductive film 110123 is made of Al, Ni, C, W, Mo, Ti, Pt, Cu, Ta, Au, M
A simple film of an element such as n, a nitride film of the element, an alloy film combining the elements, a silicide film of the element, or the like can be used. For example, as an alloy containing a plurality of the elements, an Al alloy containing C and Ti, an Al alloy containing Ni, an Al alloy containing C and Ni, an Al alloy containing C and Mn, and the like can be used. Further, in the case of providing a stacked structure, a structure in which Al is sandwiched between Mo or Ti can be employed. By carrying out like this, the tolerance with respect to the heat | fever and chemical reaction of Al can be improved.

Next, referring to a cross-sectional view of a plurality of TFTs having different structures shown in FIG.
The characteristics of each structure will be described.

Reference numeral 110101 denotes a single drain TFT, which can be manufactured by a simple method, and thus has an advantage that a manufacturing cost is low and a yield is high. Here, the semiconductor films 110113, 1
10115 has different impurity concentrations, and the semiconductor film 110113 has a channel region,
The semiconductor film 110115 is used as a source region and a drain region. Thus, the resistivity of the semiconductor film can be controlled by controlling the amount of impurities. Further, the semiconductor film and the conductive film 11
The electrical connection state with 0123 can be brought close to ohmic connection. Note that as a method of separately forming semiconductor films having different amounts of impurities, a method of doping impurities into the semiconductor film using the gate electrode 110117 as a mask can be used.

Reference numeral 110102 denotes a TFT having a taper angle of a certain level or more on the gate electrode 110117, which can be manufactured by a simple method, and thus has an advantage that the manufacturing cost is low and the yield is high. Here, the semiconductor films 110113, 110114, and 110115 have different impurity concentrations, the semiconductor film 110113 is a channel region, the semiconductor film 110114 is a lightly doped drain (LDD) region, and the semiconductor film 110115.
Is used as a source region and a drain region. Thus, the resistivity of the semiconductor film can be controlled by controlling the amount of impurities. Further, the electrical connection state between the semiconductor film and the conductive film 110123 can be made close to ohmic connection. Moreover, since it has an LDD region,
It is difficult for a high electric field to be applied to the inside of the TFT, and deterioration of the element due to hot carriers can be suppressed. As a method of separately forming semiconductor films having different amounts of impurities, the gate electrode 11
A method of doping impurities into the semiconductor film can be used with 0117 as a mask.
In 110102, since the gate electrode 110117 has a certain taper angle or more, the concentration of the impurity doped into the semiconductor film through the gate electrode 110117 can be given a gradient, and the LDD region can be easily formed. Can be formed.

Reference numeral 110103 denotes a TFT in which the gate electrode 110117 is composed of at least two layers, and the lower gate electrode is longer than the upper gate electrode. In this specification, the shape of the upper gate electrode and the lower gate electrode is referred to as a hat shape. Gate electrode 110117
Since the shape of is a hat shape, an LDD region can be formed without adding a photomask. Note that as in 110103, the LDD region has a gate electrode 11011.
7 is a GOLD structure (Gate Overlapped LDD).
). Note that the following method may be used as a method of making the shape of the gate electrode 110117 into a hat shape.

First, when the gate electrode 110117 is patterned, the lower gate electrode and the upper gate electrode are etched by dry etching so that the side surfaces are inclined (tapered). Subsequently, the upper-layer gate electrode is processed to be nearly vertical by anisotropic etching. Thereby, a gate electrode having a hat-shaped cross section is formed. Then twice,
A semiconductor film 1101 used as a channel region by doping with an impurity element
13. A semiconductor film 110114 used as an LDD region and a semiconductor film 110115 used as a source electrode and a drain electrode are formed.

Note that an LDD region overlapping the gate electrode 110117 is defined as a Lov region, and the gate electrode 11.
An LDD region that does not overlap with 0117 will be referred to as a Loff region. Where Lof
The f region has a high effect of suppressing the off-current value, but has a low effect of relaxing the electric field near the drain and preventing the deterioration of the on-current value due to hot carriers. On the other hand, the Lov region relaxes the electric field near the drain and is effective in preventing deterioration of the on-current value, but has a low effect of suppressing the off-current value. Therefore, it is preferable to manufacture a TFT having a structure corresponding to required characteristics for each of various circuits. For example, when the semiconductor device in this embodiment is used as a display device, the pixel TFT
In order to suppress the off-current value, it is preferable to use a TFT having a Loff region. On the other hand, as the TFT in the peripheral circuit, it is preferable to use a TFT having a Lov region in order to relax the electric field in the vicinity of the drain and prevent deterioration of the on-current value.

110104 is in contact with the side surface of the gate electrode 110117, and the sidewall 110121.
It is TFT which has. By including the sidewall 110121, a region overlapping with the sidewall 110121 can be an LDD region.

110105 performs LDD (Lof) by doping a semiconductor film using a mask.
f) A TFT in which a region is formed. By so doing, the LDD region can be formed reliably, and the off-current value of the TFT can be reduced.

110106 performs LDD (Lov) by doping a semiconductor film using a mask.
) TFT in which a region is formed. By doing so, the LDD region can be formed reliably, the electric field in the vicinity of the drain of the TFT can be relaxed, and the deterioration of the on-current value can be reduced.

Next, an example of a manufacturing process of a TFT that can be included in a semiconductor device to which this embodiment can be applied will be described with reference to FIGS.
Note that the structure and manufacturing process of a TFT which can be included in a semiconductor device to which this embodiment can be applied are not limited to those illustrated in FIGS. 102A and 102B, and various structures and manufacturing processes can be used.

In this embodiment mode, the insulating film 1 is formed on the surface of the substrate 110111, on the surface of the insulating film 110112, on the surface of the semiconductor film 110113, on the surface of 110114, and on the surface of 110115.
By oxidizing or nitriding the surface of 10116, the surface of the insulating film 110118, or the surface of the insulating film 110119 using plasma treatment, the semiconductor film or the insulating film can be oxidized or nitrided. In this way, the surface of the semiconductor film or the insulating film is modified by oxidizing or nitriding the semiconductor film or the insulating film using plasma treatment, and C
Since a denser insulating film can be formed as compared with an insulating film formed by a VD method or a sputtering method, defects such as pinholes can be suppressed and characteristics of the semiconductor device can be improved.

First, the surface of the substrate 110111 is cleaned using hydrofluoric acid (HF), alkali, or pure water. As the substrate 110111, a glass substrate such as barium borosilicate glass or alumino borosilicate glass, a quartz substrate, a ceramic substrate, a metal substrate including stainless steel, or the like can be used. In addition, polyethylene terephthalate (PET), polyethylene naphthalate (
It is also possible to use a substrate made of a plastic such as PEN) or polyethersulfone (PES) or a flexible synthetic resin such as acrylic. Note that here, a case where a glass substrate is used as the substrate 110111 is described.

Here, an oxide film or a nitride film may be formed on the surface of the substrate 110111 by performing plasma treatment on the surface of the substrate 110111 to oxidize or nitride the surface of the substrate 110111 (FIG. 102B). . Hereinafter, an insulating film such as an oxide film or a nitride film formed by performing plasma processing on the surface is also referred to as a plasma processing insulating film. In FIG. 102B, the insulating film 110131 is a plasma processing insulating film. In general, when a semiconductor element such as a thin film transistor is provided on a substrate such as glass or plastic, an impurity element such as alkali metal or alkaline earth metal such as Na contained in glass or plastic is mixed in the semiconductor element. Contamination may affect the characteristics of the semiconductor element. However, by nitriding the surface of a substrate made of glass or plastic, it is possible to prevent an impurity element such as an alkali metal or an alkaline earth metal such as Na contained in the substrate from entering the semiconductor element.

Note that when the surface is oxidized by plasma treatment, an oxygen atmosphere (eg, oxygen (O ₂
) And a rare gas (including at least one of He, Ne, Ar, Kr, and Xe) atmosphere, oxygen and hydrogen (H ₂ ) and a rare gas atmosphere, or dinitrogen monoxide and a rare gas atmosphere. ) Plasma treatment. On the other hand, in the case of nitriding a semiconductor film by plasma treatment, in a nitrogen atmosphere (for example, an atmosphere containing nitrogen (N ₂ ) and a rare gas (including at least one of He, Ne, Ar, Kr, and Xe), or Plasma treatment is performed in an atmosphere of nitrogen, hydrogen, and a rare gas, or NH ₃ and a rare gas. As the rare gas, for example, Ar can be used. Alternatively, a gas in which Ar and Kr are mixed may be used. Therefore, the plasma processing insulating film includes a rare gas (including at least one of He, Ne, Ar, Kr, and Xe) used for the plasma processing. For example, when Ar is used, Ar is contained in the plasma processing insulating film.

In the plasma treatment, the electron density is 1 × 10 ¹¹ cm ⁻³ in the gas atmosphere.
1 × 10 ¹³ cm ⁻³ or less and the plasma electron temperature is 0.5 ev or more and 1.5 eV.
It is preferred to do the following. Since the electron density of the plasma is high and the electron temperature in the vicinity of the object to be processed is low, damage to the object to be processed by the plasma can be prevented. In addition, since the electron density of plasma is as high as 1 × 10 ¹¹ cm ⁻³ or more, an oxide or a nitride film formed by oxidizing or nitriding an irradiation object using plasma treatment is C
Compared with a film formed by a VD method, a sputtering method, or the like, a film having excellent uniformity in film thickness and the like can be formed. Alternatively, since the electron temperature of plasma is as low as 1 eV or less, oxidation or nitridation can be performed at a lower temperature than conventional plasma treatment or thermal oxidation. For example, even if the plasma treatment is performed at a temperature that is 100 degrees or more lower than the strain point temperature of the glass substrate, the oxidation or nitriding treatment can be sufficiently performed. Note that a high frequency such as a microwave (2.45 GHz) can be used as a frequency for forming plasma. Note that the plasma treatment is performed using the above conditions unless otherwise specified.

Note that FIG. 102B illustrates the case where a plasma treatment insulating film is formed by performing plasma treatment on the surface of the substrate 110111; however, in this embodiment, the substrate 1101 is formed.
11 also includes a case where a plasma treatment insulating film is not formed on the surface of 11.

Note that in FIGS. 102C to 102G, a plasma treatment insulating film formed by performing plasma treatment on the surface of an object to be processed is not illustrated, but in this embodiment mode, a substrate 1 is used.
10111, insulating film 110112, semiconductor films 110113, 110114, 110115
Including the case where a plasma treatment insulating film formed by performing plasma treatment exists on the surface of the insulating film 110116, the insulating film 110118, or the insulating film 110119.

Next, an insulating film 110112 is formed over the substrate 110111 by a known means (a sputtering method, an LPCVD method, a plasma CVD method, or the like) (FIG. 102C). As the insulating film 110112, silicon oxide (SiOx) or silicon oxynitride (SiOxNy) (x> y) can be used.

Here, the plasma treatment insulating film may be formed on the surface of the insulating film 110112 by performing plasma treatment on the surface of the insulating film 110112 and oxidizing or nitriding the insulating film 110112. By oxidizing the surface of the insulating film 110112, the surface of the insulating film 110112 can be modified to obtain a dense film with few defects such as pinholes. Insulating film 110
By oxidizing the surface of 112, a plasma processing insulating film having a low N atom content can be formed. Therefore, when a semiconductor film is provided on the plasma processing insulating film, the interface characteristics between the plasma processing insulating film and the semiconductor film are improves. The plasma processing insulating film contains a rare gas (including at least one of He, Ne, Ar, Kr, and Xe) used for the plasma processing. In addition,
The plasma treatment can be similarly performed under the above-described conditions.

Next, island-shaped semiconductor films 110113 and 110114 are formed over the insulating film 110112 (
FIG. 102 (D)). The island-shaped semiconductor films 110113 and 110114 are formed of the insulating film 110112.
On top of the silicon (using sputtering method, LPCVD method, plasma CVD method, etc.)
An amorphous semiconductor film is formed using a material containing Si) as a main component (for example, SixGe1-x), and the amorphous semiconductor film is crystallized, and the semiconductor film is selectively etched. be able to. The crystallization of the amorphous semiconductor film may be performed by laser crystallization, thermal crystallization using an RTA or furnace annealing furnace, thermal crystallization using a metal element that promotes crystallization, or a combination of these methods. It can carry out by the well-known crystallization method. Note that here, the end portion of the island-shaped semiconductor film is provided in a shape close to a right angle (θ = 85 to 100 °).
Alternatively, the semiconductor film 110114 serving as a low-concentration drain region may be formed by doping impurities using a mask.

Here, the surface of the semiconductor films 110113 and 110114 is subjected to plasma treatment, and the semiconductor film 1
By oxidizing or nitriding the surfaces of 10113 and 110114, the semiconductor film 1101 is obtained.
A plasma treatment insulating film may be formed on the surfaces of the 13,110114. For example, the semiconductor film 1
When Si is used for 10113 and 110114, silicon oxide (SiOx) or silicon nitride (SiNx) is formed as the plasma processing insulating film. Alternatively, the semiconductor films 110113 and 110114 may be oxidized by plasma treatment and then nitrided by performing plasma treatment again. In this case, silicon oxide (SiOx) is formed in contact with the semiconductor films 110113 and 110114, and silicon nitride oxide (SiNxOy) (SiNxOy) (
x> y) is formed. Note that in the case where the semiconductor film is oxidized by plasma treatment, in an oxygen atmosphere (for example, an atmosphere of oxygen (O ₂ ) and a rare gas (including at least one of He, Ne, Ar, Kr, and Xe), or Plasma treatment is performed with oxygen and hydrogen (H ₂ ) in a rare gas atmosphere or dinitrogen monoxide and a rare gas atmosphere. On the other hand, when a semiconductor film is nitrided by plasma treatment, nitrogen (N ₂ ) and a rare gas (He, Ne, Ar, Kr, for example)
, Xe), an atmosphere, nitrogen, hydrogen, rare gas atmosphere or NH ₃ and rare gas atmosphere). As the rare gas, for example, Ar can be used. A gas in which Ar and Kr are mixed may be used. Therefore, the plasma processing insulating film includes a rare gas (including at least one of He, Ne, Ar, Kr, and Xe) used for the plasma processing. For example, when Ar is used, A is used for the plasma processing insulating film.
r is included.

Next, an insulating film 110116 is formed (FIG. 102E). The insulating film 110116 is formed using a known means (a sputtering method, an LPCVD method, a plasma CVD method, or the like) using silicon oxide (SiO 2
x), a single layer structure of an insulating film containing oxygen or nitrogen, such as silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x> y), silicon nitride oxide (SiNxOy) (x> y), or a laminate thereof It can be provided in a structure. Note that in the case where a plasma treatment insulating film is formed on the surfaces of the semiconductor films 110113 and 110114 by performing plasma treatment on the surfaces of the semiconductor films 110113 and 110114, the plasma treatment insulating film can be used as the insulating film 110116. .

Here, the plasma treatment insulating film may be formed on the surface of the insulating film 110116 by performing plasma treatment on the surface of the insulating film 110116 and oxidizing or nitriding the surface of the insulating film 110116. Note that the plasma treatment insulating film is formed of a rare gas (He, Ne) used for the plasma treatment.
, Ar, Kr, and Xe). Further, the plasma treatment can be similarly performed under the above-described conditions.

Alternatively, the insulating film 110116 may be oxidized by performing plasma treatment once in an oxygen atmosphere and then nitrided by performing plasma treatment again in a nitrogen atmosphere. In this manner, by performing plasma treatment on the insulating film 110116 and oxidizing or nitriding the surface of the insulating film 110116, the surface of the insulating film 110116 can be modified and a dense film can be formed. An insulating film obtained by performing plasma treatment is denser and has fewer defects such as pinholes than an insulating film formed by a CVD method or a sputtering method, so that characteristics of the thin film transistor can be improved.

Next, the gate electrode 110117 is formed (FIG. 102F). Gate electrode 110117
Can be formed using known means (sputtering, LPCVD, plasma CVD, etc.).

In 110101, by performing impurity doping after forming the gate electrode 110117, the semiconductor film 110115 used as a source region and a drain region can be formed.

In 110102, by performing impurity doping after the gate electrode 110117 is formed, a semiconductor film 110115 used as an LDD region and a semiconductor film 110115 used as a semiconductor film source region and a drain region can be formed.

In 110103, impurity doping is performed after the gate electrode 110117 is formed, so that a semiconductor film 110115 used as an LDD region and a semiconductor film 110115 used as a semiconductor film source region and a drain region can be formed.

110104, sidewalls 110121 are formed on the side surfaces of the gate electrode 110117.
110114 is used as an LDD region by impurity doping.
Thus, a semiconductor film 110115 used as a semiconductor film source region and a drain region can be formed.

Note that the sidewall 110121 is formed of silicon oxide (SiOx) or silicon nitride (SiNx).
) Can be used. As a method of forming the side wall 110121 on the side surface of the gate electrode 110117, for example, after forming the gate electrode 110117, a silicon oxide (SiOx) or silicon nitride (SiNx) film is formed by a known method, and then anisotropic. A method of etching a silicon oxide (SiOx) or silicon nitride (SiNx) film by etching can be used. Thus, silicon oxide (only on the side surface of the gate electrode 110117)
Since the SiOx) or silicon nitride (SiNx) film can be left, the gate electrode 1101
Sidewalls 110121 can be formed on 17 side surfaces.

In 110105, a mask 110122 is formed so as to cover the gate electrode 110117, and then impurity doping is performed to use as an LDD (Loff) region 11.
0114 and a semiconductor film 110115 used as a semiconductor film source region and drain region
Can be formed.

In 110106, by performing impurity doping after forming the gate electrode 110117, a semiconductor film 110115 used as an LDD (Lov) region and a semiconductor film 110115 used as a semiconductor film source region and a drain region can be formed.

Next, an insulating film 110118 is formed (FIG. 102G). The insulating film 110118 is formed by known means (sputtering method, plasma CVD method, or the like) using silicon oxide (SiOx) or silicon nitride (
SiNx), silicon oxynitride (SiOxNy) (x> y), silicon nitride oxide (SiNxOy)
(X> y) or other insulating film containing oxygen or nitrogen or DLC (diamond-like carbon)
A single layer structure of a film containing carbon, such as a laminated structure of these films can be provided.

Here, a plasma treatment insulating film may be formed on the surface of the insulating film 110118 by performing plasma treatment on the surface of the insulating film 110118 and oxidizing or nitriding the surface of the insulating film 110118. Note that the plasma treatment insulating film is formed of a rare gas (He, Ne) used for the plasma treatment.
, Ar, Kr, and Xe). Further, the plasma treatment can be similarly performed under the above-described conditions.

Next, an insulating film 110119 is formed. The insulating film 110119 is formed by a known means (sputtering method, plasma CVD method, or the like) using silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x> y), silicon nitride oxide (SiNxOy) ( In addition to an insulating film having oxygen or nitrogen such as x> y) or a film containing carbon such as DLC (diamond-like carbon), epoxy, polyimide, polyamide, polyvinylphenol,
A single layer structure of an organic material such as benzocyclobutene or acrylic, or a siloxane resin, or a stacked structure thereof can be used. Note that a siloxane resin corresponds to a resin including a Si—O—Si bond. Siloxane has a skeleton structure formed of a bond of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (for example, an alkyl group or an aromatic hydrocarbon) is used. A fluoro group can also be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as a substituent. The plasma processing insulating film contains a rare gas (including at least one of He, Ne, Ar, Kr, and Xe) used for the plasma processing. For example, when Ar is used, the plasma processing insulating film is used. Ar is contained in the film.

In the case where an organic material such as polyimide, polyamide, polyvinylphenol, benzocyclobutene, or acrylic, or a siloxane resin is used as the insulating film 110119, the insulating film 110119 is used.
The surface of the insulating film can be modified by oxidizing or nitriding the surface by plasma treatment. By modifying the surface, the strength of the insulating film 110119 is improved, and it is possible to reduce physical damage such as generation of cracks at the time of opening formation and the like and film reduction at the time of etching. In addition, when the surface of the insulating film 110119 is modified, adhesion with the conductive film is improved when the conductive film 110123 is formed over the insulating film 110119.
For example, in the case where siloxane resin is used as the insulating film 110119 and nitridation is performed using plasma treatment, the surface of the siloxane resin is nitrided, so that a plasma treatment insulating film containing nitrogen or a rare gas is formed, and the physical strength is increased. improves.

Next, in order to form the conductive film 110123 electrically connected to the semiconductor film 110115,
Contact holes are formed in the insulating film 110119, the insulating film 110118, and the insulating film 110116. Note that the shape of the contact hole may be tapered. By doing this,
The coverage of the conductive film 110123 can be improved.

Note that this embodiment can be freely combined with any of the other embodiments.

In addition, the content of each figure in this embodiment can be implemented in combination freely with the content of other figures.

(Embodiment 14)
In this embodiment, a detailed structure of a light-emitting element that can be applied to a display device in which this embodiment can be implemented will be described.

A light-emitting element utilizing electroluminescence is distinguished depending on whether the light-emitting material is an organic compound or an inorganic compound. Generally, the former is called an organic EL element and the latter is called an inorganic EL element.

Inorganic EL elements are classified into a dispersion-type inorganic EL element and a thin-film inorganic EL element depending on the element structure. The former has an electroluminescent layer in which particles of a luminescent material are dispersed in a binder, and the latter has an electroluminescent layer made of a thin film of luminescent material, but is accelerated by a high electric field. This is common in that it requires more electrons. Note that the obtained light emission mechanism includes donor-acceptor recombination light emission using a donor level and an acceptor level, and localized light emission using inner-shell electron transition of a metal ion. Generally, in the dispersion type inorganic EL, a donor-
In many cases, acceptor recombination light emission and thin-film inorganic EL elements emit localized light.

A light-emitting material that can be used in this embodiment mode includes a base material and an impurity element that serves as a light-emission center. By changing the impurity element to be contained, light emission of various colors can be obtained. As a method for manufacturing the light-emitting material, various methods such as a solid phase method and a liquid phase method (coprecipitation method) can be used. Alternatively, a spray pyrolysis method, a metathesis method, a precursor thermal decomposition method, a reverse micelle method, a method combining these methods with high-temperature firing, a liquid phase method such as a freeze-drying method, or the like can also be used.

In the solid phase method, a base material and an impurity element or a compound containing an impurity element are weighed and mixed in a mortar.
This is a method in which an impurity element is contained in the base material by reacting by heating and baking in an electric furnace. The firing temperature is preferably 700 to 1500 ° C. This is because the solid phase reaction does not proceed when the temperature is too low, and the base material is decomposed when the temperature is too high. In addition, although baking may be performed in a powder state, it is preferable to perform baking in a pellet state. Although firing at a relatively high temperature is required, it is a simple method, so it has high productivity and is suitable for mass production.

The liquid phase method (coprecipitation method) is a method in which a base material or a compound containing the base material and an impurity element or a compound containing the impurity element are reacted in a solution, dried, and then fired. The particles of the luminescent material are uniformly distributed, and the reaction can proceed even at a low firing temperature with a small particle size.

As a base material used for the light-emitting material, sulfide, oxide, or nitride can be used.
Examples of the sulfide include zinc sulfide (ZnS), cadmium sulfide (CdS), calcium sulfide (CaS), yttrium sulfide (Y ₂ S ₃ ), gallium sulfide (Ga ₂ S ₃ ), strontium sulfide (SrS), sulfide. Barium (BaS) or the like can be used. As the oxide, for example, zinc oxide (ZnO), yttrium oxide (Y ₂ O ₃ ), or the like can be used. As the nitride, for example, aluminum nitride (AlN), gallium nitride (GaN), indium nitride (InN), or the like can be used. Furthermore, zinc selenide (ZnSe), zinc telluride (ZnTe), and the like can also be used, and calcium sulfide-gallium sulfide (CaGa ₂ S ₄ ), strontium sulfide-gallium sulfide (SrGa ₂ S ₄ ), barium sulfide-gallium (BaGa). _It may be a ternary mixed crystal such as ₂ S ₄ ).

As the emission center of localized emission, manganese (Mn), copper (Cu), samarium (Sm), terbium (Tb), erbium (Er), thulium (Tm), europium (Eu), cerium (Ce), praseodymium (Pr) or the like can be used. Note that a halogen element such as fluorine (F) or chlorine (Cl) may be added as charge compensation.

On the other hand, as a light emission center of donor-acceptor recombination light emission, a first donor level is formed.
And a light-emitting material including a second impurity element which forms an acceptor level. As the first impurity element, for example, fluorine (F), chlorine (Cl), aluminum (Al), or the like can be used. As the second impurity element, for example, copper (Cu),
Silver (Ag) or the like can be used.

In the case where a light-emitting material for donor-acceptor recombination light emission is synthesized using a solid-phase method, a base material, a first impurity element or a compound containing the first impurity element, a second impurity element, or a second impurity element
Each of the compounds containing the impurity element is weighed and mixed in a mortar, and then heated and fired in an electric furnace. As the base material, the above-described base material can be used, and examples of the first impurity element or the compound containing the first impurity element include fluorine (F), chlorine (Cl), and aluminum sulfide (Al ₂ S). ₃ ) or the like, and examples of the second impurity element or the compound containing the second impurity element include copper (Cu), silver (Ag), copper sulfide (Cu ₂ S), and silver sulfide (Ag). ₂ S) or the like can be used. The firing temperature is preferably 700 to 1500 ° C.
This is because the solid phase reaction does not proceed when the temperature is too low, and the base material is decomposed when the temperature is too high. In addition, although baking may be performed in a powder state, it is preferable to perform baking in a pellet state.

In addition, as an impurity element in the case of using a solid phase reaction, a compound including a first impurity element and a second impurity element may be used in combination. In this case, since the impurity element is easily diffused and the solid-phase reaction easily proceeds, a uniform light emitting material can be obtained. Further, since no extra impurity element is contained, a light-emitting material with high purity can be obtained. As the compound including the first impurity element and the second impurity element, for example, copper chloride (CuCl), silver chloride (AgCl), or the like can be used.

Note that the concentration of these impurity elements may be 0.01 to 10 atom% with respect to the base material, and is preferably in the range of 0.05 to 5 atom%.

In the case of a thin film type inorganic EL, the electroluminescent layer is a layer containing the light emitting material,
Vacuum vapor deposition methods such as electron beam evaporation (EB vapor deposition), physical vapor deposition methods such as sputtering (
Chemical vapor deposition (CV) such as PVD), metal organic chemical vapor deposition, hydride transport low pressure CVD
D), an atomic epitaxy method (ALE), or the like.

FIGS. 103A to 103C illustrate an example of a thin-film inorganic EL element that can be used as a light-emitting element. 103A to 103C, the light-emitting element includes the first electrode layer 120100.
, An electroluminescent layer 120102, and a second electrode layer 120103.

A light-emitting element illustrated in FIGS. 103B and 103C has a structure in which an insulating layer is provided between the electrode layer and the electroluminescent layer in the light-emitting element in FIG. 103A. A light-emitting element illustrated in FIG. 103B includes an insulating layer 120104 between the first electrode layer 120100 and the electroluminescent layer 120102, and the light-emitting element illustrated in FIG. 103C includes the first electrode layer 120100. And electroluminescent layer 120
102, an insulating layer 120105, a second electrode layer 120103, and an electroluminescent layer 12010
2 and an insulating layer 120106. Thus, the insulating layer may be provided only between one of the pair of electrode layers sandwiching the electroluminescent layer, or may be provided between both. Also,
The insulating layer may be a single layer or a stacked layer including a plurality of layers.

Note that in FIG. 103B, the insulating layer 120104 is in contact with the first electrode layer 120100.
The second electrode layer 120103 is formed by reversing the order of the insulating layer and the electroluminescent layer.
An insulating layer 120104 may be provided in contact with the insulating layer 120104.

In the case of a dispersion-type inorganic EL, a particulate luminescent material is dispersed in a binder to form a film-like electroluminescent layer. Process into particles. When particles having a desired size cannot be obtained sufficiently by the method for manufacturing a light emitting material, the particles may be processed into particles by pulverization or the like in a mortar or the like. What is a binder?
It is a substance for fixing a granular luminescent material in a dispersed state and maintaining the shape as an electroluminescent layer. The light emitting material is uniformly dispersed and fixed in the electroluminescent layer by the binder.

In the case of a dispersion-type inorganic EL, the electroluminescent layer can be formed by a droplet discharge method capable of selectively forming an electroluminescent layer, a printing method (screen printing, offset printing, etc.), a coating method such as a spin coating method, dipping, etc. It is also possible to use a method or a dispenser method. The film thickness is not particularly limited, but is preferably in the range of 10 to 1000 nm. In the electroluminescent layer including the light emitting material and the binder, the ratio of the light emitting material may be 50 wt% or more and 80 wt% or less.

104A to 104C illustrate an example of a dispersion-type inorganic EL element that can be used as a light-emitting element. A light-emitting element in FIG. 104A has a stacked structure of a first electrode layer 120200, an electroluminescent layer 120202, and a second electrode layer 120203, and a light-emitting material 120201 held by a binder in the electroluminescent layer 120202. Including.

As a binder that can be used in this embodiment mode, an insulating material can be used. As the insulating material, an organic material and an inorganic material can be used. Alternatively, a mixed material of an organic material and an inorganic material may be used. As the organic insulating material, a polymer having a relatively high dielectric constant such as a cyanoethyl cellulose resin, or a resin such as polyethylene, polypropylene, polystyrene resin, silicone resin, epoxy resin, or vinylidene fluoride can be used. Alternatively, aromatic polyamide, polybenzimidazole (polybenzzi)
A heat-resistant polymer such as midazole) or a siloxane resin may be used. Note that a siloxane resin corresponds to a resin including a Si—O—Si bond. Siloxane has a skeleton structure formed of a bond of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (for example, an alkyl group or an aromatic hydrocarbon) is used. A fluoro group may be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as a substituent. Alternatively, a resin material such as a vinyl resin such as polyvinyl alcohol or polyvinyl butyral, a phenol resin, a novolac resin, an acrylic resin, a melamine resin, a urethane resin, or an oxazole resin (polybenzoxazole) may be used. These resins include barium titanate (BaTiO ₃ ) and strontium titanate (SrTiO ₃ ).
The dielectric constant can be adjusted by appropriately mixing fine particles having a high dielectric constant such as).

Examples of the inorganic insulating material contained in the binder include silicon oxide (SiOx) and silicon nitride (SiNx).
), Silicon containing oxygen and nitrogen, aluminum nitride (AlN), aluminum containing oxygen and nitrogen, aluminum oxide containing oxygen and nitrogen (Al ₂ O ₃ ), titanium oxide (TiO ₂ )
, BaTiO ₃ , SrTiO ₃ , lead titanate (PbTiO ₃ ), potassium niobate (KN)
bO ₃ ), lead niobate (PbNbO ₃ ), tantalum oxide (Ta ₂ O ₅ ), barium tantalate (BaTa ₂ O ₆ ), lithium tantalate (LiTaO ₃ ), yttrium oxide (Y
₂ O ₃ ), zirconium oxide (ZrO ₂ ), ZnS, and other materials including inorganic insulating materials. By including an inorganic material having a high dielectric constant in the organic material (by addition or the like), the dielectric constant of the electroluminescent layer made of the light emitting material and the binder can be further controlled, and the dielectric constant can be further increased. .

In the manufacturing process, the light-emitting material is dispersed in a solution containing a binder. As a solvent of a solution containing a binder that can be used in this embodiment mode, a method of forming an electroluminescent layer by dissolving a binder material (various wet processes) and a solution having a viscosity suitable for a desired film thickness can be manufactured. Such a solvent may be appropriately selected. For example, an organic solvent or the like can be used as the solvent. When a siloxane resin is used as the binder, propylene glycol monomethyl ether, propylene glycol monomethyl ether acetate (also referred to as PGMEA)
, 3-methoxy-3-methyl-1-butanol (also referred to as MMB) or the like can be used as a solvent.

104B and 104C each have a structure in which an insulating layer is provided between the electrode layer and the electroluminescent layer in the light-emitting element in FIG. 104A. 104B includes an insulating layer 120204 between the first electrode layer 120200 and the electroluminescent layer 120202. The light-emitting element illustrated in FIG. 104C includes the first electrode layer 120200. And electroluminescent layer 120
202 between the insulating layer 120205, the second electrode layer 120203, and the electroluminescent layer 12020.
2 and an insulating layer 120206. Thus, the insulating layer may be provided only between one of the pair of electrode layers sandwiching the electroluminescent layer, or may be provided between both. The insulating layer may be a single layer or a stacked layer having a plurality of layers.

In FIG. 104B, the insulating layer 120204 is in contact with the first electrode layer 120200.
The second electrode layer 120203 is formed by reversing the order of the insulating layer and the electroluminescent layer.
An insulating layer 120204 may be provided so as to be in contact with each other.

A material that can be used for the insulating layers such as the insulating layer 120104 in FIG. 103 and the insulating layer 120204 in FIG. 104 preferably has high insulation resistance and a dense film quality.
Furthermore, it is preferable that the dielectric constant is high. For example, silicon oxide (SiO ₂ ), yttrium oxide (Y ₂ O ₃ ), titanium oxide (TiO ₂ ), aluminum oxide (Al ₂ O ₃ ), hafnium oxide (HfO ₂ ), tantalum oxide (Ta ₂ O ₅ ), Barium titanate (BaTi
O ₃ ), strontium titanate (SrTiO ₃ ), lead titanate (PbTiO ₃ ), silicon nitride (Si ₃ N ₄ ), zirconium oxide (ZrO ₂ ), etc., a mixed film thereof, or a laminated film of two or more kinds is used. be able to. These insulating films can be formed by sputtering, vapor deposition, CVD, or the like. The insulating layer may be formed by dispersing particles of these insulating materials in a binder. The binder material may be formed using the same material and method as the binder contained in the electroluminescent layer. The film thickness is not particularly limited, but preferably 10 to 10
The range is 00 nm.

The light-emitting element described in this embodiment can emit light by applying a voltage between a pair of electrode layers sandwiching an electroluminescent layer, but can operate in either direct current drive or alternating current drive.

Note that this embodiment can be freely combined with any of the other embodiments.

In addition, the content of each figure in this embodiment can be implemented in combination freely with the content of other figures.

(Embodiment 15)
In this embodiment, an example of a display device that can implement this embodiment, particularly a case of optical handling will be described.

A rear projection display device 130100 shown in FIGS. 105A and 105B includes a projector unit 130111, a mirror 130112, and a screen panel 130101.
In addition, a speaker 130102 and operation switches 130104 may be provided. The projector unit 130111 includes a housing 130 of the rear projection display device 130100.
The projection light which is arrange | positioned under 110 and projects an image | video based on a video signal is mirror 13011.
Project toward 2 The rear projection display device 130100 includes a screen panel 130101.
It is the structure which displays the image | video projected from the back.

On the other hand, FIG. 106 shows a front projection display device 130200. The front projection display device 130200 includes a projector unit 130111 and a projection optical system 130201. The projection optical system 130201 is configured to project an image on a screen or the like disposed on the front surface.

The configuration of the projector unit 130111 applied to the rear projection display device 130100 shown in FIG. 105 and the front projection display device 130200 shown in FIG. 106 will be described below.

FIG. 107 shows a configuration example of the projector unit 130111. The projector unit 130111 includes a light source unit 130301 and a modulation unit 13030.
4 is provided. The light source unit 130301 includes a light source optical system 130303 including lenses and a light source lamp 130302. The light source lamp 130302 is housed in the housing so that stray light does not diffuse. As the light source lamp 130302, for example, a high-pressure mercury lamp or a xenon lamp capable of emitting a large amount of light is used. The light source optical system 130303 is configured by appropriately providing an optical lens, a film having a polarization function, a film for adjusting a phase difference, an IR film, and the like. The light source unit 130301
Are arranged such that the emitted light is incident on the modulation unit 130304. The modulation unit 130304 includes a plurality of display panels 130308, a color filter, a dichroic mirror 130305, a total reflection mirror 130306, a prism 130309, and the projection optical system 13.
0310. Light emitted from the light source unit 130301 is separated into a plurality of optical paths by the dichroic mirror 130305.

Each optical path is provided with a color filter that transmits light of a predetermined wavelength or wavelength band, and a display panel 130308. A transmissive display panel 130308 modulates transmitted light based on a video signal. The light of each color transmitted through the display panel 130308 is reflected by the prism 13.
0309 is entered, and an image is displayed on the screen through the projection optical system 130310. A Fresnel lens may be disposed between the mirror and the screen. The projection light projected by the projector unit 130111 and reflected by the mirror is converted into substantially parallel light by the Fresnel lens and projected onto the screen.

A projector unit 130111 shown in FIG. 108 includes a reflective display panel 130407.
, 130408, 130409 are shown.

A projector unit 130111 shown in FIG. 108 includes a light source unit 130301 and a modulation unit 130400. The light source unit 130301 may have the same configuration as that in FIG. The light from the light source unit 130301 is emitted from the dichroic mirror 13.
Divided into a plurality of optical paths by 0401, 130402, total reflection mirror 130403,
The light enters the polarizing beam splitters 130404, 130405, and 130406. The polarizing beam splitters 130404, 130405, and 130406 are provided corresponding to the reflective display panels 130407, 130408, and 130409 corresponding to the respective colors. The reflective display panels 130407, 130408, and 130409 modulate reflected light based on the video signal. The light beams of the respective colors reflected by the reflective display panels 130407, 130408, and 130409 are combined by being incident on the prism 130309 and projected through the projection optical system 13041.

Light emitted from the light source unit 130301 is transmitted through the dichroic mirror 130401 only in the red wavelength region and reflects in the green and blue wavelength regions. Further, the dichroic mirror 130402 reflects only light in the green wavelength region. The light in the red wavelength region that has passed through the dichroic mirror 130401 is reflected by the total reflection mirror 130403 and is incident on the polarization beam splitter 130404. The light in the blue wavelength region is incident on the polarization beam splitter 130405, and the green wavelength The light in the region is polarized beam splitter 1304
Incident at 06. Polarizing beam splitters 130404, 130405, 130406
It has a function of separating incident light into P-polarized light and S-polarized light, and has a function of transmitting only P-polarized light. The reflective display panels 130407, 130408, and 130409 polarize incident light based on the video signal.

Only S-polarized light corresponding to each color is incident on the reflective display panels 130407, 130408, and 130409 corresponding to the respective colors. Note that the reflective display panels 130407 and 130408 are provided.
, 130409 may be a liquid crystal panel. At this time, the liquid crystal panel operates in an electric field controlled birefringence mode (ECB). The liquid crystal molecules are vertically aligned with a certain angle with respect to the substrate. Accordingly, the display molecules of the reflective display panels 130407, 130408, and 130409 are oriented so that they are reflected without changing the polarization state of incident light when the pixel is in the off state. Further, when the pixel is in the ON state, the orientation state of the display molecules changes, and the polarization state of incident light changes.

A projector unit 130111 shown in FIG. 108 can be applied to the rear projection display device 130100 shown in FIG. 105 and the front projection display device 130200 shown in FIG.

The projector unit shown in FIG. 109 has a single-plate configuration. A projector unit 130111 shown in FIG. 109A includes a light source unit 130301 and a display panel 1.
30507, a projection optical system 130511, and a phase difference plate 130504 are provided. The projection optical system 130511 includes one or a plurality of lenses. The display panel 130507 may be provided with a color filter.

FIG. 109B shows a projector unit 1 that operates in a field sequential manner.
30111 is shown. The field sequential method is a method in which light of each color such as red, green, and blue is temporally shifted and sequentially incident on a display panel to perform color display without a color filter. In particular, when combined with a display panel having a high response speed with respect to input signal changes, a high-definition image can be displayed. In FIG. 109B, a rotary color filter plate 130505 provided with a plurality of color filters such as red, green, and blue is provided between the light source unit 130301 and the display panel 130508.

A projector unit 130111 shown in FIG. 109C shows a configuration of a color separation method using a macro lens as a color display method. In this method, a microlens array 130506 is provided on the light incident side of the display panel 130509, and color display is realized by illuminating light of each color from each direction. The projector unit 130111 that employs this method has a feature that light from the light source unit 130301 can be effectively used because light loss due to the color filter is small. FIG.
The projector unit 130111 shown in FIG. 9C includes a dichroic mirror 130501, a dichroic mirror 130502, and a dichroic mirror for red light 130503 so as to illuminate the display panel 130509 with light of each color from each direction.

Note that this embodiment can be freely combined with any of the other embodiments.

In addition, the content of each figure in this embodiment can be implemented in combination freely with the content of other figures.

(Embodiment 16)
In this embodiment, an example of an electronic device according to this embodiment will be described.

FIG. 110 shows a display panel module in which a display panel 900101 and a circuit board 900111 are combined. A display panel 900101 includes a pixel portion 900102, a scan line driver circuit 900103, and a signal line driver circuit 900104. On the circuit board 900111, for example, a control circuit 900112 and a signal dividing circuit 900113 are formed. The display panel 900101 and the circuit board 900111 are connected by a connection wiring 900114. An FPC or the like can be used for the connection wiring.

In the display panel 900101, a pixel portion 900102 and a part of peripheral driver circuits (a driver circuit having a low operating frequency among a plurality of driver circuits) are integrally formed using a TFT over a substrate, and a part of the peripheral driver circuits (a plurality of peripheral driver circuits A driver circuit having a high operating frequency among driver circuits) may be formed over an IC chip, and the IC chip may be mounted on the display panel 900101 using COG (Chip On Glass) or the like. Thus, the area of the circuit board 900111 can be reduced, and a small display device can be obtained. Alternatively, the IC chip is TAB (Tape Auto B).
mounting) or a printed circuit board, the display panel 900101 may be mounted. Thus, the area of the display panel 900101 can be reduced, so that a display device with a small frame size can be obtained.

For example, in order to reduce power consumption, a pixel portion is formed using a TFT on a glass substrate, all peripheral drive circuits are formed on an IC chip, and the IC chip is mounted on a display panel by COG or TAB. May be.

A television receiver can be completed with the display panel module illustrated in FIG. FIG. 111 is a block diagram illustrating a main configuration of a television receiver. Tuner 9002
01 receives a video signal and an audio signal. The video signal includes a video signal amplification circuit 900202,
A video signal processing circuit 900203 that converts a signal output from the video signal amplifier circuit 900202 into a color signal corresponding to each color of red, green, and blue, and a control circuit 900212 for converting the video signal into input specifications of the drive circuit. It is processed by. Control circuit 9002
12 outputs signals to the scanning line side and the signal line side, respectively. In the case of digital driving, a signal dividing circuit 900213 may be provided on the signal line side, and an input digital signal may be divided into m pieces (m is a positive integer) and supplied.

Of the signals received by the tuner 900201, the audio signal is the audio signal amplifier circuit 900205.
The output is supplied to the speaker 900207 through the audio signal processing circuit 900206. The control circuit 900208 receives the receiving station (reception frequency) and volume control information from the input unit 9.
In response to the received signal from the signal E00209, a signal is transmitted to the tuner 900201 and the audio signal processing circuit 900206.

FIG. 112A illustrates a television receiver in which a display panel module different from that in FIG. 111 is incorporated. In FIG. 112A, a display screen 900302 housed in a housing 900301 is formed using a display panel module. Speaker 90030
3. An operation switch 900304 or the like may be provided as appropriate.

FIG. 112B illustrates a television receiver that can carry only a display wirelessly. A housing 900312 includes a battery and a signal receiver, and the display portion 900313 and the speaker portion 900317 are driven by the battery. The battery can be repeatedly charged with a charger 900310. The charger 900310 can transmit and receive a video signal, and can transmit the video signal to a signal receiver of the display. The housing 900312 is controlled by operation keys 900316. Alternatively, FIG.
The apparatus illustrated in FIG. 12B operates the operation key 900316 to operate the housing 9003.
12 may be a video / audio two-way communication device capable of sending a signal from the charger 12 to the charger 900310. Alternatively, the housing 9003 is operated by operating the operation key 900316.
12 may be a general-purpose remote control device capable of controlling communication of other electronic devices by sending a signal to charger 900310 from 12 and causing other electronic devices to receive signals that can be transmitted by charger 900310. . This embodiment can be applied to the display portion 900313.

FIG. 113A illustrates a module in which a display panel 900401 and a printed wiring board 900402 are combined. A display panel 900401 includes a pixel portion 900403 provided with a plurality of pixels, a first scan line driver circuit 900404, and a second scan line driver circuit 9004.
And a signal line driver circuit 900406 for supplying a video signal to the selected pixel.

A printed wiring board 900402 includes a controller 900407, a central processing unit (CPU
) 940408, memory 900409, power supply circuit 900410, audio processing circuit 90041
1 and a transmission / reception circuit 900412 and the like. The printed wiring board 900402 and the display panel 900401 are connected by a flexible wiring board (FPC) 900413. The printed wiring board (FPC) 900413 may be provided with a storage capacitor, a buffer circuit, and the like to prevent noise from being applied to the power supply voltage and the signal and the rise of the signal from being slow. Further, the controller 900407, the audio processing circuit 9000041, the memory 900409, the central processing unit (CPU) 900408, the power supply circuit 900410, and the like can be mounted on the display panel 900401 using a COG (Chip On Glass) method. The scale of the printed wiring board 900402 can be reduced by the COG method.

Interface (I / F) unit 900414 provided on the printed circuit board 900402
Various control signals are input and output via the. Further, an antenna port 900415 for transmitting and receiving signals to and from the antenna is provided on the printed wiring board 900402.

FIG. 113B shows a block diagram of the module shown in FIG. This module includes a VRAM 900416, a DRAM 9000041, a flash memory 900418, and the like as the memory 900409. The VRAM 900416 stores image data to be displayed on the panel, the DRAM 900417 stores image data or audio data, and the flash memory stores various programs.

The power supply circuit 900410 supplies power for operating the display panel 900401, the controller 900407, the central processing unit (CPU) 9000040, the sound processing circuit 9000041, the memory 9000040, and the transmission / reception circuit 9000041. Depending on the panel specifications, the power supply circuit 900410 may be provided with a current source.

A central processing unit (CPU) 9000040 includes a control signal generation circuit 900420 and a decoder 90.
0421, a register 900422, an arithmetic circuit 90000423, a RAM 900394, an interface 900419 for a central processing unit (CPU) 900408, and the like. Various signals input to the central processing unit (CPU) 9000040 via the interface 900419 are temporarily held in the register 9000042, and then input to the arithmetic circuit 9000042, the decoder 900421, and the like. The arithmetic circuit 900423 performs an operation based on the input signal and designates a place to send various commands. On the other hand, the signal input to the decoder 900421 is decoded and input to the control signal generation circuit 900420. The control signal generation circuit 900420 generates a signal including various commands based on the input signal, and the arithmetic circuit 900
423, specifically, a memory 9000040, a transmission / reception circuit 90041
2. Send to audio processing circuit 900411, controller 900407, etc.

The memory 9000040, the transmission / reception circuit 9000041, the sound processing circuit 9000041, and the controller 900407 operate according to received commands. The operation will be briefly described below.

The signal input from the input means 9000042 is input to an interface (I / F) unit 90041
Central processing unit (CPU) 9004 mounted on a printed wiring board 900402 via 4
Sent to 08. The control signal generation circuit 900420 converts the image data stored in the VRAM 900416 into a predetermined format according to the signal sent from the input means 9000042 such as a pointing device or a keyboard, and sends it to the controller 900407.

The controller 900407 is a central processing unit (CPU) 9004 in accordance with the specifications of the panel.
Data processing is performed on a signal including image data sent from 08, and a display panel 90040 is processed.
1 is supplied. In addition, the controller 900407 is based on the power supply voltage input from the power supply circuit 900410 and various signals input from the central processing unit (CPU) 9000040.
A sync signal, a Vsync signal, a clock signal CLK, an AC voltage (AC Cont), and a switching signal L / R are generated and supplied to the display panel 900401.

In the transmission / reception circuit 9000041, a signal transmitted / received as a radio wave in the antenna 9000042 is processed. Specifically, an isolator, a band pass filter, a VCO (Volt)
age Controlled Oscillator), LPF (Low Pass)
A high frequency circuit such as a filter), a coupler, or a balun may be included. Transmission / reception circuit 90
Of the signals transmitted and received in 0412, a signal including audio information is sent to the central processing unit (CPU).
) Is sent to the audio processing circuit 900411 according to the command from 900408.

A signal including audio information sent in accordance with a command from a central processing unit (CPU) 9000040 is demodulated into an audio signal in an audio processing circuit 9000041 and is sent to a speaker 9000042. Also, the audio signal sent from the microphone 9000042 is converted into an audio processing circuit 90041.
1 and is sent to the transmission / reception circuit 900412 in accordance with a command from a central processing unit (CPU) 9000040.

Controller 9000040, central processing unit (CPU) 9000040, power supply circuit 90041
0, the audio processing circuit 900411 and the memory 9000040 can be mounted as a package of this embodiment.

Needless to say, this embodiment is not limited to a television receiver, and various uses as a display medium of a particularly large area such as a personal computer monitor, an information display board at a railway station or airport, an advertisement display board in a street, etc. Can be applied to.

Next, with reference to FIG. 114, a configuration example of the mobile phone according to the present embodiment will be described.

The display panel 900501 is incorporated in a housing 900530 so as to be detachable. The shape and size of the housing 900530 can be changed as appropriate in accordance with the size of the display panel 900501. A housing 900530 to which the display panel 900501 is fixed is fitted into the printed circuit board 900531 and assembled as a module.

The display panel 900501 is connected to the printed circuit board 900531 through the FPC 900531. A printed circuit board 900531 includes a speaker 900532 and a microphone 90.
0533, transmission / reception circuit 900534, signal processing circuit 9 including CPU and controller
00535 is formed. Such a module is combined with the input means 900566 and the battery 900577 and stored in the housing 9000053. Display panel 900501
The pixel portion is arranged so as to be visible from an opening window formed in the housing 900500.

In the display panel 900501, a pixel portion and some peripheral driver circuits (a driver circuit having a low operating frequency among a plurality of driver circuits) are integrally formed using a TFT over a substrate, and some peripheral driver circuits (a plurality of driver circuits) are formed. A driving circuit having a high operating frequency among the circuits) may be formed over an IC chip, and the IC chip may be mounted on the display panel 900501 using COG (Chip On Glass).
Alternatively, the IC chip may be connected to the glass substrate using TAB (Tape Auto Bonding) or a printed board. With such a structure, the power consumption of the display device can be reduced, and the usage time by one charge of the mobile phone can be extended. In addition, the cost of the mobile phone can be reduced.

115 includes an operation switch 9000060, a microphone 90, and the like.
A main body (A) 900601 provided with 0605 and the like, a display panel (A) 900608,
A main body (B) 9 provided with a display panel (B) 900609, a speaker 9000060, etc.
00602 is connected by a hinge 900610 so that it can be opened and closed. Display panel (A) 90
0608 and the display panel (B) 900609 together with the circuit board 900607 are the main body (B) 9
It is housed in a case 900603 of 00602. The pixel portions of the display panel (A) 900608 and the display panel (B) 900609 are arranged so as to be visible from an opening window formed in the housing 900603.

The display panel (A) 900608 and the display panel (B) 900609
Specifications such as the number of pixels can be set as appropriate in accordance with the 0600 function. For example, the display panel (A) 900608 can be combined as a main screen and the display panel (B) 900609 can be combined as a sub-screen.

The mobile phone according to the present embodiment can be transformed into various modes depending on the function and application.
For example, a mobile phone with a camera may be provided by incorporating an image sensor at the hinge 900610. In addition, even when the operation switches 9000060, the display panel (A) 900068, and the display panel (B) 900609 are housed in one housing, the above-described effects can be obtained. Further, even when the configuration of the present embodiment is applied to an information display terminal having a plurality of display units, the same effect can be obtained.

This embodiment can be applied to various electronic devices. Specifically, it can be applied to a display portion of an electronic device. Such electronic devices include video cameras, digital cameras,
Goggle type display, navigation system, sound playback device (car audio, audio component, etc.), computer, game device, portable information terminal (mobile computer, mobile phone, portable game machine, electronic book, etc.), image provided with recording medium Playback device (specifically, a recording medium such as Digital Versatile Disc (DVD))
And a device provided with a display capable of displaying the image).

FIG. 116A shows a display, which includes a housing 900711, a supporting base 900712, a display portion 900713, and the like.

FIG. 116B shows a camera, which includes a main body 900721, a display portion 900722, and an image receiving portion 900.
723, operation key 900724, external connection port 900725, shutter 900726
Etc.

FIG. 116C illustrates a computer, which includes a main body 900731, a housing 900732, and a display portion 9.
00733, a keyboard 900734, an external connection port 900735, a pointing device 900736, and the like.

FIG. 116D illustrates a mobile computer, which includes a main body 900741 and a display portion 900742.
, Switch 900743, operation key 900744, infrared port 9000074 and the like.

FIG. 116E shows a portable image reproducing device (eg, a DVD reproducing device) provided with a recording medium.
A main body 900751, a housing 900722, a display portion (A) 900733, a display portion (B
) 90074, recording medium (DVD etc.) reading unit 900755, operation key 900756
, Speaker portion 9000075 and the like. The display portion (A) 900733 can mainly display image information, and the display portion (B) 9000075 can mainly display character information.

FIG. 116F illustrates a goggle type display, which includes a main body 900761 and a display portion 90076.
2, including an earphone 900763 and a support portion 900764.

FIG. 116G illustrates a portable game machine including a housing 900771, a display portion 900772, a speaker portion 900773, operation keys 900774, a storage medium insertion portion 900775, and the like. A portable game machine in which the display device of this embodiment is used for the display portion 900772 can express bright colors.

FIG. 116H illustrates a digital camera with a television receiving function, which includes a main body 900781, a display portion 900782, operation keys 900783, speakers 900784, and a shutter 90078.
5, an image receiving unit 9000078, an antenna 9000078, and the like.

As shown in FIGS. 116A to 116E, the electronic device according to this embodiment includes a display portion for displaying some information.

Next, an application example of the semiconductor device according to this embodiment will be described.

FIG. 117 illustrates an example in which the semiconductor device according to this embodiment is provided so as to be integrated with a building. 117 shows a housing 900810, a display portion 900811, and a remote control device 9 which is an operation portion.
And the speaker unit 900813 and the like. The semiconductor device according to the present embodiment is integrated with a building as a wall-hanging type, and can be installed without requiring a large installation space.

FIG. 118 illustrates another example in which the semiconductor device according to this embodiment is provided so as to be integrated with a building. The display panel 900901 is integrally attached to the unit bath 900902, so that the bather can view the display panel 900901. Display panel 90
0901 displays information when operated by a bather and has a function that can be used as an advertisement or entertainment means.

Note that the semiconductor device according to this embodiment can be installed not only on the side wall of the unit bus 900902 shown in FIG. 118 but also in various places. For example, it may be integrated with part of the mirror surface or the bathtub itself. At this time, the shape of the display panel 900901 may be adapted to the shape of a mirror surface or a bathtub.

FIG. 119 shows another example in which the semiconductor device according to this embodiment is provided so as to be integrated with a building. The display panel 901002 is attached so as to be curved according to the curved surface of the columnar body 901001. Here, the columnar body 901001 is described as a utility pole.

A display panel 901002 illustrated in FIG. 119 is provided at a position higher than the human viewpoint.
By installing the display panel 901002 on a building that is repeatedly forested outdoors such as an electric pole, an advertisement can be made to an unspecified number of viewers. Here, the display panel 90100
2 can easily display the same image by an external control, and can easily switch the image instantly, so that highly efficient information display and advertising effect can be expected. Further, it can be said that providing a self-luminous display element in the display panel 901002 is useful as a display medium with high visibility even at night. In addition, the display panel 90 can be installed on the utility pole.
It is easy to secure 1002 power supply means. Further, in the event of an emergency such as the occurrence of a disaster, it can also be a means for quickly and accurately transmitting information to the victims.

Note that as the display panel 901002, for example, a display panel which displays an image by providing a switching element such as an organic transistor on a film-like substrate and driving the display element can be used.

Note that in this embodiment, a wall, a columnar body, and a unit bus are taken as examples of buildings, but this embodiment is not limited to this, and the semiconductor device according to this embodiment is installed in various buildings. Can do.

Next, an example in which the semiconductor device according to this embodiment is provided so as to be integrated with a moving body is described.

FIG. 120 is a diagram showing an example in which the semiconductor device according to the present embodiment is provided integrally with an automobile. A display panel 901102 is attached integrally with a vehicle body 901101 of an automobile, and can display on-demand information on the operation of the vehicle body and information input from inside and outside the vehicle body. Moreover, you may have a navigation function.

Note that the semiconductor device according to this embodiment can be installed not only in the vehicle body 901101 shown in FIG. 120 but also in various places. For example, it may be integrated with a glass window, a door, a handle, a shift lever, a seat, a room mirror, and the like. At this time, the display panel 901
The shape of 102 may be adapted to the shape of the object to be installed.

FIG. 121 is a diagram showing an example in which the semiconductor device according to the present embodiment is provided integrally with a train car.

FIG. 121 (a) is a diagram showing an example in which a display panel 901202 is provided on the glass of a door 901201 of a train car. Compared to conventional paper advertisements, there is an advantage that labor costs required for advertisement switching are not incurred. Further, the display panel 901202 can instantaneously switch an image displayed on the display unit by an external signal.
For example, the image on the display panel can be switched for each time period when the customer class of passengers on the train changes, and a more effective advertising effect can be expected.

FIG. 121 (b) shows a glass window 901203 in addition to the glass of the door 901201 of the train car.
FIG. 5 is a diagram illustrating an example in which a display panel 901202 is provided on a ceiling 901204.
As described above, since the semiconductor device according to the present embodiment can be easily installed in a place where it has been difficult to install conventionally, an effective advertising effect can be obtained. In addition, since the semiconductor device according to this embodiment can instantaneously switch the image displayed on the display unit by an external signal, the cost and time at the time of advertisement switching can be reduced and more flexible. Advertisement operation and information transmission.

Note that the semiconductor device according to this embodiment can be installed not only in the door 901201, the glass window 901203, and the ceiling 901204 shown in FIG. 121 but also in various places. For example, it may be integrated with a strap, a seat, a rail, a floor or the like. At this time, the shape of the display panel 901202 may be adapted to the shape of what is to be installed.

FIG. 122 is a diagram illustrating an example in which the semiconductor device according to this embodiment is provided so as to be integrated with a passenger airplane.

FIG. 122 (a) shows a display panel 90130 on a ceiling 901301 above the seat of a passenger airplane.
It is the figure shown about the shape at the time of use when 2 was provided. The display panel 901302 is
A ceiling 901301 and a hinge part 901303 are attached integrally, and the passenger can view the display panel 901302 by the expansion and contraction of the hinge part 901303. A display panel 901302 can display information when operated by a passenger. Furthermore, it has a function that can be used as an advertisement or entertainment means. In addition, as shown in FIG. 122 (b), by folding the hinge portion and storing it in the ceiling 901301, safety during takeoff and landing can be considered. In addition, by turning on the display element of the display panel in an emergency, it can be used as an information transmission means and a guide light.

Note that the semiconductor device according to this embodiment can be installed not only in the ceiling 901301 illustrated in FIG. 122 but also in various places. For example, seat seats, seat tables, armrests,
It may be integrated with a window or the like. In addition, a large display panel that can be viewed simultaneously by a large number of people may be installed on the wall of the aircraft. At this time, the shape of the display panel 901302 may be adapted to the shape of the object to be installed.

In the present embodiment, the moving body is exemplified as a train car body, an automobile body, and an airplane body, but is not limited to this. A motorcycle, an automobile (including an automobile, a bus, etc.),
It can be installed on various things such as trains (including monorails, railways, etc.) and ships. Since the semiconductor device according to this embodiment can instantaneously switch the display of the display panel in the moving body by an external signal, the semiconductor device according to this embodiment is installed in the moving body. The mobile body can be used for applications such as an advertisement display board targeting a large number of unspecified customers and an information display board in the event of a disaster.

Note that this embodiment can be freely combined with any of the other embodiments.

In addition, the content of each figure in this embodiment can be implemented in combination freely with the content of other figures.

(Embodiment 17)
As described above, the present specification includes at least the following inventions.

A liquid crystal display device having a pixel having a liquid crystal element and a driving circuit. The driver circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor. This drive circuit includes at least a part of the following connection relationship. The first electrode of the first transistor is electrically connected to the fourth wiring, and the second electrode of the first transistor is electrically connected to the third wiring. The first electrode of the second transistor is electrically connected to the sixth wiring, and the second electrode of the second transistor is electrically connected to the third wiring. The first of the third transistor
Are electrically connected to the fifth wiring, the second electrode of the third transistor is electrically connected to the gate electrode of the second transistor, and the gate electrode of the third transistor is electrically connected to the seventh wiring. Is electrically connected. The first electrode of the fourth transistor is electrically connected to the sixth wiring, the second electrode of the fourth transistor is electrically connected to the gate electrode of the second transistor, and the fourth transistor The gate electrode is electrically connected to the gate electrode of the first transistor. The first electrode of the fifth transistor is electrically connected to the seventh wiring, the second electrode of the fifth transistor is electrically connected to the gate electrode of the first transistor, and the fifth transistor The gate electrode is electrically connected to the first wiring. The first electrode of the sixth transistor is electrically connected to the sixth wiring, the second electrode of the sixth transistor is electrically connected to the gate electrode of the first transistor, and the sixth transistor The gate electrode is electrically connected to the gate electrode of the second transistor. The first electrode of the seventh transistor is electrically connected to the sixth wiring, the second electrode of the seventh transistor is electrically connected to the gate electrode of the first transistor, and the seventh transistor The gate electrode is electrically connected to the second wiring.

The liquid crystal display device including the pixel having the liquid crystal element and the driving circuit may include the following structure. Channel length L and channel width W of the first to seventh transistors
A configuration including a driving circuit in which the value of W / L of the first transistor is the largest among the values of the ratio W / L. The W / L value of the first transistor is 2 to 5 times the W / L value of the fifth transistor.
A configuration including a driving circuit that doubles. The configuration includes a case where the channel length L of the third transistor is larger than the channel length L of the fourth transistor. A structure including a capacitor element arranged between the second electrode of the first transistor and the gate electrode of the first transistor. First
The seventh to seventh transistors include an N-channel transistor. The first to seventh transistors include a structure in which amorphous silicon is used for a semiconductor layer.

A liquid crystal display device including a pixel having a liquid crystal element, a first driver circuit, and a second driver circuit. First
The drive circuit and the second drive circuit at least partially include the following connection relationship.
The first driver circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor. ing. The first electrode of the first transistor is electrically connected to the fourth wiring, and the second electrode of the first transistor is electrically connected to the third wiring. The first electrode of the second transistor is electrically connected to the sixth wiring, and the second electrode of the ninth transistor is electrically connected to the third wiring. The first electrode of the third transistor is electrically connected to the fifth wiring, the second electrode of the third transistor is electrically connected to the gate electrode of the second transistor, and the third transistor The gate electrode is electrically connected to the seventh wiring. A first electrode of the fourth transistor is electrically connected to the sixth wiring;
The second electrode of the first transistor is electrically connected to the gate electrode of the second transistor, and the gate electrode of the fourth transistor is electrically connected to the gate electrode of the first transistor. The first electrode of the fifth transistor is electrically connected to the seventh wiring, the second electrode of the fifth transistor is electrically connected to the gate electrode of the first transistor, and the fifth transistor The gate electrode is electrically connected to the first wiring. The first electrode of the sixth transistor is electrically connected to the sixth wiring, the second electrode of the sixth transistor is electrically connected to the gate electrode of the first transistor, and the sixth transistor The gate electrode is electrically connected to the gate electrode of the second transistor. The first electrode of the seventh transistor is electrically connected to the sixth wiring, the second electrode of the seventh transistor is electrically connected to the gate electrode of the first transistor, and the seventh transistor The gate electrode is electrically connected to the second wiring.
The second driver circuit includes an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, and a fourteenth transistor. ing. The first electrode of the eighth transistor is electrically connected to the eleventh wiring, and the second electrode of the eighth transistor is electrically connected to the tenth wiring. The first electrode of the ninth transistor is electrically connected to the thirteenth wiring, and the second electrode of the ninth transistor is electrically connected to the tenth wiring. The first electrode of the tenth transistor is electrically connected to the twelfth wiring, the second electrode of the tenth transistor is electrically connected to the gate electrode of the ninth transistor, and the tenth transistor The gate electrode is electrically connected to the 14th wiring. The first electrode of the eleventh transistor is the first
3, the second electrode of the eleventh transistor is electrically connected to the gate electrode of the ninth transistor, and the gate electrode of the eleventh transistor is connected to the gate electrode of the eighth transistor. Electrically connected. The first electrode of the twelfth transistor is the first
4 is electrically connected, the second electrode of the twelfth transistor is electrically connected to the gate electrode of the eighth transistor, and the gate electrode of the twelfth transistor is electrically connected to the eighth wire. Has been. The first electrode of the thirteenth transistor is electrically connected to the thirteenth wiring, the second electrode of the thirteenth transistor is electrically connected to the gate electrode of the eighth transistor, The gate electrode is electrically connected to the gate electrode of the ninth transistor. The first electrode of the fourteenth transistor is electrically connected to the thirteenth wiring, the second electrode of the fourteenth transistor is electrically connected to the gate electrode of the eighth transistor, The gate electrode is electrically connected to the ninth wiring.

The liquid crystal display device including the pixel having the liquid crystal element and the driving circuit may include the following structure. The fourth wiring and the eleventh wiring are electrically connected, the fifth wiring and the twelfth wiring are electrically connected, and the sixth wiring and the thirteenth wiring are electrically connected. The seventh wiring and the fourteenth wiring are electrically connected. The fourth wiring and the eleventh wiring are the same wiring, the fifth wiring and the twelfth wiring are the same wiring, and the sixth wiring and the thirteenth wiring are the same wiring. The seventh wiring and the fourteenth wiring are the same wiring. A configuration in which the third wiring and the tenth wiring are electrically connected. A configuration in which the third wiring and the tenth wiring are the same wiring. Among the values of the ratio W / L of the channel length L to the channel width W of the first transistor to the seventh transistor, the value of W / L of the first transistor is the maximum, and the eighth transistor to the fourteenth transistor A configuration in which the value of W / L of the eighth transistor is the maximum among the values of the ratio W / L of the channel length L and the channel width W of the transistor. W / L of the first transistor
Of the fifth transistor is 2 to 5 times the W / L value of the fifth transistor, and the W / L value of the eighth transistor is 2 to 5 times the W / L value of the twelfth transistor. Configuration that becomes. The channel length L of the third transistor is larger than the channel length L of the fourth transistor.
The channel length L of this transistor is larger than the channel length L of the eleventh transistor. A capacitor is disposed between the second electrode of the first transistor and the gate electrode of the first transistor, and is disposed between the second electrode of the eighth transistor and the gate electrode of the eighth transistor. A configuration in which capacitive elements are arranged. The first to fourteenth transistors are N-channel transistors. The first to fourteenth transistors have a structure in which amorphous silicon is used for a semiconductor layer.

The liquid crystal display device described in this embodiment is described in this specification, and thus has the same effects as those of the other embodiments.

S1 signal line Sj signal line VDD power supply potential VSS power supply potential G1 scanning line Gi scanning line Gn scanning line 11 transistor 12 transistor 13 transistor 14 transistor 15 transistor 16 transistor 17 transistor 21 signal line 22 signal line 23 wiring 24 signal line 25 power line 26 Power supply line 32 Silicon oxynitride film 41 Node 101 Transistor 102 Transistor 103 Transistor 104 Transistor 105 Transistor 106 Transistor 110 Wiring 107 Transistor 112 Wiring 108 Transistor 109 Transistor 121 Wiring 122 Wiring 123 Wiring 124 Wiring 125 Wiring 126 Wiring 127 Wiring 128 Wiring 129 Wiring 130 Wiring 131 Wiring 132 Wiring 133 Wiring 134 Wiring 141 Node 142 Node 221 No. 222 Signal 223 Signal 225 Signal 226 Signal 232 Signal 241 Potential 242 Potential 401 Capacitance element 402 Transistor 403 Resistance element 501 Wiring 502 Wiring 503 Wiring 504 Wiring 505 Wiring 506 Wiring 507 Wiring 508 Wiring 509 Wiring 510 Wiring 701 Transistor 702 Transistor 711 Wiring 81a Evaporation source 1001 Flip-flop 1007 Wiring 1011 Wiring 1012 Wiring 1013 Wiring 1014 Wiring 1015 Wiring 1016 Wiring 1017 Wiring 1018 Wiring 1111 Signal 1112 Signal 1113 Signal 1117 Signal 1118 Signal 1211 Signal 1218 Signal 1301 Buffer 1602 Scan line driving circuit 1801 Signal line driving circuit 1802 Scan line driver circuit 1803 Pixel 1804 Pixel portion 1805 Insulating substrate 1808 Wiring 21 8 Transistor 2132 Wiring 2301 Transistor 2302 Transistor 2303 Transistor 2304 Transistor 2305 Transistor 2306 Transistor 2307 Transistor 2321 Wiring 2322 Wiring 2323 Wiring 2324 Wiring 2325 Wiring 2326 Wiring 2327 Wiring 2328 Wiring 2329 Wiring 2330 Wiring 2331 Wiring 2341 Node 2342 Node 2423 Signal 2422 Signal 2423 2425 Signal 2426 Signal 2441 Potential 2442 Potential 2501 Conductive layer 2502 Conductive layer 2503 Conductive layer 2504 Conductive layer 2505 Conductive layer 2506 Conductive layer 2507 Conductive layer 2508 Conductive layer 2510 Conductive layer 2511 Conductive layer 2512 Conductive layer 2513 Conductive layer 2514 Conductive layer 2515 Conductive layer 2541 Wiring 2542 Wiring 254 3 wiring 2544 wiring 2545 wiring 2546 wiring 2547 wiring 2548 wiring 2548 wiring 2549 wiring 2581 semiconductor layer 2582 semiconductor layer 2583 semiconductor layer 2584 semiconductor layer 2585 semiconductor layer 2586 semiconductor layer 2587 semiconductor layer 2901 flip-flop 2907 wiring 2911 wiring 2912 wiring 2913 wiring 2914 wiring 2915 wiring 2916 wiring 2917 wiring 2918 wiring 2919 wiring 3011 signal 3018 signal 3019 signal 3101 flip-flop 3111 wiring 3120 wiring 3121 signal 3122 signal 3123 signal 3125 signal 3126 signal 3141 potential 3142 potential 3301 flip-flop 3301 wiring 3306 wiring 3311 wiring 3314 wiring 3314 wiring 3314 wiring 3315 wiring 3316 wiring 3317 wiring 318 wiring 3319 line 3320 line 3321 line 3322 line 3511 signal 3512 signal 3513 signal 3514 signal 3515 signal 3519 signal 3520 signal 3521 signal 3604 substrate film 3611 signal 3621 signal 5601 Driver IC
5602 switch group 5611 wiring 5612 wiring 5613 wiring 5621 wiring 5721 signal 5821 signal 5911 wiring 5912 wiring 5913 wiring 6001 transistor 6002 transistor 6003 transistor 6004 transistor 6005 transistor 6006 transistor 6011 wiring 6012 wiring 6013 wiring 6014 wiring 6015 wiring 6016 wiring 6022 switch group 6101 transistor 6102 transistor 6111 wiring 6112 wiring 6201 transistor 6211 wiring 6401 transistor 6402 transistor 6411 wiring 6412 wiring 8000 buffer 8011 wiring 8012 wiring 802a scanning line driver circuit 802b scanning line driver circuit 8100 buffer 8201 transistor 8202 transistor 8 11 wiring 8212 wiring 8213 wiring 8214 wiring 8214 transistor 8301 transistor 8302 transistor 8303 transistor 8304 transistor 8311 wiring 8312 wiring 8313 wiring 8314 wiring 8315 wiring 8316 wiring 8341 node 8401 transistor 8402 transistor 8403 transistor 8404 transistor 8411 wiring 8412 wiring 8413 wiring 8414 wiring 8415 wiring 8416 8417 wiring 8441 node 8501 transistor 8502 transistor 8503 transistor 8511 wiring 8512 wiring 8513 wiring 8514 wiring 8515 wiring 8516 wiring 8541 node 8601 transistor 8602 transistor 8603 transistor 8604 transistor 8611 wiring 8612 wiring 8613 wiring 8614 wiring 8615 wiring 8616 wiring 8616 wiring 8641 node 10101 substrate 10102 insulating film 10103 conductive layer 10104 insulating film 10105 semiconductor layer 10106 semiconductor layer 10107 conductive layer 10108 insulating film 10109 conductive layer 10110 alignment film 10112 alignment film 10113 conductive layer 10114 light shielding film 10115 color Filter 10116 Substrate 10117 Spacer 10118 Liquid crystal molecule 10121 Scan line 10122 Video signal line 10123 Capacitance line 10124 TFT
10125 Pixel electrode 10126 Pixel capacitance 10201 Substrate 10202 Insulating film 10203 Conductive layer 10204 Insulating film 10205 Semiconductor layer 10206 Semiconductor layer 10207 Conductive layer 10208 Insulating film 10209 Conductive layer 10210 Alignment film 10212 Alignment film 10213 Conductive layer 10214 Shading film 10215 Color filter 10216 Substrate 10217 Spacer 10218 Liquid crystal molecule 10219 Alignment control protrusion 10221 Scan line 10222 Video signal line 10223 Capacitance line 10224 TFT
10225 Pixel electrode 10226 Pixel capacitance 10301 Substrate 10302 Insulating film 10303 Conductive layer 10304 Insulating film 10305 Semiconductor layer 10306 Semiconductor layer 10307 Conductive layer 10308 Insulating film 10309 Conductive layer 10310 Alignment film 10312 Alignment film 10313 Conductive layer 10314 Light shielding film 10315 Color filter 10316 Substrate 10317 Spacer 10318 Liquid crystal molecule 10319 Electrode notch 10321 Scan line 10322 Video signal line 10323 Capacitor line 10324 TFT
10325 Pixel electrode 10326 Pixel capacitance 10401 Substrate 10402 Insulating film 10403 Conductive layer 10404 Insulating film 10405 Semiconductor layer 10406 Semiconductor layer 10407 Conductive layer 10408 Insulating film 10409 Conductive layer 10410 Alignment film 10412 Alignment film 10414 Light shielding film 10415 Color filter 10416 Substrate 10417 Spacer 10418 Liquid crystal Molecule 10421 Scanning line 10422 Video signal line 10423 Common electrode 10424 TFT
10425 Pixel electrode 10501 Substrate 10502 Insulating film 10503 Conductive layer 10504 Insulating film 10505 Semiconductor layer 10506 Semiconductor layer 10507 Conductive layer 10508 Insulating film 10509 Conductive layer 10510 Aligned film 10512 Aligned film 10513 Conductive layer 10514 Light shielding film 10515 Color filter 10516 Substrate 10517 Spacer 10518 Liquid crystal Molecule 10519 Insulating film 10521 Scan line 10522 Video signal line 10523 Common electrode 10524 TFT
10525 Pixel electrode 10600 Liquid crystal layer 10601 Substrate 10602 Substrate 10603 Layer 10604 Layer 10605 Electrode 10606 Electrode 10607 Projection 10801 Electrode 10802 Electrode 10803 Electrode 10804 Electrode 10901 Insulating layer 2002a Scan line driver circuit 2002b Scan line driver circuit 20100 Substrate 20101 Pixel portion 20102 Pixel 20103 Scan line input terminal 20104 Signal line input terminal 20105 Scan line driver circuit 20106 Signal line driver circuit 20115 Substrate 20200 FPC
20201 Driver IC
20301 Transistor 20302 Liquid crystal element 20303 Capacitance element 20304 Wiring 20305 Wiring 20306 Capacitance line 20307 Counter electrode 20501 Insulating film 20502 Semiconductor layer 20503 Insulating layer 20504 Insulating layer 20505 Insulating layer 20506 Insulating layer 20507 Insulating layer 20508 Insulating layer 20509 Insulating layer 20510 Insulating layer 20511 Insulating Film 20512 Conductive film 20513 Insulating film 20514 Insulating film 20515 Counter substrate 20516 Sealing material 20517 Anisotropic conductor layer 20518 FPC
20521 Transistor 20525 Driver circuit region 20526 Pixel region 20530 IC chip 20530 Spacer 20532 Insulating film 20533 Conductive film 20601 Driver IC
21301 Insulating film 21801 Insulating film 22001 Insulating film 2202a Scanning line driving circuit 2202b Scanning line driving circuit 22201 Insulating film 22601 Backlight unit 22602 Diffusion plate 22603 Light guide plate 22604 Reflecting plate 22605 Lamp reflector 22606 Light source 22607 Liquid crystal panel 22608 Layer 22609 Layer 22610 Slit 22270 Video signal 22702 Control circuit 22703 Signal line drive circuit 22704 Scan line drive circuit 22705 Pixel unit 22706 Illumination means 22707 Power supply 22708 Drive circuit unit 22710 Scan line 22712 Signal line 22733 Shift register 22732 Latch 22733 Latch 22734 Level shifter 22743 Shift register 22743 Shift register 22743 Buffer 2280 1 Cold Cathode Tube 22802 Light Emitting Diode 22803 Light Emitting Diode 22832 Lamp Reflector 22852 Backlight Unit 23000 Polarizing Film 23001 Protective Film 23002 Substrate Film 23002 PVA Polarizing Film 23004 Substrate Film 23005 Adhesive Layer 23006 Release Film 23100 TFT Substrate 23101 Opposite Substrate 23102 Sealing material 23103 Pixel portion 23104 Liquid crystal layer 23105 Colored layer 23106 Layer 23107 Layer 23109 Flexible wiring board 23110 Cold cathode tube 23111 Reflecting plate 23112 Circuit board 23113 Diffusion plate 23199 Control unit 2901i Flip-flop 30101 Encoding circuit 30102 Frame memory 30103 Correction circuit 30104 DA conversion circuit 0112 Frame memory 30113 Correction circuit 30121 Input voltage 30122 Input voltage 30123 Output luminance 30124 Output luminance 30131 Input video signal 30132 Output video signal 30133 Output switching signal 30201 Transistor 30202 Auxiliary capacitor 30203 Display element 30204 Video signal line 30205 Scan line 30206 Common line 30211 Transistor 30212 Auxiliary capacitor 30213 Display element 30214 Video signal line 30215 Scan line 30216 Common line 30217 Common plate 30301 Diffusion plate 30302 Cold cathode tube 30311 Diffusion plate 30312 Light source 30400 Frame period 30401 Image 30402 Intermediate image 30412 Intermediate image 30413 Intermediate image 5603a Switch 5603b Switch 5603c Switch 5703a Thailand Packaging 5703b timing 5703c timing 5803a timing 5803b timing 5803c timing 5903a transistor 5903b transistor 5903c transistor 60105 TFT
60106 wiring 60107 wiring 60108 TFT
60111 wiring 60112 counter electrode 60113 capacitor 60115 pixel electrode 60116 partition wall 60117 organic conductor film 60118 organic thin film 60119 substrate 60200 substrate 60201 wiring 60202 wiring 60203 wiring 60204 wiring 60205 TFT
60206 TFT
60207 TFT
60208 Pixel electrode 60211 Partition 60212 Organic conductor film 60213 Organic thin film 60214 Counter electrode 60300 Substrate 60301 Wiring 60302 Wiring 60303 Wiring 60304 Wiring 60305 TFT
60306 TFT
60307 TFT
60308 TFT
60309 Pixel electrode 60311 Wire 6031 Wire 60321 Partition 60322 Organic conductor film 60323 Organic thin film 60324 Counter electrode 60401 Anode 60402 Cathode 60403 Hole transport region 60404 Electron transport region 60405 Mixed region 60406 Region 60407 Region 60408 Region 60409 Region 60560 Transport chamber 60561 Transport chamber 60562 Loading chamber 60563 Unloading chamber 60564 Intermediate processing chamber 60565 Sealing processing chamber 60565 Conveying means 60567 Conveying means 60568 Heating processing chamber 60568 Deposition processing chamber 60570 Deposition processing chamber 60571 Deposition processing chamber 60573 Deposition processing chamber 60573 Deposition processing chamber 60576 Deposition processing chamber 60680 Evaporation source holder 60681 Evaporation source 60682 Distance sensor 60683 Joint arm 60684 Material supply tube 60686 Substrate stage 60687 Substrate chuck 60688 Mask chuck 60689 Substrate 60690 Shadow mask 60691 Top plate 60692 Bottom plate 6301a Transistor 6301b Transistor 6302a Transistor 6302b Transistor 8001a Inverter 8001b Inverter 8001c Inverter 8003b Inverter 8003b Inverter 8003b Inverter 8003b Inverter 8003b Inverter 8003b Inverter 8003b Inverter 8003b Inverter 8003b Inverter 80302 Drive transistor 80400 Drive transistor 80401 Switch 80402 Switch 80403 Switch 80404 Capacitor element 80405 Capacitor element 80411 Signal line 80411 Power line 80413 First scan line 80414 Second Scanning line 80415 Third scanning line 80420 Display element 80421 Electrode 80430 Driving transistor 80431 Switch 80432 Switch 80433 Switch 80434 Capacitance element 80441 Signal line 80442 Power line 80443 First scanning line 80444 Second scanning line 80445 Third scanning line 80450 Display element 80451 Electrode 80454 Scan line 10606a Electrode 10801a Electrode 10801b Electrode 10801c Electrode 10801d Electrode 10802a Electrode 10802b Electrode 10802c Electrode 10802d Electrode 8803a Electrode 10803b Electrode 10803c Electrode 10803d Electrode 10804b Electrode 10804b Electrode 10804b Electrode 10804c Electrode 11011 Semiconductor film 110115 Semiconductor film 110116 Insulating film 110117 Gate electrode 110118 Insulating film 110119 Insulating film 110121 Side wall 110122 Mask 110123 Conductive film 110131 Insulating film 120100 Electrode layer 120102 Electroluminescent layer 120103 Electrode layer 120104 Insulating layer 120105 Insulating layer 120106 Insulating layer 120200 Electrode layer 120201 Luminescent material 120202 Electroluminescent layer 120203 Electrode layer 120204 Insulating layer 120205 Insulating layer 120206 Insulating layer 120206 Rear projection display device 130101 Screen panel 130102 Speaker 130104 Operation switches 130110 Housing 130111 Projector unit 130112 Mirror 130200 Front projection display device 130201 Projection Optical system 130301 Light source unit 130301 Light source unit 130302 Light source lamp 130303 Light source optical system 130304 Modulation unit 130305 Dichroic mirror 130306 Total reflection mirror 130308 Display panel 130309 Prism 130310 Projection optical system 130400 Modulation unit 130401 Dichroic mirror 130402 Dichroic mirror 130403 Total reflection mirror 130404 Polarized beam Splitter 130405 Polarized beam splitter 130406 Polarized beam splitter 130407 Reflective display panel 130411 Projection optical system 130501 Dichroic mirror 130502 Dichroic mirror 130503 Red light dichroic mirror 130504 Phase plate 130505 Color filter Plate 130506 Microlens array 130507 Display panel 130508 Display panel 130509 Display panel 130511 Projection optical system 20102a Pixel 20102b Pixel 20105a Scan line driver circuit 20105b Scan line driver circuit 20301a Transistor 20301b Transistor 20303a Capacitor element 20303b Capacitor element 20305a Wire 20305b Wire 203076 Wire 20303 Layer 20502b Semiconductor layer 20503a Insulating layer 20503b Insulating layer 20504a Conductive layer 20504b Conductive layer 20508a Conductive layer 20508b Conductive layer 20602a Driver IC
20602b Driver IC
23190a Red light source 23190b Green light source 23190c Blue light source 60577a Gate valve 60681a Evaporation source 60681b Evaporation source 60681c Evaporation source 60685a Material supply source 60685b Material supply source 60685c Material supply source 80301a Switching transistor 80301c Switching transistor 80301d Switching transistor 80301d Switching transistor 80301d Switching transistor 80302a driving transistor 80302b driving transistor 80302c driving transistor 80302d driving transistor 80302e driving transistor 80303c diode connecting transistor 80303d diode connecting transistor 80303e erasing transistor 0304a Capacitance element 80304b Capacitance element 80304c Capacitance element 80304d Capacitance element 80304e Capacitance element 80306a Rectification element 80311a Signal line 80311b Signal line 80311c Signal line 80311d Signal line 80311e Signal line 80312a First scan line 80312b First scan line 80312c First scan Line 80312d First scan line 8031e First scan line 80313a Power line 80313b Power line 80313c Power line 80313d Power line 80313e Power line 80314b Second scan line 80314c Second scan line 80314d Second scan line 80320a Display element 80320b Display element 80321a Electrode 80321b Electrode 900101 Display panel 900102 Pixel portion 900103 Scan line driver circuit 900104 Signal Driver circuit 900111 Circuit board 900112 Control circuit 900113 Signal division circuit 900114 Connection wiring 900201 Tuner 900202 Video signal amplification circuit 900203 Video signal processing circuit 900205 Audio signal amplification circuit 900206 Audio signal processing circuit 900207 Speaker 900208 Control circuit 9000020 Input unit 900212 Control circuit 900213 Signal Division circuit 900301 Case 900302 Display screen 900303 Speaker 900304 Operation switch 900310 Charger 900312 Case 900313 Display unit 900316 Operation key 900317 Speaker unit 900401 Display panel 900402 Printed wiring board 900403 Pixel unit 900404 Scan line driver circuit 9000040 Scan line driver circuit 90 406 signal line driver circuit 900407 Controller 900408 central processing unit (CPU)
9004009 Memory 900410 Power supply circuit 900411 Audio processing circuit 900412 Transmission / reception circuit 900413 Flexible circuit board
900414 Interface (I / F) section 900415 Antenna port 900416 VRAM
900417 DRAM
900418 Flash memory 900419 Interface 900420 Control signal generation circuit 900421 Decoder 900422 Register 900423 Arithmetic circuit 900424 RAM
900425 Input unit 9000042 Microphone 9000042 Speaker 9000042 Antenna 9000050 Display panel 9000051 FPC
900530 Housing 900531 Printed circuit board 9005002 Speaker 900533 Microphone 900534 Transmission / reception circuit 90000535 Signal processing circuit 90000536 Input means 90000537 Battery 90000539 Case 900600 Cellular phone 90000601 Main body (A)
900602 body (B)
90063 Housing 9000060 Operation switches 9000060 Microphone 9000060 Speaker 900607 Circuit board 9000060 Display panel (A)
900609 Display panel (B)
900610 Hinge 900711 Case 900712 Support base 900713 Display unit 900721 Main unit 900722 Display unit 900723 Image receiving unit 900724 Operation key 900725 External connection port 900726 Shutter 900731 Main unit 900732 Case 900733 Display unit 900734 Keyboard 900735 External connection port 900731 Main unit 900741 Main unit 900741 900743 Switch 900744 Operation Key 9000074 Infrared Port 9000075 Main Body 900722 Case 90073 Display Unit (A)
90074 display part (B)
900755 part 900075 operation key 9000075 speaker part 900761 main body 900762 display part 900763 earphone 900764 support part 900771 case 900772 display part 900773 speaker part 900774 operation key 900775 storage medium insertion part 900781 main body 900782 display part 900783 operation key 900784 speaker 900785 shutter 9 900771 Antenna 900810 Housing 900811 Display unit 900812 Remote control device 9000081 Speaker unit 900901 Display panel 900902 Unit bus 901001 Column 9010102 Display panel 901101 Car body 901102 Display panel 901201 Door 901202 Display panel 901203 Glass window 90120 Ceiling 901301 ceiling 901302 display panel 901,303 hinge part

Claims (8)

A scanning line driving circuit and a pixel,
The scanning line driving circuit includes first to sixth transistors,
One of a source electrode and a drain electrode of the first transistor is electrically connected to the first wiring;
The other of the source electrode and the drain electrode of the first transistor is electrically connected to the first scan line;
One of a source electrode and a drain electrode of the second transistor is electrically connected to a second wiring;
The other of the source electrode and the drain electrode of the second transistor is electrically connected to the first scan line;
One of a source electrode and a drain electrode of the third transistor is electrically connected to a gate electrode of the first transistor;
One of a source electrode and a drain electrode of the fourth transistor is electrically connected to the second wiring;
The other of the source electrode and the drain electrode of the fourth transistor is electrically connected to the gate electrode of the first transistor;
A gate electrode of the fourth transistor is electrically connected to the second scan line;
One of the source electrode and the drain electrode of the fifth transistor is electrically connected to a third wiring to which an AC pulse is supplied ,
The other of the source electrode and the drain electrode of the fifth transistor is electrically connected to the gate electrode of the second transistor;
One of a source electrode and a drain electrode of the sixth transistor is electrically connected to a fourth wiring;
The other of the source electrode and the drain electrode of the sixth transistor is electrically connected to the gate electrode of the second transistor;
A gate electrode of the sixth transistor is electrically connected to a gate electrode of the first transistor;
The third transistor has a function of controlling a potential of a gate electrode of the first transistor so that the first transistor is turned on;
The fourth transistor has a function of controlling a potential of a gate electrode of the first transistor so that the first transistor is turned off;
The fifth transistor has a function of controlling a potential of a gate electrode of the second transistor so that the second transistor is turned on;
The sixth transistor has a function of controlling a potential of a gate electrode of the second transistor so that the second transistor is turned off;
The display device is characterized in that the pixel is electrically connected to the first scanning line. A scanning line driving circuit and a pixel,
The scanning line driving circuit includes first to sixth transistors,
One of a source electrode and a drain electrode of the first transistor is electrically connected to the first wiring;
The other of the source electrode and the drain electrode of the first transistor is electrically connected to the first scan line;
One of a source electrode and a drain electrode of the second transistor is electrically connected to a second wiring;
The other of the source electrode and the drain electrode of the second transistor is electrically connected to the first scan line;
One of a source electrode and a drain electrode of the third transistor is electrically connected to a gate electrode of the first transistor;
One of a source electrode and a drain electrode of the fourth transistor is electrically connected to the second wiring;
The other of the source electrode and the drain electrode of the fourth transistor is electrically connected to the gate electrode of the first transistor;
A gate electrode of the fourth transistor is electrically connected to the second scan line;
One of the source electrode and the drain electrode of the fifth transistor is electrically connected to a third wiring to which an AC pulse is supplied ,
The other of the source electrode and the drain electrode of the fifth transistor is electrically connected to the gate electrode of the second transistor;
One of a source electrode and a drain electrode of the sixth transistor is electrically connected to a fourth wiring;
The other of the source electrode and the drain electrode of the sixth transistor is electrically connected to the gate electrode of the second transistor;
A gate electrode of the sixth transistor is electrically connected to a gate electrode of the first transistor;
The third transistor has a function of controlling a potential of a gate electrode of the first transistor so that the first transistor is turned on;
The fourth transistor has a function of controlling a potential of a gate electrode of the first transistor so that the first transistor is turned off;
The fifth transistor has a function of controlling a potential of a gate electrode of the second transistor so that the second transistor is turned on;
The sixth transistor has a function of controlling a potential of a gate electrode of the second transistor so that the second transistor is turned off;
W / L (W is a channel width and L is a channel length) of the first transistor is larger than W / L of the second transistor,
W / L of the first transistor is larger than W / L of the third transistor,
W / L of the first transistor is larger than W / L of the fourth transistor,
W / L of the first transistor is larger than W / L of the fifth transistor,
W / L of the first transistor is larger than W / L of the sixth transistor,
W / L of the sixth transistor is larger than W / L of the fifth transistor,
The display device is characterized in that the pixel is electrically connected to the first scanning line. A scanning line driving circuit and a pixel,
The scanning line driving circuit includes first to sixth transistors,
One of a source electrode and a drain electrode of the first transistor is electrically connected to the first wiring;
The other of the source electrode and the drain electrode of the first transistor is electrically connected to the first scan line;
One of a source electrode and a drain electrode of the second transistor is electrically connected to a second wiring;
The other of the source electrode and the drain electrode of the second transistor is electrically connected to the first scan line;
One of a source electrode and a drain electrode of the third transistor is electrically connected to a gate electrode of the first transistor;
One of a source electrode and a drain electrode of the fourth transistor is electrically connected to the second wiring;
The other of the source electrode and the drain electrode of the fourth transistor is electrically connected to the gate electrode of the first transistor;
A gate electrode of the fourth transistor is electrically connected to the second scan line;
One of the source electrode and the drain electrode of the fifth transistor is electrically connected to a third wiring to which an AC pulse is supplied ,
The other of the source electrode and the drain electrode of the fifth transistor is electrically connected to the gate electrode of the second transistor;
One of a source electrode and a drain electrode of the sixth transistor is electrically connected to a fourth wiring;
The other of the source electrode and the drain electrode of the sixth transistor is electrically connected to the gate electrode of the second transistor;
A gate electrode of the sixth transistor is electrically connected to a gate electrode of the first transistor;
The third transistor has a function of controlling a potential of a gate electrode of the first transistor so that the first transistor is turned on;
The fourth transistor has a function of controlling a potential of a gate electrode of the first transistor so that the first transistor is turned off;
The fifth transistor has a function of controlling a potential of a gate electrode of the second transistor so that the second transistor is turned on;
The sixth transistor has a function of controlling a potential of a gate electrode of the second transistor so that the second transistor is turned off;
The second transistor has a first conductive layer;
The first conductive layer has a region to be one of a source electrode and a drain electrode of the second transistor,
The first conductive layer has a region to be one of a source electrode and a drain electrode of the fourth transistor,
The display device is characterized in that the pixel is electrically connected to the first scanning line. A scanning line driving circuit and a pixel,
The scanning line driving circuit includes first to sixth transistors,
One of a source electrode and a drain electrode of the first transistor is electrically connected to the first wiring;
The other of the source electrode and the drain electrode of the first transistor is electrically connected to the first scan line;
One of a source electrode and a drain electrode of the second transistor is electrically connected to a second wiring;
The other of the source electrode and the drain electrode of the second transistor is electrically connected to the first scan line;
One of a source electrode and a drain electrode of the third transistor is electrically connected to a gate electrode of the first transistor;
One of a source electrode and a drain electrode of the fourth transistor is electrically connected to the second wiring;
The other of the source electrode and the drain electrode of the fourth transistor is electrically connected to the gate electrode of the first transistor;
A gate electrode of the fourth transistor is electrically connected to the second scan line;
One of the source electrode and the drain electrode of the fifth transistor is electrically connected to a third wiring to which an AC pulse is supplied ,
The other of the source electrode and the drain electrode of the fifth transistor is electrically connected to the gate electrode of the second transistor;
One of a source electrode and a drain electrode of the sixth transistor is electrically connected to a fourth wiring;
The other of the source electrode and the drain electrode of the sixth transistor is electrically connected to the gate electrode of the second transistor;
A gate electrode of the sixth transistor is electrically connected to a gate electrode of the first transistor;
The third transistor has a function of controlling a potential of a gate electrode of the first transistor so that the first transistor is turned on;
The fourth transistor has a function of controlling a potential of a gate electrode of the first transistor so that the first transistor is turned off;
The fifth transistor has a function of controlling a potential of a gate electrode of the second transistor so that the second transistor is turned on;
The sixth transistor has a function of controlling a potential of a gate electrode of the second transistor so that the second transistor is turned off;
The first transistor has a first conductive layer;
The second transistor has a second conductive layer;
The first conductive layer has a region to be the other of the source electrode and the drain electrode of the first transistor,
The second conductive layer has a region to be the other of the source electrode and the drain electrode of the second transistor,
The first conductive layer is electrically connected to the second conductive layer via a third conductive layer;
The display device is characterized in that the pixel is electrically connected to the first scanning line. A scanning line driving circuit and a pixel,
The scanning line driving circuit includes first to sixth transistors,
One of a source electrode and a drain electrode of the first transistor is electrically connected to the first wiring;
The other of the source electrode and the drain electrode of the first transistor is electrically connected to the first scan line;
One of a source electrode and a drain electrode of the second transistor is electrically connected to a second wiring;
The other of the source electrode and the drain electrode of the second transistor is electrically connected to the first scan line;
One of a source electrode and a drain electrode of the third transistor is electrically connected to a gate electrode of the first transistor;
One of a source electrode and a drain electrode of the fourth transistor is electrically connected to the second wiring;
The other of the source electrode and the drain electrode of the fourth transistor is electrically connected to the gate electrode of the first transistor;
A gate electrode of the fourth transistor is electrically connected to the second scan line;
One of the source electrode and the drain electrode of the fifth transistor is electrically connected to a third wiring to which an AC pulse is supplied ,
The other of the source electrode and the drain electrode of the fifth transistor is electrically connected to the gate electrode of the second transistor;
One of a source electrode and a drain electrode of the sixth transistor is electrically connected to a fourth wiring;
The other of the source electrode and the drain electrode of the sixth transistor is electrically connected to the gate electrode of the second transistor;
A gate electrode of the sixth transistor is electrically connected to a gate electrode of the first transistor;
The third transistor has a function of controlling a potential of a gate electrode of the first transistor so that the first transistor is turned on;
The fourth transistor has a function of controlling a potential of a gate electrode of the first transistor so that the first transistor is turned off;
The fifth transistor has a function of controlling a potential of a gate electrode of the second transistor so that the second transistor is turned on;
The sixth transistor has a function of controlling a potential of a gate electrode of the second transistor so that the second transistor is turned off;
The pixel includes a gate electrode, a gate insulating film above the gate electrode, a semiconductor layer above the gate insulating film, a source electrode and a drain electrode above the semiconductor layer, and one of the source electrode or the drain electrode. An electrically connected pixel electrode; an insulating film above the source electrode; above the drain electrode and above the pixel electrode; and a liquid crystal layer above the insulating film;
The pixel electrode has a region in contact with one upper surface of the source electrode or the drain electrode, and a region in contact with the upper surface of the gate insulating film,
The insulating film includes a region in contact with the top surface of the gate insulating film, a region in contact with the top surface of the semiconductor layer, a region in contact with the top surface of the source electrode, a region in contact with the top surface of the drain electrode, and a pixel electrode A region in contact with the upper surface,
The display device, wherein the gate electrode is electrically connected to the first scanning line. A scanning line driving circuit and a pixel,
The scanning line driving circuit includes first to sixth transistors,
One of a source electrode and a drain electrode of the first transistor is electrically connected to the first wiring;
The other of the source electrode and the drain electrode of the first transistor is electrically connected to the first scan line;
One of a source electrode and a drain electrode of the second transistor is electrically connected to a second wiring;
The other of the source electrode and the drain electrode of the second transistor is electrically connected to the first scan line;
One of a source electrode and a drain electrode of the third transistor is electrically connected to a gate electrode of the first transistor;
One of a source electrode and a drain electrode of the fourth transistor is electrically connected to the second wiring;
The other of the source electrode and the drain electrode of the fourth transistor is electrically connected to the gate electrode of the first transistor;
A gate electrode of the fourth transistor is electrically connected to the second scan line;
One of the source electrode and the drain electrode of the fifth transistor is electrically connected to a third wiring to which an AC pulse is supplied ,
The other of the source electrode and the drain electrode of the fifth transistor is electrically connected to the gate electrode of the second transistor;
One of a source electrode and a drain electrode of the sixth transistor is electrically connected to a fourth wiring;
The other of the source electrode and the drain electrode of the sixth transistor is electrically connected to the gate electrode of the second transistor;
A gate electrode of the sixth transistor is electrically connected to a gate electrode of the first transistor;
The third transistor has a function of controlling a potential of a gate electrode of the first transistor so that the first transistor is turned on;
The fourth transistor has a function of controlling a potential of a gate electrode of the first transistor so that the first transistor is turned off;
The fifth transistor has a function of controlling a potential of a gate electrode of the second transistor so that the second transistor is turned on;
The sixth transistor has a function of controlling a potential of a gate electrode of the second transistor so that the second transistor is turned off;
W / L (W is a channel width and L is a channel length) of the first transistor is larger than W / L of the second transistor,
W / L of the first transistor is larger than W / L of the third transistor,
W / L of the first transistor is larger than W / L of the fourth transistor,
W / L of the first transistor is larger than W / L of the fifth transistor,
W / L of the first transistor is larger than W / L of the sixth transistor,
W / L of the sixth transistor is larger than W / L of the fifth transistor,
The pixel includes a gate electrode, a gate insulating film above the gate electrode, a semiconductor layer above the gate insulating film, a source electrode and a drain electrode above the semiconductor layer, and one of the source electrode or the drain electrode. An electrically connected pixel electrode; an insulating film above the source electrode; above the drain electrode and above the pixel electrode; and a liquid crystal layer above the insulating film;
The pixel electrode has a region in contact with one upper surface of the source electrode or the drain electrode, and a region in contact with the upper surface of the gate insulating film,
The insulating film includes a region in contact with the top surface of the gate insulating film, a region in contact with the top surface of the semiconductor layer, a region in contact with the top surface of the source electrode, a region in contact with the top surface of the drain electrode, and a pixel electrode A region in contact with the upper surface,
The display device, wherein the gate electrode is electrically connected to the first scanning line. A scanning line driving circuit and a pixel,
The scanning line driving circuit includes first to sixth transistors,
One of a source electrode and a drain electrode of the first transistor is electrically connected to the first wiring;
The other of the source electrode and the drain electrode of the first transistor is electrically connected to the first scan line;
One of a source electrode and a drain electrode of the second transistor is electrically connected to a second wiring;
The other of the source electrode and the drain electrode of the second transistor is electrically connected to the first scan line;
One of a source electrode and a drain electrode of the third transistor is electrically connected to a gate electrode of the first transistor;
One of a source electrode and a drain electrode of the fourth transistor is electrically connected to the second wiring;
The other of the source electrode and the drain electrode of the fourth transistor is electrically connected to the gate electrode of the first transistor;
A gate electrode of the fourth transistor is electrically connected to the second scan line;
One of the source electrode and the drain electrode of the fifth transistor is electrically connected to a third wiring to which an AC pulse is supplied ,
The other of the source electrode and the drain electrode of the fifth transistor is electrically connected to the gate electrode of the second transistor;
One of a source electrode and a drain electrode of the sixth transistor is electrically connected to a fourth wiring;
The other of the source electrode and the drain electrode of the sixth transistor is electrically connected to the gate electrode of the second transistor;
A gate electrode of the sixth transistor is electrically connected to a gate electrode of the first transistor;
The third transistor has a function of controlling a potential of a gate electrode of the first transistor so that the first transistor is turned on;
The fourth transistor has a function of controlling a potential of a gate electrode of the first transistor so that the first transistor is turned off;
The fifth transistor has a function of controlling a potential of a gate electrode of the second transistor so that the second transistor is turned on;
The sixth transistor has a function of controlling a potential of a gate electrode of the second transistor so that the second transistor is turned off;
The second transistor has a first conductive layer;
The first conductive layer has a region to be one of a source electrode and a drain electrode of the second transistor,
The first conductive layer has a region to be one of a source electrode and a drain electrode of the fourth transistor,
The pixel includes a gate electrode, a gate insulating film above the gate electrode, a semiconductor layer above the gate insulating film, a source electrode and a drain electrode above the semiconductor layer, and one of the source electrode or the drain electrode. An electrically connected pixel electrode; an insulating film above the source electrode; above the drain electrode and above the pixel electrode; and a liquid crystal layer above the insulating film;
The pixel electrode has a region in contact with one upper surface of the source electrode or the drain electrode, and a region in contact with the upper surface of the gate insulating film,
The insulating film includes a region in contact with the top surface of the gate insulating film, a region in contact with the top surface of the semiconductor layer, a region in contact with the top surface of the source electrode, a region in contact with the top surface of the drain electrode, and a pixel electrode A region in contact with the upper surface,
The display device, wherein the gate electrode is electrically connected to the first scanning line. A scanning line driving circuit and a pixel,
The scanning line driving circuit includes first to sixth transistors,
One of a source electrode and a drain electrode of the first transistor is electrically connected to the first wiring;
The other of the source electrode and the drain electrode of the first transistor is electrically connected to the first scan line;
One of a source electrode and a drain electrode of the second transistor is electrically connected to a second wiring;
The other of the source electrode and the drain electrode of the second transistor is electrically connected to the first scan line;
One of a source electrode and a drain electrode of the third transistor is electrically connected to a gate electrode of the first transistor;
One of a source electrode and a drain electrode of the fourth transistor is electrically connected to the second wiring;
The other of the source electrode and the drain electrode of the fourth transistor is electrically connected to the gate electrode of the first transistor;
A gate electrode of the fourth transistor is electrically connected to the second scan line;
One of the source electrode and the drain electrode of the fifth transistor is electrically connected to a third wiring to which an AC pulse is supplied ,
The other of the source electrode and the drain electrode of the fifth transistor is electrically connected to the gate electrode of the second transistor;
One of a source electrode and a drain electrode of the sixth transistor is electrically connected to a fourth wiring;
The other of the source electrode and the drain electrode of the sixth transistor is electrically connected to the gate electrode of the second transistor;
A gate electrode of the sixth transistor is electrically connected to a gate electrode of the first transistor;
The third transistor has a function of controlling a potential of a gate electrode of the first transistor so that the first transistor is turned on;
The fourth transistor has a function of controlling a potential of a gate electrode of the first transistor so that the first transistor is turned off;
The fifth transistor has a function of controlling a potential of a gate electrode of the second transistor so that the second transistor is turned on;
The sixth transistor has a function of controlling a potential of a gate electrode of the second transistor so that the second transistor is turned off;
The first transistor has a first conductive layer;
The second transistor has a second conductive layer;
The first conductive layer has a region to be the other of the source electrode and the drain electrode of the first transistor,
The second conductive layer has a region to be the other of the source electrode and the drain electrode of the second transistor,
The first conductive layer is electrically connected to the second conductive layer via a third conductive layer;
The pixel includes a gate electrode, a gate insulating film above the gate electrode, a semiconductor layer above the gate insulating film, a source electrode and a drain electrode above the semiconductor layer, and one of the source electrode or the drain electrode. An electrically connected pixel electrode; an insulating film above the source electrode; above the drain electrode and above the pixel electrode; and a liquid crystal layer above the insulating film;
The pixel electrode has a region in contact with one upper surface of the source electrode or the drain electrode, and a region in contact with the upper surface of the gate insulating film,
The insulating film includes a region in contact with the top surface of the gate insulating film, a region in contact with the top surface of the semiconductor layer, a region in contact with the top surface of the source electrode, a region in contact with the top surface of the drain electrode, and a pixel electrode A region in contact with the upper surface,
The display device, wherein the gate electrode is electrically connected to the first scanning line.

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