JP6130995B2 - エピタキシャル基板及び半導体装置 - Google Patents
エピタキシャル基板及び半導体装置 Download PDFInfo
- Publication number
- JP6130995B2 JP6130995B2 JP2012033655A JP2012033655A JP6130995B2 JP 6130995 B2 JP6130995 B2 JP 6130995B2 JP 2012033655 A JP2012033655 A JP 2012033655A JP 2012033655 A JP2012033655 A JP 2012033655A JP 6130995 B2 JP6130995 B2 JP 6130995B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- substrate
- epitaxial growth
- silicon
- epitaxial
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000000758 substrate Substances 0.000 title claims description 105
- 239000004065 semiconductor Substances 0.000 title claims description 50
- 239000010410 layer Substances 0.000 claims description 196
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 56
- 229910052710 silicon Inorganic materials 0.000 claims description 56
- 239000010703 silicon Substances 0.000 claims description 56
- 150000004767 nitrides Chemical class 0.000 claims description 27
- 239000002346 layers by function Substances 0.000 claims description 14
- 230000007423 decrease Effects 0.000 claims description 8
- 238000013459 approach Methods 0.000 claims 1
- 239000012528 membrane Substances 0.000 claims 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 16
- 229910002601 GaN Inorganic materials 0.000 description 15
- 238000005253 cladding Methods 0.000 description 12
- 238000004519 manufacturing process Methods 0.000 description 8
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 7
- 238000000034 method Methods 0.000 description 6
- 230000008859 change Effects 0.000 description 5
- 230000000052 comparative effect Effects 0.000 description 5
- 239000012535 impurity Substances 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 230000002093 peripheral effect Effects 0.000 description 4
- 229910002704 AlGaN Inorganic materials 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 3
- 239000012159 carrier gas Substances 0.000 description 3
- 238000009826 distribution Methods 0.000 description 3
- 230000010287 polarization Effects 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical class [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- MSNOMDLPLDYDME-UHFFFAOYSA-N gold nickel Chemical compound [Ni].[Au] MSNOMDLPLDYDME-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 230000002269 spontaneous effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
- H01L21/3228—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of AIIIBV compounds, e.g. to make them semi-insulating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02455—Group 13/15 materials
- H01L21/02458—Nitrides
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
- C30B25/02—Epitaxial-layer growth
- C30B25/18—Epitaxial-layer growth characterised by the substrate
- C30B25/183—Epitaxial-layer growth characterised by the substrate being provided with a buffer layer, e.g. a lattice matching layer
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
- C30B25/02—Epitaxial-layer growth
- C30B25/18—Epitaxial-layer growth characterised by the substrate
- C30B25/186—Epitaxial-layer growth characterised by the substrate being specially pre-treated by, e.g. chemical or physical means
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
- C30B29/10—Inorganic compounds or compositions
- C30B29/40—AIIIBV compounds wherein A is B, Al, Ga, In or Tl and B is N, P, As, Sb or Bi
- C30B29/403—AIII-nitrides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02494—Structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02538—Group 13/15 materials
- H01L21/0254—Nitrides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02587—Structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/2003—Nitride compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/30—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface
- H01L29/34—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface the imperfections being on the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Crystallography & Structural Chemistry (AREA)
- Materials Engineering (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Ceramic Engineering (AREA)
- Inorganic Chemistry (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
- Chemical Vapour Deposition (AREA)
- Junction Field-Effect Transistors (AREA)
- Led Devices (AREA)
- Recrystallisation Techniques (AREA)
Description
本発明の第1の実施形態に係るエピタキシャル基板10は、図1(a)に示すように、シリコン系基板11と、外縁部において膜厚が徐々に薄くなるようにシリコン系基板11上に配置されたエピタキシャル成長層12とを備える。つまり、エピタキシャル成長層12は、図1(a)に示したように、外縁部(端部)の膜厚方向に沿った切断面の外縁の形状が凸円弧状である。また、エピタキシャル成長層12は、格子定数及び熱膨張係数が互いに異なる第1の窒化物半導体層121と第2の窒化物半導体層122が交互に積層されたバッファ層の構造を有する。
本発明の第2の実施形態に係るエピタキシャル基板10は、図14に示すように、エピタキシャル成長層12の端部が、シリコン系基板11の端部の面取りされた領域上に位置している。その他の点は、図1(a)に示した第1の実施形態と同様である。
本発明の第3の実施形態に係るエピタキシャル基板10は、図15に示すように、エピタキシャル成長層12の端部がシリコン系基板11の端部よりも外側に伸びている。その他の点は、図1(a)に示した第1の実施形態と同様である。
上記のように、本発明は第1乃至第3の実施形態によって記載したが、この開示の一部をなす論述及び図面はこの発明を限定するものであると理解すべきではない。この開示から当業者には様々な代替実施形態、実施例及び運用技術が明らかとなろう。
11…シリコン系基板
12…エピタキシャル成長層
13…クラウン
20…機能層
21…キャリア走行層
22…キャリア供給層
23…二次元キャリアガス層
31…ソース電極
32…ドレイン電極
33…ゲート電極
40…機能層
41…n型クラッド層
42…活性層
43…p型クラッド層
100…リング
110…主面
120…バッファ層
121…第1の窒化物半導体層
122…第2の窒化物半導体層
410…n側電極
430…p側電極
Claims (4)
- シリコン系基板と、
格子定数及び熱膨張係数が互いに異なる第1及び第2の窒化物半導体層が交互に積層された構造を有し、前記第1及び第2の窒化物半導体層のそれぞれの膜厚が端部から主面の中央部に向けて徐々に厚く形成され、前記構造の外縁部において膜厚が外縁に向けて徐々に薄くなるように前記シリコン系基板上に配置されることにより、前記外縁部において膜厚が厚くなるクラウンの発生を防止されたエピタキシャル成長層と
を備えることを特徴とするエピタキシャル基板。 - 前記エピタキシャル成長層の端部が、前記シリコン系基板の端部よりも内側にあることを特徴とする請求項1に記載のエピタキシャル基板。
- 前記シリコン系基板の外縁部が、端部に近づくほど膜厚が薄くなるように面取りされており、前記エピタキシャル成長層の端部が前記シリコン系基板の面取りされた領域上に位置していることを特徴とする請求項1又は2に記載のエピタキシャル基板。
- 請求項1乃至3のいずれか1項に記載されたエピタキシャル基板と、
前記エピタキシャル成長層上に配置された、窒化物半導体からなる機能層と
を備えることを特徴とする半導体装置。
Priority Applications (7)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2012033655A JP6130995B2 (ja) | 2012-02-20 | 2012-02-20 | エピタキシャル基板及び半導体装置 |
US14/376,475 US20150028457A1 (en) | 2012-02-20 | 2013-02-14 | Epitaxial substrate, semiconductor device, and method for manufacturing semiconductor device |
CN201380009855.4A CN104115258B (zh) | 2012-02-20 | 2013-02-14 | 外延基板、半导体装置及半导体装置的制造方法 |
DE112013000648.0T DE112013000648B4 (de) | 2012-02-20 | 2013-02-14 | Epitaktisches Substrat, Halbleitervorrichtung, und Verfahren zur Herstellung einer Halbleitervorrichtung |
PCT/JP2013/000800 WO2013125185A1 (ja) | 2012-02-20 | 2013-02-14 | エピタキシャル基板、半導体装置及び半導体装置の製造方法 |
KR1020147023113A KR102045727B1 (ko) | 2012-02-20 | 2013-02-14 | 에피택셜 기판, 반도체 장치 및 반도체 장치의 제조방법 |
TW102105863A TWI543238B (zh) | 2012-02-20 | 2013-02-20 | An epitaxial substrate, a semiconductor device, and a semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2012033655A JP6130995B2 (ja) | 2012-02-20 | 2012-02-20 | エピタキシャル基板及び半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2013171898A JP2013171898A (ja) | 2013-09-02 |
JP6130995B2 true JP6130995B2 (ja) | 2017-05-17 |
Family
ID=49005384
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2012033655A Active JP6130995B2 (ja) | 2012-02-20 | 2012-02-20 | エピタキシャル基板及び半導体装置 |
Country Status (7)
Country | Link |
---|---|
US (1) | US20150028457A1 (ja) |
JP (1) | JP6130995B2 (ja) |
KR (1) | KR102045727B1 (ja) |
CN (1) | CN104115258B (ja) |
DE (1) | DE112013000648B4 (ja) |
TW (1) | TWI543238B (ja) |
WO (1) | WO2013125185A1 (ja) |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9123866B2 (en) | 2013-09-26 | 2015-09-01 | Seoul Viosys Co., Ltd. | Light emitting device having wide beam angle and method of fabricating the same |
JP6157381B2 (ja) | 2014-03-04 | 2017-07-05 | 信越半導体株式会社 | エピタキシャルウェーハの製造方法及びエピタキシャルウェーハ |
JP6261388B2 (ja) | 2014-03-05 | 2018-01-17 | 信越半導体株式会社 | 半導体エピタキシャルウェーハの製造方法 |
JP6261523B2 (ja) * | 2015-01-08 | 2018-01-17 | 信越半導体株式会社 | 電子デバイス用エピタキシャル基板の製造方法、並びに電子デバイスの製造方法 |
JP2018006575A (ja) * | 2016-07-01 | 2018-01-11 | 株式会社ディスコ | 積層ウエーハの加工方法 |
FR3055064B1 (fr) * | 2016-08-11 | 2018-10-05 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Procede de fabrication d'une couche epitaxiee sur une plaque de croissance |
US10388518B2 (en) * | 2017-03-31 | 2019-08-20 | Globalwafers Co., Ltd. | Epitaxial substrate and method of manufacturing the same |
JP2019067786A (ja) | 2017-09-28 | 2019-04-25 | 株式会社東芝 | 高出力素子 |
JP7147416B2 (ja) | 2018-09-26 | 2022-10-05 | 信越半導体株式会社 | エピタキシャルウェーハの製造方法、エピタキシャル成長用シリコン系基板及びエピタキシャルウェーハ |
CN113990940B (zh) * | 2021-08-30 | 2023-06-09 | 华灿光电(浙江)有限公司 | 碳化硅外延结构及其制造方法 |
CN113981532A (zh) * | 2021-08-30 | 2022-01-28 | 华灿光电(浙江)有限公司 | 用于碳化硅外延生长的基底以及基底的制造方法 |
JP7207588B1 (ja) | 2022-03-10 | 2023-01-18 | 信越半導体株式会社 | Iii族窒化物半導体ウエーハ及びその製造方法 |
JP2023166655A (ja) * | 2022-05-10 | 2023-11-22 | 信越半導体株式会社 | エピタキシャルウェーハ |
Family Cites Families (42)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59227117A (ja) * | 1983-06-08 | 1984-12-20 | Nec Corp | 半導体装置 |
US4925809A (en) * | 1987-05-23 | 1990-05-15 | Osaka Titanium Co., Ltd. | Semiconductor wafer and epitaxial growth on the semiconductor wafer with autodoping control and manufacturing method therefor |
JPH0636413B2 (ja) * | 1990-03-29 | 1994-05-11 | 信越半導体株式会社 | 半導体素子形成用基板の製造方法 |
JPH04129267A (ja) * | 1990-09-20 | 1992-04-30 | Fujitsu Ltd | 半導体基板およびその製造方法 |
JP3211604B2 (ja) * | 1995-02-03 | 2001-09-25 | 株式会社日立製作所 | 半導体装置 |
US5494849A (en) * | 1995-03-23 | 1996-02-27 | Si Bond L.L.C. | Single-etch stop process for the manufacture of silicon-on-insulator substrates |
WO1998013881A1 (fr) * | 1996-09-24 | 1998-04-02 | Mitsubishi Denki Kabushiki Kaisha | Dispositif a semi-conducteur et son procede de production |
JPH11204452A (ja) * | 1998-01-13 | 1999-07-30 | Mitsubishi Electric Corp | 半導体基板の処理方法および半導体基板 |
US6632292B1 (en) * | 1998-03-13 | 2003-10-14 | Semitool, Inc. | Selective treatment of microelectronic workpiece surfaces |
JP2000223682A (ja) * | 1999-02-02 | 2000-08-11 | Canon Inc | 基体の処理方法及び半導体基板の製造方法 |
JP3395696B2 (ja) * | 1999-03-15 | 2003-04-14 | 日本電気株式会社 | ウェハ処理装置およびウェハ処理方法 |
US6267649B1 (en) * | 1999-08-23 | 2001-07-31 | Industrial Technology Research Institute | Edge and bevel CMP of copper wafer |
US6482749B1 (en) * | 2000-08-10 | 2002-11-19 | Seh America, Inc. | Method for etching a wafer edge using a potassium-based chemical oxidizer in the presence of hydrofluoric acid |
JP2002313757A (ja) * | 2001-04-17 | 2002-10-25 | Hitachi Ltd | 半導体集積回路装置の製造方法 |
JP4162892B2 (ja) * | 2002-01-11 | 2008-10-08 | 日鉱金属株式会社 | 半導体ウェハおよびその製造方法 |
KR100550491B1 (ko) * | 2003-05-06 | 2006-02-09 | 스미토모덴키고교가부시키가이샤 | 질화물 반도체 기판 및 질화물 반도체 기판의 가공 방법 |
KR100513920B1 (ko) * | 2003-10-31 | 2005-09-08 | 주식회사 시스넥스 | 화학기상증착 반응기 |
US7157297B2 (en) * | 2004-05-10 | 2007-01-02 | Sharp Kabushiki Kaisha | Method for fabrication of semiconductor device |
JP4826703B2 (ja) * | 2004-09-29 | 2011-11-30 | サンケン電気株式会社 | 半導体素子の形成に使用するための板状基体 |
JP2006173354A (ja) * | 2004-12-15 | 2006-06-29 | Canon Inc | Soi基板の製造方法 |
JP4780993B2 (ja) * | 2005-03-31 | 2011-09-28 | 三洋電機株式会社 | 半導体レーザ素子およびその製造方法 |
JP4849296B2 (ja) * | 2005-04-11 | 2012-01-11 | 日立電線株式会社 | GaN基板 |
JP2007059595A (ja) * | 2005-08-24 | 2007-03-08 | Toshiba Corp | 窒化物半導体素子 |
JP4945185B2 (ja) * | 2006-07-24 | 2012-06-06 | 株式会社東芝 | 結晶成長方法 |
US7755103B2 (en) * | 2006-08-03 | 2010-07-13 | Sumitomo Electric Industries, Ltd. | Nitride gallium semiconductor substrate and nitride semiconductor epitaxial substrate |
ATE546568T1 (de) * | 2006-12-08 | 2012-03-15 | Saint Gobain Cristaux & Detecteurs | Verfahren zur herstellung eines nitrid- einkristalls durch epitaktisches aufwachsen auf ein substrat unter verhinderung von wachstum an den substraträndern |
FR2910179B1 (fr) * | 2006-12-19 | 2009-03-13 | Commissariat Energie Atomique | PROCEDE DE FABRICATION DE COUCHES MINCES DE GaN PAR IMPLANTATION ET RECYCLAGE D'UN SUBSTRAT DE DEPART |
JP4232837B2 (ja) * | 2007-03-28 | 2009-03-04 | 住友電気工業株式会社 | 窒化物半導体発光素子を作製する方法 |
FR2917232B1 (fr) * | 2007-06-06 | 2009-10-09 | Soitec Silicon On Insulator | Procede de fabrication d'une structure pour epitaxie sans zone d'exclusion. |
CN101689484B (zh) * | 2007-07-10 | 2012-02-15 | Nxp股份有限公司 | 失配衬底上的单晶生长 |
JP4514063B2 (ja) * | 2007-08-30 | 2010-07-28 | 古河電気工業株式会社 | Ed型インバータ回路および集積回路素子 |
JP4395812B2 (ja) * | 2008-02-27 | 2010-01-13 | 住友電気工業株式会社 | 窒化物半導体ウエハ−加工方法 |
JP2009256154A (ja) * | 2008-04-21 | 2009-11-05 | Nippon Telegr & Teleph Corp <Ntt> | 半導体結晶成長用基板および半導体結晶 |
US7833907B2 (en) * | 2008-04-23 | 2010-11-16 | International Business Machines Corporation | CMP methods avoiding edge erosion and related wafer |
JP5151674B2 (ja) * | 2008-05-19 | 2013-02-27 | 信越半導体株式会社 | エピタキシャルウエーハの製造方法 |
KR20110036889A (ko) * | 2008-06-27 | 2011-04-12 | 파나소닉 주식회사 | 압전체 소자와 그 제조 방법 |
US7875534B2 (en) * | 2008-07-21 | 2011-01-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Realizing N-face III-nitride semiconductors by nitridation treatment |
FR2941324B1 (fr) * | 2009-01-22 | 2011-04-29 | Soitec Silicon On Insulator | Procede de dissolution de la couche d'oxyde dans la couronne d'une structure de type semi-conducteur sur isolant. |
JP5477685B2 (ja) * | 2009-03-19 | 2014-04-23 | サンケン電気株式会社 | 半導体ウェーハ及び半導体素子及びその製造方法 |
JP5537197B2 (ja) * | 2010-03-12 | 2014-07-02 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
JPWO2011161975A1 (ja) * | 2010-06-25 | 2013-08-19 | Dowaエレクトロニクス株式会社 | エピタキシャル成長基板及び半導体装置、エピタキシャル成長方法 |
JP2015018960A (ja) * | 2013-07-11 | 2015-01-29 | 三菱電機株式会社 | 半導体装置の製造方法 |
-
2012
- 2012-02-20 JP JP2012033655A patent/JP6130995B2/ja active Active
-
2013
- 2013-02-14 US US14/376,475 patent/US20150028457A1/en not_active Abandoned
- 2013-02-14 KR KR1020147023113A patent/KR102045727B1/ko active IP Right Grant
- 2013-02-14 WO PCT/JP2013/000800 patent/WO2013125185A1/ja active Application Filing
- 2013-02-14 CN CN201380009855.4A patent/CN104115258B/zh active Active
- 2013-02-14 DE DE112013000648.0T patent/DE112013000648B4/de active Active
- 2013-02-20 TW TW102105863A patent/TWI543238B/zh active
Also Published As
Publication number | Publication date |
---|---|
TW201401337A (zh) | 2014-01-01 |
CN104115258A (zh) | 2014-10-22 |
KR102045727B1 (ko) | 2019-11-18 |
WO2013125185A1 (ja) | 2013-08-29 |
KR20140125388A (ko) | 2014-10-28 |
US20150028457A1 (en) | 2015-01-29 |
DE112013000648B4 (de) | 2023-09-28 |
DE112013000648T5 (de) | 2015-04-16 |
TWI543238B (zh) | 2016-07-21 |
JP2013171898A (ja) | 2013-09-02 |
CN104115258B (zh) | 2017-12-22 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP6130995B2 (ja) | エピタキシャル基板及び半導体装置 | |
TWI476947B (zh) | An epitaxial wafer, a gallium nitride-based semiconductor device, a gallium nitride-based semiconductor device, and a gallium oxide wafer | |
US8772831B2 (en) | III-nitride growth method on silicon substrate | |
JP5048076B2 (ja) | 電流拡散層を含む発光ダイオードの製造方法 | |
US8530935B2 (en) | Semiconductor device with buffer layer for mitigating stress exerted on compound semiconductor layer | |
US20130140525A1 (en) | Gallium nitride growth method on silicon substrate | |
US8044409B2 (en) | III-nitride based semiconductor structure with multiple conductive tunneling layer | |
JP5163045B2 (ja) | エピタキシャル成長基板の製造方法及び窒化物系化合物半導体素子の製造方法 | |
JP2010232293A (ja) | 半導体装置 | |
JP2012064956A (ja) | 半導体素子 | |
US8405067B2 (en) | Nitride semiconductor element | |
JP2016058693A (ja) | 半導体装置、半導体ウェーハ、及び、半導体装置の製造方法 | |
JP5412093B2 (ja) | 半導体ウェハ製造方法及び半導体装置製造方法 | |
US20120168771A1 (en) | Semiconductor element, hemt element, and method of manufacturing semiconductor element | |
JP5934575B2 (ja) | 窒化物半導体装置の製造方法 | |
US20140077239A1 (en) | Semiconductor device, nitride semiconductor wafer, and method for forming nitride semiconductor layer | |
JP2008071910A (ja) | 窒化物半導体発光ダイオード素子およびその製造方法 | |
JP2015070252A (ja) | 半導体装置、半導体装置の製造方法及びウェハ | |
KR20140031000A (ko) | 반도체 버퍼 구조체 및 이를 포함하는 반도체 소자 | |
JP2010177416A (ja) | 窒化物半導体装置 | |
JP5956616B2 (ja) | 窒化物半導体ショットキダイオード | |
KR20150085950A (ko) | 다중양자우물 구조 활성층을 포함하는 발광다이오드 및 이의 제조방법 | |
JP2013128103A (ja) | 窒化物半導体装置及び窒化物半導体装置の製造方法 | |
WO2015005083A1 (ja) | 窒化物半導体積層基板、窒化物半導体装置および窒化物半導体積層基板の製造方法 | |
JP2015222816A (ja) | 半導体装置及びその製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20141119 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20160119 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20160226 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20160830 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20161003 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20170404 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20170417 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 6130995 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |