JP5921473B2 - 半導体装置の製造方法 - Google Patents
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
- H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
- H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
- H01L2221/68386—Separation by peeling
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Description
以下では、半導体素子や集積回路が形成される第1基板(以下、「デバイス基板」と記載する)と第2基板(以下、「支持基板」と記載する)とを貼り合わせ、支持基板によって支持されるデバイス基板を薄化した後、支持基板から剥離する工程について説明する。
図3は、第2実施形態に係る半導体装置の製造方法を示す説明図である。第2実施形態に係る半導体装置の製造方法は、図1に示す製造工程の後に行う製造工程が第1実施形態とは異なる。このため、図3には、図1に示す製造工程の後に行う製造工程を示している。また、以下の説明では、図1および図2に示す構成要素と同一の構成要素について、図1および図2に示す符号と同一の符号を付することにより、その説明を省略する。
図4は、第3実施形態に係る半導体装置の製造方法を示す説明図である。第3実施形態に係る半導体装置の製造方法は、図1に示す製造工程の後に行う製造工程が第1実施形態とは異なる。このため、図4には、図1に示す製造工程の後に行う製造工程を示している。また、以下の説明では、図1および図2に示す構成要素と同一の構成要素について、図1および図2に示す符号と同一の符号を付することにより、その説明を省略する。
図5は、第4実施形態に係る半導体装置の製造方法を示す説明図である。第4実施形態に係る半導体装置の製造方法は、図1に示す製造工程の後に行う製造工程が第1実施形態とは異なる。このため、図5には、図1に示す製造工程の後に行う製造工程を示している。また、以下の説明では、図1および図2に示す構成要素と同一の構成要素について、図1および図2に示す符号と同一の符号を付することにより、その説明を省略する。
Claims (6)
- 第1基板の一方の主面上に第1接着剤層を設ける工程と、
熱硬化性を有し、前記第1基板と貼り合わされる第2基板および前記第1基板との間の接着力が前記第1接着剤層との間の接着力よりも大きく、前記第1接着剤層の表面を被覆する第2接着剤層を介して、前記第1基板と前記第2基板とを貼り合わせる工程と、
前記第1基板の他方の主面を研削して該第1基板を薄化する工程と、
前記第2接着剤層の周縁部へ物理的な力を加えて該第2接着剤層の外周に沿った環状の切欠部を形成する工程と、
前記第1基板側を固定し、前記第1接着剤層と前記第2接着剤層との界面とを剥離させて前記第1基板から前記第2基板を分離する工程と、を含み、
前記切欠部は、外周が前記第2接着剤層の外周より内側に位置し、かつ内周が前記第1接着剤層の外周よりも内側に位置するとともに、前記第2基板との間に前記第2接着剤層を残して形成されることを特徴とする半導体装置の製造方法。 - 第1接着剤層と、熱硬化性を有し、第1基板と貼り合わされる第2基板および前記第1基板との間の接着力が前記第1接着剤層との間の接着力よりも大きく、前記第1接着剤層の表面を被覆する第2接着剤層とを介して、前記第1接着剤層が前記第1基板側となる様に、前記第1基板の主面と前記第2基板とを貼り合わせる工程と、
前記第1基板の他方の主面を研削して該第1基板を薄化する工程と、
前記第2接着剤層の周縁部へ物理的な力を加えて該第2接着剤層の外周に沿った環状の切欠部を形成する工程と、
前記第1基板側を固定し、前記第1接着剤層と前記第2接着剤層との界面とを剥離させて前記第1基板から前記第2基板を分離する工程と
を含むことを特徴とする半導体装置の製造方法。 - 前記切欠部は、
前記第1基板と前記第2接着剤層との境界を含む領域に形成される
ことを特徴とする請求項2に記載の半導体装置の製造方法。 - 前記切欠部は、
外周が前記第2接着剤層の外周より内側に位置する
ことを特徴とする請求項2または請求項3に記載の半導体装置の製造方法。 - 前記切欠部は、
内周が前記第1接着剤層の外周よりも内側に位置する
ことを特徴とする請求項2〜4のいずれか一つに記載の半導体装置の製造方法。 - 前記切欠部は、
前記第2基板との間に前記第2接着剤層を残して形成される
ことを特徴とする請求項2〜5のいずれか一つに記載の半導体装置の製造方法。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
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JP2013058229A JP5921473B2 (ja) | 2013-03-21 | 2013-03-21 | 半導体装置の製造方法 |
TW102129027A TWI505346B (zh) | 2013-03-21 | 2013-08-13 | Manufacturing method of semiconductor device |
CN201310364759.3A CN104064506B (zh) | 2013-03-21 | 2013-08-20 | 半导体装置的制造方法 |
US14/015,164 US8975160B2 (en) | 2013-03-21 | 2013-08-30 | Manufacturing method for semiconductor device |
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JP2013058229A JP5921473B2 (ja) | 2013-03-21 | 2013-03-21 | 半導体装置の製造方法 |
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JP2014183270A JP2014183270A (ja) | 2014-09-29 |
JP5921473B2 true JP5921473B2 (ja) | 2016-05-24 |
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US (1) | US8975160B2 (ja) |
JP (1) | JP5921473B2 (ja) |
CN (1) | CN104064506B (ja) |
TW (1) | TWI505346B (ja) |
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CN105190844B (zh) * | 2013-05-24 | 2017-08-22 | 富士电机株式会社 | 半导体装置的制造方法 |
TWI671141B (zh) * | 2013-08-30 | 2019-09-11 | 半導體能源研究所股份有限公司 | 支撐體供應裝置及供應支撐體的方法 |
JP2016096218A (ja) * | 2014-11-13 | 2016-05-26 | 三菱化学株式会社 | 積層基板の製造方法及び電子デバイスの製造方法 |
US10804407B2 (en) | 2016-05-12 | 2020-10-13 | Semiconductor Energy Laboratory Co., Ltd. | Laser processing apparatus and stack processing apparatus |
JP2021048303A (ja) | 2019-09-19 | 2021-03-25 | キオクシア株式会社 | 半導体装置 |
FR3109016B1 (fr) * | 2020-04-01 | 2023-12-01 | Soitec Silicon On Insulator | Structure demontable et procede de transfert d’une couche mettant en œuvre ladite structure demontable |
FR3111142B1 (fr) * | 2020-06-09 | 2022-08-05 | Commissariat Energie Atomique | Procédé de collage temporaire |
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US5668045A (en) * | 1994-11-30 | 1997-09-16 | Sibond, L.L.C. | Process for stripping outer edge of BESOI wafers |
TW437078B (en) * | 1998-02-18 | 2001-05-28 | Canon Kk | Composite member, its separation method, and preparation method of semiconductor substrate by utilization thereof |
US20010038153A1 (en) * | 2000-01-07 | 2001-11-08 | Kiyofumi Sakaguchi | Semiconductor substrate and process for its production |
JP2002134374A (ja) * | 2000-10-25 | 2002-05-10 | Mitsubishi Electric Corp | 半導体ウェハ、その製造方法およびその製造装置 |
JP2005026413A (ja) * | 2003-07-01 | 2005-01-27 | Renesas Technology Corp | 半導体ウエハ、半導体素子およびその製造方法 |
DE102004018249B3 (de) * | 2004-04-15 | 2006-03-16 | Infineon Technologies Ag | Verfahren zum Bearbeiten eines Werkstücks an einem Werkstückträger |
CN101127343B (zh) * | 2006-08-18 | 2010-12-15 | 巨擘科技股份有限公司 | 结合ic整合基板与载板的结构及其制造方法与电子装置的制造方法 |
US20090017323A1 (en) * | 2007-07-13 | 2009-01-15 | 3M Innovative Properties Company | Layered body and method for manufacturing thin substrate using the layered body |
EP2075830A3 (en) * | 2007-10-11 | 2011-01-19 | Sumco Corporation | Method for producing bonded wafer |
CA2711266A1 (en) * | 2008-01-24 | 2009-07-30 | Brewer Science Inc. | Method for reversibly mounting a device wafer to a carrier substrate |
JP5489546B2 (ja) | 2009-06-11 | 2014-05-14 | 東京応化工業株式会社 | 貼付方法及び貼付装置 |
JP5534793B2 (ja) * | 2009-12-08 | 2014-07-02 | 株式会社ディスコ | ウエーハの加工方法 |
JP5448860B2 (ja) | 2010-01-13 | 2014-03-19 | 東京応化工業株式会社 | 分離方法及び分離装置 |
JP5571409B2 (ja) * | 2010-02-22 | 2014-08-13 | 株式会社荏原製作所 | 半導体装置の製造方法 |
JP2011181822A (ja) * | 2010-03-03 | 2011-09-15 | Elpida Memory Inc | 半導体装置の製造方法 |
US8852391B2 (en) * | 2010-06-21 | 2014-10-07 | Brewer Science Inc. | Method and apparatus for removing a reversibly mounted device wafer from a carrier substrate |
JP2012204545A (ja) * | 2011-03-24 | 2012-10-22 | Toshiba Corp | 半導体装置の製造方法および製造装置 |
JP2013131652A (ja) * | 2011-12-21 | 2013-07-04 | Fujitsu Semiconductor Ltd | 半導体装置の製造方法、半導体ウェハの加工方法、半導体ウェハ |
JP2014017462A (ja) * | 2012-03-02 | 2014-01-30 | Fujifilm Corp | 半導体装置の製造方法 |
JP6061590B2 (ja) * | 2012-09-27 | 2017-01-18 | 株式会社ディスコ | 表面保護部材および加工方法 |
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- 2013-03-21 JP JP2013058229A patent/JP5921473B2/ja active Active
- 2013-08-13 TW TW102129027A patent/TWI505346B/zh active
- 2013-08-20 CN CN201310364759.3A patent/CN104064506B/zh active Active
- 2013-08-30 US US14/015,164 patent/US8975160B2/en active Active
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Publication number | Publication date |
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CN104064506A (zh) | 2014-09-24 |
JP2014183270A (ja) | 2014-09-29 |
US8975160B2 (en) | 2015-03-10 |
TWI505346B (zh) | 2015-10-21 |
TW201438079A (zh) | 2014-10-01 |
US20140287567A1 (en) | 2014-09-25 |
CN104064506B (zh) | 2017-04-12 |
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