JP5883733B2 - Power converter - Google Patents

Description

  The present invention relates to a power conversion device including switching elements, and more particularly to control of a power conversion device including a PWM rectifier and a PWM inverter.

  FIG. 12 is an example of the configuration of the power converter. In the variable speed drive of the electric motor, as shown in FIG. 12, the DC power is converted from the AC power source 21 by the converter 11, and the DC power smoothed by the smoothing capacitor 41 is converted to AC of variable voltage and variable frequency via the inverter 12. In general, the AC motor 22 is supplied with AC power and driven. The converter 11 and the inverter 12 are composed of a pair of upper and lower switching elements (here, IGBT; described by taking an insulated gate bipolar transistor as an example) for each phase, and perform power conversion by switching the upper and lower alternately.

  Here, in IGBT, the switching loss at the time of switching and the conduction loss during a conduction | electrical_connection period generate | occur | produce. Of these, the switching loss increases with the number of times of switching, but the switching frequency is usually set to about 10 kHz for reasons such as avoiding a frequency with a strong human sensation in order to reduce noise caused by switching. In this way, the switching frequency is set to be higher than the frequency with strong human sensation, but as a method of suppressing noise discomfort even when the switching frequency is reduced, the following method is used to reduce switching loss. There is.

  First, Patent Document 1 reduces the uncomfortable feeling of noise generated by the PWM inverter by giving “1 / f fluctuation” to the carrier frequency. Similarly, Patent Document 2 also reduces noise discomfort by spreading the carrier frequency. In these examples, the carrier wave is deformed, whereas in Patent Document 3, switching is dispersed by superimposing a common component on each phase-modulated wave. The method of deforming the modulated wave has an advantage that it can be easily applied to an inverter control microcomputer.

  These noise suppression methods relate to inverters and do not mention the case where there are both PWM rectifiers and inverters. When there are a converter and an inverter, there are the following problems. In FIG. 12, since the ground stray capacitance 91 of the power source 21 and the ground stray capacitance 92 of the electric motor 22 exist, a zero phase current flows according to the change of the zero phase voltage caused by the switching of the converter 11 and the inverter 12. This zero phase current generates noise to the control circuit. Therefore, generally, as shown in FIG. 12, a filter circuit 5 having reactors 51 and 52 and a ground capacitor 53 is connected between the power source 21 and the converter 11, and the zero phase via the ground floating capacitance 92 of the motor is obtained. A method is used in which the current is not rotated to the power source 21 by making a circuit through the ground capacitor 53. However, an increase in the zero-phase current is not preferable because it causes an increase in the size of the filter circuit.

  FIG. 13 shows a schematic configuration of a zero-phase circuit when the ground capacitor 53 of the filter circuit 5 is not provided. When there is a difference ΔVz between the change amount ΔVz_c of the converter-side zero-phase voltage and the change amount ΔVz_i of the inverter-side zero-phase voltage, the zero-phase impedance Zz is zeroed via the grounding capacitances 91 and 92 of the power source 21 and the motor 22. Phase current flows.

  Therefore, in Patent Document 4, the switching between the converter and the inverter is synchronized to suppress the change in the zero-phase voltage of both to reduce the zero-phase current.

JP-A-6-14557 JP 2010-259326 A JP 2011-111777 A JP 2012-80765 A

  Although the method of Patent Document 4 is effective in reducing the zero-phase current, since the switching timing of the inverter is restricted by the switching timing of the converter, noise suppression becomes insufficient.

  The problem to be solved by the present invention is to achieve both reduction of zero-phase current caused by switching and suppression of unpleasant noise caused by switching in the power conversion device.

  In order to solve the above problems, the power converter of the present invention is connected, for example, between a DC circuit having a first potential and a second potential, a first multiphase AC, and the DC circuit. A first conversion circuit that converts electric power between direct current and alternating current by a switching element, and a second polyphase alternating current and the direct current circuit connected between the direct current and the direct current circuit, and the electric power between the direct current and the alternating current by the switching element. In a power conversion device having a second conversion circuit for conversion and a controller for controlling the first conversion circuit and the second conversion circuit, the controller includes two of the first conversion circuits. Control is performed so that at least one phase of the second conversion circuit is also changed from the first potential to the second potential at the timing when the above phases change simultaneously from the first potential to the second potential. It is characterized by doing.

  With the above configuration, it is possible to reduce discomfort due to noise caused by switching and to reduce the zero-phase current.

The block diagram which shows the structure of Example 1 of this invention. The wave form diagram which shows the waveform in the case of the general control method as a prior art example. The wave form diagram which shows the operation | movement in the case of a general control method as a prior art example. FIG. 3 is a waveform diagram showing waveforms in Example 1. FIG. 3 is a waveform diagram showing an operation in the first embodiment. The wave form diagram which shows the waveform at the time of applying patent document 4 as a comparative example. The wave form diagram which shows the operation | movement at the time of applying patent document 4 as a comparative example. The figure which shows the FFT analysis result of the terminal voltage for demonstrating the effect of this invention. The block diagram which shows the structure of Example 2 of this invention. The block diagram which shows the structure of Example 3 of this invention. The block diagram which shows the structure of Example 4 of this invention. An example of the structure of the power converter device which is an application field of this invention. Schematic configuration of a zero-phase circuit when there is no ground capacitor for the filter circuit.

  Embodiments of the present invention will be described with reference to the drawings. In each drawing and each embodiment, the same or similar components are denoted by the same reference numerals, and description thereof is omitted.

  The configuration of Embodiment 1 of the present invention is shown in FIG. The power converter of FIG. 1 can be used for driving an elevator, for example. As in FIG. 12, the power conversion device of FIG. 1 converts the DC power from the AC power source 21 by the converter 11 which is a conversion circuit, and further converts the DC power smoothed by the smoothing capacitor 41 to the inverter 12 (conversion). Circuit), the AC voltage is converted to AC with a variable voltage and variable frequency, and the AC power is supplied to the electric motor 22. In FIG. 1, the DC circuit has a first potential and a second potential. Moreover, the alternating current of the power supply 21 and the electric motor 22 is a polyphase alternating current, and has illustrated the case where it is each three-phase. A filter circuit 5 is connected between the power supply 21 and the converter 11. The converter 11 and the inverter 12 are each composed of a pair of upper and lower switching elements (in this case, an IGBT; an insulated gate bipolar transistor is described as an example), and the upper and lower alternates by the gate drive circuit 31 of the converter 11 and the gate drive circuit 32 of the inverter 12. Power conversion is performed by switching to. Here, by using a PWM rectifier having a switching element as the converter 11, even when energy regeneration occurs from the motor 22, the regenerated energy is converted into direct current by the inverter 12, and direct current is converted into alternating current by the converter 11. Can be regenerated to power.

  Converter 11 and inverter 12 are controlled by PWM controller 8 (controller). In order to control the voltage of the smoothing capacitor 41 to the target value, the converter controller 42 feedback-controls the power source current by the current detector 61 to create the respective phase voltage commands Vr_ref, Vs_ref, Vt_ref of the converter 11, Thus, the PWM controller 8 performs PWM control.

  The speed control of the electric motor 22 is feedback controlled by the speed controller 7 using the speed detector 71 with respect to the speed command. As a result, the current command created by the speed controller 7 is feedback-controlled by the inverter controller 72 using the current detector 62, and the inverter controller 72 creates each phase voltage command Vu_ref, Vv_ref, Vw_ref of the inverter 12. As a result, the PWM controller 8 performs PWM control (pulse width modulation control).

  Next, the operation of the PWM controller 8 will be described. The PWM controller 8 is configured by, for example, a microcomputer, and each function and each block in the PWM controller 8 shown in FIG. 1 can be realized by software executed by the microcomputer.

  In the PWM control of a general power conversion device, a PWM pulse is obtained by comparing the voltage command of each phase (each phase voltage command Vr_ref, Vs_ref, Vt_ref, each phase voltage command Vu_ref, Vv_ref, Vw_ref) with a carrier wave 80 as a modulation wave. Signals (gate pulse signals Sr, Ss, St, gate pulse signals Su, Sv, Sw) are generated, and the switching of the IGBT is controlled by the gate drive circuits 31 and 32 based on the PWM pulse signal.

  The first embodiment is different from the PWM control of a general power converter in the following points.

  Regarding the control of the converter 11, each phase voltage command Vr_ref, Vs_ref, Vt_ref created by the converter controller 42 is added to the common superimposed component Vadd_c (the common zero phase component) generated by the superimposed component generation unit 8104. Are added by an adder 8103 to calculate modulated waves Vr *, Vs *, and Vt *. Then, the subtraction unit 8102 subtracts the carrier wave 80 from the modulated waves Vr *, Vs *, and Vt *, and the gate pulse signal generation unit 8101 generates gate pulse signals Sr, Ss, and St depending on the magnitude. The gate pulse signals Sr, Ss, St take a value of 0 or 1. The gate drive circuit 31 controls switching of the switching elements of the converter 11 based on the gate pulse signals Sr, Ss, St. Here, as the superimposed component Vadd_c, for example, a sine wave or a random signal can be used. By adding the superimposition component Vadd_c, regular switching is distributed, and unpleasant noise accompanying switching of the converter 11 is reduced. Note that the superimposed component generation unit 8104 determines the magnitude of the superimposed component Vadd_c according to the magnitude of each phase voltage command Vr_ref, Vs_ref, Vt_ref from the converter controller 42 so that the superimposed modulated wave does not exceed the amplitude of the carrier wave. It is desirable to limit this. Note that the addition of the superimposed component Vadd_c is intended to reduce unpleasant noise associated with switching of the converter 11, and thus is not an essential configuration for reducing zero-phase voltage and noise of the inverter 12 described later. .

  The zero-phase voltage calculation unit 8106 calculates the zero-phase voltage Vz_c of the converter 11 from the average of the sum of the generated gate pulse signals Sr, Ss, St (Vz_c = ΣSc / 3 (where Sc = Sr, Ss, St) ). The previous comparison unit 8107 calculates a difference ΔVz_c from the previous zero-phase voltage by comparing with the value of the previous zero-phase voltage Vz_c.

  The difference ΔVz_c from the previous zero-phase voltage indicates the number of phases that are switched in the same potential change direction this time (strictly speaking, one phase changes from the first potential to the second potential, and another 1 When the phase changes from the second potential to the first potential, they cancel each other and the zero phase voltage becomes 0. Therefore, the difference ΔVz_c from the previous zero phase voltage is actually a phase that switches in the same potential change direction. However, there is no problem in judging whether two or more phases are simultaneously switched in the same potential change direction, and one phase changes from the first potential to the second potential. However, when the other two phases change simultaneously from the second potential to the first potential, they cancel each other out and the zero-phase voltage becomes 1/3. However, in reality, a change at such timing does not occur. There is no problem because it is not.) When two or more phases are simultaneously switched in the converter 11 in the same potential change direction (for example, the direction in which the first potential changes to the second potential), the change in the zero-phase voltage becomes large. In order to reduce the change in the zero-phase voltage, the inverter 12 is also controlled to switch at least one phase in the same potential change direction at the same timing. Therefore, the determination unit 8108 determines whether or not two or more phases are simultaneously switched in the same potential change direction in the converter 11 based on the difference ΔVz_c from the previous zero-phase voltage. ΔVadd_i is calculated. Even if not applicable, the change in the zero-phase voltage may become large, so that the process by the reverse direction change suppression unit 83 may be performed as described later. Note that the determination unit 8108 may determine using other signals such as the gate pulse signals Sr, Ss, and St instead of using the difference ΔVz_c from the previous zero-phase voltage.

  Next, control of the inverter 12 will be described. Similarly, in the control of the inverter 12, the superimposing component Vadd_i (zero phase component common to each phase) common to each phase is added to each phase voltage command Vu_ref, Vv_ref, Vw_ref created by the inverter controller 72 by the adding unit 8203. Modulated waves Vu *, Vv *, and Vw * are calculated. Then, the subtraction unit 8202 subtracts the carrier wave 80 from the modulated waves Vu *, Vv *, and Vw *, and the gate pulse signal generation unit 8201 generates the gate pulse signals Su, Sv, and Sw depending on the magnitude. . The gate pulse signals Su, Sv, Sw take a value of 0 or 1. The gate drive circuit 32 controls switching of the switching elements of the inverter 12 based on the gate pulse signals Su, Sv, Sw. Switching is controlled by the superposed component Vadd_i common to each phase so as to be different from the switching timing of a general power converter.

  The zero-phase voltage calculator 8206 calculates the zero-phase voltage Vz_i of the inverter 12 from the average of the sum of the generated gate pulse signals Su, Sv, Sw (Vz_i = ΣSi / 3 (where Si = Su, Sv, Sw) ). The previous comparison unit 8207 calculates a difference ΔVz_i from the previous zero-phase voltage by comparing with the value of the previous zero-phase voltage Vz_i.

  The difference ΔVz_i from the previous zero-phase voltage indicates the number of phases that are switched in the same potential change direction this time (strictly speaking, there is an exception as described in the difference ΔVz_c from the previous zero-phase voltage, and they do not match. But there is no hindrance). When the inverter 12 switches two or more phases at the same time in the same potential change direction (for example, the direction in which the first potential changes to the second potential), the zero-phase voltage becomes large. In order to reduce the zero-phase voltage, the inverter 12 is desirably controlled so as to suppress switching of the other phases so that only one phase switches in the same potential change direction. Therefore, the determination unit 8208 determines whether two or more phases are simultaneously switched in the same potential change direction in the inverter 12 based on the difference ΔVz_i from the previous zero-phase voltage. ΔVadd_i0 is calculated. In addition, even if not applicable, the zero-phase voltage may increase, so that processing by the reverse direction change suppression unit 83 may be performed as described later. Note that the determination unit 8208 may use other signals such as gate pulse signals Su, Sv, and Sw instead of using the difference ΔVz_i from the previous zero-phase voltage.

  Superposed voltage calculator 8210 changes (switches) only one phase of inverter 12 when two or more phases are simultaneously switched in inverter 12 in the same potential change direction (determined by determination unit 8208). Control to correct the changing timing is performed. Specifically, in this case, for example, referring to the output of the subtracting unit 8202, the inverter 12 is configured such that switching of the other phase is suppressed so that only one phase switches in the same potential change direction. A correction voltage ΔVadd_i0 to be superimposed on each phase voltage command Vu_ref, Vv_ref, Vw_ref used for control of the inverter 12 is calculated. For example, if the output of the subtracting unit 8202 of the phase that switches simultaneously in the same potential change direction is changed to plus and is 0.1 and 0.2 respectively, ΔVadd_i0 = −0.15 may be set. With this correction voltage ΔVadd_i0, simultaneous switching in the inverter 12 can be suppressed, the change in the zero-phase voltage can be reduced, and the zero-phase current can be reduced.

  When the converter 11 simultaneously switches two or more phases in the same potential change direction (when determined by the determination unit 8108), the superimposed voltage calculation unit 8209 has at least one phase of the inverter 12 having the same potential change. For example, with reference to the output of the subtraction unit 8202, the correction voltage ΔVadd_i to be superimposed on each phase voltage command Vu_ref, Vv_ref, Vw_ref used for the control of the inverter 12 is calculated so as to switch in the direction. For example, ΔVadd_i is calculated based on the magnitude and change direction of the output of the subtracting unit 8202 so that when the correction voltage ΔVadd_i is applied, the phase to be switched next is switched forward. For example, if the output from the subtracting unit 8202 that is closest to 0 among the outputs of the phase that is changing toward 0 is 0.1, ΔVadd_i = −0.11 (a value that is −0.1 or less) may be set. When the correction voltage ΔVadd_i0 is superimposed in order to suppress the two-phase simultaneous switching of the inverter 12, the ΔVadd_i is calculated in consideration of this amount. Since the correction voltage ΔVadd_i switches the inverter 12 at the same time as the converter 11, the change in the zero-phase voltage can be reduced and the zero-phase current can be reduced.

  When ΔVadd_i is calculated by the superimposed voltage calculation unit 8209, the selection unit 8205 selects the superimposed voltage calculation unit 8209 side.

  The adding unit 8204 adds the correction voltage ΔVadd_i and the correction voltage ΔVadd_i0, and outputs the result as a superimposed component Vadd_i. The corrected gate pulse signals Su, Sv, Sw are calculated by the pulse signal generation unit 8201 and output to the gate drive circuit 32.

  Note that when the inverter 12 side is switched in the same potential change direction at the same time for two or more phases on the converter 11 side (when it is determined to be applicable by the determination unit 8108), the selection unit 8205 performs the superimposed voltage calculation unit 8209. The calculated correction voltage ΔVadd_i is selected, and if not (when determined not to be applicable by the determination unit 8108), control is performed to switch to the correction voltage ΔVadd_i calculated by the reverse direction change suppression unit 83.

  The reverse direction change suppression unit 83 is processed when the determination unit 8108 determines that it is not applicable, or when the determination unit 8208 determines that it is not applicable. Here, even when only one phase is simultaneously switched between the converter 11 and the inverter 12, they are switched in opposite directions (one is changed from the first potential to the second potential and the other is the opposite). ), Since a zero-phase current flows due to a change in the zero-phase voltage, a process of calculating a correction voltage ΔVadd_i for suppressing the switching of the inverter 12 and shifting the switching timing is performed in order to suppress the zero-phase current. In other words, at the timing when only one phase changes in the direction of potential change on the converter 11 side, control is performed so that the potential does not change in the opposite direction for one phase on the inverter 12 side.

  First, the subtraction unit obtains a difference ΔVz of the zero-phase voltage difference by subtracting the difference ΔVz_i from the previous zero-phase voltage from the difference ΔVz_c from the previous zero-phase voltage. Next, the reverse direction change suppression unit 83 determines in the determination unit 832 whether or not the absolute value of the change ΔVz in the zero-phase voltage difference is larger than a predetermined threshold value. This predetermined threshold value is set to the absolute value of the zero-phase voltage when only one phase is switched in only one of converter 11 and inverter 12 (in this case, 1/3).

  The absolute value of the change ΔVz of the zero-phase voltage difference is 0 when there is no switching between the converter 11 and the inverter 12, and 1/3 when only one phase is switched in only one of the converter 11 and the inverter 12. When only one phase is simultaneously switched in the same potential change direction by the converter 11 and the inverter 12, the determination unit 832 determines that it is not applicable, and the superimposed voltage setting unit 833 determines the correction voltage ΔVadd_i = 0 ( Set to No correction required. In this case, the selection unit 835 uses the result of the superimposed voltage setting unit 833.

  In addition, the absolute value of the change ΔVz of the zero-phase voltage difference becomes 2/3 when only one phase is simultaneously switched in the opposite potential change direction by the converter 11 and the inverter 12, respectively. Based on this determination, the superimposed voltage calculation unit 834 refers to, for example, the output of the subtraction unit 8202 to calculate the correction voltage ΔVadd_i so that switching in the inverter 12 is suppressed. For example, if the output of the phase to be switched is 0.1 among the outputs of the subtracting unit 8202, ΔVadd_i = −0.11 (value of −0.1 or less) may be set. In this case, the selection unit 835 uses the result of the superimposed voltage calculation unit 834.

  The correction voltage ΔVadd_i obtained by the reverse direction change suppressing unit 83 is added by the adding unit 8204 when selected by the selecting unit 8205, or is used when not selected by the selecting unit 8205. The subsequent processing is performed.

  The above processing is calculated and output in time for the input sampling period of the gate drive circuits 31 and 32.

  Here, the carrier wave 80 is the same in the converter 11 and the inverter 12. This is because the current of the smoothing capacitor 41 can be reduced by synchronizing the carrier wave between the converter 11 and the inverter 12.

  The effect of Example 1 is demonstrated below.

  First, the reduction of the zero-phase current will be compared. Here, for simplification, the description will be made assuming that the superimposed component Vadd_c to the converter 11 (8104 in FIG. 1) is always 0.

  FIG. 2 is a waveform diagram showing waveforms in the case of a general control method as a conventional example. FIG. 3 is a waveform diagram showing an operation in the case of a general control method as a conventional example. 2 and 3, the horizontal axis represents time t [s]. Here, a case of a method of generating a gate pulse signal by comparing a voltage command and a triangular wave carrier wave, which is a general PWM control method, is taken as an example. 2A shows the voltage commands Vr_ref, Vs_ref, and Vt_ref from the converter controller 42, and FIG. 2B normalizes the waveforms of the voltage commands Vu_ref, Vv_ref, and Vw_ref from the inverter controller 72 with the size of the carrier wave 80. Is shown. FIG. 2C shows a change in the change ΔVz of the zero-phase voltage difference, which is the difference between the difference ΔVz_c between the previous zero-phase voltage of the converter 11 and the difference ΔVz_i between the previous zero-phase voltage of the inverter 12 ( ΔVz = ΔVz_c−ΔVz_i). 2A shows a modulation rate of 0.25 and a frequency of 50 Hz, and FIG. 2B shows a modulation rate of 0.5 and a frequency of 10 Hz.

  In FIG. 2, the period surrounded by the broken line is expanded, and the phase voltage commands (Vr_ref, Vs_ref, Vr_ref), the gate pulse signals (Sr, Ss, St) and the zero-phase voltage Vz_c on the converter 11 side are shown in FIG. , Each phase voltage command (Vu_ref, Vv_ref, Vw_ref), switching pulse (Su, Sv, Sw) and zero phase voltage Vz_i on the inverter 12 side are shown in FIG. 3B, and the difference Vz (the difference between zero phase voltage Vz_c and Vz_i) Vz = Vz_c−Vz_i) and the change ΔVz are shown in FIG. 3A and 3B also show the carrier wave (frequency fc = 2 kHz).

  In FIG. 3, two phases (S phase and T phase) are simultaneously switched to the positive potential on the converter 11 side at the time of t = T1 indicated by a one-dot chain line, whereas no phase is switched on the inverter 12 side. The difference Vz of the zero-phase voltage is 2/3 (two-phase switching) and ΔVz is also the same. Therefore, it is estimated that a large zero-phase current flows compared to the switching of only one phase.

  Next, a case where Example 1 is applied will be described. FIG. 4 is a waveform diagram showing waveforms in the first embodiment, and FIG. 5 is a waveform diagram showing operations in the first embodiment. When there is one corresponding to FIG. 2 and FIG. .

  The phase voltage commands Vr_ref, Vs_ref, and Vt_ref from the converter controller 42 at this time are shown in FIG. 4A, the phase voltage commands Vu_ref, Vv_ref, Vw_ref from the inverter controller 72, the superimposed component Vadd_i on the inverter 12 side, FIG. 4B shows modulated waves Vu *, Vv *, and Vw * that are superimposed and compared with the carrier wave 80. FIG. 4C shows a change ΔVz of the difference Vz between the zero-phase voltage Vz_c on the converter 11 side and the zero-phase voltage Vz_i on the inverter 12 side. In FIG. 2C, which is an example of a general control method, there is a time when ΔVz = 2/3, but in FIG. 4C, ΔVz <0.5 is suppressed.

  In FIG. 4, the period enclosed by the broken line is expanded, and the phase voltage commands (Vr_ref, Vs_ref, Vr_ref), the gate pulse signals (Sr, Ss, St) and the zero-phase voltage Vz_c on the converter 11 side are shown in FIG. FIG. 5B shows the voltage command (Vu_ref, Vv_ref, Vw_ref), the gate pulse signal (Su, Sv, Sw) and the zero-phase voltage Vz_i on the inverter 12 side, and the difference Vz between the zero-phase voltages Vz_c and Vz_i is shown in FIG. The change ΔVz is shown in FIG. In the change ΔVz in FIG. 5C, the portion surrounded by the broken line is suppressed, and the zero-phase current can be reduced.

  Next, an example in which the method of Patent Document 4 is applied as a comparative example will be described. FIG. 6 is a waveform diagram showing a waveform when Patent Document 4 is applied as a comparative example, and FIG. 7 is a waveform diagram showing an operation when Patent Document 4 is applied as a comparative example. When there is a thing corresponding to, it shows correspondingly. Incidentally, since the calculation of the correction voltage Vadd_i is not shown in Patent Document 4, the method of the first embodiment is temporarily switched to the converter 12 when the inverter 11 switches at least one phase as in Patent Document 4. ”(When the correction voltage ΔVadd_i is calculated when the determination unit 8108 is at least one phase) is assumed as a comparative example.

  2 and 4, the phase voltage commands Vr_ref, Vs_ref, and Vt_ref from the converter controller 42 are shown in FIG. 6A, and the phase voltage commands Vu_ref, Vv_ref, Vw_ref from the inverter controller 72, and the inverter 12. FIG. 6B shows the superposed component Vadd_i on the side and the modulated waves Vu *, Vv *, and Vw * that are superposed and compared with the carrier wave 80. Here, the correction voltage Vadd_i is such that the inverter 12 side is switched so as to have the same potential change at all switching timings on the converter 11 side. The change ΔVz of the difference Vz between the zero-phase voltage Vz_c on the converter 11 side and the zero-phase voltage Vz_i on the inverter 12 side is shown in FIG. 6C. The change in the zero-phase voltage on the converter 11 side at all switching timings is shown in FIG. In addition, since the inverter 12 side is also switched, the change ΔVz of the zero-phase voltage difference is always 0, and the zero-phase current is greatly reduced.

  In FIG. 6, the period enclosed by the broken line is enlarged, and the phase voltage commands (Vr_ref, Vs_ref, Vr_ref), the gate pulse signals (Sr, Ss, St) and the zero-phase voltage Vz_c on the converter 11 side are shown in FIG. Fig. 7 (b) shows the difference between the zero-phase voltages Vz_c and Vz_i. Fig. 7B shows the phase voltage commands (Vu_ref, Vv_ref, Vw_ref), the gate pulse signals (Su, Sv, Sw) and the zero-phase voltage Vz_i on the inverter 12 side. FIG. 7C shows Vz and its change ΔVz. There is a significant reduction effect for the zero-phase current.

  However, the comparative examples shown in FIGS. 6 and 7 have a problem in switching noise. FIG. 8 shows the result of harmonic analysis (FFT analysis) of the motor terminal voltage (difference between the zero-phase voltage on the inverter 12 side and the terminal voltage of each phase) contributing to noise in each method. In this case, Vadd_c is set to 0. The vertical axis represents the amplitude ratio, and the horizontal axis represents the frequency f [kHz]. Fig. 8 (1) shows the case of general PWM control (no superposition to the voltage command value), and a component near 2 times (4 kHz) and 3 times (6 kHz) of the carrier frequency (2 kHz) is generated greatly. Yes. On the other hand, in the first embodiment of the present invention shown in FIG. 8 (2), the component in the vicinity of 4 kHz is reduced. On the other hand, in the example in which Patent Document 4 shown in FIG. 8 (3) is applied, although the frequencies near 4 kHz and 6 kHz are reduced, there is a large amplitude near 8 kHz and there is noise of a specific frequency component, and a low frequency component. There is a bad effect that comes out. The maximum value of the amplitude ratio in FIG. 8 (2) is reduced compared to the maximum value of the amplitude ratio in FIGS. 8 (1) and 8 (3), and it can be seen that there is an effect in reducing noise.

  The reason why the noise is reduced in FIG. 8B is that the regular switching timing in the inverter 12 is dispersed by the correction voltage Vadd_i. In FIG. 8 (3), the effect of noise reduction by dispersion of the switching timing can be seen at 4 kHz. However, since the switching of the inverter 12 is synchronized at all the switching timings of the converter 11, the switching timing is limited. On the contrary, there is a problem that noise becomes loud at 8 kHz. When two or more phases are simultaneously switched in the direction of the same potential change in the converter 11 as in the first embodiment, by correcting the switching of the inverter 12, the timing constraint is eased, and the effect of reducing the zero-phase current is As a result, noise can be reduced.

  As described above, in the power conversion device according to the first embodiment, it is possible to achieve both reduction of the zero-phase current and reduction of annoying noise.

  In the first embodiment, the switching of the converter 11 may be corrected when two or more phases are simultaneously switched in the same potential change direction by the inverter 12. In this case, on the inverter 12 side, the switching timing accompanying the switching of the converter 11 is not corrected. Further, in order to suppress noise of the inverter 12, a sine wave or a random signal may be superimposed on each phase voltage command Vu_ref, Vv_ref, Vw_ref.

  A second embodiment of the present invention is shown in FIG. Description of the same part as Example 1 is abbreviate | omitted and only a different point is demonstrated. In the second embodiment, the carrier wave 801 of the converter 11 has a lower frequency than the carrier wave 802 of the inverter 12. Even in this case, the same effect as in the first embodiment can be obtained. On the converter 11 side with a low carrier frequency, if the correction is performed in accordance with the switching on the inverter 12 side, the number of switching times determined by the carrier 801 may increase and the loss may increase. The correction voltage ΔVadd_i is added and superimposed according to the switching of the converter 11. Note that the waveform in this case is higher in frequency than the carrier wave 802 on the inverter 12 side as compared with the first embodiment, but the effect is the same.

  A third embodiment of the present invention is shown in FIG. Only the differences from FIG. 1 will be described here. In the first embodiment and the second embodiment, correction for superimposing for reducing the zero-phase current is performed only on the inverter 12 side. In this example, correction similar to that on the inverter side is performed on the converter 11 side. That is, when the inverter 12 side switches two or more phases simultaneously in the same potential change direction, the determination unit 8208 determines that it corresponds, and the superimposed voltage calculation unit 8109 corrects the converter 11 side in the same manner as the superimposed voltage calculation unit 8209. The voltage ΔVadd_c is calculated. This correction voltage ΔVadd_c is selected by a selection unit 8105 similar to the selection unit 8205. Then, the addition unit 8103 adds the correction voltage ΔVadd_c as the superimposed component Vadd_c to each phase voltage command Vr_ref, Vs_ref, Vt_ref to calculate the modulated waves Vr *, Vs *, Vt *. On the other hand, when switching is not performed in the same potential change direction at the same time on two or more phases on the inverter 12 side (when it is determined not to be applicable by the determination unit 8108), the superimposed voltage setting unit 831 of the reverse direction change suppression unit 83 The correction voltage ΔVadd_c = 0 is set, and the selection unit 8105 uses the result of the superimposed voltage setting unit 831.

  In this case, the superimposed component on the converter side also changes due to the switching on the inverter 12 side, but the effect and operation are the same as those on the inverter 12 side in FIGS.

  As for the control on the inverter 12 side, the correction voltage ΔVadd_i0 is not calculated in the superimposed voltage calculation unit 8210, the addition unit 8204 is not required, and the correction voltage ΔVadd_i is used as it is as the superimposed component Vadd_i.

  A fourth embodiment of the present invention is shown in FIG. This is an example in which the present invention is applied when unpleasant noise is suppressed by spreading the carrier frequency as in Patent Documents 1 and 2. Only differences from the first to third embodiments will be described. Here, based on the configuration of the first embodiment, the frequency of the carrier wave 80 is spread by the frequency spreading unit 84. Accordingly, the superimposition component Vadd_c by the superimposition component generation unit 8104 and the addition unit 8103 need not be superimposed. As for the frequency spreading method, the methods described in Patent Documents 1 and 2 may be used, and the description thereof will be omitted.

  The advantage in this case is that the frequency dispersion for noise suppression can be dealt with by spreading the frequency of the carrier wave 80. Therefore, the purpose of superimposing the superimposed component Vadd_i on each phase voltage command is to reduce the change ΔVz of the zero-phase voltage difference. It is easy to achieve both. In particular, when the modulation rate is high, the allowable range of the superimposed component Vadd_i to be superimposed, that is, the range in which the absolute values of the modulation waves Vu *, Vv *, and Vw * do not exceed 1, becomes narrow. Since both the method of diffusing and the zero-phase current reduction by superimposing a superimposed component on each phase voltage command can be used, there is an advantage that it is easy to achieve both.

  Since the effect is the same with respect to this example, the description by waveform illustration is omitted.

  As mentioned above, although the Example of this invention has been described, the structure demonstrated by each Example so far is an example to the last, and this invention can be suitably changed within the range which does not deviate from a technical idea. Further, the configurations described in the respective embodiments may be used in combination as long as they do not contradict each other.

11: Converter (conversion circuit)
12: Inverter (conversion circuit)
21: Power supply 22: Electric motor 31, 32: Gate drive circuit 41: Smoothing capacitor 42: Converter controller 5: Filter circuit 51, 52: Reactor 53: Ground capacitor 61, 62: Current detector 7: Speed controller 71: Speed Detector 72: Inverter controller 8: PWM controller 91, 92: Ground stray capacitance

Claims (9)

A DC circuit having a first potential and a second potential;
A first conversion circuit connected between a first multi-phase alternating current and the direct current circuit and converting electric power between direct current and alternating current by a switching element;
A second conversion circuit connected between a second polyphase alternating current and the direct current circuit and converting power between direct current and alternating current by a switching element;
In a power converter having a controller for controlling the first converter circuit and the second converter circuit,
The controller is configured such that at least one phase of the second conversion circuit is also at the timing when two or more phases of the first conversion circuit are simultaneously changed from the first potential to the second potential. A power converter that controls to change from one potential to the second potential. In claim 1,
The controller is configured so that at least one phase of the first converter circuit is also changed to the second potential at a timing when two or more phases of the second converter circuit are simultaneously changed from the first potential to the second potential. A power converter that controls to change from one potential to the second potential. In claim 1,
When the controller attempts to simultaneously change two or more phases of the second converter circuit from the first potential to the second potential, only one phase of the second converter circuit is The power converter device which controls to correct the timing which changes so that it may change. In any one of Claim 1 to 3,
At the timing when only one phase of the first conversion circuit changes from the first potential to the second potential, both phases of the second conversion circuit are changed from the second potential to the first potential. A power converter characterized by controlling so as not to change to a potential. In any one of Claims 1-4,
The controller performs pulse width modulation control on the first conversion circuit and the second conversion circuit using a carrier wave having the same frequency. In claim 5,
The power converter according to claim 1, wherein the controller uses the carrier wave for frequency spreading. In claim 1 or 3,
The controller performs pulse width modulation control of the first conversion circuit and the second conversion circuit using carrier waves having different frequencies, and the frequency of the carrier wave used for control of the first conversion circuit is A power conversion device characterized by being lower than the frequency of a carrier wave used for controlling the second conversion circuit. In claim 1 or 3,
The controller controls the pulse width modulation of the first conversion circuit by comparing a modulated wave and a carrier wave, and outputs a sine wave or a random signal to each phase voltage command used for controlling the first conversion circuit. A power conversion device characterized in that a superimposed component of a signal is superimposed on the modulated wave. In any one of Claims 1-8,
The first converter circuit is a converter whose AC side is connected to a power source, and the second converter circuit is an inverter whose AC side is connected to an electric motor.