JP5754425B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device including a cell region and a peripheral region around the cell region.

  Conventionally, a super junction MOS transistor (hereinafter referred to as SJMOS) is known as a semiconductor device that improves the breakdown voltage and the on-resistance. This SJMOS has a repetitive structure (PN column), that is, a super junction structure, in which strip-shaped N-type columns and P-type columns are alternately and repeatedly arranged in the plane direction of the semiconductor substrate. With this structure, an energization path through which current flows easily is formed, so that the on-resistance is low, and electric field concentration is avoided by the super junction structure, so that a high breakdown voltage can be obtained. That is, both high breakdown voltage and low on-resistance are realized.

  Here, in order to ensure the withstand voltage, the withstand voltage structure in the outer peripheral portion is also important. Therefore, for example, in Patent Document 1, in order to ensure the withstand voltage in the peripheral region which is the outer peripheral portion, the column in the peripheral region is once P-rich toward the outside, and then the P-rich region is further increased. A structure in which the outside is N-rich has been proposed. With such an impurity concentration distribution, the breakdown voltage of the peripheral region can be increased.

JP 2006-73615 A

  In the above conventional technique, the N-rich region is located on the outer side of the P-rich in the peripheral region. For this reason, the equipotential lines in the PN column are pulled to the back side of the substrate by the P-rich region, and conversely, the equipotential lines are pulled to the substrate surface side in the N-rich region further outside the P-rich region. End up.

  In particular, the tip of the equipotential line in the N-rich region extends to the substrate surface side, but the position of the tip is not fixed, so there is one tip of each equipotential line in the N-rich region. There is a possibility to concentrate on. As a result, there is a problem that electric field concentration occurs, and as a result, the withstand voltage decreases.

  In view of the above points, an object of the present invention is to provide a semiconductor device that can ensure a withstand voltage without concentrating an electric field in the peripheral region in a structure that ensures a withstand voltage in the peripheral region.

  In order to achieve the above object, according to the first aspect of the present invention, the first conductivity type column region (4) and the second conductivity type column region (5) as drift regions are formed on the first conductivity type layer (3). And a semiconductor substrate (6) having a super junction structure formed by the first conductivity type column region (4) and the second conductivity type column region (5). The semiconductor device in which the region in which the element (9) is formed is the cell region (1) and the region provided on the outer periphery of the cell region (1) is the peripheral region (2). It is characterized by.

  First, the device electrode (12, 17) of the semiconductor element (9) is provided in the cell region (1), and the outermost peripheral electrode (21) electrically connected to the semiconductor substrate (6) in the peripheral region (2). Is provided.

  Further, in the peripheral region (2), the second conductivity type layer (7) is formed on the super junction structure, and the device electrodes (12, 17) and the outermost periphery are formed on the second conductivity type layer (7). A potential dividing region (23) for electrically connecting the electrode (21) and dividing the voltage between the element electrodes (12, 17) and the outermost peripheral electrode (21) into a plurality of stages is provided.

  The potential dividing region (23) is characterized in that at least a part thereof overlaps with the peripheral region (2) when viewed from the thickness direction of the semiconductor substrate (6).

As described above, since the potential dividing region (23) is located on the peripheral region (2), a shielding effect against the influence of the charges trapped in the peripheral region (2) can be realized, thereby preventing the fluctuation of the breakdown voltage. be able to. Therefore, a withstand voltage can be secured without concentrating the electric field on the peripheral region (2).
In the first aspect of the invention, the balance of the impurity concentration between the first conductivity type column region (4) and the second conductivity type column region (5) constituting the super junction structure is present in the peripheral region (2). A charge balance changing region (27) continuously changing toward the side opposite to the cell region (1) side is provided.
In such a structure, the potential distribution region (23) and the charge balance change region (27) formed in the peripheral region (2) can be overlapped, so that the potential distribution on the surface of the semiconductor substrate (6) and the potential division region ( 23) can be made to coincide with the surface potential distribution. Therefore, for example, the guard ring (19) can be provided so as to surround the cell region (1) in the potential division region (23), but there is no difference in breakdown voltage depending on the presence or absence of the guard ring (19). For this reason, the effect that the charge balance margin with respect to a pressure | voltage resistant fall can be ensured further is acquired.

  According to the second aspect of the present invention, the potential dividing region (23) includes the device electrodes (12, 17) such that the potential distribution in the super junction structure is equally spaced in the plane direction of the first conductivity type layer (3). ) Side, the voltage between the element electrodes (12, 17) and the outermost peripheral electrode (21) is divided into a plurality of stages from the outermost peripheral electrode (21) side. According to this, since the potential can be fixed at equal intervals in the potential division region (23), it is possible to secure a wide margin (charge balance margin) of variation in impurity concentration with respect to a decrease in breakdown voltage.

  In the invention according to claim 3, the length of the potential division region (23) from the cell region (1) side to the outermost peripheral electrode (21) side in the surface direction of the first conductivity type layer (3) is the second length. It is characterized by being longer than the depth reaching the first conductivity type layer (3) from the surface of the conductivity type layer (7). As a result, it is possible to prevent the breakdown voltage in the peripheral region (2) from decreasing and to ensure the breakdown voltage in the peripheral region (2) (see FIG. 5).

  The invention according to claim 4 is characterized in that the outermost peripheral electrode (21) is provided so as to overlap the super junction structure when viewed from the thickness direction of the semiconductor substrate (6). According to this, the spread of the potential distribution formed in the super junction structure can be suppressed by the outermost peripheral electrode (21).

The invention according to claim 5 is characterized in that the charge balance changing region (27) in the peripheral region (2) is adjacent to the cell region (1). According to this, since the equipotential lines are changed adjacent to the cell region (1), when the equipotential lines of the cell region (1) move in a high carrier injection state, the equipotential lines of the peripheral region (2), etc. It is easy for the potential line to follow, thereby suppressing the occurrence of avalanche due to electric field concentration.

As in the invention described in claim 6 , the first conductivity type column region (4) and the second conductivity type column region (5) constituting the super junction structure are formed of the cell region (1) and the peripheral region (2). It is repeatedly arranged throughout. The direction in which the first conductivity type column region (4) and the second conductivity type column region (5) are repeatedly arranged is defined as a repetition direction. In the peripheral region (2), the width of the second conductivity type column region (5) in the direction perpendicular to the repeating direction in the surface direction of the first conductivity type layer (3) is the second conductivity type column region (5). A structure in which the balance of the impurity concentration in the charge balance changing region (27) continuously changes by being continuously narrowed toward the end portion (5a) of the electrode may be employed.

As in the invention described in claim 7 , the pitch at which the first conductivity type column region (4) and the second conductivity type column region (5) are repeated in the cell region (1) and the peripheral region (2) is constant. In the peripheral region (2), the width of the second conductivity type column region (5) continuously narrows from the cell region (1) to the opposite side, so that the impurities in the charge balance change region (27) are reduced. A structure in which the balance of concentration continuously changes may be employed.

On the other hand, as in the invention described in claim 8 , in the peripheral region (2), the first conductivity type column region (4) and the second conductivity type column region (5) constituting the super junction structure are separated from each other in the cell region ( 1), the first conductivity type column region (4) and the second conductivity type column region (5) are repeatedly arranged toward the opposite side of the cell region (1). . The direction in which the first conductivity type column region (4) and the second conductivity type column region (5) are repeatedly arranged is defined as a repetition direction. In the peripheral region (2), the width of the first conductivity type column region (4) becomes wider as the distance from the cell region (1) in the repeat direction increases, so that the impurity concentration in the charge balance change region (27) increases. A structure in which the balance continuously changes may be used.

In the invention according to claim 9 , the super junction structure is a structure in which the second conductivity type column region (5) is dotted in the form of dots with respect to the first conductivity type column region (4), and the cell region In (1), the proportion of the second conductivity type column region (5) formed is smaller in the peripheral region (2) than in the cell region (1), and the proportion is in the outer peripheral direction of the cell region (1). It is characterized by being made smaller as it goes.

In this manner, the charge conductivity changing region (27) may be configured by forming the second conductivity type column region (5) in a dot shape with respect to the first conductivity type column region (4). Even with such a structure, the effect described in claim 1 or 5 can be obtained.

In the invention according to claim 10 , in the super junction structure, in the cell region (1), the first conductivity type column region (4) and the second conductivity type column region (5) are the first conductivity type layer (3). One direction parallel to the surface direction is defined as a column longitudinal direction, and a direction perpendicular to the longitudinal direction is repeated alternately as a column repeating direction. In the peripheral region (2), the second conductivity type column region ( 5) is formed in a multi-frame shape surrounding the cell region (1), and in the peripheral region (2), the interval between the second conductivity type column regions (5) formed in the multi-frame shape is the cell region (1). It is characterized by being widened toward the outer circumferential direction.

  As a result, the number of carriers in the first conductivity type column region (4) increases, so that the proportion of the first conductivity type impurity in the charge balance change region (27) becomes larger than the proportion of the second conductivity type impurity. In this way, the balance of impurity concentration in the charge balance change region (27) can be continuously changed.

  In addition, the code | symbol in the bracket | parenthesis of each means described in this column and the claim shows the correspondence with the specific means as described in embodiment mentioned later.

1 is a plan view of a semiconductor device according to a first embodiment of the present invention. It is AA sectional drawing of FIG. It is the top view which showed the guard ring and Zener diode of the peripheral region. (A) is a plan view in which the width of the P-type column region in the peripheral region is uniformly changed, and (b) is a plan view in which the width of the P-type column region in the peripheral region is continuously changed. It is the figure which showed the relationship between the length of an electric potential division area | region, and a proof pressure. In the structure in which the potential dividing region is not provided in the peripheral region, (a) is a simulation result of the potential distribution when the N-type impurity concentration in the peripheral region is constant, and (b) is the N-type in the peripheral region. It is the figure which showed the simulation result of the electric potential distribution of the structure where the impurity concentration of changed continuously. It is the figure which showed the simulation result of the electric potential distribution in the structure which provided the electric potential division area | region in the structure of FIG. It is the figure which showed the relationship between the surplus density | concentration of a peripheral region, and the proof pressure of a semiconductor device. It is sectional drawing of the semiconductor device which concerns on 2nd Embodiment of this invention. It is a top view of the super junction structure of the semiconductor device which concerns on 3rd Embodiment of this invention. (A) is sectional drawing of the peripheral region of the semiconductor device which concerns on 4th Embodiment of this invention, (b) is sectional drawing of the peripheral region of the semiconductor device in which the guard ring is not provided. FIG. 12 is a diagram showing a relationship between a charge Q trapped between an interlayer insulating film and an insulating layer and a withstand voltage in the structure shown in FIGS. 11A and 11B. It is a top view of the semiconductor device concerning a 5th embodiment of the present invention. It is a top view of the semiconductor device concerning a 6th embodiment of the present invention. It is sectional drawing of the semiconductor device which concerns on 7th Embodiment of this invention. It is a top view of the semiconductor device concerning an 8th embodiment of the present invention. (A), (b) is the top view which showed concentration distribution of the N type column area | region in the corner part vicinity of the super junction structure which concerns on other embodiment both.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, the same or equivalent parts are denoted by the same reference numerals in the drawings. The N type and N + type shown in the following embodiments correspond to the first conductivity type of the present invention, and the P type corresponds to the second conductivity type of the present invention.

(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a plan view of the semiconductor device according to the present embodiment. As shown in this figure, the semiconductor device includes a cell region 1 in which a semiconductor element is formed and a peripheral region 2. A peripheral region 2 is provided on the outer periphery of the cell region 1 so as to surround the rectangular cell region 1.

  2 is a cross-sectional view taken along the line AA in FIG. 1 and shows a cross section of the peripheral region 2 including the outer edge portion of the cell region 1. As shown in FIG. 2, a number of MOSFETs are formed in the cell region 1.

  First, in the semiconductor device, an N-type column region 4 and a P-type column region 5 are formed as drift regions on an N + type drain layer 3, and the N-type column region 4 and the P-type column region 5 are A semiconductor substrate 6 having a super junction structure that is repeatedly arranged in one direction parallel to the surface direction of the drain layer 3 is provided.

  A P-type layer 7 formed by epitaxial growth is provided on the super junction structure. The P-type layer 7 is provided over the cell region 1 and the peripheral region 2. On the other hand, a drain electrode 8 is formed on the opposite side of the drain layer 3 from the super junction structure.

  In the cell region 1, a trench gate type MOSFET is formed as the semiconductor element 9. Although the structure of the MOSFET is general, in brief, a trench 10 that penetrates the N + type source region and the P type channel layer formed in the P type layer 7 and reaches the N type column region 4 is formed. A gate insulating film and a gate layer are sequentially formed on the inner wall surface of the trench 10, and a trench gate structure including the trench 10, the gate insulating film, and the gate layer is configured. A P-type body region is also formed in the P-type channel layer. Note that the structure of this MOSFET is an example, and other structures may be used.

  The trench 10 is provided so that the surface direction of the surface where the N-type column region 4 and the P-type column region 5 are in contact with the extending direction in which the trench 10 is extended. Further, if one N-type column region 4 and one P-type column region 5 adjacent to the N-type column region 4 are defined as a set of column structures, a trench gate structure is provided for each set of column structures. ing.

  On the gate layer, an interlayer insulating film 11 is formed which covers the gate layer and is provided with a contact hole exposing the P-type channel layer. The interlayer insulating film 11 is, for example, LOCOS. A source electrode 12 is formed so as to cover the interlayer insulating film 11 and to be in contact with the P-type channel layer through a contact hole of the interlayer insulating film 11.

  On the other hand, in the peripheral region 2, an interlayer insulating film 11 is formed on the P-type layer 7. The thickness of this interlayer insulating film 11 is, for example, 800 nm. An insulating layer 13 is formed on the interlayer insulating film 11, and a polysilicon layer 14 having a thickness of, for example, 400 nm is formed on the insulating layer 13. The insulating layer 13 is BPSG, for example. The polysilicon layer 14 is patterned as a wiring, and a gate wiring 15 and a field plate 16 are sequentially laid out from the cell region 1 side.

  The gate wiring 15 is electrically connected to the gate layer, and a gate electrode 17 is formed on the gate wiring 15. A relay electrode 18 that is electrically connected to the source electrode 12 is formed on the field plate 16.

  A plurality of guard rings 19 are laid out at equal intervals toward the side opposite to the cell region 1 outside the field plate 16 in the polysilicon layer 14. For example, the guard rings 19 are arranged in multiple stages so as to surround the cell region 1 as a conductive region. As the guard ring 19, for example, an N-type conductive region, a P-type conductive region, or a metal may be employed.

  Further, an outermost peripheral ring 20 is laid out on the outermost side of the polysilicon layer 14, and an outermost peripheral electrode (EQR) 21 is formed on the outermost peripheral ring 20. The outermost ring 20 is electrically connected to the guard ring 19 closest to the outermost electrode 21 among the plurality of guard rings 19.

  The outermost peripheral electrode 21 is located on the outer edge side of the semiconductor device, that is, on the outermost edge portion of the peripheral region 2. The outermost peripheral electrode 21 is electrically connected to an N type epitaxial region located around the drift region via an N + type region 22 provided in the same layer as the P type layer 7.

  The gate wiring 15, the field plate 16, the plurality of guard rings 19, and the outermost peripheral ring 20 are covered with the insulating layer 13, and the gate wiring 15, the field plate 16, and a part of the outermost peripheral ring 20 are part of the insulating layer 13. Is exposed from. The total thickness of the insulating layer 13 is, for example, 800 nm. The gate electrode 17 and the relay electrode 18 are connected to the gate wiring 15 and the field plate 16 through the opening of the insulating layer 13.

  The outermost peripheral electrode 21 is provided so as to overlap the super junction structure when viewed from the thickness direction (substrate normal direction) of the semiconductor substrate 6. Thereby, the spread of the potential distribution of the super junction structure is suppressed by the outermost peripheral electrode 21.

  Of the regions where the polysilicon layer 14 is laid out in the peripheral region 2 as described above, the region where the plurality of guard rings 19 are laid out is the potential dividing region 23. That is, the potential division region 23 is a region above the P-type layer 7 (on the insulating layer 13 side), and electrically connects the source electrode 12 (relay electrode 18) and the outermost peripheral electrode 21 and at the same time the source electrode 12 ( This is a region where the voltage between the relay electrode 18) and the outermost peripheral electrode 21 is divided into a plurality of stages. Note that the length of the peripheral region 2 is, for example, 250 μm, and the length of the potential division region 23 is, for example, 100 μm.

  In order to divide the voltage into a plurality of stages, each guard ring 19 is connected by a Zener diode 24 that secures a desired breakdown voltage. In the present embodiment, the Zener diode 24 is provided so that the element potential is distributed in the outer diameter direction of the semiconductor device. The withstand voltage of the one-stage Zener diode 24 that connects one guard ring 19 and the adjacent guard ring 19 is, for example, 30V. Using such a Zener diode 24, for example, a voltage of 600 V is divided.

  The plurality of guard rings 19 are arranged at equal intervals from the source electrode 12 (relay electrode 18) side to the outermost peripheral electrode 21 side in the potential dividing region 23. For this reason, the potential dividing region 23 applies a voltage between the source electrode 12 (relay electrode 18) and the outermost peripheral electrode 21 at equal intervals from the source electrode 12 (relay electrode 18) side to the outermost peripheral electrode 21 side. Divide into multiple stages. Thereby, the potential can be fixed at equal intervals from the source electrode 12 (relay electrode 18) side to the outermost peripheral electrode 21 side in the potential division region 23, so that a margin (charge balance margin) of variation in impurity concentration with respect to a decrease in breakdown voltage can be obtained. Widely secured.

  The layout in which the guard rings 19 are arranged at equal intervals is an example. If the potential distribution generated in the semiconductor substrate 6 in the potential dividing region 23 can be fixed at equal intervals, the guard rings 19 may not be arranged at equal intervals. good.

  FIG. 3 is an enlarged plan view of a part of the peripheral region 2 of FIG. 2, in particular, a plan view showing the guard ring 19 and the Zener diode 24. As shown in this figure, the Zener diode 24 includes N-type regions 25 and P arranged alternately between one guard ring 19 and the other guard ring 19 along the extending direction of the guard ring 19. It consists of a mold region 26. These N-type region 25 and P-type region 26 are formed by ion implantation into polysilicon. In this way, the Zener diodes 24 are arranged in series, so that the potential of each stage of each guard ring 19 is divided.

  Next, the charge balance of the super junction structure of the semiconductor substrate 6 will be described. First, in this embodiment, the N-type column region 4 and the P-type column region 5 constituting the super junction structure are repeatedly arranged over the entire cell region 1 and the peripheral region 2. The depth of the N-type column region 4 and the P-type column region 5 is, for example, 47 μm and the pitch is 7 μm.

  In the cell region 1, the N-type column region 4 and the P-type column region 5 have the same impurity concentration, and the PN column has the same number of P carriers and the same number of N carriers. Balance conditions are met. For example, the impurity concentration of the N-type column region 4 and the P-type column region 5 is 5 × 10 15 cm −3, respectively.

  On the other hand, the peripheral region 2 is provided with a region in which the balance of impurity concentration between the N-type column region 4 and the P-type column region 5 continuously changes toward the side opposite to the cell region 1 side. This region is a region below the P-type layer 7 (on the drain layer 3 side) and is a charge balance change region 27. The outermost peripheral electrode 21 is located around the charge balance change region 27.

  Here, in the charge balance changing region 27 of the peripheral region 2, the impurity concentration balance continuously changes toward the side opposite to the cell region 1 side. This will be described with reference to FIG. Examples of the planar layout of the super junction structure located in the peripheral region 2 are shown in FIGS. 4 (a) and 4 (b), respectively. In FIG. 4, the peripheral region 2 is expressed as an “N rich region”. An N type epitaxial region around the drift region is expressed as an “N epi region”.

  Assuming that the direction in which the N-type column region 4 and the P-type column region 5 are repeatedly arranged is a repeat direction, in FIG. 4A, in the repeat direction, the width of the P-type column region 5 located in the peripheral region 2 is the cell. The width is uniformly narrower than the width of the P-type column region 5 located in the region 1. However, since the width of the P-type column region 5 is constant in the peripheral region 2, the balance of the impurity concentration is constant in the charge balance changing region 27 of the peripheral region 2 without changing.

  On the other hand, in FIG. 4B, in the peripheral region 2, the width of the P-type column region 5 in the direction perpendicular to the repeating direction in the surface direction of the drain layer 3 continues toward the end portion 5 a of the P-type column region 5. It becomes narrower. That is, the end portion 5a of the P-type column region 5 is tapered in the vertical direction. In other words, the width of the N-type column region 4 in the vertical direction is continuously increased. As a result, the volume of the N-type column region 4 continuously increases in the peripheral region 2 as the distance from the cell region 1 increases, so that the impurity concentration is more imbalanced than the N-type in the repetition direction. That is, the N type becomes dominant and becomes N rich toward the outermost edge side of the peripheral region 2. As described above, the balance of the impurity concentration in the charge balance changing region 27 continuously changes depending on the planar layout of the P-type column region 5.

  In the present embodiment, the potential division region 23 is disposed so as to overlap the charge balance change region 27 when viewed from the thickness direction of the semiconductor substrate 6.

  In addition, the inventors examined the relationship between the length of the potential division region 23 and the breakdown voltage. The result is shown in FIG. The “length of the potential dividing region 23” corresponds to the length of the potential dividing region 23 from the cell region 1 side to the outermost peripheral electrode 21 side in the surface direction of the drain layer 3.

  Then, when looking at FIG. 5, the length of the potential dividing region 23 is 50 μm or more, and the breakdown voltage is stably secured. Here, the length of 50 μm is a value longer than the depth reaching the drain layer 3 from the surface of the P-type layer 7.

  That is, when the length of the potential division region 23 is short, the breakdown voltage is determined by the peripheral region 2, but the length of the potential division region 23 is longer than the depth reaching the drain layer 3 from the surface of the P-type layer 7. In this case, a stable withstand voltage of 600 V or more can be obtained, and the withstand voltage in the peripheral region 2 can be reliably ensured. Therefore, the length of the potential dividing region 23 is longer than the depth reaching the drain layer 3 from the surface of the P-type layer 7.

  Subsequently, the inventors examined the breakdown voltage of the semiconductor device in the presence or absence of the potential division region 23 in the peripheral region 2 and in the presence or absence of the charge balance change region 27 in the peripheral region 2. The results are shown in FIGS.

  First, in FIG. 6, the potential dividing region 23 (the guard ring 19 and the Zener diode 24) is not provided in the peripheral region 2, and the impurity concentration of the N-type column region 4 in the peripheral region 2 is the impurity concentration of the P-type column region 5. For example, this is a simulation result of the potential distribution of a structure that is 10% higher than that of FIG.

  FIG. 6A shows a simulation result in a layout structure in which the super junction structure of the peripheral region 2 is shown in FIG. That is, the surplus concentration = {(the impurity amount in the N-type column region 4) − (the impurity amount in the P-type column region 5)} / (the volume of the column portion) / the structure in which the surplus concentration obtained in the peripheral region 2 is uniform. The potential distribution is shown. From this result, it can be seen that equipotential lines are concentrated on the cell region 1 side in the peripheral region 2, and there is a possibility that electric field concentration occurs.

  On the other hand, FIG. 6B shows a simulation result in the layout structure in which the super junction structure of the peripheral region 2 is shown in FIG. That is, it is a simulation result of a structure in which the balance of impurity concentration continuously changes in the charge balance changing region 27 of the peripheral region 2. Looking at this result, the equipotential lines gradually change from the cell region 1 side of the peripheral region 2.

  FIG. 7 shows a simulation result of the potential distribution of the structure in which the guard ring 19 is provided in the structure of the potential distribution as described above. Since the guard ring 19 is provided, the potential on the guard ring 19 side of the super junction structure is fixed.

  FIG. 7A shows a simulation result in a structure in which the guard ring 19 is provided in the structure of FIG. Looking at this result, the equipotential lines in the peripheral region 2 are not drawn smoothly, and the intervals between the equipotential lines are not uniform.

  On the other hand, FIG. 7B shows a simulation result in a structure in which a guard ring 19 in which potentials are fixed at equal intervals is added to the structure in FIG. 6B. Looking at this result, the equipotential lines in the super junction structure are drawn smoothly, and the equipotential lines are evenly spaced.

  FIG. 8 is a diagram showing the relationship between the excess concentration in the peripheral region 2 and the breakdown voltage of the semiconductor device. In FIG. 8, the breakdown voltage of the structure without the guard ring 19 is shown by a broken line, and the breakdown voltage of the structure with the guard ring 19 is shown by a solid line.

  FIG. 8A shows the breakdown voltage due to the presence or absence of the guard ring 19 in a structure in which the charge balance change region 27 is not provided. From this result, it can be seen that there is a difference in the withstand voltage depending on the presence or absence of the guard ring 19 regardless of the change in the excess concentration in the peripheral region 2. This is because the potential distribution formed by the super junction structure in the peripheral region 2 is affected because the potential distribution on the silicon surface formed by the super junction structure in the peripheral region 2 does not match the surface potential distribution defined by the guard ring 19. In the case of FIG. 8A, the breakdown voltage is reduced in the vicinity of the outermost peripheral ring 20 in the peripheral region 2.

  On the other hand, FIG. 8B shows the breakdown voltage due to the presence or absence of the guard ring 19 in the structure in which the charge balance change region 27 is provided. Looking at this result, even if the surplus concentration in the peripheral region 2 changes, there is no difference in the withstand voltage with or without the guard ring 19. Thus, by matching the potential distribution on the silicon surface formed by the super junction structure in the peripheral region 2 with the surface potential distribution defined by the guard ring 19, a margin of variation in impurity concentration with respect to a decrease in breakdown voltage (charge balance margin). ) Can be secured widely. In the present embodiment, as described above, the surface potential distribution of the super junction structure in the peripheral region 2 is obtained by arranging the guard rings 19 at equal intervals while having a structure in which the balance of the impurity concentration in the peripheral region 2 continuously changes. Are equally spaced.

  Next, a method for manufacturing a semiconductor device in which the semiconductor substrate 6 includes the charge balance change region 27 and the potential division region 23 on the interlayer insulating film 11 will be described. First, a semiconductor substrate 6 having a super junction structure is prepared. Here, since the super junction structure corresponding to the peripheral region 2 has the planar layout of FIG. 4B, for example, the balance of the impurity concentration of the charge balance changing region 27 in the peripheral region 2 continuously changes. Prepare what you have.

  Then, the semiconductor element in the cell region 1 is formed by a normal semiconductor process. In addition, a P-type layer 7 is formed on the outer periphery of the cell region 1 in the semiconductor substrate 6, and an interlayer insulating film 11 is formed on the P-type layer 7.

  Thereafter, an insulating layer 13 and a polysilicon layer 14 are formed on the interlayer insulating film 11, and the polysilicon layer 14 is laid out on the gate wiring 15, the field plate 16, the plurality of guard rings 19, and the outermost peripheral ring 20. Further, the polysilicon layer 14 is left so as to connect the guard rings 19. Here, each guard ring 19 is laid out so that a plurality of guard rings 19 positioned in the potential division region 23 are positioned on the charge balance change region 27.

  Then, N-type regions 25 and P-type regions 26 are alternately formed along the extending direction of the guard ring 19 by performing ion implantation into the polysilicon layer 14 between the guard rings 19. Subsequently, an insulating layer 13 is further formed so as to cover each guard ring 19, the N-type region 25, and the P-type region 26, and a part of the insulating layer 13 is opened, and the source electrode 12, the entire cell region 1 to the peripheral region 2, The gate electrode 17, the relay electrode 18, and the outermost peripheral electrode 21 are formed together. Thus, the semiconductor device shown in FIGS. 1 to 3 is completed.

  As described above, in the present embodiment, the charge balance changing region 27 in which the balance of impurity concentration continuously changes is provided in the peripheral region 2, and a plurality of voltages between the source electrode 12 and the drain electrode 8 are provided thereon. It is characterized in that a potential dividing region 23 to be divided is provided.

  Thus, since the potential dividing region 23 is located on the charge balance changing region 27 in which the impurity concentration continuously changes, it is trapped between the interlayer insulating film 11 and the insulating layer 13 in the peripheral region 2. It is possible to realize a shielding effect against the influence of electric charges and to prevent fluctuations in breakdown voltage. Therefore, a withstand voltage can be secured without concentrating the electric field on the peripheral region 2.

  As for the correspondence between the description of the present embodiment and the description of the claims, the N-type column region 4 corresponds to the “first conductivity type column region” in the claims, and the P-type column region 5 This corresponds to the “second conductivity type column region” in the claims. The source electrode 12 corresponds to an “element electrode” in the claims.

(Second Embodiment)
In the present embodiment, parts different from the first embodiment will be described. FIG. 9 is a cross-sectional view of the semiconductor device according to the present embodiment. In FIG. 9, the wiring between the electrodes and the Zener diode 24 are omitted.

  As shown in FIG. 9, in this embodiment, each guard ring 19 extending in a direction perpendicular to the repeating direction of the N-type column region 4 and the P-type column region 5 in the surface direction of the drain layer 3 is a semiconductor. It overlaps with the P-type column region 5 when viewed from the thickness direction of the substrate 6. Thus, the end of the guard ring 19 may be positioned above the P-type column region 5.

(Third embodiment)
In the present embodiment, parts different from the first and second embodiments will be described. FIG. 10 is a plan view showing a layout of the super junction structure according to this embodiment located in the peripheral region 2. As shown in FIG. 10, in the peripheral region 2, the N-type column region 4 and the P-type column region 5 constituting the super junction structure are laid out in a ring shape (multiple frame shape) surrounding the cell region 1. An N-type column region 4 and a P-type column region 5 are repeatedly arranged toward the side opposite to the cell region 1.

  Here, in FIG. 10A, the widths of the N-type column region 4 and the P-type column region 5 are constant in the repeating direction in which the N-type column region 4 and the P-type column region 5 are repeatedly arranged, and N The mold column regions 4 are arranged at equal intervals. In this arrangement, there is no change in the impurity concentration balance in the charge balance changing region 27 in the peripheral region 2.

  On the other hand, in FIG. 10B, the width of the N-type column region 4 of the charge balance changing region 27 becomes wider as the distance from the cell region 1 increases in the repetition direction. In other words, the distance between the P-type column regions 5 increases as the distance from the cell region 1 increases. As a result, the number of carriers in the N-type column region 4 increases, and the charge balance change region 27 becomes N-rich. In this way, the impurity concentration balance in the charge balance change region 27 can be continuously changed.

(Fourth embodiment)
In the present embodiment, parts different from the first to third embodiments will be described. In each of the above embodiments, each guard ring 19 is connected by the Zener diode 24 that is a potential dividing element, but in the present embodiment, each guard ring 19 is connected by a resistor.

  FIG. 11A is a cross-sectional view in the peripheral region 2 of the semiconductor device according to the present embodiment. As shown in this figure, in this embodiment, the gate electrode 17 and the drain electrode 8 are potential-divided by the potential-dividing region 23. A resistor 28 is used as a potential dividing element. The resistance value is, for example, 1 × 1010Ω.

  The inventors examined the breakdown voltage depending on the presence or absence of the potential division region 23 in the structure of the peripheral region 2 shown in FIG. The result is shown in FIG. FIG. 12 shows the relationship between the charge Q trapped between the interlayer insulating film 11 and the insulating layer 13 and the withstand voltage. As shown in this figure, in the structure in which the potential division region 23 shown in FIG. 11B is not provided, the breakdown voltage changes in an unstable manner according to the presence of the charge Q. On the other hand, as shown in FIG. 11, it was found that a constant breakdown voltage can be obtained without depending on the presence of the charge Q in the structure in which the potential dividing region 23 is provided.

  Note that the same results as in FIG. 12 were obtained in the structure using the Zener diode 24 as the potential dividing element.

  As described above, the resistor 28 may be used as the potential dividing element. As the resistor 28, the N-type region 25 and the P-type region 26 constituting the Zener diode 24 may be used as the resistor 28 by lowering the impurity concentration when forming the Zener diode 24 shown in the first embodiment. it can.

  Further, since the voltage between the gate electrode 17 and the drain electrode 8 is divided, the relay electrode 18 for connecting the guard ring 19 and the source electrode 12 becomes unnecessary. Therefore, the semiconductor device can be downsized accordingly.

  As for the correspondence between the description of this embodiment and the description of the claims, the gate electrode 17 corresponds to the “element electrode” in the claims.

(Fifth embodiment)
In the present embodiment, parts different from the first to fourth embodiments will be described. FIG. 13 is a plan view of a semiconductor device according to the fifth embodiment of the present invention. As shown in this figure, in the present embodiment, one guard ring 19 is arranged in a spiral shape. Thereby, the potential of each stage can be divided by using the resistance component of the guard ring 19.

(Sixth embodiment)
In the present embodiment, parts different from the first to fifth embodiments will be described. FIG. 14 is a plan view of a semiconductor device according to the sixth embodiment of the present invention.

  As shown in this figure, in the present embodiment, the layout of the pattern is such that the P-type column region 5 is dotted in the form of dots with respect to the N-type column region 4. That is, the N-type column region 4 and the P-type column region 5 are alternately and repeatedly arranged in the radial direction from the center of the cell region 1. The rate at which the P-type column region 5 is formed is smaller in the peripheral region 2 than in the cell region 1, and the proportion is reduced as it goes in the outer peripheral direction of the cell region 1.

  Thus, even if the P-type column region 5 is formed in a dot shape with respect to the N-type column region 4, the charge balance change region 27 can be formed, and the same effect as in the first embodiment can be obtained. it can.

(Seventh embodiment)
In the present embodiment, parts different from the first to sixth embodiments will be described. FIG. 15 is a cross-sectional view of the semiconductor device according to the seventh embodiment of the present invention, and corresponds to the AA cross section of FIG.

  As shown in this figure, the N-type column region 4 and the p-type column region 5 can be formed up to the surface of the semiconductor substrate 6, and the p-type layer 7 can be formed by ion implantation instead of epitaxial growth.

  As described above, when the p-type layer 7 is formed by ion implantation, the N-type column region 4 can be formed up to the surface of the semiconductor substrate 6, so that the N + -type region 22 (as shown in the first embodiment) ( 2), the N-type epitaxial region around the drift region and the outermost peripheral electrode 21 can be electrically connected.

(Eighth embodiment)
In the present embodiment, parts different from the first embodiment will be described. FIG. 16 is a plan view of a semiconductor device according to the eighth embodiment of the present invention.

  As shown in this figure, in the semiconductor device of the present embodiment, in the column repetition direction, the pitch of each column is kept constant without changing from the cell region 1 toward the outer circumferential direction, while the P-type column region 5 The width is narrowed from the cell region 1 toward the outer peripheral direction. In addition, the end 5a of the P-type column region 5 is tapered in the direction perpendicular to the repeating direction, and the taper angle of the tapered portion is repeated as the width of the P-type column region 5 is reduced, that is, repeated. In the direction, it is made smaller toward the outer peripheral direction of the cell region 1.

  As described above, since the taper angle of the end portion 5a becomes smaller as the width of the P-type column region 5 becomes smaller, the corner portion when the entire super junction structure is regarded as a square (hereinafter simply referred to as a corner portion of the super junction structure). The electric field concentration at can be suppressed.

  Further, by gradually reducing the width of the P-type column region 5, the balance of the impurity concentration between the N-type column region 4 and the P-type column region 5 is continuously increased from the cell region 1 toward the outer peripheral direction. Can be changed.

  As described above, even if the width of the P-type column region 5 is changed in the column repeating direction, the peripheral region 2 is made an N-rich region where N-type carriers are dominant, and the cell region 1 is directed to the outer peripheral direction. Thus, the N-type impurity concentration is continuously changed to be higher than the P-type impurity concentration. Therefore, the same effect as that of the first embodiment can be obtained.

(Other embodiments)
The configurations of the semiconductor devices described in the above embodiments are examples, and the present invention is not limited to the configurations described above, and other configurations that can realize the present invention may be employed. For example, the semiconductor element is not limited to a MOSFET but may be a diode or the like. The MOSFET may be a planar type instead of a trench gate type.

  Even in the structure in which the resistor 28 is used as the potential dividing element, the N-type column region 4 in the charge balance change region 27 is not limited to the layout shown in FIG. 4B, but also in the layout shown in FIG. good.

  In each of the above embodiments, the potential dividing region 23 entirely overlaps the charge balance changing region 27 when viewed from the thickness direction of the semiconductor substrate 6. However, this is an example of arrangement, and at least a part of the potential dividing region 23 only has to overlap with the peripheral region 2, preferably the charge balance changing region 27 when viewed from the thickness direction of the semiconductor substrate 6. In other words, if the potential dividing region 23 is positioned at least on the peripheral region 2, a shielding effect against the influence of charges trapped in the peripheral region 2 can be realized, and as a result, fluctuations in breakdown voltage can be prevented. Therefore, the breakdown voltage can be secured without concentrating the electric field on the peripheral region 2. If the potential dividing region 23 overlaps the charge balance changing region 27, the potential distribution on the silicon surface can be matched with the surface potential distribution defined by the guard ring 19, and there is a difference in breakdown voltage depending on the presence or absence of the guard ring. No longer occurs. For this reason, the effect that the charge balance margin with respect to a pressure | voltage resistant fall can be ensured further is acquired.

  In the first embodiment, the voltage between the outermost peripheral electrode 21 (drain electrode 8) and the source electrode 12 is divided in the potential division region 23. However, as in the fourth embodiment, the outermost peripheral electrode 21 is divided. The structure may be such that the voltage between the (drain electrode 8) and the gate electrode 17 is divided. As a result, the lead electrode for the gate can be used, and the area for the relay electrode 18 for leading the source electrode to the outside is not necessary, so that the area of the semiconductor device can be reduced accordingly.

  Furthermore, in the first embodiment, the potential is divided using the Zener diode 24 as the potential dividing element. However, as in the fourth embodiment, the resistor 28 may be used.

  In each of the above embodiments, the balance of the impurity concentration is continuously changed in the charge balance changing region 27. However, the continuous change in the balance of the impurity concentration is the charge balance changing region in the peripheral region 2. It is preferable to start from an area closer to the cell area 1 than 27. That is, it is preferable that the charge balance changing region 27 in the peripheral region 2 is adjacent to the cell region 1. As a result, the equipotential lines start to bend from the cell region 1 side, so that a deviation in the amount of carrier supply between the cell region 1 and the peripheral region 2 when a high carrier injection state occurs is suppressed.

  It is preferable to change the N-type impurity concentration in the N-type epitaxial region located around the drift region in accordance with the structure of the charge balance changing region 27.

  For example, in the structure shown in FIG. 4B, the widths of the P-type column regions 5 arranged in the repeating direction are made constant, and the taper angle of the tapered end portion 5a is also made constant. The pitch of the P-type column regions 5 is increased toward the outer peripheral direction of the cell region 1 in the repetition direction. In the case of such a structure, the ratio of the N-type impurity concentration to the P-type impurity concentration increases toward the outer peripheral direction of the cell region 1 in both the repeating direction and the vertical direction.

  For this reason, when the corner portion of the super junction structure is increased at the same rate as the ratio of the N-type impurity concentration in the repeat direction and the direction perpendicular thereto, the other portion of the charge balance change region 27 is Further, the ratio of the N-type impurity concentration is increased. That is, in the corner portion, the ratio of the N-type impurity concentration is multiplied by the ratio of the N-type impurity concentration in the repeat direction and the direction perpendicular thereto, so that the N-type impurity concentration ratio becomes higher.

  Therefore, in the case of the structure shown in FIG. 4B, at the corner portion, a portion where the ratio of the N-type impurity concentration in the repetition direction is the same as a portion where the ratio of the N-type impurity concentration in the vertical direction is the same. In this way, the ratio of the N-type impurity concentration may be set. In other words, if a line indicating the same N-type impurity concentration ratio is defined as an isoconcentration line, the isoconcentration line may be tapered at the corner as shown in FIG. As a result, it is possible to suppress the N-type impurity concentration ratio at the corner portion from becoming higher than the other portions of the charge balance change region 27.

  In the structure shown in FIG. 16, the width of each P-type column region 5 arranged in the repeating direction is gradually reduced, and the taper angle of the tapered end portion 5a is also gradually reduced. . The pitch of the P-type column region 5 is made constant in the repetition direction. Even in such a structure, the ratio of the N-type impurity concentration to the P-type impurity concentration increases toward the outer peripheral direction of the cell region 1 in both the repeating direction and the vertical direction. For this reason, also in this case, if the ratio of the N-type impurity concentration in the corner portion is set so that the portions where the ratio of the N-type impurity concentration to the concentration of the P-type impurity concentration is the same in the repetition direction and the vertical direction are connected to each other. good.

  However, as compared with the structure of FIG. 4B, even if the corner portion of the super junction structure is increased at the same rate as the ratio of the N-type impurity concentration in the repeat direction and the direction perpendicular thereto, N The degree of increasing the ratio of the type impurity concentration is small. For this reason, as shown in FIG. 17B, the isoconcentration lines at the corners are shaped so that the curvature gradually increases toward the outer periphery of the cell region 1. As a result, it is possible to suppress the N-type impurity concentration ratio at the corner portion from becoming higher than the other portions of the charge balance change region 27.

  In each of the above embodiments, the concentration of the N-type impurity and the P-type impurity constituting the N-type column region 4 and the P-type column region 5 is constant, and the formation area (volume) thereof is set in the outer peripheral direction of the cell region 1. The charge balance change region 27 is configured by changing the direction of the charge balance. This is because the manufacturing process can be simplified if the concentration of the N-type impurity and the P-type impurity constituting the N-type column region 4 and the P-type column region 5 is constant. However, if the manufacturing process of the N-type column region 4 and the P-type column region 5 is divided into a plurality of times according to the impurity concentration, the concentration of the N-type impurity and P-type impurity constituting them can be changed. Therefore, the charge balance change region 27 is formed by changing the concentration of the N-type impurity and the P-type impurity constituting the N-type column region 4 and the P-type column region 5 as it goes toward the outer periphery of the cell region 1. May be.

  In short, the charge balance change region 27 only needs to have a smaller charge amount as it goes toward the outer periphery of the cell region 1. For this reason, for example, the N-type impurity concentration in the N-type column region 4 may be increased toward the outer peripheral direction of the cell region 1 while the P-type impurity concentration in the P-type column region 5 is kept constant. .

  Similarly, in the case of the structure in which the P-type column regions 5 are scattered in a dot shape as in the sixth embodiment, the dots constituting the P-type column region 5 are moved toward the outer periphery of the cell region 1. The charge balance change region 27 may be configured to reduce the formation area (volume).

DESCRIPTION OF SYMBOLS 1 Cell region 2 Peripheral region 3 Drain layer 4 N-type column region 5 P-type column region 5a End of P-type column region 6 Semiconductor substrate 7 P-type layer 9 Semiconductor element 12 Source electrode 17 Gate electrode 21 Outermost peripheral electrode 23 Potential division Area 27 Charge Balance Change Area

Claims (10)

A first conductivity type column region (4) and a second conductivity type column region (5) as drift regions are formed on the first conductivity type layer (3), and the first conductivity type column region (4 And a semiconductor substrate (6) in which a super junction structure is constituted by the second conductivity type column region (5),
Of the semiconductor substrate (6), a region where the semiconductor element (9) is formed is a cell region (1), and a region provided on the outer periphery of the cell region (1) is a peripheral region (2). A semiconductor device,
In the cell region (1), device electrodes (12, 17) of the semiconductor device (9) are provided, and an outermost peripheral electrode (electrically connected to the semiconductor substrate (6) in the peripheral region (2) ( 21)
In the peripheral region (2), a second conductivity type layer (7) is formed on the super junction structure, and on the second conductivity type layer (7), the device electrodes (12, 17) and A potential dividing region (23) for electrically connecting the outermost peripheral electrode (21) and dividing the voltage between the element electrodes (12, 17) and the outermost peripheral electrode (21) into a plurality of stages is provided. And
The potential dividing region (23) is at least partially overlapped with the peripheral region (2) when viewed from the thickness direction of the semiconductor substrate (6) ,
Further, the peripheral region (2) has a balance of impurity concentration between the first conductivity type column region (4) and the second conductivity type column region (5) constituting the super junction structure in the cell region (1). A semiconductor device comprising a charge balance changing region (27) that continuously changes toward a side opposite to the) side .   The potential dividing region (23) extends from the element electrode (12, 17) side so that the potential distribution in the super junction structure is equally spaced in the plane direction of the first conductivity type layer (3). 2. The semiconductor device according to claim 1, wherein the voltage between the element electrodes (12, 17) and the outermost peripheral electrode (21) is divided into a plurality of stages toward the outer peripheral electrode (21) side. .   The length of the potential division region (23) from the cell region (1) side to the outermost peripheral electrode (21) side in the surface direction of the first conductivity type layer (3) is the second conductivity type layer ( 7. The semiconductor device according to claim 1, wherein the depth is longer than a depth reaching the first conductivity type layer from the surface of 7).   The said outermost peripheral electrode (21) is provided so that it may overlap with the said super junction structure seeing from the thickness direction of the said semiconductor substrate (6), The one of Claim 1 thru | or 3 characterized by the above-mentioned. Semiconductor device. Wherein said charge balance change area of the peripheral region (2) (27) The semiconductor device according to any one of claims 1 to 4, characterized in that adjacent to the cell area (1) . The first conductivity type column region (4) and the second conductivity type column region (5) constituting the super junction structure are repeatedly arranged over the entire cell region (1) and the peripheral region (2). And
When the direction in which the first conductivity type column region (4) and the second conductivity type column region (5) are repeatedly arranged is a repetition direction,
In the peripheral region (2), the width of the second conductivity type column region (5) in the direction perpendicular to the repeating direction in the surface direction of the first conductivity type layer (3) is the second conductivity type column region ( 5. The impurity concentration balance in the charge balance change region (27) is continuously changed by being narrowed continuously toward the end (5a) of 5). The semiconductor device according to any one of 1 to 5 . In the cell region (1) and the peripheral region (2), the pitch in which the first conductivity type column region (4) and the second conductivity type column region (5) are repeated is constant, and the peripheral region In (2), the width of the second conductivity type column region (5) continuously narrows from the cell region (1) toward the opposite side, so that the impurity concentration in the charge balance change region (27) is reduced. The semiconductor device according to claim 6 , wherein the balance continuously changes. In the peripheral region (2), the first conductivity type column region (4) and the second conductivity type column region (5) constituting the super junction structure are laid out in a ring shape surrounding the cell region (1). And the first conductivity type column region (4) and the second conductivity type column region (5) are repeatedly arranged toward the opposite side of the cell region (1),
When the direction in which the first conductivity type column region (4) and the second conductivity type column region (5) are repeatedly arranged is a repetition direction,
In the peripheral region (2), the width of the first conductivity type column region (4) becomes wider as the distance from the cell region (1) in the repetitive direction increases. the semiconductor device according to any one of claims 1 to 5, wherein the balance of the impurity concentration is continuously changed. The super junction structure is a structure in which the second conductivity type column region (5) is dotted in a dot shape with respect to the first conductivity type column region (4).
In the cell region (1), the proportion of the second conductivity type column region (5) formed in the peripheral region (2) is smaller than that in the cell region (1), and the proportion is the cell region. 6. The semiconductor device according to claim 1 , wherein the semiconductor device is reduced in a direction toward the outer peripheral direction of (1). In the super junction structure, in the cell region (1), the first conductivity type column region (4) and the second conductivity type column region (5) are arranged in a plane direction of the first conductivity type layer (3). A parallel direction is defined as a column longitudinal direction, and a direction perpendicular to the longitudinal direction is defined as a column repetition direction. The second conductivity type column region (5) is formed in the peripheral region (2). Is configured in a multi-frame shape surrounding the cell region (1),
In the peripheral region (2), the interval between the second conductivity type column regions (5) configured in the multiple frame shape is widened toward the outer peripheral direction of the cell region (1). A semiconductor device according to any one of claims 1 to 5 .