JP4126910B2

JP4126910B2 - Semiconductor device

Info

Publication number: JP4126910B2
Application number: JP2002001282A
Authority: JP
Inventors: 達司永岡; 泰彦大西
Original assignee: Fuji Electric Device Technology Co Ltd
Current assignee: Fuji Electric Co Ltd
Priority date: 2002-01-08
Filing date: 2002-01-08
Publication date: 2008-07-30
Anticipated expiration: 2022-01-08
Also published as: JP2003204065A

Description

【０００１】
【発明の属する技術分野】
本発明は、ＭＯＳＦＥＴ（絶縁ゲート型電界効果トランジスタ）、ＩＧＢＴ（伝導度変調型ＭＯＳＦＥＴ）、バイポーラトンラジスタ等の能動素子やダイオード等の受動素子に適用可能で高耐圧化と大電流容量化が両立する縦形パワー半導体装置に関する。
【０００２】
基板の両面に電極部を備えてその基板の厚さ方向に電流が流れる縦形ドリフト部を持つ縦形半導体装置においては、オン抵抗（電流容量）と耐圧との間にはトレードオフ関係が存在することから、縦形ドリフト部として、不純物濃度を高めた縦形ｎ型領域と縦形ｐ型領域とを基板の沿面方向へ交互に繰り返して成る並列ｐｎ構造を採用することが知られている。しかし、この並列ｐｎ構造の縦形ドリフト部では速く空乏化するものの、ドリフト部の周りで電流が実質上流れない耐圧構造部では空乏層が外方向や基板深部へは拡がり難く、電界強度がシリコンの臨界電界強度に速く達するため、耐圧構造部で耐圧が制限されてしまう。設計耐圧を得るには、耐圧構造部にも並列ｐｎ構造を採用した縦形半導体装置とすることが望ましい。
【０００３】
図９は縦形ＭＯＳＦＥＴにおけるドリフト部及び素子外周部（耐圧構造部）を示す平面図、図１０は図９中のＡ−Ａ′線に沿って切断した状態を示す縦断面図、図１１は図９中のＢ−Ｂ′線に沿って切断した状態を示す縦断面図である。なお、図９ではドリフト部の１／４を斜線部分で示してある。
【０００４】
このｎチャネル縦形ＭＯＳＦＥＴは、裏側のドレイン電極１８が導電接触した低抵抗のｎ^＋ドレイン層（コンタクト層）１１の上に形成された第１の並列ｐｎ構造のドレイン・ドリフト部２２と、このドリフト部２２の表面層に選択的に形成された素子活性領域たる高不純物濃度のｐベース領域（ｐウェル，チャネル領域）１３ａと、そのｐベース領域１３ａ内の表面側に選択的に形成された高不純物濃度のｎ^＋ソース領域１４と、基板表面上にゲート絶縁膜１５を介して設けられたポリシリコン等のゲート電極層１６と、層間絶縁膜１９ａに開けたコンタクト孔を介してｐベース領域１３ａ及びｎ^＋ソース領域１４に跨って導電接触するソース電極１７とを有している。ウェル状のｐベース領域１３ａの中にｎ^＋ソース領域１４が浅く形成されており、２重拡散型ＭＯＳ部を構成している。なお、２６はｐ^＋コンタクト領域で、また、図示しない部分でゲート電極層１６の上に金属膜のゲート配線が導電接触している。
【０００５】
第１の並列ｐｎ構造のドレイン・ドリフト部２２は、基板の厚み方向に配向する第１の層状縦形のｎ型領域２２ａと基板の厚み方向に配向する第１の層状縦形のｐ型領域２２ｂとを交互に繰り返して接合した構造である。上端がｐベース領域１３ａの挾間領域１２ｅに達する第１の層状縦形のｎ型領域２２ａが実質的な電路領域となっている。第１の層状縦形のｎ型領域２２ａの下端はｎ^＋ドレイン層１１に接している。また、第１の層状縦形のｐ型領域２２ｂは、その上端がｐベース領域１３ａのウェル底面に接し、その下端がｎ^＋ドレイン層１１に接している。
【０００６】
基板表面とｎ^＋ドレイン層１１との間で縦形ドレイン・ドリフト部２２の周りの耐圧構造部２０にも、基板の厚さ方向に配向する第２の層状縦形のｎ型領域２０ａと、基板の厚さ方向に配向する第２の層状縦形のｐ型領域２０ｂとを基板の沿面方向へ交互に繰り返して接合して成る第２の並列ｐｎ構造が形成されている。耐圧構造部２０の第２の並列ｐｎ構造の表面上には、表面保護及び安定化のために、熱酸化膜又は燐シリカガラス（ＰＳＧ）から成る酸化膜（絶縁膜）２３が成膜されている。第２の並列ｐｎ構造では空乏層が拡がり易くするために、第２の並列ｐｎ構造の不純物濃度を第１の並列ｐｎ構造の不純物濃度に比して低下するか、或いは第２の並列ｐｎ構造の繰り返しピッチＰ２を第１の並列ｐｎ構造の繰り返しピッチＰ１よりも小さくしてある。
【０００７】
【発明が解決しようとする課題】
しかしながら、図９乃至図１１に示す縦形ＭＯＳＦＥＴにあっては、次のような問題点があった。
【０００８】
即ち、ドレイン・ドリフト部２２である第１の並列ｐｎ構造の最外側における第１の層状縦形のｎ型領域２２ａａの周りに、これとは不純物濃度又は繰り返しピッチの異なる第２の並列ｐｎ構造の最内側における第２の縦形層状のｐ型領域２０ｂｂが存在するため、ｎ型領域２２ａａとｐ型領域２０ｂｂとのチャージバランスがどうしても崩れる。そのため、第１の並列ｐｎ構造と第２の並列ｐｎ構造との境界の表面Ｘ付近では電界集中を招き、耐圧を低下させてしまう。このような構造においては、設計耐圧を得ることが困難であって、耐圧構造部２０に第２の並列ｐｎ構造を設けることの意義が没却している。
【０００９】
そこで、上記問題点に鑑み、本発明の課題は、第１の並列ｐｎ構造であるドリフト部の周りにも耐圧構造部として第２の並列ｐｎ構造を有する半導体装置において、耐圧構造部での表面電界を緩和することにより、高耐圧化及び大電流化を一層図り得る半導体装置を提供することにある。
【００１０】
【課題を解決するための手段】
上記課題を解決するために、本発明に係る半導体装置の基本構造は、基板の第１主面側に選択的に形成されて成る素子活性部に導電接続する第１の電極層と、基板の第２主面側に形成されて成る第１導電型の低抵抗層に導電接続する第２の電極層と、素子活性部と低抵抗層との間に介在し、オン状態ではドリフト電流が縦方向に流れると共にオフ状態では空乏化する縦形ドリフト部と、素子活性部及び縦形ドリフト部の周りで第１主面と低抵抗層との間に介在し、オン状態では非電路領域であってオフ状態では空乏化する耐圧構造部とを有するものである。縦形ドリフト部は基板の厚み方向に配向する第１の縦形第１導電型領域と基板の厚み方向に配向する第１の縦形第２導電型領域とを交互に繰り返して接合して成る第１の並列ｐｎ構造である。また、耐圧構造部は基板の厚み方向に配向する第２の縦形第１導電型領域と基板の厚み方向に配向する第２の縦形第２導電型領域とを交互に繰り返して接合して成る第２の並列ｐｎ構造を有している。そして、第２の並列ｐｎ構造の不純物濃度が第１の並列ｐｎ構造の不純物濃度よりも低くなっているか、及び／又は、第２の並列ｐｎ構造の繰り返しピッチが第１の並列ｐｎ構造の繰り返しピッチよりも小さくなっている。なお、基板の第１主面側に選択的に形成された素子活性部とは、例えば縦型ＭＯＳＦＥＴの場合は第１主面側で反転層を形成するチャネル拡散層とソース領域を含むスイッチング部、バイポーラトランジスタの場合はエミッタ又はコレクタ領域を含むスイッチング部であり、ドリフト部の第１主面側で導通と非導通の選択機能を持つ能動部分又は受動部分を指す。
【００１１】
斯かる基本構造において、本発明におけるドリフト部の周りの耐圧構造部は、第２の並列ｐｎ構造のみから成るのではなく、ドリフト部に隣接して繰り返しピッチが当該ドリフト部から引き続き１ピッチ以上外側へ延長された第１の並列ｐｎ構造の一部分である内周構造部と、この内周構造部に隣接した第２の並列ｐｎ構造である外周構造部とを有するものである。このため、ドリフト部の隣接周辺部分には第１の並列ｐｎ構造と第２の並列ｐｎ構造との境界が存在せず、その境界は耐圧構造部の内周構造部と外周構造部との間に存在することになるため、ドリフト部の隣接外周部分では並列ｐｎ構造のチャージバランスの崩れが起こらず、それ故、ドリフト部の隣接外周部分での表面電界を抑制でき、高耐圧化を図ることができる。
【００１２】
また、本発明では、耐圧構造部の第１主面上の絶縁膜の上には内周構造部を覆って先端が外周構造部の上にまで張り出て成るフィールドプレートを有する。このため、フィールドプレートが長く張り出し、その先端直下の電界集中部分がドリフト部の隣接外周部分から外れて外周構造部になるので、内周構造部での表面電界を更に抑制でき、一層の高耐圧化を図ることができる。
【００１３】
このとき、絶縁膜で十分に耐圧を確保すれば、絶縁膜下の並列ｐｎ構造部分での耐圧分担が小さくなる。そうすれば仮に第１と第２の並列ｐｎ構造の境界部分でチャージバランスが崩れたとしても、それによる耐圧の低下分は絶縁膜が保持する耐圧で補われるので、素子全体としては影響を受けずに済む。また、フィールドプレートの先端より外側に位置する耐圧構造部においても、耐圧の分担が小さくなれば表面電界の集中が抑えられる。そこで本発明では、絶縁膜の膜厚をドリフト部側から外周構造部側に向けて厚く形成することで、高耐圧化を図ることができる。
【００１４】
この絶縁膜はその膜厚がドリフト部側から外周構造部側に向けて漸増するものが望ましい。しかしながら、このような絶縁膜の成膜は困難であることから、その絶縁膜はドリフト部側から外周構造部側にかけて段階的に厚く形成する。設計耐圧７００Ｖクラスでは、絶縁膜の膜厚段数は２以上とすることが望ましい。しかしながら、膜厚の急変部分でフィールドプレートには段差が生じるので、その直下で電界集中が生じる。
【００１５】
この問題を解決するため、本発明では、内周構造部の第１の並列ｐｎ構造のうちで第１の縦形第２導電型領域を外側に持つｐｎ接合面の第１主面側位置とフィールドプレートの段差位置とを合致させてある。第１の縦形第２導電型領域は凡そ電位浮遊状態であるが、第１の縦形第２導電型領域が第１の縦形第１導電型領域よりも外側にあるので第１主面側で互いに接近する等電位線のうち高電位側の等電位線を第１の縦形第２導電型領域の外側へ振り分ける。このため、フィールドプレートの段差直下での等電位線同士の密集が解消し、電界集中を有効的に緩和することができ、高耐圧化を図ることができる。
【００１６】
このように、第１の並列ｐｎ構造と第２の並列ｐｎ構造との境界のチャージバランスの崩れによる電界集中やフィールドプレートの段差直下の電界集中を緩和できるが、耐圧構造部の外周構造部でのフィールドプレートの先端直下で生じる電界集中も緩和することが必要である。例えば、外周構造部における第２の並列ｐｎ構造の第１の主面側に第１導電型の高抵抗層を形成し、その第１の主面側に第２導電型のガードリングを正規に形成しても構わないが、本発明では、正規のガードリングを形成する代わりに、第２の並列ｐｎ構造のうちで第２の縦形第２導電型領域を外側に持つｐｎ接合面の第１主面側位置とフィールドプレートの先端位置とを合致させてある。第２の縦形第２導電型領域は凡そ電位浮遊状態であるが、第２の縦形第２導電型領域が第２の縦形第１導電型領域よりも外側にあるので、第１主面側で互いに接近する等電位線のうち高電位側の等電位線を第２の第２導電型領域の外側へ振り分ける。このため、フィールドプレートの先端直下での等電位線同士の密集が解消し、電界集中を緩和することができ、高耐圧化を図ることができる。
【００１７】
なお、このフィールドプレートの先端と第２の縦形第２導電型領域を外側に持つｐｎ接合面の第１主面側位置とを合致させる構成は、内周構造を持たない耐圧構造部であっても有効である。
【００１８】
また、フィールドプレートの先端よりも外側に位置する耐圧構造部での表面電界を緩和する必要もある。本発明は、第２の並列ｐｎ構造のうちでフィールドプレートの先端よりも外側に位置する第２の縦形第２導電型領域の第１主面側の不純物濃度が隣接する第２の縦形第１導電型領域の第１主面側の不純物濃度に比して高いことを特徴とする。その第２の縦形第１導電型領域の第１主面側が空欠化しても、隣接する第２の縦形第２導電型領域の第１主面側は完全には空欠化せず、第２導電型領域としてキャリアが幾分残るため、これがガードリングとして機能し、また第２の縦形第２導電型領域が第２の縦形第１導電型領域よりも外側にあるので、第１主面側で互いに接近する等電位線のうち高電位側の等電位線を第２の第２導電型領域の外側へ振り分ける。このため、フィールドプレートの先端よりも外側に位置する耐圧構造部での表面電界が緩和し、高耐圧化を図ることができる。
【００１９】
このように、第２の第２導電型領域の第１主面側をガードリングとして機能させるためには、第２の縦形第２導電型領域の第１主面側の幅寸法が隣接する第２の縦形第１導電型領域の第１主面側の幅寸法に比して広くても良いし、また、第２の縦形第１導電型領域の第１主面側の不純物濃度が隣接する第２の第２導電型領域の第１主面側の不純物濃度に比して低くても良い。なお、このようなフィールドプレートの先端よりも外側に位置する耐圧構造部での表面電界を緩和させる構成は、内周構造を持たない耐圧構造部であっても有効である。
【００２０】
第１の並列ｐｎ構造における繰り返しピッチの方向と第２の並列ｐｎ構造における繰り返しピッチの方向とが同じである場合に限らず、略直交していても構わない。
【００２１】
また、外周構造部を取り囲む第１導電型囲繞領域と、この第１主面側に導電接触する第３の電極部を設けることにより、漏れ電流を抑制することができる。
【００２２】
【発明の実施の形態】
以下に本発明の実施形態を説明する。以下でｎ又はｐを冠記した層や領域では、ぞれぞれ電子又は正孔が多数キャリアであることを意味する。また＋は比較的高不純物濃度であることを意味している。すべての実施例において第１導電型にｎを、第２導電型にｐを選んでいるが、これが逆の場合であっても良い。
【００２３】
［実施例１］
図１は本発明の実施例１に係る縦形ＭＯＳＦＥＴ素子のチップを示す概略平面図、図２は図１中のＡ−Ａ′線に沿って切断した状態を示す縦断面図である。なお、図１ではドレイン・ドリフト部の１／４を示してある。
【００２４】
本例の縦形ＭＯＳＦＥＴは、裏側のドレイン電極１８が導電接触した低抵抗のｎ^＋ドレイン層（コンタクト層）１１の上に形成された第１の並列ｐｎ構造のドレイン・ドリフト部２２と、このドレイン・ドリフト部２２の表面層に選択的に形成された素子活性領域たる高不純物濃度のｐベース領域（ｐウェル）１３ａと、そのｐベース領域１３ａ内の表面側に選択的に形成された高不純物濃度のｎ^＋ソース領域１４と、基板表面上にゲート絶縁膜１５を介して設けられたポリシリコン等のゲート電極層１６と、層間絶縁膜１９ａに開けたコンタクト孔を介してｐベース領域１３ａ及びｎ^＋ソース領域１４に跨って導電接触するソース電極１７とを有している。ウェル状のｐベース領域１３ａの中にｎ^＋ソース領域１４が浅く形成されており、２重拡散型ＭＯＳ部を構成している。なお、２６はｐ^＋コンタクト領域で、また、図示しない部分でゲート電極層１６の上に金属膜のゲート配線が導電接触している。
【００２５】
ドレイン・ドリフト部２２は、素子活性領域たる複数ウェルのｐベース領域１３の直下部分に相当し、基板の厚み方向に配向する層状縦形の第１のｎ型領域２２ａと基板の厚み方向に配向する層状縦形の第１のｐ型領域２２ｂとを繰り返しピッチＰ１で基板の沿面方向へ交互に繰り返して接合して成る第１の並列ｐｎ構造である。いずれかの第１のｎ型領域２２ａは、その上端がｐベース領域１３の挾間領域１２ｅに達し、その下端がｎ^＋ドレイン層１１に接している。挾間領域１２ｅに達する第１のｎ型領域２２ａはオン状態では電路領域であるが、その余の第１のｎ型領域２２ａは概ね非電路領域となっている。また第１のｐ型領域２２ｂは、その上端がｐベース領域１３ａのウェル底面に接し、その下端がｎ^＋ドレイン層１１に接している。
【００２６】
ドレイン・ドリフト部２２の周りは並列ｐｎ構造から成る耐圧構造部（素子周縁部）となっているが、この耐圧構造部は、ドレイン・ドリフト部２２の第１の並列ｐｎ構造に隣接して繰り返しピッチ及び不純物濃度が同じである内周構造部３０と、この内周構造部３０に隣接した第２の並列ｐｎ構造である外周構造部４０とを有する。内周構造部３０に属する第１の並列ｐｎ構造の繰り返しピッチは数ピッチとなっている。外周構造部４０に属する第２の並列ｐｎ構造は、基板の厚み方向に配向する層状縦形の第２のｎ型領域４１と基板の厚み方向に配向する層状縦形の第２のｐ型領域４２とを交互に繰り返して接合して成る。本例では、第２の並列ｐｎ構造での空欠層をより拡がり易くするため、第２の並列ｐｎ構造の不純物濃度は第１の並列ｐｎ構造の不純物濃度よりも低く、また第２の並列ｐｎ構造の繰り返しピッチＰ２は第１の並列ｐｎ構造の繰り返しピッチＰ１よりも狭くなっている。しかし、いずれか一方の条件を満足するだけでも、第２の並列ｐｎ構造での空欠層を拡がり易くできることは言う迄もない。
【００２７】
内周構造部３０及び外周構造部４０の表面には絶縁膜主面には酸化膜（絶縁膜）１２３が形成されている。この酸化膜１２３はその膜厚がドリフト部２２から外周構造部４０にかけて厚くなるように形成されており、内周構造部３０の上では段階的に厚くなっている。即ち、酸化膜１２３は、内周構造部３０の上でドリフト部２２に隣接して形成された最小厚の内周域酸化膜１２３ａと、内周構造部３０の上に形成された中間域酸化膜１２３ｂと、内周構造部３０の上から外周構造部４０にかけて形成された最大厚の外周域酸化膜１２３ｃとを一体的に有し、膜厚段数は２となっている。そして、ソース電極１７から延長され、耐圧構造部の酸化膜１２３の上には内周構造部３０を覆って先端が外周構造部４０の上にまで張り出て成るフィールドプレートＦＰが形成されている。このフィールドプレートＦＰは酸化膜１２３の段差を反映して段差Ｓ１，Ｓ２を有している。内周域酸化膜１２３ａと中間域酸化膜１２３ｂとの段差、即ち、フィールドプレートＦＰの段差Ｓ１は内周構造部３０に属する第１の並列ｐｎ構造の一部分のうちで第１のｐ型領域２２ｂを外側に持つｐｎ接合面の表面側位置Ｔ１に合致している。また、中間域酸化膜１２３ｂと外周域酸化膜１２３ｃとの段差、即ち、フィールドプレートＦＰの段差Ｓ２は内周構造部３０に属する第１の並列ｐｎ構造の一部分のうちで第２のｐ型領域２２ｂを外側に持つｐｎ接合面の表面側位置Ｔ２に合致している。更に、フィールドプレートＦＰの先端Ｓ３は第２の並列ｐｎ構造のうちで第２のｐ型領域４２を外側に持つｐｎ接合面の表面側位置Ｔ３に合致している。
【００２８】
そして、外周構造部４０の外側にはチャネルストッパーとしてｎ型囲繞領域５０が形成され、このｎ型囲繞領域５０の表面側にはストッパー電極５１が導電接触している。
【００２９】
本例の縦形ＭＯＳＦＥＴは耐圧６００Ｖクラスであり、ｎ^＋ドレイン層１１の不純物濃度は２×１０^１８ｃｍ^−３、第１のｎ型領域２２ａ及び第１のｐ型領域２２ｂの不純物濃度は２．５７×１０^１５ｃｍ^−３で、その基板深さ（厚さ）は４４μｍ、第１の繰り返しピッチＰ１は１６μｍであって、第２のｐ型領域４１及び第２のｐ型領域４２の不純物濃度は１．２×１０^１５ｃｍ^−３で、その基板深さ（厚さ）は４４μｍ、第２の繰り返しピッチＰ２は８μｍである。酸化膜１２３の内周域酸化膜１２３ａの膜厚は０．１μｍ、中間域酸化膜１２３ｂの膜厚は０．８μｍ、外周域酸化膜１２３ｃの膜厚は３．０μｍである。
【００３０】
このように、ドレイン・ドリフト部２２の周りの耐圧構造部は、第２の並列ｐｎ構造である外周構造部４０のみから成るのではなく、ドレイン・ドリフト部２２と外周構造部４０との間にドレイン・ドリフト部２２に隣接して繰り返しピッチが当該ドリフト部から引き続き１ピッチ以上外側へ延長された第１の並列ｐｎ構造の一部分である内周構造部３０を有している。このため、ドレイン・ドリフト部２２の隣接周辺部分には第１の並列ｐｎ構造と第２の並列ｐｎ構造との境界の表面位置が存在せず、その境界の表面位置Ｔ４は内周構造部３０と外周構造部４０との間に存在することになる。ドレイン・ドリフト部２２の隣接外周部分Ｔ５では並列ｐｎ構造のチャージバランスの崩れが起こらず、それ故、ドレイン・ドリフト部の隣接外周部分での表面電界を抑制でき、高耐圧化を図ることができる。
【００３１】
また、フィールドプレートＦＰはその先端Ｓ３が内周構造部３０を覆って外周構造部４０の上にまで長く張り出ているため、その先端Ｓ３直下の電界集中部分がドレイン・ドリフト部２２の隣接外周部分から外れて外周構造部４０になるので、内周構造部３０での表面電界を更に抑制でき、一層の高耐圧化を図ることができる。
【００３２】
このとき、酸化膜１２３で十分に耐圧を確保すれば、酸化膜１２３下の並列ｐｎ構造部分での耐圧分担が小さくなる。そうすれば仮に第１と第２の並列ｐｎ構造の境界部分でチャージバランスが崩れたとしても、それによる耐圧の低下分は酸化膜１２３が保持する耐圧で補われるので、素子全体としては影響を受けずに済む。また、フィールドプレートＦＰの先端Ｓ３より外側に位置する耐圧構造部においても、耐圧の分担が小さくなれば表面電界の集中が抑えられる。そこで、酸化膜１２３の膜厚をドリフト部２２側から外周構造部４０側に向けて厚く形成することで、高耐圧化を図ることができる。
【００３３】
ただ、酸化膜１２３は段階的に厚く形成されているため、その膜厚の急変部分でフィールドプレートＦＰには段差Ｓ１，Ｓ２が生じるので、その直下で電界集中が生じる。この問題を解決するため、フィールドプレートＦＰの段差Ｓ１は内周構造部３０に属する第１の並列ｐｎ構造の一部分のうちで第１のｐ型領域２２ｂを外側に持つｐｎ接合面の表面側位置Ｔ１に合致し、フィールドプレートＦＰの段差Ｓ２は内周構造部３０に属する第１の並列ｐｎ構造の一部分のうちで第２のｐ型領域２２ｂを外側に持つｐｎ接合面の表面側位置Ｔ２に合致している。第１のｐ型領域２２ｂは凡そ電位浮遊状態であるが、第１のｐ型領域２２ｂが第１のＮ型領域２２ａよりも外側にあるので、表面側で互いに接近する等電位線のうち高電位側の等電位線を第１のｐ型領域２２ｂの外側へ振り分ける。このため、フィールドプレートＦＰの段差Ｓ１，Ｓ２直下での等電位線同士の密集が解消し、電界集中を有効的に緩和することができ、高耐圧化を図ることができる。
【００３４】
このように、第１の並列ｐｎ構造と第２の並列ｐｎ構造との境界のチャージバランスの崩れによる電界集中やフィールドプレートＦＰの段差Ｓ１，Ｓ２直下の電界集中を緩和できるが、耐圧構造部の外周構造部４０でのフィールドプレートＦＰの先端Ｓ３直下で生じる電界集中も緩和することが必要である。本例では、外周構造部４０の表面側に正規のガードリングを形成する代わりに、第２の並列ｐｎ構造のうちで第２のｐ型領域４２を外側に持つｐｎ接合面の第１主面側位置Ｔ３とフィールドプレートＦＰの先端位置Ｓ３とを合致させてある。第２のｐ型領域４２は凡そ電位浮遊状態であるが、第２のｐ型領域４２が第２のｎ型領域４１よりも外側にあるので、表面側で互いに接近する等電位線のうち高電位側の等電位線を第２のｐ型領域４２の外側へ振り分ける。このため、フィールドプレートＦＰの先端Ｓ３直下での等電位線同士の密集が解消し、電界集中を緩和することができ、高耐圧化を図ることができる。
【００３５】
更に本例では、外周構造部４０を取り囲むｎ型囲繞領域５０と、ストッパー電極５１とが形成されているため、漏れ電流を抑制することができる。
【００３６】
［実施例２］
図３は本発明の実施例２に係る縦形ＭＯＳＦＥＴを示す部分縦断面図である。図３は同じく図１のＡ−Ａ′線に沿って切断した状態を示す縦断面図である。
【００３７】
本例において実施例１の構成と異なる点は、外周構造部４０の第２の並列ｐｎ構造のうちでフィールドプレートＦＰの先端よりも外側に位置する第２のｐ型領域４２は表面側部分４２ａを有し、この表面側部分４２ａは、その不純物濃度が隣接する第２のｎ型領域４１の表面側の不純物濃度に比して高く、しかもその幅寸法が隣接する第２のｎ型領域４１の表面側の幅寸法に比して広くなっているところにある。換言すれば、表面側部分４２ａは、その不純物濃度が第２のｐ型領域４２の不純物濃度に比して高く、またその幅寸法が隣接する第２のｐ型領域４２の幅寸法に比して広くなっている。なお、表面側部分４２ａは不純物濃度が高く、しかも幅寸法を広く形成してあるが、いずれか一方でも構わない。
【００３８】
オフ状態において、第２のｎ型領域４１の表面側が空欠化しても、隣接する表面側部分４２ａは完全には空欠化せず、ｐ型領域としてキャリアが幾分残るため、これがガードリングとして機能し、表面側で互いに接近する等電位線のうち高電位側の等電位線を表面側部分４２ａの外側へ振り分ける。このため、フィールドプレートＦＰの先端よりも外側に位置する耐圧構造部４０での表面電界が緩和し、高耐圧化を図ることができる。
【００３９】
［実施例３］
図４は本発明の実施例３に係る縦形ＭＯＳＦＥＴ素子のチップを示す概略平面図、図５は図４中のＡ−Ａ′線に沿って切断した状態を示す縦断面図である。なお、図４ではドレイン・ドリフト部の１／４を示してある。
【００４０】
本例において実施例１の構成と異なる点は、外側構造部４０の第２の並列ｐｎ構造の繰り返しピッチＰ２は第１の並列ｐｎ構造の繰り返しピッチＰ１と同じになっており、第２の並列ｐｎ構造の不純物濃度は第１の並列ｐｎ構造の不純物濃度よりも十分低くなっているところにある。なお、第２の並列ｐｎ構造の不純物濃度が第１の並列ｐｎ構造の不純物濃度よりも十分低ければ、繰り返しピッチＰ２は繰り返しピッチＰ１よりも広くても構わない。
【００４１】
また本例では、外側耐圧部４０のうちでフィールドプレートＦＰの先端よりも外側に位置する第２のｎ型領域４１の表面側部分４１ａは、その不純物濃度が隣接する第２のｐ型領域４２の表面側の不純物濃度に比して低くなっている。斯かる場合でも、オフ状態において第２のｎ型領域４１の表面側部分４１ａが空欠化しても、隣接する第２のｐ型領域４２の表面側は完全には空欠化せず、ｐ型領域としてキャリアが幾分残るため、これがガードリングとして機能し、表面側で互いに接近する等電位線のうち高電位側の等電位線を第２のｐ型領域４２の表面側部分の外側へ振り分ける。このため、フィールドプレートＦＰの先端よりも外側に位置する耐圧構造部４０での表面電界が緩和し、高耐圧化を図ることができる。
【００４２】
このように本例では、第２の並列ｐｎ構造のうち第２のｐ型領域４２の表面側部分４２ａのように幅広に形成する必要がなく、不純物の調節で済むから、不純物導入マスクを減らすことができる。なお、第２のｐ型領域４２の表面側部分の不純物濃度は第２のｎ型領域４１の表面側部分の不純物濃度よりも高くしても良い。
【００４３】
［実施例４］
図６は本発明の実施例４に係る縦形ＭＯＳＦＥＴ素子のチップを示す概略平面図、図７は図６中のＡ−Ａ′線に沿って切断した状態を示す縦断面図、図８は図６中のＢ−Ｂ′線に沿って切断した状態を示す縦断面図である。
【００４４】
実施例１では、第１の並列ｐｎ構造における繰り返しピッチＰ１の方向と第２の並列ｐｎ構造における繰り返しピッチＰ２の方向とが同方向なっているが、本例では、第１の並列ｐｎ構造における繰り返しピッチＰ１の方向と第２の並列ｐｎ構造における繰り返しピッチＰ２の方向とが直交している。即ち、第１の並列ｐｎ構造の平面的ストライプと第２の並列ｐｎ構造の平面的ストライプとが直交している。ストライプ方向が変わっても、逆電圧印加時に空乏化して耐圧を維持できることにか変わりが無く、またストライプ方向の変わり目でのチャージバランスが崩れた場合でも、内側耐圧部３０が存在しているため、高耐圧化を図ることができる。
【００４５】
なお、本発明は、上記実施例は縦形ＭＯＳＦＥＴ素子について説明したが、縦形ドリフト部を持つ半導体装置一般に適用できることは言う迄もない。
【００４６】
【発明の効果】
以上説明したように、本発明において、ドリフト部の周りの耐圧構造部は、ドリフト部に隣接して繰り返しピッチが当該ドリフト部から引き続き１ピッチ以上外側へ延長された第１の並列ｐｎ構造一部分である内周構造部と、この内周構造部に隣接した第２の並列ｐｎ構造である外周構造部とを有することを特徴としているため、ドリフト部の隣接周辺部分には第１の並列ｐｎ構造と第２の並列ｐｎ構造との境界が存在せず、その境界は耐圧構造部の内周構造部と外周構造部との間に存在することになるため、ドリフト部の隣接外周部分では並列ｐｎ構造のチャージバランスの崩れが起こらず、それ故、ドリフト部の隣接外周部分での表面電界を抑制でき、高耐圧化及び大電流化を図ることができる。
【図面の簡単な説明】
【図１】本発明の実施例１に係る縦形ＭＯＳＦＥＴ素子のチップを示す概略平面図である。
【図２】図１中のＡ−Ａ′線に沿って切断した状態を示す縦断面図である。
【図３】本発明の実施例２に係る縦形ＭＯＳＦＥＴを示す部分縦断面図である。
【図４】本発明の実施例３に係る縦形ＭＯＳＦＥＴ素子のチップを示す概略平面図である。
【図５】図４中のＡ−Ａ′線に沿って切断した状態を示す縦断面図である。
【図６】本発明の実施例４に係る縦形ＭＯＳＦＥＴ素子のチップを示す概略平面図である。
【図７】図６中のＡ−Ａ′線に沿って切断した状態を示す縦断面図である。
【図８】図６中のＢ−Ｂ′線に沿って切断した状態を示す縦断面図である。
【図９】縦形ＭＯＳＦＥＴにおけるドリフト部及び素子外周部（耐圧構造部）を示す平面図である。
【図１０】図９中のＡ−Ａ′線に沿って切断した状態を示す縦断面図である。
【図１１】図９中のＢ−Ｂ′線に沿って切断した状態を示す縦断面図である。
【符号の説明】
１１…ｎ^＋ドレイン層（コンタクト層）
１２ｅ…挾間領域
１３ａ…ｐベース領域（ｐウェル）
１４…ｎ^＋ソース領域
１５…ゲート絶縁膜
１６…ゲート電極層
１７…ソース電極
１８…ドレイン電極
１９ａ…層間絶縁膜
２２…ドレイン・ドリフト部
２２ａ…第１のｎ型領域
２２ｂ…第１のｐ型領域
２６…ｐ^＋コンタクト領域
３０…内周構造部
４０…外周構造部
４１…第２のｎ型領域
４１ａ，４２ａ…表面側部分
４２…第２のｐ型領域
５０…ｎ型囲繞領域
５１…ストッパー電極
１２３…酸化膜
１２３ａ…内周域酸化膜
１２３ｂ…中間域酸化膜
１２３ｃ…外周域酸化膜
Ｐ１…第１の並列ｐｎ構造の繰り返しピッチ
Ｐ２…第２の並列ｐｎ構造の繰り返しピッチ
ＦＰ…フィールドプレート
Ｓ１，Ｓ２…段差
Ｓ３…フィールドプレートの先端
Ｔ１〜Ｔ５…ｐｎ接合面の表面側位置[0001]
BACKGROUND OF THE INVENTION
The present invention can be applied to active elements such as MOSFETs (insulated gate field effect transistors), IGBTs (conductivity modulation MOSFETs) and bipolar transistors, and passive elements such as diodes. The present invention relates to a compatible vertical power semiconductor device.
[0002]
In a vertical semiconductor device having a vertical drift portion in which electrodes are provided on both sides of a substrate and a current flows in the thickness direction of the substrate, there is a trade-off relationship between on-resistance (current capacity) and breakdown voltage. Therefore, it is known to adopt a parallel pn structure in which vertical n-type regions and vertical p-type regions with an increased impurity concentration are alternately repeated in the creeping direction of the substrate as the vertical drift portion. However, although the vertical drift portion of this parallel pn structure is depleted quickly, the depletion layer is difficult to spread outward or deep in the substrate in the withstand voltage structure portion where the current does not substantially upstream around the drift portion, and the electric field strength is silicon. Since the critical electric field strength is reached quickly, the breakdown voltage is limited by the breakdown voltage structure. In order to obtain the design withstand voltage, it is desirable to use a vertical semiconductor device that employs a parallel pn structure in the withstand voltage structure.
[0003]
9 is a plan view showing a drift portion and an element outer peripheral portion (withstand voltage structure portion) in the vertical MOSFET, FIG. 10 is a longitudinal sectional view showing a state cut along the line AA ′ in FIG. 9, and FIG. 9 is a longitudinal sectional view showing a state cut along a line BB ′ in FIG. In FIG. 9, ¼ of the drift portion is indicated by a hatched portion.
[0004]
This n-channel vertical MOSFET has a low resistance n-type in which the drain electrode 18 on the back side is in conductive contact. ⁺ A drain / drift portion 22 having a first parallel pn structure formed on the drain layer (contact layer) 11, and a high impurity concentration p which is an element active region selectively formed on the surface layer of the drift portion 22 Base region (p well, channel region) 13a and n of high impurity concentration selectively formed on the surface side in the p base region 13a ⁺ The source region 14, the gate electrode layer 16 such as polysilicon provided on the substrate surface via the gate insulating film 15, and the p base regions 13a and n through the contact holes opened in the interlayer insulating film 19a ⁺ A source electrode 17 in conductive contact with the source region 14; N in the well-shaped p base region 13a ⁺ The source region 14 is formed shallow and constitutes a double diffusion type MOS portion. 26 is p ⁺ The gate wiring of the metal film is in conductive contact on the gate electrode layer 16 in the contact region and in a portion (not shown).
[0005]
The drain / drift portion 22 of the first parallel pn structure includes a first layered vertical n-type region 22a oriented in the thickness direction of the substrate and a first layered vertical p-type region 22b oriented in the thickness direction of the substrate. It is the structure which joined by repeating alternately. A first layer-like vertical n-type region 22a whose upper end reaches the intercostal region 12e of the p base region 13a is a substantial electric circuit region. The lower end of the first layered vertical n-type region 22a is n ⁺ It is in contact with the drain layer 11. The upper end of the first layered vertical p-type region 22b is in contact with the well bottom of the p base region 13a, and the lower end is n. ⁺ It is in contact with the drain layer 11.
[0006]
Substrate surface and n ⁺ A second layered vertical n-type region 20a oriented in the thickness direction of the substrate is also formed in the breakdown voltage structure 20 around the vertical drain / drift portion 22 between the drain layer 11 and the thickness direction of the substrate. A second parallel pn structure is formed by alternately joining the second layered vertical p-type regions 20b in the creeping direction of the substrate. An oxide film (insulating film) 23 made of a thermal oxide film or phosphor silica glass (PSG) is formed on the surface of the second parallel pn structure of the breakdown voltage structure 20 for surface protection and stabilization. Yes. In the second parallel pn structure, the impurity concentration of the second parallel pn structure is decreased as compared with the impurity concentration of the first parallel pn structure, or the second parallel pn structure is easily expanded. The repetition pitch P2 is made smaller than the repetition pitch P1 of the first parallel pn structure.
[0007]
[Problems to be solved by the invention]
However, the vertical MOSFETs shown in FIGS. 9 to 11 have the following problems.
[0008]
That is, around the first layered vertical n-type region 22aa on the outermost side of the first parallel pn structure which is the drain / drift portion 22, the second parallel pn structure having a different impurity concentration or repetitive pitch from this. Since there is the second vertical layered p-type region 20bb on the innermost side, the charge balance between the n-type region 22aa and the p-type region 20bb is inevitably broken. Therefore, electric field concentration is caused near the surface X at the boundary between the first parallel pn structure and the second parallel pn structure, and the breakdown voltage is reduced. In such a structure, it is difficult to obtain a design withstand voltage, and the significance of providing the second parallel pn structure in the withstand voltage structure 20 has been lost.
[0009]
In view of the above problems, an object of the present invention is to provide a surface of a breakdown voltage structure portion in a semiconductor device having a second parallel pn structure as a breakdown voltage structure portion around the drift portion which is the first parallel pn structure. It is an object of the present invention to provide a semiconductor device that can further increase the breakdown voltage and increase the current by relaxing the electric field.
[0010]
[Means for Solving the Problems]
In order to solve the above problems, the basic structure of the semiconductor device according to the present invention is formed on the first main surface side of the substrate. Selectively A first electrode layer that is conductively connected to the formed element active portion, a second electrode layer that is conductively connected to a low-resistance layer of the first conductivity type formed on the second main surface side of the substrate, and an element A vertical drift portion interposed between the active portion and the low resistance layer, in which the drift current flows in the vertical direction in the on state and is depleted in the off state; Element active part and It is interposed between the first main surface and the low resistance layer around the vertical drift part, Is non- It has an electric circuit region and a withstand voltage structure portion that is depleted in an off state. The vertical drift portion includes a first vertical first conductivity type region oriented in the thickness direction of the substrate and a first vertical second conductivity type region oriented in the thickness direction of the substrate, which are alternately and repeatedly joined. It is a parallel pn structure. The breakdown voltage structure is formed by alternately and repeatedly joining a second vertical first conductivity type region oriented in the thickness direction of the substrate and a second vertical second conductivity type region oriented in the thickness direction of the substrate. 2 parallel pn structures. The impurity concentration of the second parallel pn structure is lower than the impurity concentration of the first parallel pn structure, and / or the repetition pitch of the second parallel pn structure is the repetition of the first parallel pn structure. It is smaller than the pitch. On the first main surface side of the substrate Selectively For example, in the case of a vertical MOSFET, the formed element active portion is a switching portion including a channel diffusion layer and a source region forming an inversion layer on the first main surface side, and in the case of a bipolar transistor, switching including an emitter or collector region. This is an active part or passive part having a selection function of conduction and non-conduction on the first main surface side of the drift part.
[0011]
In such a basic structure, the pressure-resistant structure around the drift part in the present invention is not composed of only the second parallel pn structure, but the repeat pitch is adjacent to the drift part and is continuously one pitch or more outside the drift part. An inner peripheral structure portion that is a part of the first parallel pn structure extended to the inner periphery, and an outer peripheral structure portion that is a second parallel pn structure adjacent to the inner peripheral structure portion. For this reason, there is no boundary between the first parallel pn structure and the second parallel pn structure in the adjacent peripheral portion of the drift portion, and the boundary is between the inner peripheral structure portion and the outer peripheral structure portion of the breakdown voltage structure portion. Therefore, the charge balance of the parallel pn structure does not occur in the adjacent outer peripheral portion of the drift portion, and therefore, the surface electric field in the adjacent outer peripheral portion of the drift portion can be suppressed, and high breakdown voltage can be achieved. Can do.
[0012]
Further, in the present invention, the field plate is formed on the insulating film on the first main surface of the pressure-resistant structure portion so as to cover the inner peripheral structure portion and have the tip projecting over the outer peripheral structure portion. For this reason, the field plate projects long, and the electric field concentration part immediately below the tip is separated from the adjacent outer peripheral part of the drift part to become the outer peripheral structure part. Therefore, the surface electric field at the inner peripheral structure part can be further suppressed, and the higher breakdown voltage can be obtained. Can be achieved.
[0013]
At this time, if a sufficient breakdown voltage is secured by the insulating film, the breakdown of the breakdown voltage in the parallel pn structure portion under the insulating film is reduced. Then, even if the charge balance is lost at the boundary between the first and second parallel pn structures, the reduction in breakdown voltage is compensated by the breakdown voltage held by the insulating film, and the entire element is affected. You do n’t have to. Even in the pressure-resistant structure portion located outside the front end of the field plate, the concentration of the surface electric field can be suppressed if the breakdown of the breakdown voltage is reduced. Therefore, in the present invention, by increasing the thickness of the insulating film from the drift portion side toward the outer peripheral structure portion side, a high breakdown voltage can be achieved.
[0014]
This insulating film desirably has a film thickness that gradually increases from the drift portion side toward the outer peripheral structure portion side. However, since it is difficult to form such an insulating film, the insulating film is formed thick in steps from the drift portion side to the outer peripheral structure portion side. In the design withstand voltage 700V class, it is desirable that the number of steps of the insulating film is 2 or more. However, a step occurs in the field plate at the sudden change in film thickness, and electric field concentration occurs immediately below the step.
[0015]
In order to solve this problem, in the present invention, the first main surface side position and the field of the pn junction surface having the first vertical second conductivity type region on the outside in the first parallel pn structure of the inner peripheral structure portion It matches with the step position of the plate. Although the first vertical second conductivity type region is approximately in a floating state, the first vertical second conductivity type region is located outside the first vertical first conductivity type region, so that the first main surface side is mutually Among the approaching equipotential lines, the equipotential line on the high potential side is distributed outside the first vertical second conductivity type region. For this reason, the concentration of equipotential lines directly under the step of the field plate is eliminated, the electric field concentration can be effectively reduced, and a high breakdown voltage can be achieved.
[0016]
As described above, the electric field concentration due to the collapse of the charge balance at the boundary between the first parallel pn structure and the second parallel pn structure and the electric field concentration immediately below the step of the field plate can be alleviated. It is necessary to alleviate the electric field concentration that occurs immediately under the tip of the field plate. For example, a high conductivity layer of the first conductivity type is formed on the first main surface side of the second parallel pn structure in the outer peripheral structure portion, and a second conductivity type guard ring is normally formed on the first main surface side. In the present invention, instead of forming a regular guard ring, the first pn junction surface of the second parallel pn structure having the second vertical second conductivity type region on the outside is formed instead of forming a regular guard ring. The main surface side position is matched with the tip position of the field plate. The second vertical second conductivity type region is approximately in a potential floating state, but the second vertical second conductivity type region is located outside the second vertical first conductivity type region, so that the first main surface side Of the equipotential lines approaching each other, the equipotential line on the high potential side is distributed to the outside of the second second conductivity type region. For this reason, the concentration of equipotential lines directly under the tip of the field plate is eliminated, the electric field concentration can be relaxed, and a high breakdown voltage can be achieved.
[0017]
In addition, the structure which makes the front-end | tip of this field plate correspond to the 1st main surface side position of the pn junction surface which has a 2nd vertical 2nd conductivity type area | region outside is a pressure | voltage resistant structure part which does not have an inner peripheral structure. Is also effective.
[0018]
In addition, it is necessary to alleviate the surface electric field at the pressure-resistant structure located outside the front end of the field plate. In the second parallel type pn structure, the impurity concentration on the first main surface side of the second vertical second conductivity type region located outside the front end of the field plate in the second parallel pn structure is adjacent. It is characterized by being higher than the impurity concentration on the first main surface side of the conductivity type region. Even if the first main surface side of the second vertical first conductivity type region is empty, the first main surface side of the adjacent second vertical second conductivity type region is not completely empty. Since some carriers remain as the second conductivity type region, this functions as a guard ring, and the second vertical second conductivity type region is located outside the second vertical first conductivity type region. The equipotential lines on the high potential side among the equipotential lines approaching each other on the side are distributed to the outside of the second second conductivity type region. For this reason, the surface electric field in the breakdown voltage structure located outside the tip of the field plate is relaxed, and a high breakdown voltage can be achieved.
[0019]
Thus, in order for the first main surface side of the second second conductivity type region to function as a guard ring, the width dimension of the second main surface side of the second vertical second conductivity type region is adjacent to the first main surface side. 2 may be wider than the width dimension on the first main surface side of the two vertical first conductivity type regions, and the impurity concentration on the first main surface side of the second vertical first conductivity type region is adjacent. It may be lower than the impurity concentration on the first main surface side of the second second conductivity type region. It should be noted that such a structure that reduces the surface electric field in the pressure-resistant structure portion located outside the front end of the field plate is effective even in a pressure-resistant structure portion that does not have an inner peripheral structure.
[0020]
The direction of the repetition pitch in the first parallel pn structure is not limited to the case where the direction of the repetition pitch in the second parallel pn structure is the same, and may be substantially orthogonal.
[0021]
Further, the leakage current can be suppressed by providing the first conductivity type surrounding region surrounding the outer peripheral structure portion and the third electrode portion in conductive contact with the first main surface side.
[0022]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below. In the following layers and regions where n or p is named, it means that each electron or hole is a majority carrier. Moreover, + means a relatively high impurity concentration. In all the embodiments, n is selected for the first conductivity type and p is selected for the second conductivity type, but this may be reversed.
[0023]
[Example 1]
FIG. 1 is a schematic plan view showing a chip of a vertical MOSFET element according to Embodiment 1 of the present invention, and FIG. 2 is a vertical sectional view showing a state cut along the line AA ′ in FIG. In FIG. 1, ¼ of the drain / drift portion is shown.
[0024]
The vertical MOSFET of this example has a low resistance n-type in which the drain electrode 18 on the back side is in conductive contact. ⁺ A drain / drift portion 22 having a first parallel pn structure formed on the drain layer (contact layer) 11 and a high impurity concentration as an element active region selectively formed on the surface layer of the drain / drift portion 22 P base region (p well) 13a and n of high impurity concentration selectively formed on the surface side in the p base region 13a ⁺ The source region 14, the gate electrode layer 16 such as polysilicon provided on the substrate surface via the gate insulating film 15, and the p base regions 13a and n through the contact holes opened in the interlayer insulating film 19a ⁺ A source electrode 17 in conductive contact with the source region 14; N in the well-shaped p base region 13a ⁺ The source region 14 is formed shallow and constitutes a double diffusion type MOS portion. 26 is p ⁺ The gate wiring of the metal film is in conductive contact on the gate electrode layer 16 in the contact region and in a portion (not shown).
[0025]
The drain / drift portion 22 corresponds to a portion immediately below the p base region 13 of a plurality of wells as an element active region, and is aligned in the thickness direction of the substrate with the first layered vertical n-type region 22a oriented in the thickness direction of the substrate. This is a first parallel pn structure in which layered vertical first p-type regions 22b are alternately and repeatedly joined in the creeping direction of the substrate at a pitch P1. One of the first n-type regions 22a has an upper end that reaches the intercostal region 12e of the p base region 13, and a lower end that is n ⁺ It is in contact with the drain layer 11. The first n-type region 22a reaching the intercostal region 12e is an electric circuit region in the ON state, but the remaining first n-type region 22a is generally a non-electric circuit region. The upper end of the first p-type region 22b is in contact with the bottom surface of the well of the p base region 13a, and the lower end is n. ⁺ It is in contact with the drain layer 11.
[0026]
Around the drain / drift portion 22 is a breakdown voltage structure portion (element peripheral portion) having a parallel pn structure, and this breakdown voltage structure portion is repeated adjacent to the first parallel pn structure of the drain / drift portion 22. It has an inner peripheral structure portion 30 having the same pitch and impurity concentration, and an outer peripheral structure portion 40 that is a second parallel pn structure adjacent to the inner peripheral structure portion 30. The repetition pitch of the first parallel pn structure belonging to the inner peripheral structure portion 30 is several pitches. The second parallel pn structure belonging to the outer peripheral structure portion 40 includes a layered vertical second n-type region 41 oriented in the thickness direction of the substrate and a layered vertical second p-type region 42 oriented in the thickness direction of the substrate. These are joined by repeating alternately. In this example, the impurity concentration of the second parallel pn structure is lower than the impurity concentration of the first parallel pn structure in order to make the void layer in the second parallel pn structure easier to spread. The repetition pitch P2 of the pn structure is narrower than the repetition pitch P1 of the first parallel pn structure. However, it goes without saying that the vacancy layer in the second parallel pn structure can be easily expanded only by satisfying either one of the conditions.
[0027]
An oxide film (insulating film) 123 is formed on the main surface of the insulating film on the surfaces of the inner peripheral structure portion 30 and the outer peripheral structure portion 40. The oxide film 123 is formed so that its film thickness increases from the drift portion 22 to the outer peripheral structure portion 40, and increases gradually on the inner peripheral structure portion 30. In other words, the oxide film 123 includes the minimum thickness of the inner peripheral region oxide film 123 a formed adjacent to the drift portion 22 on the inner peripheral structure portion 30 and the intermediate region oxidation formed on the inner peripheral structure portion 30. The film 123b and the maximum thickness outer peripheral region oxide film 123c formed from the top of the inner peripheral structure portion 30 to the outer peripheral structure portion 40 are integrally formed, and the number of film thickness steps is two. A field plate FP is formed extending from the source electrode 17 and covering the inner peripheral structure portion 30 and having the tip extending over the outer peripheral structure portion 40 on the oxide film 123 of the breakdown voltage structure portion. . The field plate FP has steps S1 and S2 reflecting the step of the oxide film 123. The step between the inner peripheral region oxide film 123a and the intermediate region oxide film 123b, that is, the step S1 of the field plate FP is the first p-type region 22b in a part of the first parallel pn structure belonging to the inner peripheral structure portion 30. It coincides with the surface side position T1 of the pn junction surface having the outside. Further, the step between the intermediate region oxide film 123b and the outer region oxide film 123c, that is, the step S2 of the field plate FP is a second p-type region in a part of the first parallel pn structure belonging to the inner peripheral structure portion 30. This coincides with the surface side position T2 of the pn junction surface having 22b on the outside. Furthermore, the tip S3 of the field plate FP coincides with the surface side position T3 of the pn junction surface having the second p-type region 42 on the outside in the second parallel pn structure.
[0028]
An n-type surrounding region 50 is formed as a channel stopper outside the outer peripheral structure portion 40, and a stopper electrode 51 is in conductive contact with the surface side of the n-type surrounding region 50.
[0029]
The vertical MOSFET in this example has a withstand voltage of 600 V class, and n ⁺ The impurity concentration of the drain layer 11 is 2 × 10 ¹⁸ cm ^-3 The impurity concentration of the first n-type region 22a and the first p-type region 22b is 2.57 × 10. ¹⁵ cm ^-3 The substrate depth (thickness) is 44 μm, the first repetition pitch P1 is 16 μm, and the impurity concentration of the second p-type region 41 and the second p-type region 42 is 1.2 × 10. ¹⁵ cm ^-3 The substrate depth (thickness) is 44 μm, and the second repetition pitch P2 is 8 μm. The film thickness of the inner peripheral region oxide film 123a of the oxide film 123 is 0.1 μm, the film thickness of the intermediate region oxide film 123b is 0.8 μm, and the film thickness of the outer peripheral region oxide film 123c is 3.0 μm.
[0030]
Thus, the breakdown voltage structure around the drain / drift portion 22 is not composed of only the outer peripheral structure portion 40 which is the second parallel pn structure, but between the drain / drift portion 22 and the outer peripheral structure portion 40. Adjacent to the drain / drift portion 22, there is an inner peripheral structure portion 30 that is a part of the first parallel pn structure in which the repetition pitch is continuously extended outward from the drift portion by one pitch or more. For this reason, the surface position of the boundary between the first parallel pn structure and the second parallel pn structure does not exist in the adjacent peripheral portion of the drain / drift portion 22, and the surface position T4 of the boundary is the inner peripheral structure portion 30. And the outer peripheral structure portion 40. In the adjacent outer peripheral portion T5 of the drain / drift portion 22, the charge balance of the parallel pn structure does not occur. Therefore, the surface electric field in the adjacent outer peripheral portion of the drain / drift portion can be suppressed, and a high breakdown voltage can be achieved. .
[0031]
Further, the field plate FP has its tip S3 covering the inner peripheral structure portion 30 and extending over the outer peripheral structure portion 40 so that the electric field concentration portion immediately below the tip S3 is adjacent to the outer periphery of the drain / drift portion 22. Since the outer peripheral structure portion 40 is removed from the portion, the surface electric field at the inner peripheral structure portion 30 can be further suppressed, and a higher breakdown voltage can be achieved.
[0032]
At this time, if a sufficient breakdown voltage is secured in the oxide film 123, the breakdown voltage sharing in the parallel pn structure portion under the oxide film 123 is reduced. Then, even if the charge balance is lost at the boundary between the first and second parallel pn structures, the reduction in breakdown voltage is compensated by the breakdown voltage held by the oxide film 123. You do n’t have to. Further, even in the breakdown voltage structure portion located outside the tip S3 of the field plate FP, concentration of the surface electric field can be suppressed if the breakdown of the breakdown voltage is reduced. Therefore, by increasing the thickness of the oxide film 123 from the drift portion 22 side toward the outer peripheral structure portion 40 side, a high breakdown voltage can be achieved.
[0033]
However, since the oxide film 123 is formed to be thicker in steps, the step S1 and S2 occur in the field plate FP at the sudden change portion of the film thickness. In order to solve this problem, the step S1 of the field plate FP is a position on the surface side of the pn junction surface having the first p-type region 22b on the outside of a part of the first parallel pn structure belonging to the inner peripheral structure portion 30. The step S2 of the field plate FP coincides with T1 and is located at the surface side position T2 of the pn junction surface having the second p-type region 22b on the outside of a part of the first parallel pn structure belonging to the inner peripheral structure portion 30. It matches. Although the first p-type region 22b is approximately in a potential floating state, since the first p-type region 22b is located outside the first N-type region 22a, the first p-type region 22b is higher than the equipotential lines approaching each other on the surface side. The equipotential lines on the potential side are distributed outside the first p-type region 22b. For this reason, the concentration of equipotential lines immediately below the steps S1 and S2 of the field plate FP is eliminated, the electric field concentration can be effectively reduced, and a high breakdown voltage can be achieved.
[0034]
As described above, the electric field concentration due to the collapse of the charge balance at the boundary between the first parallel pn structure and the second parallel pn structure and the electric field concentration immediately below the steps S1 and S2 of the field plate FP can be alleviated. It is also necessary to alleviate the electric field concentration that occurs immediately below the tip S3 of the field plate FP in the outer peripheral structure portion 40. In this example, instead of forming a regular guard ring on the surface side of the outer peripheral structure portion 40, the first main surface of the pn junction surface having the second p-type region 42 outside in the second parallel pn structure. The side position T3 and the tip position S3 of the field plate FP are matched. The second p-type region 42 is approximately in a potential floating state. However, since the second p-type region 42 is located outside the second n-type region 41, the high potential of the equipotential lines approaching each other on the surface side is high. The equipotential lines on the potential side are distributed to the outside of the second p-type region. For this reason, the concentration of equipotential lines directly under the tip S3 of the field plate FP is eliminated, the electric field concentration can be reduced, and a high breakdown voltage can be achieved.
[0035]
Furthermore, in this example, since the n-type surrounding region 50 surrounding the outer peripheral structure portion 40 and the stopper electrode 51 are formed, the leakage current can be suppressed.
[0036]
[Example 2]
FIG. 3 is a partial longitudinal sectional view showing a vertical MOSFET according to Embodiment 2 of the present invention. 3 is a longitudinal sectional view showing a state cut along the line AA ′ of FIG.
[0037]
The difference from the configuration of the first embodiment in this example is that the second p-type region 42 located outside the tip of the field plate FP in the second parallel pn structure of the outer peripheral structure portion 40 is a surface side portion 42a. The surface side portion 42a has a higher impurity concentration than the impurity concentration on the surface side of the adjacent second n-type region 41, and has a width dimension adjacent to the second n-type region 41. It is in a place that is wider than the width dimension on the surface side. In other words, the surface side portion 42a has a higher impurity concentration than the impurity concentration of the second p-type region 42, and its width dimension is larger than that of the adjacent second p-type region 42. And getting wider. The surface side portion 42a has a high impurity concentration and a wide width, but either one may be used.
[0038]
Even when the surface side of the second n-type region 41 is depleted in the off state, the adjacent surface-side portion 42a is not completely depleted, and some carriers remain as the p-type region. Among the equipotential lines approaching each other on the surface side, the equipotential lines on the high potential side are distributed outside the surface side portion 42a. For this reason, the surface electric field in the pressure | voltage resistant structure part 40 located outside the front-end | tip of the field plate FP is relieve | moderated, and a high pressure | voltage resistance can be achieved.
[0039]
[Example 3]
4 is a schematic plan view showing a chip of a vertical MOSFET element according to Embodiment 3 of the present invention, and FIG. 5 is a vertical cross-sectional view showing a state cut along the line AA ′ in FIG. In FIG. 4, ¼ of the drain / drift portion is shown.
[0040]
The difference from the configuration of the first embodiment in this example is that the repetition pitch P2 of the second parallel pn structure of the outer structure portion 40 is the same as the repetition pitch P1 of the first parallel pn structure, and the second parallel The impurity concentration of the pn structure is sufficiently lower than the impurity concentration of the first parallel pn structure. Note that the repetition pitch P2 may be wider than the repetition pitch P1 as long as the impurity concentration of the second parallel pn structure is sufficiently lower than the impurity concentration of the first parallel pn structure.
[0041]
In this example, the surface side portion 41a of the second n-type region 41 located outside the front end of the field plate FP in the outer pressure-resistant portion 40 has a second p-type region 42 in which the impurity concentration is adjacent. This is lower than the impurity concentration on the surface side. Even in such a case, even when the surface side portion 41a of the second n-type region 41 is depleted in the off state, the surface side of the adjacent second p-type region 42 is not completely depleted, and p Since some carriers remain as the mold region, this functions as a guard ring, and among the equipotential lines approaching each other on the surface side, the equipotential lines on the high potential side to the outside of the surface side portion of the second p-type region 42. Distribute. For this reason, the surface electric field in the pressure | voltage resistant structure part 40 located outside the front-end | tip of the field plate FP is relieve | moderated, and a high pressure | voltage resistance can be achieved.
[0042]
Thus, in this example, it is not necessary to form the second parallel pn structure as wide as the surface side portion 42a of the second p-type region 42, and impurities can be adjusted, so that the impurity introduction mask is reduced. be able to. The impurity concentration in the surface side portion of the second p-type region 42 may be higher than the impurity concentration in the surface side portion of the second n-type region 41.
[0043]
[Example 4]
FIG. 6 is a schematic plan view showing a chip of a vertical MOSFET element according to Embodiment 4 of the present invention, FIG. 7 is a vertical cross-sectional view showing a state cut along the line AA 'in FIG. 6, and FIG. 6 is a longitudinal sectional view showing a state cut along line BB ′ in FIG.
[0044]
In Example 1, the direction of the repetition pitch P1 in the first parallel pn structure and the direction of the repetition pitch P2 in the second parallel pn structure are the same direction, but in this example, in the first parallel pn structure The direction of the repetition pitch P1 and the direction of the repetition pitch P2 in the second parallel pn structure are orthogonal to each other. That is, the planar stripe of the first parallel pn structure and the planar stripe of the second parallel pn structure are orthogonal to each other. Even if the stripe direction changes, there is no change in that the withstand voltage can be maintained by depletion when the reverse voltage is applied, and even when the charge balance at the change of the stripe direction is lost, the inner withstand voltage portion 30 exists, High breakdown voltage can be achieved.
[0045]
Although the present invention has been described with respect to the vertical MOSFET element in the above embodiments, it goes without saying that the present invention can be applied to general semiconductor devices having a vertical drift portion.
[0046]
【The invention's effect】
As described above, in the present invention, the breakdown voltage structure portion around the drift portion is a part of the first parallel pn structure in which the repetitive pitch is continuously extended from the drift portion to the outside by one pitch or more adjacent to the drift portion. Since it has an inner peripheral structure portion and an outer peripheral structure portion that is a second parallel pn structure adjacent to the inner peripheral structure portion, the first parallel pn structure is provided in the adjacent peripheral portion of the drift portion. And the second parallel pn structure does not exist, and the boundary exists between the inner peripheral structure part and the outer peripheral structure part of the pressure-resistant structure part. The charge balance of the structure does not collapse, so that the surface electric field at the adjacent outer peripheral portion of the drift portion can be suppressed, and a high breakdown voltage and a large current can be achieved.
[Brief description of the drawings]
FIG. 1 is a schematic plan view showing a chip of a vertical MOSFET element according to Embodiment 1 of the present invention.
FIG. 2 is a longitudinal sectional view showing a state cut along line AA ′ in FIG. 1;
FIG. 3 is a partial longitudinal sectional view showing a vertical MOSFET according to a second embodiment of the invention.
FIG. 4 is a schematic plan view showing a chip of a vertical MOSFET element according to Example 3 of the invention.
5 is a longitudinal sectional view showing a state cut along the line AA ′ in FIG. 4;
FIG. 6 is a schematic plan view showing a chip of a vertical MOSFET element according to Embodiment 4 of the present invention.
7 is a longitudinal sectional view showing a state cut along the line AA ′ in FIG. 6;
8 is a longitudinal sectional view showing a state cut along the line BB ′ in FIG. 6;
FIG. 9 is a plan view showing a drift portion and an element outer peripheral portion (withstand voltage structure portion) in a vertical MOSFET.
10 is a longitudinal sectional view showing a state cut along the line AA ′ in FIG. 9;
11 is a longitudinal sectional view showing a state cut along the line BB ′ in FIG. 9;
[Explanation of symbols]
11 ... n ⁺ Drain layer (contact layer)
12e ... Intercostal area
13a ... p base region (p well)
14 ... n ⁺ Source area
15 ... Gate insulating film
16 ... Gate electrode layer
17 ... Source electrode
18 ... Drain electrode
19a ... Interlayer insulating film
22 ... Drain / drift section
22a ... first n-type region
22b ... first p-type region
26 ... p ⁺ Contact area
30 ... Inner circumferential structure
40. Peripheral structure
41 ... second n-type region
41a, 42a ... surface side portion
42 ... second p-type region
50 ... n-type go region
51. Stopper electrode
123 ... Oxide film
123a ... Inner circumference oxide film
123b. Intermediate region oxide film
123c ... Peripheral region oxide film
P1: Repetitive pitch of the first parallel pn structure
P2: Repetitive pitch of the second parallel pn structure
FP ... Field plate
S1, S2 ... steps
S3 ... The tip of the field plate
T1 to T5 ... surface side position of pn junction surface

Claims

A first electrode layer conductively connected to an element active portion selectively formed on the first main surface side of the substrate; and a first conductive type low resistance layer formed on the second main surface side of the substrate interposed between the second electrode layer to be electrically connected, and the element active portion and the low-resistance layer, and the vertical drift region deplete in the off state with a drift current flows in the vertical direction in the on state, the There is a breakdown voltage structure that is interposed between the first main surface and the low-resistance layer around the element active portion and the vertical drift portion, and is a non- electric path region in the on state and depleted in the off state. The vertical drift portion alternately and repeatedly joins the first vertical first conductivity type region oriented in the thickness direction of the substrate and the first vertical second conductivity type region oriented in the thickness direction of the substrate. A first parallel pn structure, and the withstand voltage structure portion includes the base A second parallel pn structure formed by alternately and repeatedly joining a second vertical first conductivity type region oriented in the thickness direction and a second vertical second conductivity type region oriented in the thickness direction of the substrate. A semiconductor device in which the impurity concentration of the second parallel pn structure is lower than the impurity concentration of the first parallel pn structure;
The pressure-resistant structure part includes an inner peripheral structure part adjacent to the drift part and a part of the first parallel pn structure in which a repeating pitch is continuously extended from the drift part by one pitch or more, and the inner peripheral structure. And a peripheral structure portion which is the second parallel pn structure adjacent to the portion.

A first electrode layer conductively connected to an element active portion selectively formed on the first main surface side of the substrate; and a first conductive type low resistance layer formed on the second main surface side of the substrate interposed between the second electrode layer to be electrically connected, and the element active portion and the low-resistance layer, and the vertical drift region deplete in the off state with flowing drift current in the vertical direction in the on state, the There is a breakdown voltage structure that is interposed between the first main surface and the low-resistance layer around the element active portion and the vertical drift portion, and is a non- electric path region in the on state and depleted in the off state. The vertical drift portion alternately and repeatedly joins the first vertical first conductivity type region oriented in the thickness direction of the substrate and the first vertical second conductivity type region oriented in the thickness direction of the substrate. A first parallel pn structure, and the withstand voltage structure portion includes the base A second parallel pn structure formed by alternately and repeatedly joining a second vertical first conductivity type region oriented in the thickness direction and a second vertical second conductivity type region oriented in the thickness direction of the substrate. A semiconductor device in which a repetition pitch of the second parallel pn structure is smaller than a repetition pitch of the first parallel pn structure;
The pressure-resistant structure part includes an inner peripheral structure part adjacent to the drift part and a part of the first parallel pn structure in which a repeating pitch is continuously extended from the drift part by one pitch or more, and the inner peripheral structure. And a peripheral structure portion which is the second parallel pn structure adjacent to the portion.

3. The insulating film according to claim 1, further comprising an insulating film on the first main surface of the pressure-resistant structure portion, the inner peripheral structure portion being covered on the insulating film and having a tip on the outer peripheral structure portion. A semiconductor device having a field plate protruding to

4. The semiconductor device according to claim 3, wherein the insulating film has a thickness that increases from the drift portion side toward the outer peripheral structure portion side.

5. The semiconductor device according to claim 4, wherein the thickness of the insulating film is increased stepwise from the drift portion side toward the outer peripheral structure portion side.

6. The semiconductor device according to claim 5, wherein the number of film thickness steps of the insulating film is two or more.

7. The first main surface of a pn junction surface having the first vertical second conductivity type region outside in a part of the first parallel pn structure belonging to the inner peripheral structure portion according to claim 5. A semiconductor device characterized in that a side position matches a step position of the field plate.

8. The first principal surface side position of a pn junction surface having the second vertical second conductivity type region on the outside in the second parallel pn structure according to claim 3, A semiconductor device characterized in that the tip position of a field plate matches.

9. The first main surface of the second vertical second conductivity type region according to claim 3, wherein the second vertical second conductivity type region is located outside the front end of the field plate in the second parallel pn structure. The semiconductor device is characterized in that the impurity concentration on the side is higher than the impurity concentration on the first main surface side of the adjacent second vertical first conductivity type region.

9. The first main surface of the second vertical second conductivity type region according to claim 3, wherein the second vertical second conductivity type region is located outside the front end of the field plate in the second parallel pn structure. A semiconductor device characterized in that the width dimension on the side is wider than the width dimension on the first main surface side of the adjacent second vertical first conductivity type region.

9. The first main surface of the second vertical first conductivity type region according to claim 3, wherein the second vertical first conductivity type region is positioned outside the front end of the field plate in the second parallel pn structure. A semiconductor device characterized in that the impurity concentration on the side is lower than the impurity concentration on the first main surface side of the adjacent second second conductivity type region.

12. The semiconductor device according to claim 1, wherein the first parallel pn structure and the second parallel pn structure have a planar stripe shape. 13.

In any one of claims 1 to 12, and characterized in that the direction of the repetitive pitch in the direction and the second parallel pn structure of the repeat pitch in the first parallel pn structure is interlinked straight Semiconductor device.

14. The semiconductor device according to claim 1, further comprising a first conductivity type surrounding region surrounding the outer peripheral structure portion.

15. The semiconductor device according to claim 14, further comprising a third electrode portion in conductive contact with the first main surface side of the first conductivity type surrounding region.

A first electrode layer conductively connected to an element active portion selectively formed on the first main surface side of the substrate; and a first conductive type low resistance layer formed on the second main surface side of the substrate interposed between the second electrode layer to be electrically connected, and the element active portion and the low-resistance layer, and the vertical drift region deplete in the off state with a drift current flows in the vertical direction in the on state, the There is a breakdown voltage structure that is interposed between the first main surface and the low-resistance layer around the element active portion and the vertical drift portion, and is a non- electric path region in the on state and depleted in the off state. The vertical drift portion alternately repeats a first vertical first conductivity type drift region oriented in the thickness direction of the substrate and a first vertical second conductivity type partition region oriented in the thickness direction of the substrate. A first parallel pn structure formed by bonding and the breakdown voltage structure; A second vertical first conductive type region oriented in the thickness direction of the substrate and a second vertical second conductive type region oriented in the thickness direction of the substrate are alternately and repeatedly joined together. In a semiconductor device having a parallel pn structure and having a field plate formed on an insulating film on the first main surface of the breakdown voltage structure portion,
In the second parallel pn structure, the first principal surface side position of the pn junction surface having the second vertical second conductivity type region on the outside matches the tip position of the field plate. A semiconductor device.

A first electrode layer conductively connected to an element active portion selectively formed on the first main surface side of the substrate; and a first conductive type low resistance layer formed on the second main surface side of the substrate interposed between the second electrode layer to be electrically connected, and the element active portion and the low-resistance layer, and the vertical drift region deplete in the off state with a drift current flows in the vertical direction in the on state, the There is a breakdown voltage structure that is interposed between the first main surface and the low-resistance layer around the element active portion and the vertical drift portion, and is a non- electric path region in the on state and depleted in the off state. The vertical drift portion alternately repeats a first vertical first conductivity type drift region oriented in the thickness direction of the substrate and a first vertical second conductivity type partition region oriented in the thickness direction of the substrate. A first parallel pn structure formed by bonding and the breakdown voltage structure; A second vertical first conductive type region oriented in the thickness direction of the substrate and a second vertical second conductive type region oriented in the thickness direction of the substrate are alternately and repeatedly joined together. In a semiconductor device having a parallel pn structure and having a field plate formed on an insulating film on the first main surface of the breakdown voltage structure portion,
In the second parallel pn structure, the second vertical first adjacent impurity concentration on the first main surface side of the second vertical second conductivity type region located outside the tip of the field plate is adjacent. A semiconductor device characterized by being higher than the impurity concentration on the first main surface side of the conductive type region.

A first electrode layer conductively connected to an element active portion selectively formed on the first main surface side of the substrate; and a first conductive type low resistance layer formed on the second main surface side of the substrate interposed between the second electrode layer to be electrically connected, and the element active portion and the low-resistance layer, and the vertical drift region deplete in the off state with a drift current flows in the vertical direction in the on state, the There is a breakdown voltage structure that is interposed between the first main surface and the low-resistance layer around the element active portion and the vertical drift portion, and is a non- electric path region in the on state and depleted in the off state. The vertical drift portion alternately repeats a first vertical first conductivity type drift region oriented in the thickness direction of the substrate and a first vertical second conductivity type partition region oriented in the thickness direction of the substrate. A first parallel pn structure formed by bonding and the breakdown voltage structure; A second vertical first conductive type region oriented in the thickness direction of the substrate and a second vertical second conductive type region oriented in the thickness direction of the substrate are alternately and repeatedly joined together. In a semiconductor device having a parallel pn structure and having a field plate formed on an insulating film on the first main surface of the breakdown voltage structure portion,
Of the second parallel pn structure, the second vertical first adjacent width dimension on the first main surface side of the second vertical second conductivity type region located outside the front end of the field plate is adjacent. A semiconductor device characterized in that it is wider than a width dimension on the first main surface side of a conductive type region.

A first electrode layer conductively connected to an element active portion selectively formed on the first main surface side of the substrate; and a first conductive type low resistance layer formed on the second main surface side of the substrate interposed between the second electrode layer to be electrically connected, and the element active portion and the low-resistance layer, and the vertical drift region deplete in the off state with a drift current flows in the vertical direction in the on state, the There is a breakdown voltage structure that is interposed between the first main surface and the low-resistance layer around the element active portion and the vertical drift portion, and is a non- electric path region in the on state and depleted in the off state. The vertical drift portion alternately repeats a first vertical first conductivity type drift region oriented in the thickness direction of the substrate and a first vertical second conductivity type partition region oriented in the thickness direction of the substrate. A first parallel pn structure formed by bonding and the breakdown voltage structure; A second vertical first conductive type region oriented in the thickness direction of the substrate and a second vertical second conductive type region oriented in the thickness direction of the substrate are alternately and repeatedly joined together. In a semiconductor device having a parallel pn structure and having a field plate formed on an insulating film on the first main surface of the breakdown voltage structure portion,
In the second parallel pn structure, the second second conductivity in which the impurity concentration on the first main surface side of the second vertical first conductivity type region located outside the front end of the field plate is adjacent. A semiconductor device characterized by being lower than the impurity concentration on the first main surface side of the mold region.