JP5430002B2 - Wiring board and manufacturing method thereof - Google Patents

Description

  The present invention relates to a wiring board for mounting a semiconductor integrated circuit element and a method for manufacturing the same, and more particularly to a build-up type wiring board in which build-up layers are stacked on the upper and lower surfaces of a core substrate and a method for manufacturing the same. Is.

  Conventionally, a wiring board formed by a build-up method is known as a wiring board for mounting a semiconductor integrated circuit element. FIG. 8 is a schematic sectional view showing a conventional wiring board 100 formed by a build-up method.

  As shown in FIG. 8, in the conventional wiring board 100, build-up insulating layers 104 and build-up wiring conductors 105 are alternately laminated on the upper and lower surfaces of the core board 101 having the core insulating plate 102 and the core wiring conductor 103. ing.

  The core insulating plate 102 is made of an electrically insulating material in which a glass cloth is impregnated with a thermosetting resin such as an epoxy resin or a bismaleimide triazine resin. Core wiring conductors 103 made of copper foil or a copper plating layer are attached to the upper and lower surfaces of the core insulating plate 102. A plurality of through holes 106 are formed in the core insulating plate 102 from the upper surface to the lower surface. A through-hole conductor 107 made of a copper plating layer is attached to the inner wall of the through-hole 106. The core wiring conductor 103 is formed so as to cover the through hole 106 and is connected to the through hole conductor 107. The through hole 106 is filled with a hole filling resin 108.

  The build-up insulating layer 104 is made of a resin-based electrical insulating material containing a thermosetting resin such as an epoxy resin and an inorganic insulating filler such as silica. A plurality of via holes 109 are formed in each of the build-up insulating layers 104, and a build-up wiring conductor 105 made of a copper plating layer is deposited on the surface of each build-up insulating layer 104 including the via holes 109. Yes. The build-up wiring conductor 105 is electrically connected to the core wiring conductor 103 while being connected to each other via the via hole 109. Further, a part of the build-up wiring conductor 105 deposited on the outermost build-up insulating layer 104 on the upper surface side is electrically connected to the electrode terminal T of the semiconductor integrated circuit element S via the conductive bump B1. The semiconductor element connection pads 105a are connected to each other, and a large number of these semiconductor element connection pads 105a are arranged in a grid. Further, a part of the lower surface side deposited on the outermost buildup insulating layer 104 is a circular external connection pad 105b that is electrically connected to the wiring conductor of the external electric circuit board. 105b is formed in a plurality of rows in a lattice pattern.

  Further, a solder resist layer 110 that exposes the semiconductor element connection pads 105a and the external connection pads 105b is deposited on the outermost buildup insulating layer 104 and the buildup wiring conductor 105 thereon. The electrode terminal T of the semiconductor integrated circuit element S is electrically connected to the exposed portion of the semiconductor element connection pad 105a via the conductive bump B1 made of solder, gold or the like, and is not shown in the exposed portion of the external connection pad 105b. The wiring conductor of the external electric circuit board is electrically connected via the solder ball B2.

  A method for manufacturing such a conventional wiring substrate 100 will be described with reference to FIGS. First, as shown in FIG. 9A, a double-sided copper-clad plate for a core substrate 101, in which a copper foil 123 for a core wiring conductor 103 is laminated on the upper and lower surfaces of a glass-resin plate 122 for a core insulating plate 102. 121 is prepared. The thickness of the glass-resin plate 122 is, for example, about 400 to 800 μm, and the thickness of the copper foil 123 is, for example, about 2 to 18 μm.

  Next, as shown in FIG. 9B, a through hole 106 is formed by drilling from the upper surface to the lower surface of the double-sided copper-clad plate 121. As a result, the core insulating plate 102 having the through hole 106 is formed. The diameter of the through hole 106 is about 100 to 300 μm.

  Next, as shown in FIG. 9C, a plated conductor layer 124 is formed by sequentially depositing an electroless copper plating layer and an electrolytic copper plating layer over the entire inner wall of the through hole 106 and the entire surface of the copper foil 123. Form. As a result, the through-hole conductor 107 composed of the plated conductor layer 124 is formed in the through-hole 106. The thickness of the electroless copper plating layer forming the plating conductor layer 124 is about 0.1 to 1 μm, and the thickness of the electrolytic copper plating layer is about 5 to 30 μm.

  Next, as shown in FIG. 9D, the hole filling resin 108 is filled into the through hole 106 to which the plated conductor layer 124 is deposited.

  Next, as shown in FIG. 9E, the upper and lower ends of the hole filling resin 108 and the surface of the plating conductor layer 124 are polished so that the copper foil 123 layer remains on the upper and lower surfaces of the core insulating plate 102. Flatten. At this time, the thickness of the copper foil 123 remaining on the core insulating plate 102 is about 2 to 8 μm.

  Next, as shown in FIG. 10 (f), the electroless copper plating layer and the electrolytic copper plating layer are formed over the entire surface of the remaining copper foil 123, the end face of the plated conductor layer 124, and the end face of the hole filling resin 108. A plated conductor layer 125 is formed by being sequentially deposited. The thickness of the electroless copper plating layer forming the plating conductor layer 125 is about 0.1 to 1 μm, and the thickness of the electrolytic copper plating layer is about 10 to 30 μm.

  Next, as shown in FIG. 10G, an etching resist layer 131 is formed on the surface of the plated conductor layer 125 so as to cover the region corresponding to the periphery of the through hole 106 and the periphery of the plated conductor layer 125.

  Next, as shown in FIG. 10H, the plating conductor layer 125 exposed from the etching resist layer 131 and the layer of the copper foil 123 thereunder are removed by etching. As a result, the core wiring conductor 103 having a shape corresponding to the etching resist layer 131 is formed.

  Next, as shown in FIG. 10I, the etching resist layer 131 is peeled off from the conductor layer 125. Thereby, the core substrate 101 having the core wiring conductor 103 having a predetermined pattern covering the through hole 106 is formed.

  Next, as illustrated in FIG. 11J, an insulating resin layer 126 for the buildup insulating layer 104 is laminated on the upper and lower surfaces of the core substrate 101. The insulating resin layer 126 is a resin-based electrical insulating material containing a thermosetting resin such as an epoxy resin and an inorganic insulating filler such as silica, and has a thickness of about 20 to 50 μm.

  Next, as shown in FIG. 11K, the insulating resin layer 126 is subjected to laser processing to form a via hole 109 having the core wiring conductor 103 as a bottom surface. Thereby, the build-up insulating layer 104 having the via hole 109 is formed.

  Next, as shown in FIG. 11L, a buildup wiring conductor 105 made of a plated conductor layer connected to the core wiring conductor 103 is formed in the via hole 109 and on the surface of the buildup insulating layer 104. The build-up wiring conductor 105 is composed of a plating conductor layer on which an electroless plating layer and an electrolytic copper plating layer are sequentially deposited, and is formed using a known semi-additive method.

  Next, as shown in FIG. 11 (m), the build-up insulating layer 104 and the build-up wiring conductor 105 of the next layer are formed in a predetermined number of layers as required. Finally, as shown in FIG. 11 (n), A solder resist layer 110 is deposited on the outermost build-up insulating layer 104 and the build-up wiring conductor 105 to complete the conventional wiring substrate 100.

  In recent years, with the miniaturization of electronic devices, semiconductor integrated circuit elements have rapidly become highly integrated and have become larger in size. High-density fine wiring is also mounted on the wiring board on which these elements are mounted. It is becoming required. In order to respond to the demand for such high-density fine wiring, the core substrate is formed by reducing the diameter of the through holes in the core substrate to a small value of, for example, 75 to 150 μm or less and the pitch of the through holes to 150 to 300 μm or less. Attempts have been made to increase the wiring density of core wiring conductors.

  However, when the diameter of the through hole in the core substrate is as small as 75 to 150 μm, in order to satisfactorily deposit the through hole conductor composed of the plated conductor layer in the through hole, the thickness of the core substrate is, for example, 600 μm or less. It should be thin. If the diameter of the through hole is 75 to 150 μm and the thickness of the core substrate exceeds 600 μm, the plating solution cannot flow well into the through hole, and the entire surface of the through hole has a sufficient thickness. The conductor layer cannot be satisfactorily deposited, and the risk that the through-hole conductor is broken increases.

  However, when the thickness of the core substrate is 600 μm or less, the rigidity of the core substrate is low because the thickness is small. When the rigidity of the core substrate is low, the rigidity of the entire wiring board using the core substrate is also low. If the rigidity of the wiring board is low, thermal stress or external force applied when a semiconductor integrated circuit element is mounted on the wiring board or when a wiring board on which the semiconductor integrated circuit element is mounted is mounted on an external electric circuit board. Etc., the wiring board is likely to be greatly bent. In particular, when a semiconductor integrated circuit element whose size is increased is mounted, a large stress is applied when the semiconductor integrated circuit element is mounted, so that the wiring board is also easily bent. When such a large deflection occurs, the electrical connection between the semiconductor integrated circuit element mounted on the wiring board and the wiring board is cut off, or the semiconductor integrated circuit element is cracked or cracked. However, the semiconductor integrated circuit element mounted on the wiring board cannot be normally operated.

JP 2001-144410 A

  The problem of the present invention is that, in a wiring board on which a semiconductor integrated circuit element is mounted, even when the through-hole diameter formed in the core substrate is small, the rigidity of the core substrate can be increased by increasing the thickness of the core substrate. Even when a large-sized semiconductor integrated circuit element is mounted, it is not greatly bent due to thermal stress or external force applied when mounting the semiconductor integrated circuit element or mounting on an external electric circuit board. Semiconductor integrated circuit to be mounted by effectively preventing electrical connection between the semiconductor integrated circuit element mounted on the wiring board and the wiring board, or cracking or cracking in the semiconductor integrated circuit element. An object of the present invention is to provide a wiring board of high-density wiring with high rigidity capable of operating an element normally and a manufacturing method thereof.

  The wiring board according to the present invention has through holes having a diameter of 75 to 150 μm, which are covered with through hole conductors at the same position, at a pitch of 150 to 300 μm, and covers the through holes on both main surfaces. Two core insulating plates having a thickness of 400 to 600 μm having a core wiring conductor connected to the through hole conductor have a through hole having a diameter of 50 to 120 μm at a position coinciding with the through hole, and the inside of the through hole Characterized in that a build-up insulating layer and a build-up wiring conductor are formed on the upper and lower surfaces of a core substrate laminated with an insulating adhesive layer having a thickness of 50 to 200 μm filled with conductive paste. It is.

  In the method for manufacturing a wiring board according to the present invention, through holes having a diameter of 75 to 150 μm, the insides of which are covered with through hole conductors, are arranged at the same position, with a pitch of 150 to 300 μm and the through holes are covered on both main surfaces. In this way, there are two core insulating plates having a thickness of 400 to 600 μm having a core wiring conductor connected to the through hole conductor, and a through hole having a diameter of 50 to 120 μm at a position coinciding with the through hole. The step of preparing a prepreg having a thickness of 50 to 200 μm, in which a through-hole is filled with a conductive paste, and the two core insulating plates are arranged so that the through-hole and the through-hole overlap each other vertically. The two core insulating plates are laminated through an insulating adhesive layer formed by laminating the prepreg and heating and pressing to cure the prepreg. Forming a core substrate in which core wiring conductors of the two core insulating plates are electrically connected to each other through the conductive paste, and build-up insulating layers on the upper and lower surfaces of the core substrate; And a step of forming a build-up wiring conductor.

  According to the wiring board and the manufacturing method thereof of the present invention, the core board is formed by bonding two core insulating plates having a thickness of 400 to 600 μm with an insulating adhesive layer having a thickness of 50 to 200 μm. It is as thick as 900 to 1400 μm, so that the rigidity is extremely high. Furthermore, although each core insulating plate constituting the core substrate has through-holes with a small diameter of 75 to 150 μm at a pitch of 150 to 300 μm, the thickness is as thin as 400 to 600 μm. A through-hole conductor can be satisfactorily deposited. Therefore, even when a large-sized semiconductor integrated circuit element is mounted, it is not greatly bent due to thermal stress or external force applied when mounting the semiconductor integrated circuit element or mounting on an external electric circuit board, A semiconductor to be mounted by effectively preventing the electrical connection between the semiconductor integrated circuit element mounted on the wiring board and the wiring board from being broken or the semiconductor integrated circuit element from being cracked or cracked. It is possible to provide a high-rigidity high-density wiring board capable of operating an integrated circuit element normally and a method for manufacturing the wiring board.

FIG. 1 is a schematic cross-sectional view showing an example of an embodiment of a wiring board according to the present invention. (A), (b) is a schematic sectional drawing for demonstrating an example of embodiment in the manufacturing method of the wiring board of this invention. (C), (d) is a schematic sectional drawing for demonstrating an example of embodiment in the manufacturing method of the wiring board of this invention. (E), (f) is a schematic sectional drawing for demonstrating an example of embodiment in the manufacturing method of the wiring board of this invention. (A)-(d) is a schematic sectional drawing for demonstrating an example of embodiment in the manufacturing method of the wiring board of this invention. (E)-(h) is a schematic sectional drawing for demonstrating an example of embodiment in the manufacturing method of the wiring board of this invention. (A)-(d) is a schematic sectional drawing for demonstrating an example of embodiment in the manufacturing method of the wiring board of this invention. It is a schematic sectional drawing which shows the conventional wiring board. (A)-(e) is a schematic sectional drawing for demonstrating the manufacturing method of the conventional wiring board. (F)-(i) is a schematic sectional drawing for demonstrating the manufacturing method of the conventional wiring board. (J)-(n) is a schematic sectional drawing for demonstrating the manufacturing method of the conventional wiring board.

Hereinafter, a wiring board and a manufacturing method thereof according to the present invention will be described in detail with reference to the drawings.
FIG. 1 is a schematic cross-sectional view showing an example of an embodiment of a wiring board 50 of the present invention, and shows a case where an area array type semiconductor integrated circuit element S is mounted by flip chip connection.

  As shown in FIG. 1, the wiring board 50 of this example is formed by alternately laminating a plurality of buildup insulating layers 2 and buildup wiring conductors 3 on the upper and lower surfaces of the core substrate 1, and a solder resist layer on the outermost surface thereof. 4 is attached.

  The core substrate 1 includes two core insulating plates 6 bonded with an insulating adhesive layer 5. The core insulating plate 6 has a thickness of about 400 to 600 μm, and is made of, for example, an electrically insulating material in which a glass cloth in which glass fiber bundles are woven vertically and horizontally is impregnated with a thermosetting resin such as a bismaleimide triazine resin or an epoxy resin.

  In the two core insulating plates 6, a plurality of through holes 7 having a diameter of 75 to 150 μm are formed at the same position at a pitch of 150 to 300 μm from the upper surface to the lower surface. A through-hole conductor 8 made of a plated conductor layer such as copper plating is deposited on the inner wall of the through-hole 7 and the inside of the through-hole conductor 8 is filled with a hole filling resin 9. A core wiring conductor 10 covering the through hole 7 is attached to the upper and lower surfaces of each core insulating plate 6 so as to connect to the through hole conductor 8. The core wiring conductor 10 is made of a copper foil and a copper plating layer.

  The insulating adhesive layer 5 is made of, for example, an electrically insulating material obtained by impregnating an allyl-modified polyphenylene ether resin into a glass cloth in which glass fiber bundles are woven vertically and horizontally. The thickness of the insulating adhesive layer 5 is about 50 to 200 μm. A through hole 11 is formed in the insulating adhesive layer 5 at a position coinciding with the through hole 7, and the inside thereof is filled with the conductive paste 12. The diameter of the through hole 11 is about 50 to 100 μm. The conductive paste 12 contains, for example, a metal powder containing bismuth, tin, silver, and copper and a resin component such as triallyl isocyanurate. The conductive paste 12 is cured by reacting with the surrounding allyl-modified polyphenylene ether resin, and electrically connects the upper and lower core wiring conductors 10 to each other.

  Thus, in the wiring substrate 50 of this example, the core substrate 1 is formed by bonding the two core insulating plates 6 having a thickness of 400 to 600 μm with the insulating adhesive layer 5 having a thickness of 50 to 200 μm. The thickness is as thick as 900 to 1400 μm, and therefore the rigidity is extremely high. Further, each core insulating plate 6 constituting the core substrate 1 has small through holes 7 with a diameter of 75 to 150 μm at a pitch of 150 to 300 μm, but the thickness is as thin as 400 to 600 μm. The through-hole conductor 8 can be satisfactorily deposited from the plated conductor layer. When the thickness of the insulating adhesive layer 5 is less than 50 μm, it tends to be difficult to bond the two core insulating plates 6 well with the insulating adhesive layer 5. It becomes difficult to satisfactorily fill with the conductive paste 12.

  The build-up insulating layer 2 has a thickness of about 20 to 50 μm, and a plurality of via holes 13 having a diameter of about 50 to 100 μm are formed in each of the build-up insulating layers 2. The build-up wiring conductor 3 is deposited. The buildup wiring conductor 3 is connected to the core wiring conductor 10 through a part of the via hole 13. Further, a part of the build-up wiring conductor 3 deposited on the outermost build-up insulating layer 2 on the upper surface side of the wiring substrate 50 has a conductive bump B1 applied to the electrode terminal T of the semiconductor integrated circuit element S. A circular semiconductor element connection pad 3a that is electrically connected by flip-chip connection is formed, and a plurality of these semiconductor connection pads 3a are formed in a lattice pattern. These semiconductor element connection pads 3a are covered with the solder resist layer 4 at the outer periphery thereof, and the central part of the upper surface is exposed from the solder resist layer 4. The electrode terminal T of the circuit element S is electrically connected through a conductive bump B1 made of solder, gold or the like.

  On the other hand, a portion of the lower surface side of the wiring board 50 that is deposited on the outermost buildup insulating layer 2 is a circular external connection pad 3b that is electrically connected to the wiring conductor of the external electric circuit board. A plurality of external connection pads 3b are arranged in a lattice. The external connection pad 3b is covered with a solder resist layer 4 at the outer periphery thereof, and the central portion of the lower surface is exposed from the solder resist layer 4, and an external electric circuit (not shown) is exposed at the exposed portion of the external connection pad 3b. The wiring conductor of the board is electrically connected via the solder ball B2. The solder resist layer 4 protects the outermost build-up wiring conductor 3 and defines exposed portions of the semiconductor element connection pads 3a and the external connection pads 3b. The solder resist layer 4 is made of a thermosetting resin having photosensitivity such as an acrylic-modified epoxy resin.

  Next, an example of an embodiment of the manufacturing method of the present invention for manufacturing such a wiring board 50 will be described with reference to FIGS. First, as shown in FIG. 2A, through holes 7 having a diameter of 75 to 150 [mu] m and covered with through hole conductors 8 at the same position at a pitch of 150 to 300 [mu] m and through holes 7 are formed on both main surfaces. Two core insulating plates 6 having a thickness of 400 to 600 μm having a core wiring conductor 10 connected to the through hole conductor 8 so as to cover the through hole, and a through hole having a diameter of 50 to 120 μm at a position coinciding with the through hole 7 And a prepreg 5P having a thickness of 50 to 200 μm formed by filling the through-hole 11 with an uncured conductive paste 12.

  Here, a method for preparing the core insulating plate 6 having the through-hole conductor 8 in the through-hole 7 and having the core wiring conductor 10 on the upper and lower surfaces will be described. First, as shown in FIG. 5 (a), drilling or laser processing is performed on the double-sided copper-clad plate for the core insulating plate 6 with the copper foils 21 applied to the upper and lower surfaces thereof, from the upper surface to the lower surface. A plurality of through holes 7 are drilled to produce the core insulating plate 6. The thickness of the copper foil 21 is about 2 to 18 μm.

  Next, as shown in FIG. 5B, a plated conductor layer 22 is formed by sequentially depositing an electroless copper plating layer and an electrolytic copper plating layer over the entire inner wall of the through hole 7 and the entire surface of the copper foil 21. Adhere. As a result, the through-hole conductor 8 composed of the plated conductor layer 22 is formed in the through-hole 7. The thickness of the electroless copper plating layer forming the plating conductor layer 22 is about 0.1 to 1 μm, and the thickness of the electrolytic copper plating layer is about 5 to 30 μm. At this time, although the core insulating plate 6 has small through holes 7 with a diameter of 75 to 150 μm at a pitch of 150 to 300 μm, the thickness is as thin as 400 to 600 μm. The through-hole conductor 8 can be satisfactorily deposited.

  Next, as shown in FIG. 5C, a hole filling resin 9 is filled into the through hole 7 in which the through hole conductor 8 is formed. The hole filling resin 9 is made of, for example, a thermosetting resin such as an epoxy resin. Such hole-filling resin 9 is formed by filling a resin paste containing a thermosetting resin into the through-hole 7 using a screen printing method and thermosetting it.

  Next, as shown in FIG. 5D, the upper and lower ends of the hole filling resin 9 and the surface of the plated conductor layer 22 are polished so that the copper foil 21 layer remains on the upper and lower surfaces of the core insulating plate 6. Flatten. At this time, the thickness of the layer of the copper foil 21 remaining on the core insulating plate 6 is about 2 to 8 μm.

  Next, as shown in FIG. 6E, an electroless copper plating layer and an electrolytic copper plating layer are formed over the entire surface of the remaining copper foil 21 layer, the end face of the through-hole conductor 8 and the end face of the hole-filling resin 9. A plated conductor layer 23 is formed by being sequentially deposited. The thickness of the electroless copper plating layer forming the plating conductor layer 23 is about 0.1 to 1 μm, and the thickness of the electrolytic copper plating layer is about 10 to 30 μm.

  Next, as shown in FIG. 6 (f), an etching resist layer 31 is formed on the surface of the plating conductor layer 23 so as to cover the region corresponding to the through hole 7 and the periphery thereof in the plating conductor layer 23.

  Next, as shown in FIG. 6G, the plating conductor layer 23 exposed from the etching resist layer 31 and the layer of the copper foil 21 thereunder are removed by etching. As a result, the core wiring conductor 10 having a shape corresponding to the etching resist layer 31 is formed.

  Next, as shown in FIG. 6H, the etching resist layer 31 is peeled off from the conductor layer 23. As a result, the core insulating plate 6 having the predetermined pattern of the core wiring conductor 10 covering the through hole 7 is formed.

  Further, a method for preparing a prepreg 5P having the through hole 11 and filled with the conductive paste 12 in the through hole 11 will be described. First, as shown to Fig.7 (a), the prepreg 5P by which the protective film 24 was stuck on the upper and lower surfaces so that peeling was possible was prepared. The prepreg 5P is obtained by impregnating a glass cloth with, for example, an uncured allyl-modified polyphenylene ether resin and semi-curing it. For the protective film 24, for example, polyethylene terephthalate is used. The thickness of the protective film 24 is, for example, about 5 to 25 μm.

  Next, as shown in FIG. 7B, a plurality of through holes 11 are formed by performing laser processing from the upper surface to the lower surface of the prepreg 5P.

  Next, as shown in FIG. 7C, the conductive paste 12 is filled into the through hole 11. In order to fill the conductive paste 12, a method of supplying the conductive paste 12 on the protective film 24 on the upper surface side and filling the conductive paste 12 by sliding a hard rubber squeegee while scratching the conductive paste 12 is adopted. Is done. The conductive paste 12 is made of, for example, a metal powder made of an alloy of tin, silver, bismuth, and copper and a triazine such as triallyl cyanurate, triallyl isocyanurate, trisepoxypropyl isocyanurate, tris (2-hydroxyethyl) isocyanurate. Containing thermosetting resin.

  Next, as shown in FIG. 7 (d), the protective film 24 is peeled off and removed from the upper and lower surfaces of the prepreg 5 </ b> P, thereby forming the prepreg 5 </ b> P filled with the conductive paste 12 in the through holes 11.

  Next, as shown in FIG. 2B, the two core insulating plates 6 are laminated with the prepreg 5P interposed therebetween so that the through holes 7 and the through holes 11 overlap each other and heated and pressurized. The two core insulating plates 6 are bonded to each other through the insulating adhesive layer 5 formed by curing the prepreg 5P, and the core wiring conductors 10 of the two core insulating plates 6 are electrically connected to each other through the cured conductive paste 12. The core substrate 1 that is connected electrically is obtained.

  Thus, since the core substrate 1 is obtained by bonding the two core insulating plates 6 having a thickness of 400 to 600 μm with the insulating adhesive layer 5 having a thickness of 50 to 200 μm, the thickness of the core substrate 1 is set to 900 to 1400 μm. Can be thicker. Thereby, the rigidity of the core substrate 1 can be made extremely high.

  Next, as shown in FIG. 3C, the insulating resin layer 25 for the buildup insulating layer 2 is laminated on the upper and lower surfaces of the core substrate 1. The insulating resin layer 25 is a resin-based electrical insulating material containing a thermosetting resin such as an epoxy resin and an inorganic insulating filler such as silica, and has a thickness of about 20 to 50 μm.

  Next, as shown in FIG. 3D, the via hole 13 having the core wiring conductor 10 as a bottom surface is formed by performing laser processing on the insulating layer 25. Thereby, the build-up insulating layer 2 having the via hole 13 is formed.

  Next, as shown in FIG. 4 (e), the build-up wiring conductor 3 composed of a plated conductor layer connected to the core wiring conductor 10 is formed in the via hole 13 and on the surface of the build-up insulating layer 2. The build-up wiring conductor 3 is composed of a plating conductor layer in which an electroless plating layer having a thickness of about 0.1 to 1 μm and an electrolytic copper plating layer having a thickness of about 5 to 30 μm are sequentially deposited, and a known semi-additive method is used. Form.

  Finally, as shown in FIG. 4 (f), after forming a predetermined number of layers of the build-up insulating layer 2 and the build-up wiring conductor 3 as the next layer as necessary, the outermost build-up insulating layer 2 and the build-up wiring are formed. The solder resist layer 4 is deposited on the conductor 3 to complete the wiring board 50 of this example.

  Thus, according to the wiring board and the manufacturing method thereof of the present invention, even when a large-sized semiconductor integrated circuit element is mounted, when mounting the semiconductor integrated circuit element or mounting on an external electric circuit board, etc. There is no significant deflection due to applied thermal stress or external force, the electrical connection between the semiconductor integrated circuit element mounted on the wiring board and the wiring board is broken, or cracks or cracks occur in the semiconductor integrated circuit element. Therefore, it is possible to provide a high-rigidity, high-density wiring board capable of operating the mounted semiconductor integrated circuit element normally and a manufacturing method thereof. In addition, this invention is not limited to the above-mentioned embodiment, A various change is possible if it is a range which does not deviate from the summary of this invention.

1: Core substrate 2: Build-up insulating layer 3: Build-up wiring conductor 5: Insulating adhesive layer 5P: Prepreg 6: Core insulating plate 7: Through hole 8: Through hole conductor 10: Core wiring conductor 11: Through hole 12: Conductive paste

Claims (2)

  At the same position, there are through holes with a diameter of 75 to 150 μm covered with through hole conductors at a pitch of 150 to 300 μm, and are connected to the through hole conductors so as to cover the through holes on both main surfaces. Two core insulating plates having a thickness of 400 to 600 μm having core wiring conductors having through holes having a diameter of 50 to 120 μm at positions corresponding to the through holes and filled with conductive paste in the through holes A wiring board comprising: a build-up insulating layer and a build-up wiring conductor formed on the upper and lower surfaces of a core substrate laminated with an insulating adhesive layer interposed therebetween.   At the same position, there are through holes with a diameter of 75 to 150 μm covered with through hole conductors at a pitch of 150 to 300 μm, and are connected to the through hole conductors so as to cover the through holes on both main surfaces. Two core insulating plates having a thickness of 400 to 600 μm having core wiring conductors and through holes having a diameter of 50 to 120 μm at positions corresponding to the through holes and filled with conductive paste in the through holes Preparing the prepreg, and laminating the two core insulating plates with the prepreg sandwiched therebetween so that the through hole and the through hole overlap each other, and heating and pressurizing the prepreg The two core insulating plates are bonded to each other through a cured insulating adhesive layer and the two sheets are bonded to each other through the conductive paste. Performing a step of forming a core substrate in which core wiring conductors of the core insulating plate are electrically connected to each other, and a step of forming a buildup insulating layer and a buildup wiring conductor on the upper and lower surfaces of the core substrate. A method for manufacturing a wiring board.

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