[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

JP4070193B2 - Wiring board and electronic component mounting structure - Google Patents

Wiring board and electronic component mounting structure Download PDF

Info

Publication number
JP4070193B2
JP4070193B2 JP2002312875A JP2002312875A JP4070193B2 JP 4070193 B2 JP4070193 B2 JP 4070193B2 JP 2002312875 A JP2002312875 A JP 2002312875A JP 2002312875 A JP2002312875 A JP 2002312875A JP 4070193 B2 JP4070193 B2 JP 4070193B2
Authority
JP
Japan
Prior art keywords
insulating layer
glass cloth
wiring board
wiring
warp
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2002312875A
Other languages
Japanese (ja)
Other versions
JP2004179171A (en
Inventor
正明 堀
賢 下之薗
勇 桐木平
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP2002312875A priority Critical patent/JP4070193B2/en
Publication of JP2004179171A publication Critical patent/JP2004179171A/en
Application granted granted Critical
Publication of JP4070193B2 publication Critical patent/JP4070193B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)

Description

【0001】
【発明の属する技術分野】
本発明は、半導体素子や抵抗器等の電子部品を搭載するための配線基板および電子部品実装構造体に関する。
【0002】
【従来の技術】
従来、半導体素子や抵抗器等の電子部品を搭載するために用いられる配線基板として、撚糸である縦糸および横糸を両者の軸方向のなす角度が直角方向となるように織って成るガラスクロスに熱硬化性樹脂を含浸させて成る絶縁層と銅箔から成る配線導体とを交互に複数積層して成るプリント基板が知られている。このようなプリント基板は、まず絶縁層表面に被着した銅箔をエッチングして所定パターンの配線導体を形成し、次に配線導体が形成された絶縁層を熱硬化性樹脂から成る接着材を間に挟んで複数枚積層圧着して積層基板を製作し、次にドリルで積層基板の表裏を貫通するスルーホールを形成し、しかる後、スルーホールの内面に銅めっきを被着して上下に位置する配線導体間を電気的に接続するスルーホール導体を形成することによって製作される。
【0003】
なお通常、各絶縁層は、1枚のガラスクロスに熱硬化性樹脂を含浸させて成り、種々の径の撚糸を選択することにより所望の厚みのガラスクロスを得るとともにこれに熱硬化性樹脂を含浸させることにより、所望の厚みとなる。
【0004】
近年、電子機器は、その高密度化に伴って半導体素子も年々高集積化されてきており、半導体素子を搭載する配線基板の配線導体に対する密度向上の要求も益々高まってきている。しかしながら、上述のプリント基板は、積層基板を表裏を貫通するスルーホール構造をとるため、配線導体の密度を向上させることが困難であるという問題点を有していた。
【0005】
このような問題点を解決するために、スルーホール構造に代えて、各絶縁層毎に貫通孔を形成し、この貫通孔に導体を充填して上下の各配線導体間を接続したインナービアホール構造が実用化されている。このようなインナービアホール構造では貫通孔の径が200μm以下と微細加工が要求され、ドリルでは200μm以下の小径の穿孔は難しいことから、レーザで貫通孔を穿孔することが一般的に行なわれている。
【0006】
しかしながら、絶縁層を構成するガラスクロスは、撚糸を縦・横に織った構造となっており、ガラスクロスを上面視したときに、縦・横の撚糸が重なっている部分と、どちらか一方の撚糸が存在している部分と、撚糸が存在しない部分、すなわち縦・横の撚糸により囲まれた隙間の3種類の部分が混在しているとともに、その隙間の開口の全面積がガラスクロスの面積の5〜12%となっており、このようなガラスクロスに熱硬化性樹脂を含浸させて成る絶縁層にレーザを用いて貫通孔を穿孔した場合、縦・横の撚糸が重なっている撚糸の密な部分では貫通孔の内部径や出射径が小さくなり、撚糸の存在しない隙間部分では貫通孔の内部径や出射径が大きくなり、均一な内部径や出射径を有する貫通孔を穿孔できないという問題点があった。
【0007】
このような問題点を解決するために、複数の絶縁層を積層して基板を製作する際に、上下に位置する各絶縁層に含まれるガラスクロスの織り目位置が互いに異なるように、絶縁層を積層することが提案されている(特許文献1参照)。
【0008】
【特許文献1】
特開2002−76548号公報
【0009】
【発明が解決しようとする課題】
しかしながら、従来のガラスクロスは、その隙間の開口の全面積がガラスクロスの面積の5〜12%と開口の全面積の割合が大きいことから、上下に位置する各絶縁層に含まれるガラスクロスの織り目位置が互いに異なるように積層したとしても、依然として撚糸の密な部分と疎な部分が存在してしまい、基板にレーザを用いて貫通孔を穿孔する場合、均一な内部径や出射径を有する貫通孔を穿孔することが困難であり、貫通孔に導電性材料を充填して貫通導体を形成した場合に、貫通導体の抵抗が部分的に高くなったり、断線してしまうという問題点があった。
【0010】
また、各絶縁層が1枚のガラスクロスに熱硬化性樹脂を含浸させて成ることから、絶縁層の厚みが厚い場合、ガラスクロスを構成する撚糸の径も大きなものとなり、開口の全面積が大きくなるとともに撚糸の密な部分と疎な部分との疎密差がより大きなものとなってしまうという問題点もあった。さらに、絶縁層の厚みが薄い場合、ガラスクロス1枚のみではその剛性が低下して、大型のLSI等の半導体素子を配線基板に実装した際に、半導体素子の動作時に半導体素子と配線基板との熱膨張係数の相違に起因して大きな応力が発生し、この応力によって半導体素子が配線基板から剥がれてしまう、あるいは半導体素子が破壊されてしまうという問題点もあった。
【0011】
本発明はかかる従来技術の問題点に鑑み完成されたものであり、その目的は、微細な貫通導体を有する高密度な配線基板において、レーザ加工で径が均一な貫通孔が形成でき貫通導体の電気的接続信頼性に優れるとともに、半導体素子を良好に実装できる配線基板を提供するものである。
【0012】
【課題を解決するための手段】
本発明の配線基板は、縦糸および横糸を織って成るガラスクロスを複数積層するとともにこの積層したガラスクロスに熱硬化性樹脂を含浸させて成る絶縁層の上下面に配線導体を形成し、絶縁層を挟んで上下に位置する配線導体同士を絶縁層に設けた貫通導体を介して電気的に接続して成り、ガラスクロスは、縦糸および横糸に囲まれた隙間の開口の全面積がガラスクロスの面積の0.01〜2%であり、かつ開口が上下に重ならないように積層され、前記積層したガラスクロスのうち上下に接するものは、上側の前記縦糸の軸方向と下側の前記縦糸の軸方向とのなす角度が15〜75度となるように積層されており、前記配線導体は前記絶縁層の表面に埋入されていることを特徴とするものである。
また、本発明の電子部品実装構造体は、上記本発明の配線基板の前記配線導体に半田バンプを介して電子部品が接合されてなることを特徴とするものである。
【0013】
本発明によれば、ガラスクロスを複数積層するとともにこの積層したガラスクロスに熱硬化性樹脂を含浸させて成る絶縁層の上下面に配線導体を形成し、絶縁層を挟んで上下に位置する配線導体同士を絶縁層に設けた貫通導体を介して電気的に接続して成ることから、絶縁層の厚みが厚い場合においてもガラスクロスを構成する撚糸の径を大きなものとする必要はなく、その結果、ガラスクロスの隙間の開口の全面積が大きくなることはなく、撚糸の密な部分と疎な部分との疎密差が大きなものとなることはない。
【0014】
また、ガラスクロスは、その隙間の開口の全面積がガラスクロスの面積の0.01〜2%であり、かつ開口が上下に重ならないように積層されていることから、撚糸の密な部分と疎な部分との疎密差がより小さなものとなり、配線基板にレーザを用いて貫通孔を穿孔する際、均一な内部径や出射径を有する貫通孔を穿孔することができ、貫通孔に導電性材料を充填して貫通導体を形成した場合に、貫通導体の抵抗が部分的に高くなったり、断線してしまうということはない。
【0015】
さらに、絶縁層はガラスクロスを複数積層するとともにこの積層したガラスクロスに熱硬化性樹脂を含浸させて成ることから、絶縁層が薄い場合でも複数のガラスクロスを積層したほうが絶縁層の剛性の低下を減少させることができ、その結果、大型のLSI等の半導体素子を配線基板に実装した際、半導体素子の動作時に半導体素子と配線基板との熱膨張係数の相違に起因して大きな応力が発生しても、半導体素子が配線基板から剥がれてしまう、あるいは半導体素子が破壊されてしまうことはない。
【0017】
また、本発明によれば、ガラスクロスの縦糸および横糸の軸方向の弾性率と、縦糸および横糸の交点間を結ぶ方向の弾性率との差が大きいが、積層したガラスクロスのうち上下に接するものは、上側の縦糸の軸方向と下側の縦糸の軸方向とのなす角度を15〜75度となるように積層することにより、絶縁層の方向毎の弾性率の差異を小さくすることでき、その結果、配線基板に大型のLSI等の半導体素子を実装した時に発生する応力による配線基板の変形を抑制でき、半導体素子が配線基板から剥がれてしまう、あるいは半導体素子が破壊されてしまうということをより有効に防止することができる。
【0018】
【発明の実施の形態】
次に、本発明の配線基板を添付の図面に基づいて詳細に説明する。
図1は、本発明の配線基板の実施の形態の一例を示す断面図、図2は図1に示す配線基板を構成するガラスクロスの平面図であり、上側のガラスクロスと下側のガラスクロスとの位置関係が明確となるように、下側のガラスクロスの輪郭を実線で示してある。これらの図において、1はガラスクロス、2は熱硬化性樹脂、3は絶縁層、4は配線導体、5は貫通孔、6は貫通導体、7aは隙間、7bは開口である。
【0019】
本発明の配線基板は、縦糸1aおよび横糸1bを両者の軸方向が略垂直となるように織って成るガラスクロス1を複数積層するとともにこの積層したガラスクロス1に熱硬化性樹脂2を含浸させて成る絶縁層3の上下面に配線導体4を形成し、絶縁層3を挟んで上下に位置する配線導体4同士を絶縁層3に設けた貫通導体6を介して電気的に接続して成るものであり、図1にはこのような配線基板を4層積層して成る積層配線基板の例を示している。
【0020】
絶縁層3は、その厚みが50〜150μmであり、配線導体4を支持するとともに上下に位置する配線導体4間の絶縁を保持する機能を有し、複数枚のガラスクロス1にエポキシ樹脂やビスマレイミドトリアジン樹脂・変性ポリフェニレンエーテル樹脂等の熱硬化性樹脂2を含浸させて成る。なお、絶縁層3の厚みが50μm未満であると配線基板の剛性が低下して、配線基板が撓みやすくなる傾向があり、150μmを超えると絶縁層3の厚みが不要に厚いものとなり配線基板の軽量化が困難となる傾向がある。従って、絶縁層3は、その厚みを50〜150μmとすることが好ましい。
【0021】
ガラスクロス1は、その織り方により平織、綾織、朱子織等の種類があり、図2には、縦・横糸1a・1bが1本毎に上下に交差して成る平織の平面図を示している。ガラスクロス1は、その厚みが10〜50μmであり、厚みが10μmより薄くなると縦糸1aおよび横糸1bが非常に細くなり均等に織ることが難しくなるので硬化後に絶縁層3が反ってしまう傾向にあり、50μmより厚いと絶縁層3が不要に厚くなり配線基板の軽量化が困難となる傾向がある。従って、ガラスクロス1の厚みは10〜50μmであることが好ましい。
【0022】
そして本発明の配線基板は、ガラスクロス1を複数積層するとともにこの積層したガラスクロス1に熱硬化性樹脂2を含浸させて成る絶縁層3の上下面に配線導体4を形成し、絶縁層3を挟んで上下に位置する配線導体4同士を絶縁層3に設けた貫通導体6を介して電気的に接続して成り、ガラスクロス1は、縦糸1aおよび横糸に囲まれた隙間7aの開口7bの全面積がガラスクロス1の面積の0.01〜2%であり、かつ開口7bが上下に重ならないように積層されている。そして、本発明においては、ガラスクロス1の隙間7aの開口7bの全面積がガラスクロス1の面積の0.01〜2%であり、かつこの開口7bが上下に重ならないように積層されていることが重要である。
【0023】
本発明の配線基板によれば、ガラスクロス1を複数積層するとともにこの積層したガラスクロス1に熱硬化性樹脂2を含浸させて成る絶縁層3の上下面に配線導体4を形成し、絶縁層3を挟んで上下に位置する配線導体4同士を絶縁層1に設けた貫通導体6を介して電気的に接続して成ることから、絶縁層3の厚みが厚い場合においてもガラスクロス1を構成する撚糸の縦糸1aや横糸1bの径を大きなものとする必要はなく、その結果、ガラスクロス1の隙間7aの開口7bの全面積が大きくなることはなく、撚糸の密な部分と疎な部分との疎密差が大きなものとなることはない。
【0024】
また、ガラスクロス1の隙間7aの開口7bの全面積がガラスクロス1の面積の0.01〜2%であり、かつ開口7bが上下に重ならないように積層されていることから、撚糸の密な部分と疎な部分との疎密差がより小さなものとなり、配線基板にレーザを用いて貫通孔5を穿孔する際、均一な内部径や出射径を有する貫通孔5を穿孔することができ、貫通孔5に導電性材料を充填して貫通導体6を形成した場合に、貫通導体6の抵抗が部分的に高くなったり、断線してしまうということはない。
【0025】
さらに、絶縁層3はガラスクロス1を複数積層するとともにこの積層したガラスクロス1に熱硬化性樹脂2を含浸させたて成ることから、絶縁層3が薄い場合でも複数のガラスクロス1を積層したほうが絶縁層3の剛性の低下を減少させることができ、その結果、大型のLSI等の半導体素子(図示せず)を配線基板に実装した際、半導体素子の動作時に半導体素子と配線基板との熱膨張係数の相違に起因して大きな応力が発生しても、半導体素子が配線基板から剥がれてしまう、あるいは半導体素子が破壊されてしまうことはない。
【0026】
なお、ガラスクロス1における隙間7aの開口7bの全面積がガラスクロス1の面積の0.01%より小さいとガラスクロス1に熱硬化性樹脂2を良好に含浸できず、絶縁層3の絶縁性が低下してしまう傾向にあり、2%を超えると隙間7aに貫通孔5を穿孔する確率が高くなり、均一な径の貫通孔5を穿孔できなくなる傾向にある。従って、ガラスクロス1の隙間7aの開口7bの全面積をガラスクロス1の面積の0.01〜2%とすることが重要である。
【0027】
このような開口7bの全面積は、ガラスクロス1を高圧水流処理やロールによる加圧処理等により扁平加工することにより、ガラスクロス1における隙間7aの開口7bの全面積がガラスクロス1の面積の0.01〜2%となるように調製される。
【0028】
なお、ガラスクロス1の表面には、熱硬化性樹脂2との密着性を向上するために、シランカップリング処理がなされている。また、これらのガラスクロス1は通常Eガラスと呼ばれるガラスが使用されているが、DガラスやSガラス・高誘電率ガラスなどを用いて良い。
【0029】
また、本発明の配線基板においては、ガラスクロス1を上側の縦糸の軸方向と下側の縦糸の軸方向とのなす角度が15〜75度となるように積層することが好ましい。
【0030】
本発明の配線基板によれば、ガラスクロス1の縦糸1aおよび横糸1bの軸方向の弾性率と、縦糸1aおよび横糸1bの交点間を結ぶ方向の弾性率との差が大きいが、ガラスクロス1を上側の縦糸1aの軸方向と下側の縦糸1aの軸方向とのなす角度が15〜75度となるように積層していることから、絶縁層3の方向における弾性率の差異を小さくすることでき、その結果、配線基板に大型のLSI等の半導体素子を実装した時に発生する応力による配線基板の変形を抑制でき、半導体素子が配線基板から剥がれてしまう、あるいは半導体素子が破壊されてしまうということを有効に防止することができる。
【0031】
なお、上側の縦糸1aの軸方向と下側の縦糸1aの軸方向とのなす角度が15度未満あるいは75度を超えると、ガラスクロス1の縦糸1aおよび横糸1bの軸方向とその斜め方向との弾性率の差が大きなものとなり、配線基板に大型のLSI等の半導体素子を実装した時に発生する応力により配線基板が変形し、半導体素子が配線基板から剥がれてしまう、あるいは半導体素子が破壊されてしまう危険性が大きなものとなる傾向がある。従って、上側の縦糸の軸方向と下側の縦糸の軸方向とのなす角度を15〜75度の範囲とすることが好ましい。
【0032】
また、絶縁層3を構成する熱硬化性樹脂2としては、150〜200℃の温度で硬化するエポキシ樹脂やビスマレイミドトリアジン樹脂・変性ポリフェニレンエーテル樹脂等の熱硬化性樹脂2が用いられる。なお、熱硬化性樹脂2をガラスクロス1に良好に含浸するために、界面活性剤や無機フィラー等を添加しても良い。
【0033】
さらに、絶縁層3の表面には配線導体4が埋入されている。配線導体4は、配線基板に搭載される半導体素子等の電子部品の各電極を外部電気回路基板(図示せず)に電気的に接続する導電路の一部としての機能を有し、幅が20〜200μm、厚みが5〜50μmで、銅やアルミニウム・ニッケル・銀・金等の金属箔から成り、特に加工性および安価という観点からは銅箔から成ることが好ましい。配線導体4の幅が20μm未満となると配線導体4の変形や断線が発生しやすくなる傾向があり、200μmを超えると高密度配線が形成できなくなる傾向がある。また、配線導体4の厚みが5μm未満になると配線導体4の強度が低下し変形や断線が発生しやすくなる傾向があり、50μmを超えると絶縁層3への埋入が困難となる傾向がある。従って、配線導体4は、その幅を20〜200μm、厚みを5〜50μmとすることが好ましい。
【0034】
また、絶縁層3には、その上面から下面にかけて貫通導体6が複数個配設されている。貫通導体6は、絶縁層1の上下に位置する配線導体2間を電気的に接続する機能を有し、その直径が30〜100μmであり、絶縁層3に設けた貫通孔5に錫を主成分とする金属粉末とトリアジン系熱硬化性樹脂等とから成る導電性材料を埋め込み熱硬化することにより形成されている。なお、貫通導体5の直径が30μm未満になるとその加工が困難となる傾向があり、100μmを超えると高密度配線が形成できなくなる傾向がある。従って、貫通導体4は、その直径を30〜100μmとすることが好ましい。
【0035】
なお、本発明の配線基板においては、ガラスクロス1の隙間7aの開口7bの全面積がガラスクロス1の面積の0.01〜2%であり、かつ開口7bが上下に重ならないように積層されていることから、直径が30〜100μmの範囲で、均一な直径の貫通孔5を形成することができる。
【0036】
また、導電性材料の金属粉末5の含有量は80〜95重量%が好ましい。金属粉末5の含有量が80重量%より少ないと、トリアジン系熱硬化性樹脂により金属粉末5同士の接続が妨げられ導通抵抗が上昇してしまう傾向があり、95重量%を超えると導電性材料の粘度が上がり過ぎて良好に埋め込みできない傾向がある。従って、導電性材料の金属粉末の含有量は80〜95重量%が好ましい。
【0037】
さらに、絶縁層3の一方の最外層表面に形成された配線導体4の一部は、電子部品(図示せず)の各電極に半田バンプ(図示せず)を介して接合される電子部品接続用の実装用電極11aを形成し、絶縁層3の他方の最外層表面に形成された配線導体2の一部は、外部電気回路基板(図示せず)の各電極に導体バンプ(図示せず)を介して接続される外部接続用の実装用電極11bを形成している。
【0038】
なお、実装用電極11a・11bの表面には、その酸化腐蝕を防止するとともに半田バンプ(図示せず)との接続を良好とするために、半田との濡れ性が良好で耐腐蝕性に優れたニッケル−金等のめっき層が被着されている。
【0039】
また、最外層の絶縁層3および実装用電極11a・11bには、必要に応じて実装用電極11a・11bの中央部を露出させる開口を有する耐半田樹脂層12が被着されている。耐半田樹脂層12は、その厚みが10〜50μmであり、例えばアクリル変性エポキシ樹脂等の感光性樹脂と光開始剤等とから成る混合物に30〜70重量%のシリカやタルク等の無機粉末フィラーを含有させた絶縁材料から成り、隣接する実装用電極11a・11b同士が半田バンプ(図示せず)により電気的に短絡することを防止するとともに、実装用電極11a・11bと絶縁層3との接合強度を向上させる機能を有する。
【0040】
このような耐半田樹脂層12は、感光性樹脂と光開始剤と無機粉末フィラーとから成る未硬化樹脂フィルムを最外層の絶縁層3表面に被着させる、あるいは、熱硬化性樹脂と無機粉末フィラーとから成る未硬化樹脂ワニスを最外層の絶縁層3表面に塗布するとともに乾燥し、しかる後、露光・現像により開口部を形成し、これをUV硬化および熱硬化させることにより形成される。
【0041】
なお、配線基板は、以下に述べる方法により製作される。まず、例えば、厚みが50μmのガラスクロス1にエポキシ樹脂や変性ポリフェニレン樹脂等から成る熱硬化樹脂2前駆体を含浸させたプリプレグを、ガラスクロス1の開口7bが上下に重ならないように2枚貼り合わせてプレス平坦化することにより絶縁層3となる絶縁シートを製作し、次に、絶縁シートの所定の位置に炭酸ガスレーザやYAGレーザ等の従来周知の方法を採用して直径が30〜100μmの貫通孔5を穿設する。
【0042】
そして、貫通孔5に従来周知のスクリーン印刷法を採用して、錫を主成分とする金属粉およびトリアジン系樹脂等の熱硬化性樹脂前駆体を含む導電性材料をスクリーン印刷法(圧入)で充填することによって貫通導体6を形成する。その後、別途準備した、表面に銅箔から成る配線導体4を絶縁シート上に所定のパターンに被着形成した、ポリエチレンテレフタレート(PET)樹脂等の耐熱性樹脂から成るる転写シートを絶縁シートに、所定の貫通導体5と配線導体4とが接続するように位置合わせして重ね合わせ、これらを熱プレス機を用いて100〜150℃の温度で数分間プレスすることにより転写シートを絶縁シートに圧接して、配線導体4を絶縁シートに転写埋入し、最後に150〜200℃の温度で数時間加熱することにより製作される。
【0043】
あるいは必要に応じて、転写シートを剥離した絶縁シートを複数枚上下に重ね合わせ、熱プレス機を用いて150〜200℃の温度で数時間加熱プレスすることにより積層配線基板が製作される。
【0044】
かくして、本発明の配線基板によれば、ガラスクロス1の縦糸1aおよび横糸1bに囲まれた隙間7aの開口7bの全面積がガラスクロス1の面積の0.01〜2%であり、かつ開口7bが上下に重ならないように複数枚積層したことから、隙間7aの開口7bに貫通孔5を穿孔する確率が小さくできるとともに上下に連続することがないので、レーザ加工で均一な貫通孔5径が形成でき貫通導体6の抵抗が高くなることがない、また、薄いガラスクロス1を複数枚積層して絶縁層3を形成したので配線基板の剛性が向上し、半導体素子を配線基板に実装する際に薄い配線基板でも、反りや半田バンプの破壊のない接続信頼性に優れた配線基板とすることができる。
【0045】
なお、本発明は上述の実施例に限定されるものではなく、本発明の要旨を逸脱しない範囲であれば種々の変更は可能であり、例えば上述の実施例では本発明の配線基板を4層積層して成る積層配線基板の例を示したが、5層以上の配線基板を積層してもよい。
【0046】
【実施例】
本発明の配線基板の評価するために次に説明する配線基板を製作し、その絶縁層の絶縁抵抗および貫通導体の導通抵抗を評価した。
【0047】
まず、開口7bの全面積がガラスクロスの面積の0.008〜3%であり、厚みが50μmのガラスクロス1にエポキシ樹脂や変性ポリフェニレン樹脂等から成る熱硬化樹脂組成物2を含浸させたプリプレグを、ガラスクロス1の開口7bが上下に重ならないように2枚貼り合わせてプレス平坦化することにより絶縁シートを製作した。
【0048】
次に、絶縁シートの所定の位置に炭酸ガスレーザやYAGレーザ等の従来周知の方法を採用して直径が30〜100μmの貫通孔5を穿設した。そして、貫通孔5に従来周知のスクリーン印刷法を採用して、錫を主成分とする金属粉およびトリアジン系樹脂等の熱硬化性樹脂前駆体を含む導電性材料をスクリーン印刷法(圧入)で充填することによって貫通導体6を形成した。その後、別途準備した、表面に銅箔から成る配線導体4を絶縁シート上に所定のパターンに被着形成した、ポリエチレンテレフタレート(PET)樹脂等の耐熱性樹脂から成る転写シートを絶縁シートに、所定の貫通導体5と配線導体4とが接続するように位置合わせして重ね合わせ、これらを熱プレス機を用いて100〜150℃の温度で数分間プレスすることにより転写シートを絶縁シートに圧接して、配線導体4を絶縁シートに転写埋入した。
【0049】
しかる後、転写シートを絶縁シートから剥離するとともに転写シートを剥離した絶縁シートを複数枚上下に重ね合わせ、熱プレス機を用いて150〜200℃の温度で数時間加熱プレスして配線基板を製作した。絶縁層3の絶縁抵抗値および貫通導体5の導通抵抗値は、4端子測定で測定した。結果を表1に示す。
【0050】
【表1】

Figure 0004070193
【0051】
表1に示すように、ガラスクロス1の開口7bの全面積の比率が0.01%未満の場合(試料No.1)、絶縁層3の絶縁抵抗値が1013Ω未満となり絶縁性が低下することがわかった。また、2%より大きい場合(試料No.6)、均一な径の貫通孔が形成できず、貫通導体5の導通抵抗が10mΩ以上と高くなることがわかった。それに対して、ガラスクロス1の開口7bの全面積の比率を0.01〜2%の場合(試料No.2〜5)、絶縁層3の絶縁抵抗値が1013Ω以上、貫通導体5の導通抵抗が10mΩ未満となり絶縁抵抗性に優れ、導通抵抗が低い配線基板となることがわかった。
【0052】
また、ガラスクロス1を上側の縦糸1aの軸方向と下側の縦糸1aの軸方向とのなす角度が0〜90度となるように積層して、上記と同様にして試料を製作した。次に、配線基板の実装電極11a上に半田バンプを形成し、その半田バンプを介して上面に半導体素子を実装した。実装後の半導体素子と配線基板との剥れの有無を超音波探傷機で測定した。また別途、絶縁層3のみを加熱プレスして絶縁層3の縦糸1aの軸方向とこれと45度をなす方向の弾性率を測定した。その結果を表2に示す。
【0053】
【表2】
Figure 0004070193
【0054】
表2に示すように、上側の縦糸1aの軸方向と下側の縦糸1aの軸方向とのなす角度が15度未満および75度を超えた場合(試料No.7、8、14、15)、絶縁層3の縦糸方向とその45度方向の弾性率の差が20%以上と大きな値となることがわかった。それに対して、上側の縦糸1aの軸方向と下側の縦糸1aの軸方向とのなす角度が15〜75度の場合(試料No.9〜13)、絶縁層3の縦糸方向1aとその45度方向の弾性率の差が10%以下と小さな値となることがわかった。
【0055】
【発明の効果】
本発明によれば、ガラスクロスを複数積層するとともにこの積層したガラスクロスに熱硬化性樹脂を含浸させて成る絶縁層の上下面に配線導体を形成し、絶縁層を挟んで上下に位置する配線導体同士を絶縁層に設けた貫通導体を介して電気的に接続して成ることから、絶縁層の厚みが厚い場合においてもガラスクロスを構成する撚糸の径を大きなものとする必要はなく、その結果、ガラスクロスの隙間の開口の全面積が大きくなることはなく、撚糸の密な部分と疎な部分との疎密差が大きなものとなることはない。
【0056】
また、ガラスクロスの隙間の開口の全面積がガラスクロスの面積の0.01〜2%であり、かつ開口が上下に重ならないように積層されていることから、撚糸の密な部分と疎な部分との疎密差がより小さなものとなり、配線基板にレーザを用いて貫通孔を穿孔する際、均一な内部径や出射径を有する貫通孔を穿孔することができ、貫通孔に導電性材料を充填して貫通導体を形成した場合に、貫通導体の抵抗が部分的に高くなったり、断線してしまうということはない。
【0057】
さらに、絶縁層はガラスクロスを複数積層するとともにこの積層したガラスクロスに熱硬化性樹脂を含浸させたて成ることから、絶縁層が薄い場合でも複数のガラスクロスを積層したほうが絶縁層の剛性の低下を減少させることができ、その結果、大型のLSI等の半導体素子を配線基板に実装した際、半導体素子の動作時に半導体素子と配線基板との熱膨張係数の相違に起因して大きな応力が発生しても、半導体素子が配線基板から剥がれてしまう、あるいは半導体素子が破壊されてしまうことはない。
【0058】
また、本発明によれば、ガラスクロスの縦糸および横糸の軸方向の弾性率と、縦糸および横糸の交点間を結ぶ方向の弾性率との差が大きいが、積層したガラスクロスのうち上下に接するものは、上側の縦糸の軸方向と下側の縦糸の軸方向とのなす角度を15〜75度となるように積層することにより、絶縁層の方向毎の弾性率の差異を小さくすることでき、その結果、配線基板に大型のLSI等の半導体素子を実装した時に発生する応力による配線基板の変形を抑制でき、半導体素子が配線基板から剥がれてしまう、あるいは半導体素子が破壊されてしまうということを有効に防止することができる。
【図面の簡単な説明】
【図1】本発明の配線基板の実施の形態の一例を示す断面図である。
【図2】図1に示すガラスクロスの平面図である。
【符号の説明】
1・・・・・・・ガラスクロス
1a・・・・・縦糸
1b・・・・・横糸
2・・・・・・・熱硬化性樹脂
3・・・・・・・絶縁層
4・・・・・・・配線導体
5・・・・・・・貫通孔
6・・・・・・・貫通導体
7a・・・・・・隙間
7b・・・・・・開口[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a wiring board and an electronic component mounting structure for mounting electronic components such as semiconductor elements and resistors.
[0002]
[Prior art]
Conventionally, as a wiring board used for mounting electronic components such as semiconductor elements and resistors, heat is applied to a glass cloth formed by weaving warps and wefts, which are twisted yarns, so that the angle formed by the two axial directions is a perpendicular direction. There is known a printed circuit board in which a plurality of insulating layers impregnated with a curable resin and wiring conductors made of copper foil are alternately laminated. In such a printed circuit board, the copper foil deposited on the surface of the insulating layer is first etched to form a predetermined pattern of wiring conductor, and then the insulating layer on which the wiring conductor is formed is coated with an adhesive made of a thermosetting resin. A multilayer substrate is manufactured by laminating a plurality of layers sandwiched between them, and then a through hole is formed by drilling through the front and back of the multilayer substrate, and then copper plating is applied to the inner surface of the through hole and It is manufactured by forming through-hole conductors that electrically connect the wiring conductors located.
[0003]
Normally, each insulating layer is formed by impregnating a glass cloth with a thermosetting resin, and by selecting twisted yarns of various diameters, a glass cloth having a desired thickness is obtained and a thermosetting resin is added thereto. By impregnating, a desired thickness is obtained.
[0004]
In recent years, with the increase in density of electronic devices, semiconductor elements have been highly integrated year by year, and the demand for higher density of wiring conductors on wiring boards on which semiconductor elements are mounted is increasing. However, the above-described printed circuit board has a problem that it is difficult to improve the density of the wiring conductor because the printed circuit board has a through-hole structure penetrating the front and back of the multilayer substrate.
[0005]
In order to solve such a problem, instead of the through-hole structure, an inner via-hole structure in which a through hole is formed for each insulating layer and a conductor is filled in the through hole to connect the upper and lower wiring conductors. Has been put to practical use. In such an inner via hole structure, fine processing is required with a diameter of the through hole being 200 μm or less, and drilling of a small diameter of 200 μm or less is difficult with a drill. Therefore, it is common practice to drill a through hole with a laser. .
[0006]
However, the glass cloth that constitutes the insulating layer has a structure in which twisted yarns are woven in the vertical and horizontal directions. When the glass cloth is viewed from the top, the portion where the vertical and horizontal twisted yarns overlap, There are three types of parts, the part where the twisted yarn is present and the part where the twisted yarn is not present, that is, the gap surrounded by the vertical and horizontal twisted yarns, and the total area of the opening of the gap is the area of the glass cloth When a through hole is drilled using a laser in an insulating layer formed by impregnating a thermosetting resin into such a glass cloth, the twisted yarn in which the vertical and horizontal twisted yarns overlap. The inner diameter and exit diameter of the through hole are reduced in the dense part, and the inner diameter and exit diameter of the through hole are increased in the gap part where the twisted yarn does not exist, and the through hole having a uniform inner diameter and exit diameter cannot be drilled. There was a problem.
[0007]
In order to solve such problems, when manufacturing a substrate by laminating a plurality of insulating layers, the insulating layers are formed so that the texture positions of the glass cloth included in each of the insulating layers positioned above and below are different from each other. Lamination is proposed (see Patent Document 1).
[0008]
[Patent Document 1]
JP 2002-76548 A
[0009]
[Problems to be solved by the invention]
However, in the conventional glass cloth, since the total area of the opening of the gap is 5 to 12% of the area of the glass cloth and the ratio of the total area of the opening is large, the glass cloth included in each insulating layer located above and below Even if they are laminated so that the weaving positions are different from each other, there are still dense and sparse portions of the twisted yarn, and when the through hole is drilled using a laser on the substrate, it has a uniform inner diameter and emission diameter It is difficult to drill a through hole, and when a through conductor is formed by filling the through hole with a conductive material, there is a problem that the resistance of the through conductor is partially increased or disconnected. It was.
[0010]
In addition, since each insulating layer is formed by impregnating a glass cloth with a thermosetting resin, when the insulating layer is thick, the diameter of the twisted yarn constituting the glass cloth is large, and the total area of the opening is There is also a problem that the density difference between the dense part and the sparse part of the twisted yarn becomes larger as the size becomes larger. Furthermore, when the insulating layer is thin, the rigidity of the single glass cloth is reduced, and when a semiconductor element such as a large LSI is mounted on the wiring board, the semiconductor element and the wiring board are Due to the difference in thermal expansion coefficient, a large stress is generated, and the semiconductor element is peeled off from the wiring board due to the stress, or the semiconductor element is destroyed.
[0011]
The present invention has been completed in view of the problems of the prior art, and an object of the present invention is to form a through-hole having a uniform diameter by laser processing in a high-density wiring board having fine through-conductors. The present invention provides a wiring board that is excellent in electrical connection reliability and that can satisfactorily mount a semiconductor element.
[0012]
[Means for Solving the Problems]
A wiring board according to the present invention is formed by laminating a plurality of glass cloths made of warps and wefts, and forming wiring conductors on upper and lower surfaces of an insulating layer formed by impregnating the laminated glass cloth with a thermosetting resin. Wiring conductors that are positioned above and below are electrically connected through a through conductor provided in an insulating layer, and the glass cloth has the entire area of the opening of the gap surrounded by the warp and weft as the glass cloth. The laminated glass cloth is 0.01 to 2% of the area so that the openings do not overlap vertically, and the glass cloths that are in contact with the top and bottom are the axial direction of the upper warp and the axial direction of the lower warp And the wiring conductor is embedded in the surface of the insulating layer. The wiring conductor is embedded in the surface of the insulating layer.
The electronic component mounting structure of the present invention is characterized in that an electronic component is bonded to the wiring conductor of the wiring board of the present invention via a solder bump.
[0013]
According to the present invention, a plurality of glass cloths are laminated, and wiring conductors are formed on the upper and lower surfaces of an insulating layer formed by impregnating the laminated glass cloth with a thermosetting resin, and wirings positioned above and below the insulating layer. Since the conductors are electrically connected through a through conductor provided in the insulating layer, it is not necessary to increase the diameter of the twisted yarn constituting the glass cloth even when the insulating layer is thick. As a result, the entire area of the opening of the gap of the glass cloth does not increase, and the density difference between the dense part and the sparse part of the twisted yarn does not become large.
[0014]
Moreover, since the glass cloth is laminated so that the entire area of the opening of the gap is 0.01 to 2% of the area of the glass cloth and the openings do not overlap vertically, it is sparse with the dense part of the twisted yarn. When the through hole is drilled in the wiring board using a laser, the through hole having a uniform internal diameter and emission diameter can be drilled, and a conductive material is used for the through hole. When the through conductor is formed by filling, the resistance of the through conductor does not partially increase or break.
[0015]
Furthermore, since the insulating layer is made by laminating a plurality of glass cloths, and the laminated glass cloth is impregnated with a thermosetting resin, the rigidity of the insulating layer is lowered by laminating a plurality of glass cloths even when the insulating layer is thin. As a result, when a semiconductor element such as a large LSI is mounted on a wiring board, a large stress occurs due to the difference in thermal expansion coefficient between the semiconductor element and the wiring board during the operation of the semiconductor element. However, the semiconductor element is not peeled off from the wiring board or the semiconductor element is not destroyed.
[0017]
In addition, according to the present invention, there is a large difference between the elastic modulus in the axial direction of the warp and weft yarns of the glass cloth and the elastic modulus in the direction connecting the intersections of the warp and weft yarns. By stacking so that the angle between the axial direction of the upper warp and the axial direction of the lower warp is 15 to 75 degrees, the difference in elastic modulus for each direction of the insulating layer can be reduced. As a result, it is possible to suppress deformation of the wiring board due to stress generated when a semiconductor element such as a large LSI is mounted on the wiring board, and the semiconductor element is peeled off from the wiring board or the semiconductor element is destroyed. Can be prevented more effectively.
[0018]
DETAILED DESCRIPTION OF THE INVENTION
Next, the wiring board of the present invention will be described in detail with reference to the accompanying drawings.
1 is a cross-sectional view showing an example of an embodiment of a wiring board according to the present invention, and FIG. 2 is a plan view of a glass cloth constituting the wiring board shown in FIG. 1, with an upper glass cloth and a lower glass cloth. The outline of the lower glass cloth is shown by a solid line so that the positional relationship with In these drawings, 1 is a glass cloth, 2 is a thermosetting resin, 3 is an insulating layer, 4 is a wiring conductor, 5 is a through hole, 6 is a through conductor, 7a is a gap, and 7b is an opening.
[0019]
In the wiring board of the present invention, a plurality of glass cloths 1 formed by weaving warp yarns 1a and weft yarns 1b so that their axial directions are substantially vertical are laminated, and the laminated glass cloths 1 are impregnated with a thermosetting resin 2. The wiring conductors 4 are formed on the upper and lower surfaces of the insulating layer 3, and the wiring conductors 4 positioned above and below the insulating layer 3 are electrically connected to each other through a through conductor 6 provided in the insulating layer 3. FIG. 1 shows an example of a laminated wiring board in which four such wiring boards are laminated.
[0020]
The insulating layer 3 has a thickness of 50 to 150 μm, has a function of supporting the wiring conductor 4 and maintaining insulation between the wiring conductors 4 positioned above and below, and an epoxy resin or screw on a plurality of glass cloths 1. It is formed by impregnating a thermosetting resin 2 such as maleimide triazine resin or modified polyphenylene ether resin. If the thickness of the insulating layer 3 is less than 50 μm, the rigidity of the wiring board tends to decrease and the wiring board tends to bend easily. If the thickness exceeds 150 μm, the thickness of the insulating layer 3 becomes unnecessarily thick and the wiring board There is a tendency that weight reduction becomes difficult. Therefore, the insulating layer 3 preferably has a thickness of 50 to 150 μm.
[0021]
The glass cloth 1 may be of a plain weave, twill weave, satin weave, or the like depending on the weaving method, and FIG. 2 shows a plan view of a plain weave in which warp and weft yarns 1a and 1b intersect each other vertically. Yes. The glass cloth 1 has a thickness of 10 to 50 μm, and if the thickness is less than 10 μm, the warp 1a and the weft 1b become very thin and difficult to weave uniformly, so that the insulating layer 3 tends to warp after curing. If it is thicker than 50 μm, the insulating layer 3 becomes unnecessarily thick and it tends to be difficult to reduce the weight of the wiring board. Accordingly, the thickness of the glass cloth 1 is preferably 10 to 50 μm.
[0022]
In the wiring board of the present invention, a plurality of glass cloths 1 are laminated, and wiring conductors 4 are formed on the upper and lower surfaces of an insulating layer 3 formed by impregnating the laminated glass cloth 1 with a thermosetting resin 2. Is formed by electrically connecting the wiring conductors 4 positioned above and below via a through conductor 6 provided in the insulating layer 3, and the glass cloth 1 has an opening 7b of a gap 7a surrounded by the warp 1a and the weft. The total area of the glass cloth 1 is 0.01 to 2% of the area of the glass cloth 1, and the openings 7b are laminated so as not to overlap each other. In the present invention, the entire area of the opening 7b of the gap 7a of the glass cloth 1 is 0.01 to 2% of the area of the glass cloth 1, and the openings 7b are stacked so as not to overlap each other. is important.
[0023]
According to the wiring board of the present invention, a plurality of glass cloths 1 are laminated, and wiring conductors 4 are formed on the upper and lower surfaces of an insulating layer 3 formed by impregnating the laminated glass cloth 1 with a thermosetting resin 2. Since the wiring conductors 4 positioned above and below the 3 are electrically connected via the through conductors 6 provided in the insulating layer 1, the glass cloth 1 is configured even when the insulating layer 3 is thick. It is not necessary to increase the diameter of the warp yarn 1a and the weft yarn 1b of the twisted yarn, and as a result, the entire area of the opening 7b of the gap 7a of the glass cloth 1 does not increase, and the dense portion and the sparse portion of the twisted yarn There is no big difference in density.
[0024]
In addition, since the entire area of the opening 7b of the gap 7a of the glass cloth 1 is 0.01 to 2% of the area of the glass cloth 1, and the openings 7b are laminated so as not to overlap vertically, a dense portion of the twisted yarn When the through hole 5 is drilled in the wiring board using a laser, the through hole 5 having a uniform internal diameter and emission diameter can be drilled. When the through conductor 6 is formed by filling 5 with a conductive material, the resistance of the through conductor 6 is not partially increased or disconnected.
[0025]
Furthermore, since the insulating layer 3 is formed by laminating a plurality of glass cloths 1 and impregnating the laminated glass cloth 1 with a thermosetting resin 2, a plurality of glass cloths 1 are laminated even when the insulating layer 3 is thin. As a result, a decrease in rigidity of the insulating layer 3 can be reduced. As a result, when a semiconductor element (not shown) such as a large LSI is mounted on the wiring board, the semiconductor element and the wiring board are not operated during the operation of the semiconductor element. Even if a large stress is generated due to the difference in thermal expansion coefficient, the semiconductor element is not peeled off from the wiring board or the semiconductor element is not destroyed.
[0026]
If the total area of the opening 7b of the gap 7a in the glass cloth 1 is smaller than 0.01% of the area of the glass cloth 1, the glass cloth 1 cannot be satisfactorily impregnated with the thermosetting resin 2, and the insulating property of the insulating layer 3 is lowered. If it exceeds 2%, the probability of drilling the through hole 5 in the gap 7a increases, and the through hole 5 having a uniform diameter tends to be unable to be drilled. Therefore, it is important that the total area of the opening 7 b of the gap 7 a of the glass cloth 1 is 0.01 to 2% of the area of the glass cloth 1.
[0027]
The total area of the opening 7b is such that the glass cloth 1 is flattened by high pressure water flow treatment or pressure treatment with a roll, so that the total area of the opening 7b of the gap 7a in the glass cloth 1 is equal to the area of the glass cloth 1. It is prepared to be 0.01 to 2%.
[0028]
The surface of the glass cloth 1 is subjected to a silane coupling treatment in order to improve the adhesion with the thermosetting resin 2. These glass cloths 1 are usually made of glass called E glass, but D glass, S glass, high dielectric constant glass, or the like may be used.
[0029]
In the wiring board of the present invention, the glass cloth 1 is preferably laminated so that the angle formed by the upper warp axial direction and the lower warp axial direction is 15 to 75 degrees.
[0030]
According to the wiring board of the present invention, there is a large difference between the elastic modulus in the axial direction of the warp 1a and the weft 1b of the glass cloth 1 and the elastic modulus in the direction connecting the intersections of the warp 1a and the weft 1b. Is laminated so that the angle formed by the axial direction of the upper warp 1a and the axial direction of the lower warp 1a is 15 to 75 degrees, so that the difference in elastic modulus in the direction of the insulating layer 3 is reduced. As a result, deformation of the wiring board due to stress generated when a semiconductor element such as a large LSI is mounted on the wiring board can be suppressed, and the semiconductor element is peeled off from the wiring board or the semiconductor element is destroyed. This can be effectively prevented.
[0031]
If the angle between the axial direction of the upper warp 1a and the axial direction of the lower warp 1a is less than 15 degrees or more than 75 degrees, the axial direction of the warp 1a and the weft 1b of the glass cloth 1 and its diagonal direction The difference in elastic modulus becomes large, and the wiring board is deformed by the stress generated when a semiconductor element such as a large LSI is mounted on the wiring board, and the semiconductor element is peeled off from the wiring board, or the semiconductor element is destroyed. There is a tendency that the risk of becoming large. Therefore, it is preferable that the angle formed by the axial direction of the upper warp and the axial direction of the lower warp is in the range of 15 to 75 degrees.
[0032]
Moreover, as the thermosetting resin 2 which comprises the insulating layer 3, thermosetting resins 2, such as an epoxy resin hardened | cured at the temperature of 150-200 degreeC, bismaleimide triazine resin, and modified polyphenylene ether resin, are used. In order to satisfactorily impregnate the glass cloth 1 with the thermosetting resin 2, a surfactant or an inorganic filler may be added.
[0033]
Further, a wiring conductor 4 is embedded in the surface of the insulating layer 3. The wiring conductor 4 has a function as a part of a conductive path for electrically connecting each electrode of an electronic component such as a semiconductor element mounted on the wiring board to an external electric circuit board (not shown). It is 20 to 200 μm, has a thickness of 5 to 50 μm, and is made of a metal foil such as copper, aluminum, nickel, silver, or gold, and is preferably made of a copper foil from the viewpoint of workability and low cost. If the width of the wiring conductor 4 is less than 20 μm, the wiring conductor 4 tends to be deformed or disconnected, and if it exceeds 200 μm, high-density wiring tends to be unable to be formed. Further, when the thickness of the wiring conductor 4 is less than 5 μm, the strength of the wiring conductor 4 tends to be reduced and deformation or disconnection tends to occur, and when it exceeds 50 μm, embedding in the insulating layer 3 tends to be difficult. . Therefore, it is preferable that the wiring conductor 4 has a width of 20 to 200 μm and a thickness of 5 to 50 μm.
[0034]
The insulating layer 3 is provided with a plurality of through conductors 6 from the upper surface to the lower surface. The through conductor 6 has a function of electrically connecting the wiring conductors 2 positioned above and below the insulating layer 1 and has a diameter of 30 to 100 μm. The through hole 5 provided in the insulating layer 3 is mainly made of tin. It is formed by embedding and thermosetting a conductive material composed of a metal powder as a component and a triazine-based thermosetting resin. When the diameter of the through conductor 5 is less than 30 μm, the processing tends to be difficult, and when it exceeds 100 μm, there is a tendency that high-density wiring cannot be formed. Therefore, the through conductor 4 preferably has a diameter of 30 to 100 μm.
[0035]
In the wiring board of the present invention, the entire area of the opening 7b of the gap 7a of the glass cloth 1 is 0.01 to 2% of the area of the glass cloth 1, and the openings 7b are stacked so as not to overlap each other. Therefore, the through-hole 5 having a uniform diameter can be formed in the range of 30 to 100 μm in diameter.
[0036]
The content of the metal powder 5 of the conductive material is preferably 80 to 95% by weight. If the content of the metal powder 5 is less than 80% by weight, the triazine-based thermosetting resin tends to prevent the metal powders 5 from being connected to each other, and the conduction resistance tends to increase. There is a tendency that the viscosity of the resin is too high to be embedded well. Therefore, the content of the metal powder of the conductive material is preferably 80 to 95% by weight.
[0037]
Further, a part of the wiring conductor 4 formed on the surface of one outermost layer of the insulating layer 3 is connected to each electrode of the electronic component (not shown) via a solder bump (not shown). A part of the wiring conductor 2 formed on the surface of the other outermost layer of the insulating layer 3 is formed on each electrode of an external electric circuit board (not shown). The mounting electrode 11b for external connection that is connected via a) is formed.
[0038]
It should be noted that the surface of the mounting electrodes 11a and 11b has good wettability with solder and excellent corrosion resistance in order to prevent oxidative corrosion and to make good connection with solder bumps (not shown). A plating layer such as nickel-gold is applied.
[0039]
In addition, the outermost insulating layer 3 and the mounting electrodes 11a and 11b are covered with a solder-resistant resin layer 12 having an opening for exposing the central portions of the mounting electrodes 11a and 11b as necessary. The solder-resistant resin layer 12 has a thickness of 10 to 50 μm. For example, 30 to 70% by weight of an inorganic powder filler such as silica or talc in a mixture of a photosensitive resin such as an acrylic-modified epoxy resin and a photoinitiator. And the adjacent mounting electrodes 11a and 11b are prevented from being electrically short-circuited by solder bumps (not shown), and the mounting electrodes 11a and 11b and the insulating layer 3 are It has a function of improving the bonding strength.
[0040]
Such a solder-resistant resin layer 12 is formed by depositing an uncured resin film composed of a photosensitive resin, a photoinitiator, and an inorganic powder filler on the surface of the outermost insulating layer 3, or a thermosetting resin and an inorganic powder. An uncured resin varnish composed of a filler is applied to the surface of the outermost insulating layer 3 and dried. After that, an opening is formed by exposure and development, and this is UV cured and thermally cured.
[0041]
The wiring board is manufactured by the method described below. First, for example, two prepregs in which a glass cloth 1 having a thickness of 50 μm is impregnated with a thermosetting resin 2 precursor made of an epoxy resin or a modified polyphenylene resin are attached so that the openings 7b of the glass cloth 1 do not overlap vertically. Then, an insulating sheet to be the insulating layer 3 is manufactured by pressing and flattening. Next, a conventionally known method such as a carbon dioxide laser or a YAG laser is adopted at a predetermined position of the insulating sheet, and the diameter is 30 to 100 μm. A through hole 5 is formed.
[0042]
Then, a conventionally well-known screen printing method is adopted for the through-hole 5, and a conductive material including a metal powder mainly composed of tin and a thermosetting resin precursor such as a triazine resin is screen-printed (press-fit). The through conductor 6 is formed by filling. Thereafter, separately prepared transfer sheet made of a heat-resistant resin such as polyethylene terephthalate (PET) resin, which is prepared by depositing the wiring conductor 4 made of copper foil on the surface in a predetermined pattern, is formed on the insulating sheet. The predetermined through conductor 5 and the wiring conductor 4 are aligned and overlapped so as to be connected, and these are pressed at a temperature of 100 to 150 ° C. for several minutes using a hot press machine, so that the transfer sheet is pressed against the insulating sheet. Then, the wiring conductor 4 is transferred and embedded in an insulating sheet and finally heated at a temperature of 150 to 200 ° C. for several hours.
[0043]
Alternatively, if necessary, a laminated wiring board is manufactured by stacking a plurality of insulating sheets from which the transfer sheet has been peeled up and down and heat-pressing them at a temperature of 150 to 200 ° C. for several hours using a hot press.
[0044]
Thus, according to the wiring board of the present invention, the total area of the opening 7b of the gap 7a surrounded by the warp 1a and the weft 1b of the glass cloth 1 is 0.01-2% of the area of the glass cloth 1, and the opening 7b is Since a plurality of layers are stacked so as not to overlap each other, the probability of drilling the through-hole 5 in the opening 7b of the gap 7a can be reduced and it does not continue vertically, so a uniform through-hole 5 diameter is formed by laser processing. In addition, the resistance of the through conductor 6 is not increased, and the insulating layer 3 is formed by laminating a plurality of thin glass cloths 1, so that the rigidity of the wiring board is improved and the semiconductor element is mounted on the wiring board. Even a thin wiring board can be a wiring board having excellent connection reliability without warping or destruction of solder bumps.
[0045]
It should be noted that the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the present invention. For example, in the above-described embodiments, the wiring board of the present invention has four layers. Although an example of a laminated wiring board formed by laminating is shown, five or more wiring boards may be laminated.
[0046]
【Example】
In order to evaluate the wiring board of the present invention, a wiring board described below was manufactured, and the insulation resistance of the insulating layer and the conduction resistance of the through conductor were evaluated.
[0047]
First, a prepreg in which the entire area of the opening 7b is 0.008 to 3% of the area of the glass cloth and the glass cloth 1 having a thickness of 50 μm is impregnated with the thermosetting resin composition 2 made of an epoxy resin, a modified polyphenylene resin or the like, Two sheets were laminated and press-flattened so that the openings 7b of the glass cloth 1 did not overlap vertically, thereby producing an insulating sheet.
[0048]
Next, a through hole 5 having a diameter of 30 to 100 μm was formed at a predetermined position of the insulating sheet by employing a conventionally known method such as a carbon dioxide laser or a YAG laser. Then, a conventionally well-known screen printing method is adopted for the through-hole 5, and a conductive material including a metal powder mainly composed of tin and a thermosetting resin precursor such as a triazine resin is screen-printed (press-fit). The through conductor 6 was formed by filling. Thereafter, a separately prepared transfer sheet made of a heat-resistant resin such as polyethylene terephthalate (PET) resin, which is prepared by depositing a wiring conductor 4 made of copper foil on the surface in a predetermined pattern, is formed on the insulating sheet. The through conductors 5 and the wiring conductors 4 are aligned and overlapped so as to be connected, and these are pressed for several minutes at a temperature of 100 to 150 ° C. using a hot press machine, so that the transfer sheet is pressed against the insulating sheet. Then, the wiring conductor 4 was transferred and embedded in the insulating sheet.
[0049]
After that, the transfer sheet is peeled off from the insulating sheet and a plurality of insulating sheets from which the transfer sheet has been peeled are stacked one on top of the other, and then heated and pressed at a temperature of 150 to 200 ° C. for several hours using a hot press machine to produce a wiring board. did. The insulation resistance value of the insulating layer 3 and the conduction resistance value of the through conductor 5 were measured by 4-terminal measurement. The results are shown in Table 1.
[0050]
[Table 1]
Figure 0004070193
[0051]
As shown in Table 1, when the ratio of the total area of the openings 7b of the glass cloth 1 is less than 0.01% (sample No. 1), the insulation resistance value of the insulating layer 3 is 10 13 It was found that the insulation was reduced because it was less than Ω. Moreover, when larger than 2% (sample No. 6), it was found that a through hole having a uniform diameter could not be formed, and the conduction resistance of the through conductor 5 was as high as 10 mΩ or more. On the other hand, when the ratio of the total area of the opening 7b of the glass cloth 1 is 0.01 to 2% (sample Nos. 2 to 5), the insulation resistance value of the insulating layer 3 is 10 13 It has been found that the conductive resistance of the through conductor 5 is less than 10 mΩ with a resistance of Ω or more, which is excellent in insulation resistance and has a low conductive resistance.
[0052]
Further, the glass cloth 1 was laminated so that the angle formed by the axial direction of the upper warp 1a and the axial direction of the lower warp 1a was 0 to 90 degrees, and a sample was manufactured in the same manner as described above. Next, a solder bump was formed on the mounting electrode 11a of the wiring board, and a semiconductor element was mounted on the upper surface via the solder bump. The presence or absence of peeling between the semiconductor element after mounting and the wiring board was measured with an ultrasonic flaw detector. Separately, only the insulating layer 3 was heated and pressed, and the elastic modulus in the axial direction of the warp 1a of the insulating layer 3 and the direction forming 45 degrees with this was measured. The results are shown in Table 2.
[0053]
[Table 2]
Figure 0004070193
[0054]
As shown in Table 2, when the angle between the axial direction of the upper warp 1a and the axial direction of the lower warp 1a is less than 15 degrees and exceeds 75 degrees (Sample Nos. 7, 8, 14, 15) It was found that the difference in elastic modulus between the warp direction of the insulating layer 3 and its 45 degree direction was as large as 20% or more. On the other hand, when the angle between the axial direction of the upper warp 1a and the axial direction of the lower warp 1a is 15 to 75 degrees (sample No. 9 to 13), the warp direction 1a of the insulating layer 3 and its 45 It was found that the difference in the elastic modulus in the direction of the degree was as small as 10% or less.
[0055]
【The invention's effect】
According to the present invention, a plurality of glass cloths are laminated, and wiring conductors are formed on the upper and lower surfaces of an insulating layer formed by impregnating the laminated glass cloth with a thermosetting resin, and wirings positioned above and below the insulating layer. Since the conductors are electrically connected through a through conductor provided in the insulating layer, it is not necessary to increase the diameter of the twisted yarn constituting the glass cloth even when the insulating layer is thick. As a result, the entire area of the opening of the gap of the glass cloth does not increase, and the density difference between the dense part and the sparse part of the twisted yarn does not become large.
[0056]
Moreover, since the total area of the opening of the gap of the glass cloth is 0.01 to 2% of the area of the glass cloth and the openings are laminated so that they do not overlap vertically, When the through hole is drilled using a laser in the wiring board, the through hole having a uniform internal diameter and emission diameter can be drilled, and the through hole is filled with a conductive material. Thus, when the through conductor is formed, the resistance of the through conductor is not partially increased or disconnected.
[0057]
Furthermore, since the insulating layer is formed by laminating a plurality of glass cloths and impregnating the laminated glass cloths with a thermosetting resin, even if the insulating layers are thin, it is better to laminate the plurality of glass cloths. As a result, when a semiconductor element such as a large LSI is mounted on a wiring board, a large stress is caused due to the difference in thermal expansion coefficient between the semiconductor element and the wiring board during operation of the semiconductor element. Even if it occurs, the semiconductor element is not peeled off from the wiring board or the semiconductor element is not destroyed.
[0058]
In addition, according to the present invention, there is a large difference between the elastic modulus in the axial direction of the warp and weft yarns of the glass cloth and the elastic modulus in the direction connecting the intersections of the warp and weft yarns. By stacking so that the angle between the axial direction of the upper warp and the axial direction of the lower warp is 15 to 75 degrees, the difference in elastic modulus for each direction of the insulating layer can be reduced. As a result, it is possible to suppress deformation of the wiring board due to stress generated when a semiconductor element such as a large LSI is mounted on the wiring board, and the semiconductor element is peeled off from the wiring board or the semiconductor element is destroyed. Can be effectively prevented.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing an example of an embodiment of a wiring board according to the present invention.
FIG. 2 is a plan view of the glass cloth shown in FIG.
[Explanation of symbols]
1 .... glass cloth
1a ... warp
1b ... Weft
2 .... Thermosetting resin
3. Insulating layer
4 .... Wiring conductor
5 .... Through hole
6 .... Penetration conductor
7a ... ・ Gap
7b ... Open

Claims (2)

縦糸および横糸を織って成るガラスクロスを複数積層するとともに該積層したガラスクロスに熱硬化性樹脂を含浸させて成る絶縁層の上下面に配線導体を形成し、前記絶縁層を挟んで上下に位置する前記配線導体同士を前記絶縁層に設けた貫通導体を介して電気的に接続して成り、
前記ガラスクロスは、前記縦糸および横糸に囲まれた隙間の開口の全面積が前記ガラスクロスの面積の0.01〜2%であり、かつ前記開口が上下に重ならないように積層され
前記積層したガラスクロスのうち上下に接するものは、上側の前記縦糸の軸方向と下側の前記縦糸の軸方向とのなす角度が15〜75度となるように積層されており、
前記配線導体は前記絶縁層の表面に埋入されていることを特徴とする配線基板。
A plurality of glass cloths made of warp and weft yarns are laminated and wiring conductors are formed on the upper and lower surfaces of an insulating layer formed by impregnating the laminated glass cloth with a thermosetting resin, and are positioned above and below the insulating layer The wiring conductors are electrically connected via through conductors provided in the insulating layer,
The glass cloth is laminated so that the entire area of the opening of the gap surrounded by the warp and weft is 0.01 to 2% of the area of the glass cloth, and the opening does not overlap vertically ,
Among the laminated glass cloths, those that are in contact with the top and bottom are laminated so that the angle formed by the axial direction of the upper warp and the axial direction of the lower warp is 15 to 75 degrees,
The wiring board, wherein the wiring conductor is embedded in a surface of the insulating layer .
請求項1記載の配線基板の前記配線導体に半田バンプを介して電子部品が接合されてなることを特徴とする電子部品実装構造体。  An electronic component mounting structure, wherein an electronic component is bonded to the wiring conductor of the wiring board according to claim 1 via a solder bump.
JP2002312875A 2002-10-01 2002-10-28 Wiring board and electronic component mounting structure Expired - Fee Related JP4070193B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2002312875A JP4070193B2 (en) 2002-10-01 2002-10-28 Wiring board and electronic component mounting structure

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2002288647 2002-10-01
JP2002312875A JP4070193B2 (en) 2002-10-01 2002-10-28 Wiring board and electronic component mounting structure

Publications (2)

Publication Number Publication Date
JP2004179171A JP2004179171A (en) 2004-06-24
JP4070193B2 true JP4070193B2 (en) 2008-04-02

Family

ID=32715610

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002312875A Expired - Fee Related JP4070193B2 (en) 2002-10-01 2002-10-28 Wiring board and electronic component mounting structure

Country Status (1)

Country Link
JP (1) JP4070193B2 (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007114392A1 (en) 2006-03-30 2007-10-11 Kyocera Corporation Wiring board and mounting structure
JP4953875B2 (en) * 2006-03-30 2012-06-13 京セラ株式会社 Wiring board and mounting structure
JP5200565B2 (en) * 2007-04-09 2013-06-05 日立化成株式会社 Printed wiring board and electronic device
WO2008126640A1 (en) * 2007-04-09 2008-10-23 Hitachi Chemical Company, Ltd. Printed wiring board and electronic device
JP2009205669A (en) * 2008-01-31 2009-09-10 Semiconductor Energy Lab Co Ltd Semiconductor device
JP5444136B2 (en) * 2010-06-18 2014-03-19 新光電気工業株式会社 Wiring board

Also Published As

Publication number Publication date
JP2004179171A (en) 2004-06-24

Similar Documents

Publication Publication Date Title
US5888627A (en) Printed circuit board and method for the manufacture of same
JP4119205B2 (en) Multilayer wiring board
JP2587596B2 (en) Circuit board connecting material and method for manufacturing multilayer circuit board using the same
WO2004064467A1 (en) Multilayer wiring board, method for producing the same, and method for producing fiber reinforced resin board
CN104869753A (en) Printed Circuit Board And Method Of Manufacturing The Same
JP2015122545A (en) Multilayer wiring board and manufacturing method of the same
CN100558222C (en) Multiwiring board and manufacture method thereof
JP5170253B2 (en) Wiring board and method of manufacturing wiring board
JP4070193B2 (en) Wiring board and electronic component mounting structure
JP2004152904A (en) Electrolytic copper foil, film and multilayer wiring substrate therewith, and method of manufacturing the same
JP2009054930A (en) Multi-layer printed wiring board having built-in parts and method of manufacturing the same
US20120012553A1 (en) Method of forming fibrous laminate chip carrier structures
JP4917271B2 (en) Wiring board manufacturing method
JP2004179545A (en) Wiring board
JP4587576B2 (en) Multilayer wiring board
JP3440174B2 (en) Multilayer printed wiring board and method of manufacturing the same
JP2003318550A (en) Laminated wiring board and multilayer wiring assembly, and method for manufacturing the same
JP3230727B2 (en) Multilayer printed wiring board and method of manufacturing the same
JP3695844B2 (en) Manufacturing method of multilayer printed wiring board
JP3588888B2 (en) Method for manufacturing multilayer printed wiring board
JP2001127389A (en) Circuit board, insulation material therefor, and method for manufacturing the same
JP2009141301A (en) Printed wiring board with built-in resistive element
JP4632514B2 (en) Wiring board and manufacturing method thereof
JP5134713B2 (en) Wiring board
JP2004200501A (en) Wiring board

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20050413

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20070605

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20070806

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20071218

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20080111

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110125

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110125

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120125

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120125

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130125

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140125

Year of fee payment: 6

LAPS Cancellation because of no payment of annual fees