JP5423390B2 - Group III nitride compound semiconductor device and method for manufacturing the same - Google Patents

Description

  The present invention relates to insulating protection in a semiconductor device manufactured by forming a group III nitride compound semiconductor layer on a growth substrate and then bonding the uppermost layer to a conductive support substrate and removing the growth substrate. The present invention relates to a semiconductor element having improved film adhesion and a method for manufacturing the same.

  Conventionally, a manufacturing method is known in which after a group III nitride compound semiconductor layer is epitaxially grown on a growth substrate, the final growth layer of the epitaxial growth layer is bonded to a conductive support substrate and the growth substrate is removed. . A sapphire substrate or the like is used as the growth substrate. As the support substrate, a metal such as copper, a conductive silicon substrate, or the like is used. As a method of removing the growth substrate from the epitaxial growth layer, a laser lift-off method, a method of providing a sacrificial layer capable of wet etching between the growth substrate and the epitaxial growth layer, etching the sacrificial layer, and peeling the growth substrate, There is a method of removing the growth substrate itself by etching.

  The technologies disclosed in the following Patent Documents 1, 2, and 3 are semiconductor device manufacturing methods in which an epitaxial growth layer grown on the growth substrate is bonded to a support substrate with a metal layer, and the growth substrate is removed. In these manufacturing methods, after the epitaxial growth layer is bonded to the support substrate with the metal layer, the growth substrate is removed, and a groove for element isolation is formed from the uppermost layer of the epitaxial growth layer on the support substrate. After the trench is formed, an insulating protective film is formed to protect the periphery of the surface of the uppermost layer of the epitaxial growth layer and the side surface of the epitaxial growth layer exposed as the sidewall of the trench.

Special table 2007-536725 JP2009-65182A Special table 2005-522873

  In the technique of the above-mentioned patent document 1, with the support substrate facing down and the epitaxial growth layer facing up, the upper surface of the epitaxial growth layer is made of Ni / Au that is the uppermost layer of a metal layer made of a plurality of metal layers. Etching is performed until the p-type contact metal is exposed, and an isolation trench is formed. Then, an insulating protective film is formed on the side surface of the epitaxial growth layer exposed on the side surface of the groove and the surface of the p-type contact metal exposed on the bottom surface of the groove. In the technique of Patent Document 2, a contact layer (the uppermost layer of a plurality of metal layers) formed of an epitaxially grown layer and aluminum underneath it is etched and a metal made of gold or silver underneath is etched. The reflective layer is exposed to form an isolation trench, and an insulating protective film such as silicon dioxide is formed on the upper surface of the metal reflective layer and the side surface of the epitaxial growth layer. In the technique of Patent Document 3, the p-contact layer existing between the epitaxial growth layer and a metal support layer made of titanium nitride or the like corresponding to the support substrate and the epitaxial growth layer are etched to form an element isolation groove. An inactive layer corresponding to the insulating protective film is formed on the exposed upper surface of the metal support layer and the side surface of the epitaxial growth layer.

  In any of the above prior arts, the insulating protective film is bonded to the side surface of the epitaxial growth layer that forms the sidewall of the inter-element isolation trench and the metal layer exposed on the bottom surface of the inter-element isolation trench. However, there is a problem that the adhesion between the metal layer and the insulating protective film is poor, the insulating protective film peels off, and the semiconductor element cannot be properly protected.

  The present invention has been made in order to solve the above-described problems, and an object of the present invention is to provide a semiconductor device in which an epitaxial growth layer is bonded to a support substrate with a metal layer, and the growth substrate is removed. The reliability of the element is improved by improving the adhesion of the insulating protective film to be protected to the element.

According to the present invention, an epitaxial growth layer composed of a group III nitride compound semiconductor layer is grown on a crystal growth substrate, and a p-type group III nitride compound semiconductor layer which is the final growth layer of the epitaxial growth layer The final growth layer made of is bonded to the support substrate by the metal layer, the crystal growth substrate is removed, and the base layer made of the n-type group III nitride compound semiconductor layer, which is the initial growth layer of the epitaxial growth layer, is supported on the support substrate In the method for manufacturing a semiconductor device as the uppermost layer of the epitaxial growth layer, in the metal layer forming step, a first layer made of a metal having nitrogen reactivity is formed from the side of the final growth layer, and the first layer is formed on the first layer. Forming a second layer made of a metal having resistance to chlorine plasma etching and capable of being wet-etched, and having nitrogen reactivity on the second layer. Then, a third layer made of a metal having resistance is formed, a fourth layer made of a laminated structure of a plurality of metals is formed on the third layer, and the second layer from the base layer of the semiconductor element is used as an etching stopper layer. Etching with chlorine plasma so that the surface of the second layer is exposed on the bottom surface to form an element isolation groove, and removing the second layer exposed on the bottom surface of the element isolation groove by wet etching to form a third layer Is exposed to the bottom surface of the element isolation trench, and at least the side surface of the epitaxial growth layer facing the element isolation trench and the surface of the third layer located at the bottom surface of the element isolation trench are covered with an insulating protective film, The third layer is made of titanium (Ti), tantalum (Ta), vanadium (V), zirconium (Zr), tungsten (W), molybdenum (Mo), niobium (Nb), chromium (Cr), or a metal thereof. No Single layer composed of two or more alloys, the, or consists multilayered, insulating protective film, III group, wherein silicon dioxide, silicon nitride, titanium oxide, that comprises at least one of titanium nitride This is a method for manufacturing a nitride-based compound semiconductor device.

Further, the device invention has a p-type group III nitride compound which has an epitaxially grown layer composed of a group III nitride compound semiconductor layer crystallized on a crystal growth substrate and is the final grown layer of the epitaxially grown layer. A final growth layer made of a semiconductor layer is bonded to a conductive support substrate by a metal layer, and the crystal growth substrate is removed to form an n-type group III nitride compound semiconductor layer that is an initial growth layer of the epitaxial growth layer. In the semiconductor device in which the base layer is the uppermost layer of the epitaxial growth layer on the support substrate, the metal layer has a first layer made of a metal having nitrogen reactivity and a resistance to chlorine plasma etching from the side of the final growth layer. A second layer made of metal capable of wet etching, a third layer made of metal having nitrogen reactivity and resistance to wet etching, and a plurality of layers A device isolation groove extending from the base layer of the semiconductor element to the surface of the third layer, at least a side surface of the epitaxial growth layer facing the element isolation groove, and a bottom surface of the element isolation groove. An insulating protective film that covers the surface of the third layer positioned at the first layer, and the first layer and the third layer are made of titanium (Ti), tantalum (Ta), vanadium (V), zirconium (Zr), An insulating protective film consisting of a single layer or multiple layers of tungsten (W), molybdenum (Mo), niobium (Nb), chromium (Cr), or an alloy of two or more of these metals. Is a group III nitride compound semiconductor device comprising at least one of silicon dioxide, silicon nitride, titanium oxide, and titanium nitride .

The description about each component of said method invention and element invention is as follows. The crystal growth substrate is a substrate on which a group III nitride compound semiconductor layer is epitaxially grown, and a sapphire substrate, SiC, silicon substrate, or other insulating substrate or conductive substrate capable of epitaxial growth can be used. The group III nitride compound semiconductor layer includes binary GaN, InN, AlN, ternary In _x Ga _1-x N (0 <x <1), Al _x Ga _1-x N (0 < x <1), In _x Al _1-x N (0 <x <1), quaternary Al _x In _y Ga _1-xy N (0 <x <1, 0 <y <1, 0 <x + y < 1) can be used. Moreover, some of these Group III elements may be substituted with other Group III elements. Further, a part of the N element may be substituted with another group V element. Further, an n-type dopant such as Si or a p-type dopant such as Mg may be added. As a growth method, a halide vapor phase growth method or the like can be used in addition to a metal organic gas vapor phase growth method (MOCVD). As the support substrate, a conductive substrate is used when an electrode is formed on the back surface of the substrate. When the electrode for the p layer and the electrode for the n layer are formed on the same surface side, an insulating substrate may be used. In that case, a substrate with high heat dissipation and high thermal conductivity is desirable. Therefore, as the support substrate, a conductive semiconductor substrate such as a conductive silicon substrate, a metal substrate such as copper or aluminum, an AlN ceramic substrate having high thermal conductivity, an artificial diamond substrate, or the like can be used.

  The final growth layer of the epitaxial growth layer is a semiconductor layer grown last, and in the case of a group III nitride compound semiconductor layer, it is usually a p-type layer due to p-type activation. However, it is not limited to the p-type layer. The base layer is a layer that serves as a base for each layer constituting the element. When a sapphire substrate is used as a growth substrate, an undoped GaN layer, a Si-doped GaN layer, etc. are formed on the buffer layer after a low-temperature formation buffer layer such as AlN or GaN is formed. However, a layer to be grown first among the epitaxial growth layers excluding the buffer layer is defined as a base layer. In the case of a group III nitride compound semiconductor layer, it is usually an n-type layer. However, it is not limited to the n-type layer.

  The metal layer is a layer formed of a stack of a plurality of metals that joins the epitaxial growth layer and the support substrate. The metal layer includes a low melting point alloy layer such as solder. In addition, the metal layer includes a contact electrode, a reflective electrode for the final growth layer of the epitaxial growth layer, a metal layer for improving the adhesion of these electrodes to the epitaxial growth layer, a metal layer for suppressing electromigration, and a low melting point metal such as solder. A barrier metal layer for preventing diffusion to the epitaxial growth layer is included.

  The present invention includes a first layer made of a metal having nitrogen reactivity from the side of the final growth layer of the epitaxial growth layer, a second layer made of metal having resistance to chlorine plasma etching, and a third layer made of metal having nitrogen reactivity. It is the feature that provided. Examples of the metal having nitrogen reactivity include titanium (Ti), tantalum (Ta), vanadium (V), zirconium (Zr), tungsten (W), molybdenum (Mo), niobium (Nb), chromium (Cr), or Two or more kinds of these metals can be used. These metals are also metals that are resistant to wet etching. Nickel (Ni), platinum (Pt), or an alloy of these metals can be used as the metal resistant to chlorine plasma etching. These metals are also metals that can be wet etched. The first layer and the third layer may be made of the same metal or different metals. Most preferably, Ti is used for the first and third layers, and Ni is used for the second layer. The fourth layer is defined as a metal layer that exists between a supporting layer and a third layer other than the first layer, the second layer, and the third layer, such as a low melting point metal such as Au, Pt, or solder.

The element isolation groove is a groove formed in the epitaxial growth layer for isolation into each element. Further, within the width of the groove, the support substrate is separated for each element to form an element piece. In the element invention, since each element is separated, half of the side surface and the bottom surface of one side of the element isolation groove is left. Therefore, in the element isolation groove in the element invention, a half of the element isolation groove formed in the manufacturing stage is defined as the element isolation groove. That is, the portion where the epitaxial growth layer around the device is removed is used as the device isolation trench. As the insulating protective film, any insulating ceramic and dielectric such as SiO ₂ , silicon nitride, titanium oxide, and titanium nitride can be used.

  Further, it is desirable that the total thickness of the first layer and the second layer is thinner than the thickness of the insulating protective film. When this condition is satisfied, when an insulating protective film is formed, there is no separation at the intersection line between the side surface and the bottom surface of the element isolation trench, and it is uniform from the bottom surface to the side surface. An insulating protective film can be formed with a sufficient thickness. Both the first layer and the second layer are desirably 1000 mm or less and 50 mm or more. When the thickness of the first layer exceeds 1000 mm, when etching is performed by chlorine plasma, the portion located below the final growth layer of the first epitaxial growth layer is deeply etched in the lateral direction parallel to the surface (side etching). ) Is not desirable. On the other hand, if the first layer is thinner than 50 mm, the adhesion of the epitaxial growth layer to the final growth layer is lowered, and the adhesion between the support substrate and the epitaxial growth layer is lowered. In addition, when the first layer is formed so as to cover a contact electrode or a reflection electrode made of silver or the like, the adhesion of the contact electrode or the reflection electrode is lowered, and the effect of preventing migration of silver or the like is reduced. This is undesirable because it decreases. The thickness of the second layer is preferably 1000 mm or less and 100 mm or more. If the thickness of the second layer exceeds 1000 mm, the film formation time for the second layer and the time for removing the second layer by wet etching increase, which is not desirable. On the other hand, if the second layer is thinner than 100 mm, it is not desirable because the function as an etching stopper layer is insufficient when the epitaxial growth layer is etched with chlorine plasma to form the element isolation trench. The thickness of the third layer is desirably 300 mm or more and 1 μm mm or less. If the thickness is less than 300 mm, the adhesion to the insulating protective film is lowered and the resistance to wet etching is lowered, which is not desirable. If it is thicker than 1 μm, it takes time to form a film, which is not desirable.

  In the present invention, in the metal layer formed between the final growth layer of the epitaxial growth layer and the support substrate, the first layer joined to the final growth layer is made of a metal having nitrogen reactivity. Adhesiveness to the system compound semiconductor layer is high, and the reliability of the element can be improved. In addition, since the second layer is made of a metal having resistance to chlorine plasma etching, when the element isolation groove is formed by chlorine plasma etching, the epitaxial growth layer and the first layer are removed, and the surface of the second layer is formed. Since it can be exposed, the processing accuracy is improved. Further, since the second layer is a wet-etchable layer and the third layer is a layer resistant to wet etching, the surface of the third layer is accurately exposed at the bottom of the element isolation groove. be able to. As a result, the insulating protective film can be coated on at least the periphery of the surface of the uppermost layer of the epitaxial growth layer, the side surface of the epitaxial growth layer, and the upper surface of the third layer. At this time, since the third layer is made of a metal having nitrogen reactivity, the adhesion of the insulating protective film to the metal of the third layer can be improved, and the reliability of the element can be improved. .

Sectional drawing which shows the structure of the group III nitride compound semiconductor element (blue LED) obtained by the manufacturing method which concerns on this invention. Process drawing (sectional drawing) which shows 1 process of the manufacturing method which concerns on this invention. Process drawing (sectional drawing) which shows 1 process of the manufacturing method which concerns on this invention. Process drawing (sectional drawing) which shows 1 process of the manufacturing method which concerns on this invention. Process drawing (sectional drawing) which shows 1 process of the manufacturing method which concerns on this invention. Process drawing (sectional drawing) which shows 1 process of the manufacturing method which concerns on this invention. Process drawing (sectional drawing) which shows 1 process of the manufacturing method which concerns on this invention. Process drawing (sectional drawing) which shows 1 process of the manufacturing method which concerns on this invention. Process drawing (sectional drawing) which shows 1 process of the manufacturing method which concerns on this invention. Process drawing (sectional drawing) which shows 1 process of the manufacturing method which concerns on this invention. Process drawing (sectional drawing) which shows 1 process of the manufacturing method which concerns on this invention. Process drawing (sectional drawing) which shows 1 process of the manufacturing method which concerns on this invention. Process drawing (sectional drawing) which shows 1 process of the manufacturing method which concerns on this invention. Process drawing (sectional drawing) which shows 1 process of the manufacturing method which concerns on this invention. Process drawing (sectional drawing) which shows 1 process of the manufacturing method which concerns on this invention. Process drawing (sectional drawing) which shows 1 process of the manufacturing method which concerns on this invention. Process drawing (sectional drawing) which shows 1 process of the manufacturing method which concerns on this invention.

  Hereinafter, the present invention will be described based on specific examples. The present invention is not limited to the following examples.

  FIG. 1 is a cross-sectional view showing a configuration of a group III nitride compound semiconductor device (blue LED) 1000 obtained by a manufacturing method according to a specific embodiment of the present invention. A group III nitride compound semiconductor device (blue LED) 1000 in FIG. 1 is formed by stacking a plurality of metals on the surface of a conductive support substrate 200 that is a p-type silicon substrate from the side closer to the support substrate 200. 2 conductive layers 222, a solder layer (solder layer) 50 which is a low melting point alloy layer, a first conductive layer 122 made of a stack of a plurality of metals, a p contact electrode 121, and a p-type group III nitride compound semiconductor layer. It has a laminated structure of a p-type layer 12 that is a single layer or a multiple layer, a light emitting layer L, an n-type layer 11 that is a single layer or multiple layers of an n-type Group III nitride compound semiconductor layer, and an n-contact electrode .

  The epitaxial growth layer of claim is composed of a p-type layer 12, a light emitting layer L, and an n-type layer 11, and the metal layer existing between the epitaxial growth layer of claim and the support substrate is a first conductive layer 122, a solder layer. (Solder layer) 50, second conductive layer 122, and p-contact electrode 121. The configuration of the first conductive layer 122 is a feature of the present invention. The base layer corresponds to the lowermost layer (excluding the buffer layer) during the growth of the n-type layer 11, and the final growth layer corresponds to the uppermost layer of the p-type layer 12 during the growth.

  The arrangement of FIG. 1 is opposite to the vertical relationship when the epitaxial growth, the p contact electrode 121, the first conductive layer 122, the solder layer (solder layer) 50, and the second conductive layer 222 are formed. The first conductive layer 122 has a 300-thickness first layer 21 made of Ti bonded to the final growth layer of the p-type layer 12 of the epitaxial growth layer, and a 500-thickness first layer 21 made of Ni bonded to the first layer. It is formed of two layers and a third layer having a thickness of 3500 mm made of Ti bonded to the second layer. Then, a 3000-thick Pt layer 24 made of Pt is joined to the third layer, and a 500-thick Au layer 25 is joined to the Pt layer 24. The Au layer 25 is bonded to the second conductive layer 222 via the solder layer (solder layer) 50, and the epitaxial growth layer 10 is connected to the support substrate 200 via the conductive metal layer. In the present embodiment, the fourth layer of the claims is composed of a Pt layer 24, an Au layer 25, a solder layer (solder layer) 50, and a second conductive layer 222.

The outer peripheral side surface 10a of the epitaxial growth layer 10 constitutes a side wall of the element isolation trench 41, and the bottom surface 41a of the element isolation trench 41 is constituted by a third layer 23 made of Ti. The bottom surface 41a of the element isolation trench 41, the outer peripheral side surface 10a of the epitaxial growth layer 10, and the outer peripheral portion 10b of the upper surface of the n-type layer 11 are covered with an insulating protective film 40 made of SiO ₂ and having a thickness of 3000 mm. ing. The insulating protective film 40 is about four times thicker than the total thickness 800 mm of the first layer 21 made of Ti and the second layer 22 made of Ni. Therefore, the side walls of the first layer 21 and the second layer 22 exposed on the side surfaces of the element isolation trench 41 are completely covered with the side surfaces of the insulating protective film 40 deposited on the bottom surface 41a. As a result, at the intersection of the bottom surface 41a of the element isolation trench 41 and the outer peripheral side surface 10a of the epitaxial growth layer 10, the insulating protective film 40 deposited on the outer peripheral side surface 10a and the insulating protective film 40 deposited on the bottom surface 41a Are separated, and a gap is formed in the insulating protective film 40, thereby preventing the epitaxial growth layer 10, the first layer 21, and the second layer 22 from being exposed.

  The horizontal sectional area of the epitaxial growth layer 10 gradually decreases from the support substrate side 200 side of the p-type layer 12 toward the n contact electrode 130 side of the n-type layer 11. For this reason, the outer peripheral side surface 10a of the epitaxial growth layer covered with the insulating protective film 40 is inclined (in order) so as to spread from the upper side where the n contact electrode 130 is formed toward the lower side which is the support substrate side 200 side. Taper). The n-type layer 11 has a surface 11s having fine irregularities in order to improve light extraction efficiency. In addition, a third conductive layer 232 and a solder layer (solder layer) 235 made of a stack of a plurality of metals are formed on the back surface of the support substrate 200.

In this embodiment, each layer is configured as follows.
The second conductive layer 222 made of a stack of a plurality of metals is stacked in the order of titanium (Ti), nickel (Ni), and gold (Au) from the support substrate 200 side. The third conductive layer 232 made of a stack of a plurality of metals is formed by stacking platinum (Pt), titanium (Ti), and gold (Au) in this order from the support substrate 200 side. The solder layers (solder layers) 50 and 235 are each formed of solder made of an alloy of gold and tin (Au—Sn). The p contact electrode 121 is made of a silver (Ag) alloy. The first conductive layer 122 made of a stack of a plurality of metals includes titanium (Ti) as the first layer 21, nickel (Ni) as the second layer 22, from the side close to the p-type layer 12 and the p contact electrode 121, Titanium (Ti) which is the third layer 23, platinum (Pt) which is a part of the fourth layer, and gold (Au) are laminated in this order.

In the first conductive layer 122, the second conductive layer 222, and the third conductive layer 232, the nickel (Ni) layer is a nickel (Ni) layer in which the tin (Sn) in the solder layer (solder layer) 50 or 235 is moderate. It is a layer that diffuses into the solder layer and firmly adheres to the solder layer (solder layer) 50. The titanium (Ti) layer improves adhesion to the bonding surface of the conductive layer and prevents the diffusion of tin (Sn). The second layer 22 made of Ni also functions as an etching stopper when the element isolation trench 41 is etched with chlorine plasma. Further, the third layer 23 made of Ti also functions as an etching stopper when the Ni of the second layer 22 is wet-etched. The n-contact electrode 130 has a laminated structure of tungsten (W), titanium (Ti), and gold (Au). The insulating protective film 40 is made of silicon dioxide (SiO ₂ ).

  The group III nitride compound semiconductor device (blue LED) 1000 of FIG. 1 was manufactured as follows. The process drawing (cross-sectional view) at this time is shown in FIG. A to FIG. Indicated by P.

  The epitaxial growth layer 10 was formed by MOCVD. A low-temperature buffer layer made of AlN is formed on an epitaxial growth substrate 100 which is a crystal growth substrate made of sapphire having a thickness of 500 μm, and an n-type layer 11 made of a plurality of layers and a p-type made of a plurality of layers are formed on the buffer layer. The layer 12 was epitaxially grown in order to obtain an epitaxially grown layer 10 (FIG. 2.A). The light emitting layer L is formed with an MQW structure. In A, it is simply indicated by a thick broken line.

  Next, the 1st groove | channel tr-1 used as the air hole at the time of laser lift-off was formed with the dicer. The first trench tr-1 was formed by removing the total thickness of the p-type layer 12 and the n-type layer 11 of about 4 μm and the depth of the epitaxial growth substrate 100 of about 10 μm. The width of the first groove tr-1 was about 20 μm (FIG. 2.B). Next, an Ag alloy layer was formed on the entire surface by a sputtering apparatus, a resist mask was formed, an unnecessary portion of the Ag alloy layer was removed, and an Ag alloy layer was formed in a portion corresponding to the light emitting region. Next, the resist mask was removed, and then heated at 550 ° C. for 3 minutes to alloy the Ag alloy and the final growth layer of the p-type layer 12 to form a p-contact electrode 121 made of Ag alloy ( Figure 2.C).

  Next, a sputtering apparatus is used to form a Ti film with a thickness of 300 mm, a Ni film with a thickness of 500 mm, and a Ti film with a thickness of 3500 mm. The first layer 21 shown in FIG. A second layer 22 and a third layer 23 were formed. Subsequently, Pt was formed to a thickness of 3000 mm to form the Pt layer 24 shown in FIG. 1, and then Au was formed to a thickness of 500 mm to form the Au layer 25 shown in FIG. FIG. D to FIG. In P, these five layers are collectively shown as a first conductive layer 122. These layers are formed by a sputtering apparatus, but may be formed by a vapor deposition apparatus. Next, an AuSn layer having a thickness of 1.5 μm (Au is 80 wt%, Sn is 20 wt%) and a thickness of 0 are formed as a solder layer 125 on the Au layer 25 of the first conductive layer 122 by an electron beam evaporation apparatus. A 2 μm-thick AuSn layer (Au: 10 wt%, Sn: 90 wt%) and an Au layer having a thickness of 100 mm were formed on the entire surface. The Au layer is a thin film for preventing oxidation of tin (Sn) (FIG. 2.D).

  Next, a Ti film having a thickness of 2000 mm and a Pt film having a thickness of 500 mm were formed on the support substrate 200 made of p-type conductive silicon having a thickness of 500 μm by a sputtering apparatus. Next, heat treatment was performed at 600 ° C. for 1 minute to alloy Ti and Si of the support substrate 200. On the support substrate 200 thus treated, a sputtering apparatus was further used to deposit Ti on the entire surface to a thickness of 3000 mm, Pt to a thickness of 3000 mm, and Au to a thickness of 500 mm. In this way, the second conductive layer 222 made of Ti, Pt, Ti, Pt, and Au was formed. Next, an AuSn layer having a thickness of 1.5 μm (Au is 80 wt%, Sn is 20 wt%) and an AuSn having a thickness of 0.2 μm are formed on the second conductive layer 222 as a solder layer 225 by an electron beam evaporation apparatus. A layer (Au: 10 wt%, Sn: 90 wt%) and an Au layer having a thickness of 100 mm were formed on the entire surface (FIG. 2.E). The Au layer is a thin film for preventing oxidation of tin (Sn).

Next, the epitaxial growth substrate 100 having the epitaxial growth layer 10 and the support substrate 200 are joined with the solder layers (solder layers) 125 and 225 facing each other. The solder layers (solder layers) 125 and 225 are low melting point alloy layers. The heating temperature was 320 ° C., and the pressure was 196 kPa (about 2 atm, 2 kgf / cm ² ) (FIG. 2.E). At this time, in the joining of the solder layer (solder layer) 125 and the solder layer (solder layer) 225, there are two Au thin films between the AuSn layers. The layer is absorbed into one AuSn layer. FIG. F-2. In P, the solder layers (solder layers) 125 and 225 joined together are shown as a single solder layer (solder layer) 50.

  Next, laser lift-off is performed. Laser irradiation is performed near the interface 11 sf between the n-type layer 11 and the epitaxial growth substrate 100 to decompose the thin-film portion of the n-type layer 11. At this time, the laser irradiation region (shot area) was a square region having a side of 2 mm including 16 square chips formed at a pitch of 500 μm. FIG. In F, the entire thin film portion near the interface 11sf between the n-type layer 11 and the epitaxial growth substrate 100 was decomposed, and the epitaxial growth substrate 100 was separated from the epitaxial growth layer 10 (FIG. 2.G). Even if nitrogen gas is generated by the decomposition of the n-type layer 11 in this stripping step, the first groove tr-1 communicates with the outside of the wafer, so that the nitrogen gas immediately passes through the first groove tr-1 to the wafer. It is discharged outside. For this reason, only a small load is applied to the epitaxial growth layer 10, the epitaxial growth substrate 100, the support substrate 200, and the conductive layers formed therebetween by the laser irradiation. Therefore, it was finally confirmed that no peeling or cracking occurred in these conductive layers.

Next, element isolation trenches 41 were formed by dry etching using chlorine plasma using a mask. The element isolation trench 41 includes the first trench tr-1 and has a width wider than the width of the trench, and is formed in the outer peripheral portion of the epitaxial growth layer 10 (FIG. 2.H). As an etching mask used at this time, a SiO ₂ film formed by CVD having a predetermined shape was used. In the etching using chlorine plasma, the first layer 21 made of Ti located on the bottom surface 41a of the element isolation groove 41 was completely etched. However, the second layer 22 made of Ni is not etched, or the etching rate is very slow compared to the etching rate of the epitaxial growth layer 10 and the first layer made of Ti. Therefore, the second layer 22 made of Ni functions as an etching stopper layer when the element isolation trench 41 is formed by etching with chlorine plasma. Next, after removing the SiO ₂ mask, the second layer 22 made of Ni was etched by wet etching with film nitric acid to expose the third layer 23 made of Ti. Ti is not etched by nitric acid, or the etching rate is very slow compared to Ni. Therefore, when the second layer 22 made of Ni is removed by etching, the third layer 23 made of Ti functions as an etching stopper layer for wet etching with nitric acid.

Next, in order to form the insulating protective film 40, SiO ₂ was formed on the entire surface to a thickness of 3000 mm by a sputtering apparatus (FIG. 2.I). At this time, the insulating protective film 40 made of SiO ₂ is also deposited on the bottom of the first trench tr-1 on the solder layer (solder layer) 50 side. Next, of the insulating protective film 40, the insulating protective film 40 on the outer peripheral side surface 10a of the upper surface of the n-type layer 11 and the bottom surface 41a of the element isolation trench 41, the outer peripheral side surface 10a of the epitaxial growth layer 10 is left. The other parts were removed by etching. Thus, the surface 11f corresponding to the light emitting region of the n-type layer 11 was exposed (FIG. 2.J). The surface 11f of the n-type layer 11 is an N-polar surface, that is, a (000-1) surface and a -c surface, and is easily etched. Therefore, the surface of the n-type layer 11 was left at 60 ° C. in a state immersed in the TMAH solution to form a fine uneven surface 11s (FIG. 2.K).

Next, SiO ₂ was formed on the entire surface with a thickness of 2000 mm by a sputtering apparatus to form a second insulating protective film 42 (FIG. 2.L). Next, a window was opened by etching in the region where the electrode 130 is to be formed in the second insulating protective film 42 on the upper surface of the n-type layer 11. Next, on the fine uneven surface 11s of the n-type layer 11, a pseudo silicon heavy doped layer was formed in the window portion of the second insulating protective film 42 by plasma treatment with a compound gas containing silicon. After this, no treatment with a chemical having fluorine ions was performed. The plasma conditions were as follows. The introduced gas was SiCl ₄ and introduced at a flow rate of 30 sccm. The pressure inside the process was 3 Pa. The electric field inside the process was a high frequency of 13.56 MHz with an antenna power of 300 W. Separately from this, a bias power of a high frequency of 300 W was supplied to the support substrate 200 made of p-type silicon. The processing time was 60 seconds. This process is a process for reducing the contact resistance between the n-type layer 11 and the n-electrode 130. Since the surface 11f of the n-type layer 11 is an N-polar surface, it is difficult to obtain ohmic contact. Further, since the alloying of the n-type layer 11 and the n-electrode 130 is performed with the solder layer (solder layer) 50, the temperature is lower than the melting point of the solder layer 50, for example, a temperature of 400 ° C. or less. Need to be alloyed. This treatment improves the electron concentration of the surface 11f of the n-type layer 11 so that the n-electrode 130 excellent in low contact resistance and ohmic contact can be formed even when alloyed at a low temperature of 100 ° C. or higher and 350 ° C. or lower. It is to make it.

  Next, a resist mask is formed in a portion other than the window, and tungsten (W) is deposited to a thickness of 1000 mm, titanium (Ti) to a thickness of 500 mm, and gold (Au) to a thickness of 3 μm. The n-electrode 130 was formed by lifting off the resist mask (FIG. 2.M). Thereafter, the n-type layer 11 and tungsten (W) were alloyed by annealing at 300 ° C. for 1 minute.

  Next, the back surface of the support substrate 200 made of silicon was polished and thinned to a thickness of 130 μm (FIG. 2.N). Next, a sputtering apparatus is used to deposit Pt with a thickness of 750 mm, Ti with a thickness of 3000 mm, Pt with a thickness of 3000 mm, and Au with a thickness of 500 mm on the polished surface of the support substrate 200 made of silicon. , A third conductive layer 232 including a Pt layer, a Ti layer, a Pt layer, and an Au layer was formed. Next, as a solder layer 235, an AuSn layer (Au is 80 wt%, Sn is 20 wt%) and an AuSn layer (Au is 10 wt%, Sn is formed as a solder layer 235 by an electron beam evaporation apparatus. 90 wt%) and an Au layer having a thickness of 100 mm was formed on the entire surface (FIG. 2.O). The Au layer is a thin film for preventing oxidation of tin (Sn). The solder layer (solder layer) 235 may not be formed. Next, the support substrate 200 was cut using a laser (FIG. 2.P). FIG. The inside of the two broken lines indicated by P and C was decomposed and melted by a laser to separate each element. Thus, a group III nitride compound semiconductor device (blue LED) 1000 of FIG. 1 was obtained.

In the group III nitride compound semiconductor device (blue LED) 1000, the uppermost layer of the n-type layer 11 in FIG. 1, that is, the base layer, is constituted by a contact layer made of n-type GaN, and the p-type layer 12 The final growth layer in the lowermost layer in the arrangement of FIG. 1 is composed of a contact layer made of p-type GaN. These layers may be contact layers such as InGaN and AlGaN. In the group III nitride compound semiconductor device (blue LED) 1000 manufactured in this way, the side surface 10a of the epitaxial growth layer 10, the upper surface of the n-type layer 11, and the third layer 23 made of Ti are insulated from SiO _2. The protective film 40 is bonded. As a result, since the bonding strength between SiO ₂ and Ti is strong, the insulating protective film 40 can be prevented from peeling off, and moisture, contaminating atoms, etc. can be prevented from entering the epitaxial growth layer 10 from the outside, and the reliability of the device can be improved. improves.

  In the above embodiment, the first layer 21 is made of Ti. However, in addition to Ti, a metal having nitrogen reactivity can be used. For example, for the first layer 21, Ti, Ta, V, Zr, W, Mo, Nb, Cr, or an alloy of two or more of these metals can be used. In addition, Ni is used for the second layer 22, but in addition to Ni, a metal that is resistant to chlorine plasma etching and can be wet etched can be used. For example, Ni, Pt, or an alloy of these metals can be used for the second layer 22. Further, although Ti is used for the third layer 23, in addition to Ti, a metal having nitrogen reactivity and resistance to wet etching of the second layer can be used. For example, for the third layer 23, Ti, Ta, V, Zr, W, Mo, Nb, Cr, or an alloy of two or more of these metals can be used.

In the above embodiment, the insulating protective film 40 and the second insulating protective film 42 are formed of SiO ₂ , but may be formed of SiN _x . Alternatively, the insulating protective film 40 may be made of SiO ₂ and the second insulating protective film 42 may be made of SiN _x . In the above embodiment, the thickness of the first layer 21 is 300 mm, but is preferably 1000 mm or less and 50 mm or more. The thickness of the second layer 22 is 500 mm, but is preferably 1000 mm or less and 100 mm or more. Although the thickness of the third layer 23 is 3500 mm, a thickness of 300 mm or more and 1 μm or less is desirable. Although a sapphire substrate is used as the epitaxial growth substrate 100, any substrate such as a conductive substrate or an insulating substrate can be used as long as it is a substrate on which a group III nitride compound semiconductor is grown. Further, although the silicon-doped n-type silicon substrate is used as the support substrate 200, a metal such as copper, ceramics or crystal having high thermal conductivity such as AlN, artificial diamond, or the like may be used.

  Moreover, in the said Example, although the TMAH solution was used to form the fine uneven surface 11s on the surface 11f of the n-type layer 11, a potassium hydroxide aqueous solution (KOHaq) having a concentration of 1 mol / L (1M) was used. Good. The n electrode 130 is a metal layer in which tungsten (W), titanium (Ti), and gold (Au) are stacked from the n-type layer 11 side. Is made of vanadium (V), chromium (Cr), nickel (Ni), platinum (Pt), niobium (Nb) or iron (Fe), and then laminated with titanium (Ti) and gold (Au). You may use the made metal layer.

  The method and structure of the present invention can be used for the manufacturing method and structure of an electronic device such as a light emitting device, and is effective in improving the reliability of the device.

1000: Group III nitride compound semiconductor device (blue LED)
100: Sapphire substrate (epitaxial growth substrate)
11: n-type layer 11f: N-polar surface of n-type layer 11 11s: surface with fine irregularities L: light-emitting layer 12: p-type layer 21: first layer 22: second layer 23: third layer 121: p Contact electrode 122: first conductive layer 222: second conductive layer 232: third conductive layer 125, 225, 235, 50: solder layer (solder layer)
130: n-electrode 200: silicon substrate (support substrate)
40: Insulating protective film 41: Element isolation groove 42: Second insulating protective film

Claims (8)

An epitaxial growth layer made of a group III nitride compound semiconductor layer is crystal-grown on the crystal growth substrate, and the final growth layer made of a p-type group III nitride compound semiconductor layer, which is the final growth layer of the epitaxial growth layer, is made of metal. The substrate is bonded to the support substrate by the layer, the crystal growth substrate is removed, and a base layer made of an n-type group III nitride compound semiconductor layer, which is an initial growth layer of the epitaxial growth layer, is formed on the epitaxial growth layer on the support substrate. In the manufacturing method of the semiconductor element as the uppermost layer,
In the step of forming the metal layer,
Forming a first layer of a metal having nitrogen reactivity from the side of the final growth layer;
On the first layer, a second layer made of a metal having resistance to chlorine plasma etching and capable of being wet etched is formed.
Forming a third layer made of a metal having nitrogen reactivity and resistance to wet etching on the second layer;
Forming a fourth layer having a laminated structure of a plurality of metals on the third layer;
Etching with chlorine plasma so that the surface of the second layer is exposed on the bottom surface, using the second layer as an etching stopper layer from the base layer of the semiconductor element to form an element isolation groove,
Removing the second layer exposed on the bottom surface of the element isolation trench by wet etching to expose the third layer on the bottom surface of the element isolation trench;
Covering at least the side surface of the epitaxial growth layer facing the element isolation trench and the surface of the third layer located at the bottom surface of the element isolation trench with an insulating protective film,
The first layer and the third layer include titanium (Ti), tantalum (Ta), vanadium (V), zirconium (Zr), tungsten (W), molybdenum (Mo), niobium (Nb), and chromium (Cr). Or a single layer composed of an alloy of two or more of these metals, or a multilayer .
The method of manufacturing a group III nitride compound semiconductor device, wherein the insulating protective film is made of at least one of silicon dioxide, silicon nitride, titanium oxide, and titanium nitride .   2. The group III nitride according to claim 1, wherein the second layer is formed of a single layer or a plurality of layers made of nickel (Ni), platinum (Pt), or an alloy of these metals. For manufacturing a semiconductor compound semiconductor device.   3. The group III nitride compound semiconductor device according to claim 1, wherein a total thickness of the first layer and the second layer is made thinner than a thickness of the insulating protective film. Manufacturing method.   Before forming the first layer, a light-reflective contact electrode is formed on the final growth layer except at least around the final growth layer, and the first layer covers the contact electrode, The method for producing a group III nitride compound semiconductor device according to any one of claims 1 to 3, wherein the final growth layer is bonded to at least the periphery of the final growth layer. A final growth layer comprising a p-type group III nitride compound semiconductor layer having an epitaxial growth layer composed of a crystal-grown group III nitride compound semiconductor layer on a crystal growth substrate and being a final growth layer of the epitaxial growth layer Is bonded to a conductive support substrate by a metal layer, the crystal growth substrate is removed, and a base layer made of an n-type group III nitride compound semiconductor layer, which is an initial growth layer of the epitaxial growth layer, is formed on the support substrate. In the semiconductor element that is the uppermost layer of the upper epitaxial growth layer,
The metal layer includes, from the side of the final growth layer, a first layer made of a metal having nitrogen reactivity, a second layer made of a metal having resistance to chlorine plasma etching and capable of wet etching, and a nitrogen reaction. And a third layer made of a metal having resistance to wet etching and a fourth layer made of a laminated structure of a plurality of metals,
An element isolation groove extending from the base layer of the semiconductor element to the surface of the third layer;
An insulating protective film that covers at least a side surface of the epitaxial growth layer facing the element isolation trench and a surface of the third layer located at the bottom surface of the element isolation trench;
The first layer and the third layer are made of titanium (Ti), tantalum (Ta), vanadium (V), zirconium (Zr), tungsten (W), molybdenum (Mo), niobium (Nb), chromium (Cr). Or a single layer composed of an alloy of two or more of these metals, or a multilayer .
The group III nitride compound semiconductor device, wherein the insulating protective film is made of at least one of silicon dioxide, silicon nitride, titanium oxide, and titanium nitride .   6. The group III nitride according to claim 5, wherein the second layer is formed of a single layer or a plurality of layers made of nickel (Ni), platinum (Pt), or an alloy of these metals. Compound semiconductor device.   The group III nitride compound semiconductor device according to claim 5 or 6, wherein a total thickness of the first layer and the second layer is thinner than a thickness of the insulating protective film.   A light-reflective contact electrode formed on the final growth layer except at least the periphery of the final growth layer, the contact electrode being covered with the first layer, and the first layer being 8. The group III nitride compound semiconductor device according to claim 5, wherein the group III nitride compound semiconductor element is bonded to the final growth layer at least around the final growth layer.

Images