JP5486735B2 - Semiconductor device - Google Patents

Description

The present invention relates to a semiconductor device.

Semiconductor integrated circuits, in particular, integrated circuits using MOS transistors, are becoming increasingly highly integrated. Along with this high integration, the MOS transistors used therein have been miniaturized to the nano-range. The basic circuit of a digital circuit is an inverter circuit. However, as the MOS transistors that make up this inverter circuit are miniaturized, it is difficult to suppress leakage current, resulting in reduced reliability due to the hot carrier effect. There is a problem that the occupied area of the circuit cannot be made small because of a demand for securing a sufficient amount of current. In order to solve such a problem, a Surrounding Gate Transistor (SGT) having a structure in which a source, a gate, and a drain are arranged in a vertical direction with respect to a substrate and the gate surrounds an island-like semiconductor layer has been proposed (for example, a patent) Literature 1, Patent Literature 2, Patent Literature 3).

In a static memory cell, it is known to ensure operational stability by setting the current driving capability of a driver transistor to be twice that of an access transistor (Non-patent Document 1).

If an attempt is made to configure a static memory cell with the above SGT, to ensure that the current driving capability of the driver transistor is twice that of the access transistor in order to ensure operational stability, the gate width is reduced. Since it must be doubled, two driver transistors are used. That is, the memory cell area increases. Alternatively, in order to double the gate width, the silicon pillar diameter must be doubled or quadrilateral and the long side doubled, which increases the area occupied by the driver transistor, which also increases the memory cell area. Increase.

JP 2-71556 JP 2-188966 JP-A-3-145761

H. Kawasaki, M. Khater, M. Guillorn, N. Fuller, J. Chang, S. Kanakasabapathy, L. Chang, R. Muralidhar, K. Babich, Q. Yang, J. Ott, D. Klaus, E. Kratschmer, E. Sikorski, R. Miller, R. Viswanathan, Y. Zhang, J. Silverman, Q. Ouyang, A. Yagishita, M. Takayanagi, W. Haensch, and K. Ishimaru, “Demonstration of Highly Scaled FinFET SRAM Cells with High-κ / Metal Gate and Investigation of Characteristic Variability for the 32 nm node and beyond ”, IEDM, pp.237-240, 2008.

Therefore, it is an object to provide a static memory cell that is highly integrated and uses SGT to ensure operation stability.

In order to achieve the above object, a static memory cell according to one aspect of the present invention includes a six-transistor SRAM cell, and the six-transistor SRAM cell includes a first driver transistor, a first load transistor, Including a selection transistor and a first gate wiring;
The first driver transistor is
A first island-like semiconductor layer;
A first first-conductivity-type high-concentration semiconductor layer formed on the first island-shaped semiconductor layer;
A second first-conductivity-type high-concentration semiconductor layer formed under the first island-shaped semiconductor layer;
A first second conductivity type semiconductor layer formed between the first first conductivity type high concentration semiconductor layer and the second first conductivity type high concentration semiconductor layer;
A first gate insulating film formed around the first second conductivity type semiconductor layer;
A first gate electrode made of at least metal and formed around the first gate insulating film;
Consists of
The first selection transistor is
A second island-like semiconductor layer;
A third first-conductivity-type high-concentration semiconductor layer formed on the second island-shaped semiconductor layer;
A fourth first-conductivity-type high-concentration semiconductor layer formed under the second island-shaped semiconductor layer;
A second second conductive semiconductor layer formed between the third first conductive high concentration semiconductor layer and the fourth first conductive high concentration semiconductor layer;
A second gate insulating film formed around the second second conductivity type semiconductor layer;
A second gate electrode made of at least metal and formed around the second gate insulating film;
Consists of
The first load transistor is
A third island-like semiconductor layer;
A third second-conductivity-type high-concentration semiconductor layer formed on the third island-shaped semiconductor layer;
A fourth second-conductivity type high-concentration semiconductor layer formed under the third island-shaped semiconductor layer;
A fifth first conductivity type semiconductor layer formed between the third second conductivity type high concentration semiconductor layer and the fourth second conductivity type high concentration semiconductor layer;
A third gate insulating film formed around the fifth first conductivity type semiconductor layer;
A third gate electrode made of at least metal and formed around the third gate insulating film;
Consists of
A first gate line connected to the second gate electrode;
The peripheral length of the first island-shaped semiconductor layer is less than twice the peripheral length of the second island-shaped semiconductor layer,
The voltage applied to the second gate electrode is lower than the voltage applied to the third first conductivity type high-concentration semiconductor layer.

The static memory cell further includes a first pass transistor,
The first pass transistor includes:
A fourth island-shaped semiconductor layer;
A sixth first-conductivity type high-concentration semiconductor layer formed on the fourth island-shaped semiconductor layer;
A seventh first conductivity type high-concentration semiconductor layer formed under the fourth island-shaped semiconductor layer;
A fifth second conductivity type semiconductor layer formed between the sixth first conductivity type high concentration semiconductor layer and the seventh first conductivity type high concentration semiconductor layer;
A fourth gate insulating film formed around the fifth second conductivity type semiconductor layer;
A fourth gate electrode made of at least metal and formed around the fourth gate insulating film;
Consists of
The seventh first conductivity type high-concentration semiconductor layer and the first gate wiring are connected by wiring;
A power supply voltage is applied to the sixth first conductivity type high concentration semiconductor layer, and a voltage lower than the power supply voltage is output to the seventh first conductivity type high concentration semiconductor layer.

The static memory cell further includes a first pass transistor,
The first pass transistor includes:
A fourth island-shaped semiconductor layer;
A sixth first-conductivity type high-concentration semiconductor layer formed on the fourth island-shaped semiconductor layer;
A seventh first conductivity type high-concentration semiconductor layer formed under the fourth island-shaped semiconductor layer;
A fifth second conductivity type semiconductor layer formed between the sixth first conductivity type high concentration semiconductor layer and the seventh first conductivity type high concentration semiconductor layer;
A fourth gate insulating film formed around the fifth second conductivity type semiconductor layer;
A fourth gate electrode made of at least metal and formed around the fourth gate insulating film;
Consists of
The sixth first-conductivity type high-concentration semiconductor layer and the first gate wiring are connected by wiring;
A power supply voltage is applied to the seventh first conductivity type high concentration semiconductor layer, and a voltage lower than the power supply voltage is output to the sixth first conductivity type high concentration semiconductor layer .

In the static memory cell , the voltage applied to the fourth gate electrode is the power supply voltage.

According to the present invention, when the gate width of the driver transistor is less than twice the gate width of the selection transistor, by reducing the voltage applied to the gate of the selection transistor, the current driving capability of the selection transistor is reduced and high integration is achieved. It is possible to provide a static memory cell that ensures operational stability. Further, by adding an SGT pass transistor between the first gate wiring and the power supply line, the voltage applied to the first gate wiring can be lowered by the threshold voltage of SGT. Therefore, the area for the step-down circuit can be reduced, and the step-down circuit can be realized only by the area occupied by the SGT. That is, it is possible to provide a static memory cell that is highly integrated and ensures operational stability.

Since the body of the SGT is completely surrounded by the gate, the threshold voltage does not increase due to the back bias effect in principle. In other words, a constant threshold voltage can always be set, and when SGT is used as a pass transistor, a static memory cell that ensures operational stability can be provided.
On the other hand, bulk MOSFETs, SOI MOSFETs, double gate MOSFETs, and trigate MOSFETs have a body that is not completely surrounded by a gate, so that in principle the threshold voltage increases due to the back bias effect. That is, when a bulk MOSFET, SOI MOSFET, double gate MOSFET, or trigate MOSFET is used for the pass transistor of the present invention, the threshold voltage changes depending on the source voltage, so that the operation stability is impaired.

FIG. 1 is a bird's eye view of a static memory cell according to the present invention. 2 is a cross-sectional view of the static memory cell according to the present invention taken along the line X1-X1 'in FIG. 3 is a cross-sectional view of the static memory cell according to the present invention taken along the line X2-X2 'in FIG. FIG. 4 is a circuit diagram of a static memory cell according to the present invention. FIG. 5 is a circuit diagram of a static memory cell according to the present invention. FIG. 6 is a circuit diagram of a pass transistor according to the present invention. FIG. 7 is a circuit diagram of a static memory cell and a pass transistor according to the present invention. FIG. 8 is a circuit diagram of a pass transistor according to the present invention. FIG. 9 is a bird's-eye view of the selection transistor and the pass transistor according to the present invention. 10 is a z cross-sectional view of the pass transistor according to the present invention in FIG.

Embodiments of the present invention will be described below with reference to the drawings. In addition, this invention is not limited by embodiment shown below.

FIG. 1 shows a bird's-eye view of a static memory cell according to the present invention,
FIG. 2 is a cross-sectional view of the static memory cell according to the present invention, taken along X1-X1 ′ in FIG.
FIG. 3 is a cross-sectional view of the static memory cell according to the present invention taken along the line X2-X2 ′ in FIG.
The static memory cell according to the present invention includes a first island-like silicon layer 107,
A first n + silicon layer 119 formed on the first island-like silicon layer 107;
A second n + silicon layer 135 formed under the first island-like silicon layer 107;
A first p silicon layer 160 formed between the first n + silicon layer 119 and the second n + silicon layer 135;
A first gate insulating film 113 formed around the first p silicon layer 160;
A first gate electrode 125 made of at least metal and formed around the first gate insulating film 113;
The first driver transistor 101 is configured.

The static memory cell according to the present invention includes a second island-shaped silicon layer 109,
A third n + silicon layer 121 formed on the second island-like silicon layer 109;
A fourth n + silicon layer 137 formed under the second island-like silicon layer 109;
A second p silicon layer 162 formed between the third n + silicon layer 121 and the fourth n + silicon layer 137;
A second gate insulating film 115 formed around the second p silicon layer 162;
A second gate electrode 127 made of at least metal and formed around the second gate insulating film 115;
The first selection transistor 103 is configured.

The static memory cell according to the present invention includes a third island-like silicon layer 108,
A third p + silicon layer 120 formed on top of the third island-like silicon layer 108;
A fourth p + silicon layer 136 formed under the third island-like silicon layer 108;
A fifth n silicon layer 161 formed between the third p + silicon layer 120 and the fourth p + silicon layer 136;
A third gate insulating film 114 formed around the fifth n silicon layer 161;
A third gate electrode 126 made of at least metal and formed around the third gate insulating film 114;
A first load transistor 102 comprising:
And a first gate line 132 connected to the second gate electrode 127.
Since the electrode used for the gate electrode determines the threshold voltage of the transistor based on the work function, at least a metal or a metal compound is preferable.

In addition, the static memory cell according to the present invention includes a gate wiring 131 connected to the first gate electrode 125 and the third gate electrode 126;
A wiring 141 for connecting the second n + silicon layer 135, the fourth n + silicon layer 137, and the fourth p + silicon layer 136 is provided.
The wiring 141 is preferably made of silicon or a compound of metal and silicon.

The static memory cell according to the present invention is
An island-like silicon layer 112;
An n + silicon layer 124 formed on the island-like silicon layer 112;
An n + silicon layer 140 formed under the island-like silicon layer 112;
A p silicon layer 165 formed between the n + silicon layer 124 and the n + silicon layer 140;
A gate insulating film 118 formed around the p silicon layer 165;
A gate electrode 130 made of at least a metal formed around the gate insulating film 118;
The driver transistor 106 comprised by this is included.

The static memory cell according to the present invention includes an island-like silicon layer 110,
An n + silicon layer 122 formed on the island-like silicon layer 110;
An n + silicon layer 138 formed under the island-like silicon layer 110;
A p silicon layer 163 formed between the n + silicon layer 122 and the n + silicon layer 138;
A gate insulating film 116 formed around the p silicon layer 163;
A gate electrode 128 made of at least a metal formed around the gate insulating film 116;
The selection transistor 104 is configured.

The static memory cell according to the present invention includes an island-like silicon layer 111,
A p + silicon layer 123 formed on the island-like silicon layer 111;
A p + silicon layer 139 formed under the island-like silicon layer 111;
An n silicon layer 164 formed between the p + silicon layer 123 and the p + silicon layer 139;
A gate insulating film 117 formed around the n silicon layer 164;
A gate electrode 129 made of at least metal and formed around the gate insulating film 117;
A load transistor 105 composed of:
And a gate wiring 133 connected to the gate electrode 128.
Since the electrode used for the gate electrode determines the threshold voltage of the transistor based on the work function, at least a metal or a metal compound is preferable.

In addition, the static memory cell according to the present invention includes a gate wiring 134 connected to the gate electrode 129 and the gate electrode 130, and
A wiring 142 for connecting the n + silicon layer 140, the n + silicon layer 138, and the p + silicon layer 139 is provided.
The wiring 142 is preferably silicon or a compound of metal and silicon.
At this time,
The peripheral length W1 of the first island-shaped silicon layer 107 is less than twice the peripheral length W2 of the second island-shaped silicon layer 109,
The voltage applied to the second gate electrode 127 is:
The voltage applied to the third n + silicon layer 121 is lower.

The peripheral length W1 of the first island-shaped silicon layer 107 is less than twice the peripheral length W2 of the second island-shaped silicon layer 109, thereby suppressing an increase in the area occupied by the first driver transistor 101. Thus, an increase in the memory cell area is suppressed. Although described as less than twice, W1 = W2 is particularly desirable. At this time, the occupied area of the first driver transistor 101 is the same as the occupied area of the first selection transistor 103 , and high integration can be achieved.
Further, by applying a voltage lower than the voltage applied to the third n + silicon layer 121 of the first selection transistor 103 to the second gate electrode 127 of the first selection transistor 103 , the first selection transistor It is possible to provide a static memory cell in which the current driving capability of 103 is lowered and the operation stability is highly integrated.

FIG. 4 shows a circuit diagram of a static memory cell according to the present invention.
The gate wiring 131 and the wiring 142 are connected by a wiring or a contact 143,
The gate wiring 134 and the wiring 141 are connected by a wiring or a contact 144,
A GND line 145 is connected to the first n + silicon layer 119,
A power line 146 is connected to the third p + silicon layer 120,
A bit line 147 is connected to the third n + silicon layer 121,
A GND line 149 is connected to the n + silicon layer 124,
A power line 146 is connected to the p + silicon layer 123,
Bit line 148 is connected to n + silicon layer 122.

FIG. 5 shows a circuit diagram of a static memory cell according to the present invention.
FIG. 4 shows applied voltages at the time of data reading according to the present invention. A VDD-B voltage is applied to the first gate wiring 132 and the second gate electrode 127. VDD is a power supply voltage. B is a positive number. A power supply voltage VDD is applied to the bit line. Accordingly, by applying a voltage lower than the voltage applied to the third n + silicon layer 121 of the first selection transistor 103 to the second gate electrode 127 of the selection transistor, the current drive of the first selection transistor 103 is performed. It is possible to provide a static memory cell with reduced power, high integration and operation stability.

At this time, a step-down circuit is required to create a voltage of VDD-B. If the area of the step-down circuit is large, it may not be highly integrated. Therefore, a circuit configuration capable of performing step-down with a minimum area is required. FIG. 6 is a circuit diagram of a pass transistor according to the present invention. When the power supply voltage VDD is input to the drain and the power supply voltage VDD is input to the gate, the pass transistor outputs a value obtained by subtracting the threshold voltage (Vth0 + A) from the power supply voltage VDD from the source. However, Vth0 is a threshold voltage when the source is 0V, and A is an increase of the threshold voltage increased by the back bias effect.

This pass transistor is added to the static memory cell according to the present invention. FIG. 7 is a circuit diagram of a static memory cell and a pass transistor according to the present invention. This pass transistor is not necessary for each static memory cell, but may be provided at the end of the word line, and may be provided at the end of the static memory cell array. That is, since at least one word line is required, the area for the step-down circuit can be reduced.

When the power supply voltage VDD is input to the drain and the power supply voltage VDD is input to the gate, the pass transistor outputs a value obtained by subtracting the threshold voltage (Vth0 + A) from the power supply voltage VDD from the source. However, Vth0 is a threshold voltage when the source is 0V, and A is an increase of the threshold voltage increased by the back bias effect. Therefore, the increase A of the threshold voltage increased by the back bias effect changes due to the back bias.

FIG. 8 is a circuit diagram of a pass transistor according to the present invention.
In bulk MOSFETs, SOI MOSFETs, double gate MOSFETs, and tri gate MOSFETs, the body is not completely surrounded by the gate, so that the threshold voltage increases in principle due to the back bias effect. The increment A of the threshold voltage increased by the back bias effect is a positive number. That is, when a bulk MOSFET, SOI MOSFET, double gate MOSFET, or trigate MOSFET is used for the pass transistor of the present invention, the threshold voltage changes depending on the source voltage, so that the operation stability is impaired.
On the other hand, since the body of the SGT is completely surrounded by the gate, the threshold voltage does not increase due to the back bias effect in principle. The increment A of the threshold voltage increased by the back bias effect is zero. In other words, a constant threshold voltage can always be set, and when SGT is used as a pass transistor, a static memory cell that ensures operational stability can be provided.

Therefore, SGT is used as a pass transistor.
FIG. 9 is a bird's-eye view of the selection transistor and the pass transistor according to the present invention.
10 is a z cross-sectional view of the pass transistor according to the present invention in FIG.
The static memory cell according to the present invention includes a fourth island-like silicon layer 154,
A sixth n + silicon layer 153 formed on top of the fourth island-like silicon layer 154;
A seventh n + silicon layer 152 formed below the fourth island-like silicon layer 154;
A fifth p silicon layer 166 formed between the sixth n + silicon layer 153 and the seventh n + silicon layer 152;
A fourth gate insulating film 155 formed around the fifth p silicon layer 166;
A fourth gate electrode 151 made of at least metal and formed around the fourth gate insulating film 155;
And a first pass transistor 150 configured by:
The seventh n + silicon layer 152 and the first gate wiring 132 are connected via a wiring 156, a contact 157, a wiring 159, and a contact 158,
A power supply voltage is applied to the sixth n + silicon layer 153.

The SGT pass transistor is not required for each static memory cell, but may be provided at the end of the word line and may be provided at the end of the static memory cell array. That is, since at least one word line is required, the area for the step-down circuit can be reduced.
Further, since the body of the SGT is completely surrounded by the gate, the threshold voltage does not increase due to the back bias effect in principle. The increment A of the threshold voltage increased by the back bias effect is zero. In other words, a constant threshold voltage can always be set, and when SGT is used as a pass transistor, a static memory cell that ensures operational stability can be provided.

Further, the sixth n + silicon layer 153 and the first gate wiring 132 are connected by wiring,
A power supply voltage may be applied to the seventh n + silicon layer 152.
Since the electrode used as the gate electrode of the SGT pass transistor determines the threshold voltage of the transistor by the work function, at least a metal or a metal compound is preferable.
Further, when the current driving capability of the SGT pass transistor is insufficient, there may be a plurality of SGT pass transistors.

  It should be noted that the present invention can be variously modified and modified without departing from the broad spirit and scope of the present invention. The above-described embodiment is for explaining an example of the present invention, and the technical scope of the present invention is not limited by the above-described embodiment. In addition, in the above description, it is obvious to those skilled in the art that p-type (including p + type) and n-type (including n + type) are each in the opposite conductivity type and are also included in the technical scope of the present invention. is there.

101. Driver transistor 102. Load transistor 103. Select transistor 104. Select transistor 105. Load transistor 106. Driver transistor 107. Island-like silicon layer 108. Island-like silicon layer 109. Island-like silicon layer 110. Island-like silicon layer 111. Island-like silicon layer 112. Island-like silicon layer 113. Gate insulating film 114. Gate insulating film 115. Gate insulating film 116. Gate insulating film 117. Gate insulating film 118. Gate insulating film 119. n + silicon layer 120. p + silicon layer 121. n + silicon layer 122. n + silicon layer 123. p + silicon layer 124. n + silicon layer 125. Gate electrode 126. Gate electrode 127. Gate electrode 128. Gate electrode 129. Gate electrode 130. Gate electrode 131. Gate wiring 132. Gate wiring 133. Gate wiring 134. Gate wiring 135. n + silicon layer 136. p + silicon layer 137. n + silicon layer 138. n + silicon layer 139. p + silicon layer 140. n + silicon layer 141. Wiring 142. Wiring 143. Wiring or contact 144. Wiring or contact 145. GND line 146. Power line 147. Bit line 148. Bit line 149. GND line 150. Pass transistor 151. Gate electrode 152. n + silicon layer 153. n + silicon layer 154. Island-like silicon layer 155. Gate insulating film 156. Wiring 157. Contact 158. Contact 159. Wiring 160. p silicon layer 161. n silicon layer 162. p silicon layer 163. p silicon layer 164. n silicon layer 165. p silicon layer 166. p silicon layer

Claims (4)

A first island-like semiconductor layer;
A first first-conductivity-type high-concentration semiconductor layer formed on the first island-shaped semiconductor layer;
A second first-conductivity-type high-concentration semiconductor layer formed under the first island-shaped semiconductor layer;
A first second conductivity type semiconductor layer formed between the first first conductivity type high concentration semiconductor layer and the second first conductivity type high concentration semiconductor layer;
A first gate insulating film formed around the first second conductivity type semiconductor layer;
A first gate electrode made of at least metal and formed around the first gate insulating film;
A first driver transistor comprising:
A second island-like semiconductor layer;
A third first-conductivity-type high-concentration semiconductor layer formed on the second island-shaped semiconductor layer;
A fourth first-conductivity-type high-concentration semiconductor layer formed under the second island-shaped semiconductor layer;
A second second conductive semiconductor layer formed between the third first conductive high concentration semiconductor layer and the fourth first conductive high concentration semiconductor layer;
A second gate insulating film formed around the second second conductivity type semiconductor layer;
A second gate electrode made of at least metal and formed around the second gate insulating film;
A first selection transistor comprising:
A third island-like semiconductor layer;
A third second-conductivity-type high-concentration semiconductor layer formed on the third island-shaped semiconductor layer;
A fourth second-conductivity type high-concentration semiconductor layer formed under the third island-shaped semiconductor layer;
A fifth first conductivity type semiconductor layer formed between the third second conductivity type high concentration semiconductor layer and the fourth second conductivity type high concentration semiconductor layer;
A third gate insulating film formed around the fifth first conductivity type semiconductor layer;
A third gate electrode made of at least metal and formed around the third gate insulating film;
A first load transistor comprising:
A first gate line connected to the second gate electrode;
A six-transistor SRAM cell comprising:
The peripheral length of the first island-shaped semiconductor layer is less than twice the peripheral length of the second island-shaped semiconductor layer,
The voltage applied to the second gate electrode is
It is lower than the voltage applied to the third first conductivity type high concentration semiconductor layer,
further,
A fourth island-shaped semiconductor layer;
A sixth first-conductivity type high-concentration semiconductor layer formed on the fourth island-shaped semiconductor layer;
A seventh first conductivity type high-concentration semiconductor layer formed under the fourth island-shaped semiconductor layer;
A fifth second conductivity type semiconductor layer formed between the sixth first conductivity type high concentration semiconductor layer and the seventh first conductivity type high concentration semiconductor layer;
A fourth gate insulating film formed around the fifth second conductivity type semiconductor layer;
A fourth gate electrode made of at least metal and formed around the fourth gate insulating film;
A first pass transistor configured with:
The seventh first conductivity type high concentration semiconductor layer and the first gate wiring are connected by wiring, and a power supply voltage is applied to the sixth first conductivity type high concentration semiconductor layer,
A voltage lower than the power supply voltage is output to the seventh first conductivity type high-concentration semiconductor layer.   The semiconductor device according to claim 1, wherein the voltage applied to the fourth gate electrode is the power supply voltage. A first island-like semiconductor layer;
A first first-conductivity-type high-concentration semiconductor layer formed on the first island-shaped semiconductor layer;
A second first-conductivity-type high-concentration semiconductor layer formed under the first island-shaped semiconductor layer;
A first second conductivity type semiconductor layer formed between the first first conductivity type high concentration semiconductor layer and the second first conductivity type high concentration semiconductor layer;
A first gate insulating film formed around the first second conductivity type semiconductor layer;
A first gate electrode made of at least metal and formed around the first gate insulating film;
A first driver transistor comprising:
A second island-like semiconductor layer;
A third first-conductivity-type high-concentration semiconductor layer formed on the second island-shaped semiconductor layer;
A fourth first-conductivity-type high-concentration semiconductor layer formed under the second island-shaped semiconductor layer;
A second second conductive semiconductor layer formed between the third first conductive high concentration semiconductor layer and the fourth first conductive high concentration semiconductor layer;
A second gate insulating film formed around the second second conductivity type semiconductor layer;
A second gate electrode made of at least metal and formed around the second gate insulating film;
A first selection transistor comprising:
A third island-like semiconductor layer;
A third second-conductivity-type high-concentration semiconductor layer formed on the third island-shaped semiconductor layer;
A fourth second-conductivity type high-concentration semiconductor layer formed under the third island-shaped semiconductor layer;
A fifth first conductivity type semiconductor layer formed between the third second conductivity type high concentration semiconductor layer and the fourth second conductivity type high concentration semiconductor layer;
A third gate insulating film formed around the fifth first conductivity type semiconductor layer;
A third gate electrode made of at least metal and formed around the third gate insulating film;
A first load transistor comprising:
A first gate line connected to the second gate electrode;
A six-transistor SRAM cell comprising:
The peripheral length of the first island-shaped semiconductor layer is less than twice the peripheral length of the second island-shaped semiconductor layer,
The voltage applied to the second gate electrode is
It is lower than the voltage applied to the third first conductivity type high concentration semiconductor layer,
further,
A fourth island-shaped semiconductor layer;
A sixth first-conductivity type high-concentration semiconductor layer formed on the fourth island-shaped semiconductor layer;
A seventh first conductivity type high-concentration semiconductor layer formed under the fourth island-shaped semiconductor layer;
A fifth second conductivity type semiconductor layer formed between the sixth first conductivity type high concentration semiconductor layer and the seventh first conductivity type high concentration semiconductor layer;
A fourth gate insulating film formed around the fifth second conductivity type semiconductor layer;
A fourth gate electrode made of at least metal and formed around the fourth gate insulating film;
A first pass transistor configured with:
The sixth first-conductivity-type high-concentration semiconductor layer and the first gate wiring are connected by wiring, and a power supply voltage is applied to the seventh first-conductivity-type high-concentration semiconductor layer;
A voltage lower than the power supply voltage is output to the sixth first conductivity type high concentration semiconductor layer.   The semiconductor device according to claim 3, wherein the voltage applied to the fourth gate electrode is the power supply voltage.

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