JP2008205168A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the formation area of a CMOS inverter circuit using a vertical transistor. <P>SOLUTION: pMOS and nMOS transistors Tr1 and Tr2 in which p-type and n-type impurity regions 1p and 1n are formed on an element forming region 5 defined by an insulated separation band 2 and which use the regions as drain regions and use a nanowire 3 provided on the drain regions as a channel are provided on a semiconductor substrate 1. A connection region 4 in ohmic contact with the impurity regions 1p and 1n is formed on the front surface of the element forming region 5. The connection region 4 is connected with an output signal via 16 on the outside of the transistors Tr1 and Tr2. Further, an input signal via 17 is connected to gate electrode wiring 15 to which a gate electrode 13 is connected of the transistors Tr1 and Tr2. If there is a region for forming the two transistors and the two via holes, the CMOS circuit can be formed. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device capable of forming a CMOS inverter circuit in a small area region using a vertical transistor including a nanowire or a nanotube as a channel formation region and a gate electrode around the channel formation region, and a manufacturing method thereof.

  Although it is now possible to form a pattern of several tens of nanometers with the progress of photolithography, it is very difficult to industrially manufacture a MOS transistor having a gate length of several tens of nanometers or less using photolithography. Therefore, as a method for manufacturing a MOS transistor having a small element area without using photolithography, a nanowire transistor or a nanotube transistor using a nanowire or a nanotube as a channel formation region has attracted attention. In particular, a vertical transistor in which a channel is arranged perpendicular to the substrate surface and a source / drain is arranged at the upper and lower ends thereof is arranged so that the nanowires constituting the source / drain regions and the channel are superimposed, so that the transistor occupying the semiconductor substrate The area of the formation region can be extremely reduced.

  FIG. 20 is a cross-sectional view of a conventional semiconductor device and shows the structure of a transistor used in a semiconductor device using a nanowire transistor or a nanotube transistor. 20A shows a conventional first semiconductor device transistor using a vertical nanotube transistor as a switching element, and FIG. 20B shows a conventional CMOS circuit using a nanowire transistor parallel to the substrate surface. FIG. 20C shows one vertical nanowire transistor constituting a CMOS circuit included in the conventional third semiconductor device.

  Referring to FIG. 20A, in the first conventional semiconductor device, a carbon nanotube 107 is erected on a source electrode 103 formed on the surface of a substrate 101, and a drain electrode 104 is disposed on the upper end thereof. . Note that an insulating film 102 having a small hole 102 a through which the carbon nanotube 107 passes is provided on the substrate 101, and a gate electrode 105 is provided on the insulating film 102. Further, the drain electrode 104 is formed on the insulating film 102 and on the nonconductive thin film 106 in which the carbon nanotube 107 and the gate electrode 105 are flatly embedded. (For example, refer to Patent Document 1).

  In the conventional nMOS transistor of the first semiconductor device, the source / drain regions are arranged so as to overlap the upper and lower ends of the carbon nanotube 107 where the channel is formed. In this vertical nanotube nMOS transistor, an nMOS transistor can be formed in one source or drain region. Therefore, compared to a planar MOS transistor in which source / drain electrodes and a channel region are arranged in a plane on the substrate surface. The area of the formation region can be greatly reduced.

  However, for high integration of elements, it is indispensable not only to reduce the element area but also to reduce power consumption. For this reason, CMOS circuits with low power consumption are widely used in highly integrated semiconductor devices. In the conventional first semiconductor device described above, a single nMOS transistor is provided as a switching element, and no pMOS transistor is provided, so that a CMOS circuit cannot be formed.

  FIG. 19 is a circuit diagram of a CMOS circuit. FIG. 19A is a CMOS inverter circuit, and FIG. 19B is a CMOS flip-flop in which the input / output terminals of two CMOS inverter circuits are connected to so-called “shaking”. FIG. 19C shows an SRAM memory cell circuit using the CMOS flip-flop circuit of FIG. 19B as a storage element.

  Referring to FIG. 19, the CMOS circuit is an inverter circuit including a series connection of pMOS transistors Tr1 and Tr3 and nMOS transistors Tr2 and Tr4 whose gate electrodes are connected to each other and whose drains are connected to nodes N, N1, or N2. As a basic circuit. The source electrodes of the pMOS transistors Tr1 and Tr3 and the nMOS transistors Tr2 and Tr4 are connected to the circuit power supply Vdd and the circuit ground Vss, respectively.

  A second conventional semiconductor device in which such a CMOS circuit is configured using nanowire MOS transistors is disclosed. (For example, refer to Patent Document 2).

  Referring to FIG. 20B, in the conventional second semiconductor device, source / drain electrodes 111 having a planar pattern are formed on a substrate 101. Then, the source / drain electrodes 111 are bridged by semiconductor nanowires 112 grown using the catalyst spheres 113, and a gate electrode 115 is provided on the nanowires 112 via an insulating film 114. On the substrate 101, a pMOS transistor 110p using the nanowire 112 doped with an n-type impurity as a channel region and an nMOS transistor 110p using the nanowire 112 doped as a p-type impurity as a channel region are formed. The CMOS inverter circuit is formed by connecting the pMOS transistor 110p and the nMOS transistor 110p in series.

  This CMOS circuit requires four source / drain electrodes 111 arranged in a plane and two channel forming regions. Further, in order to connect the source / drain electrode 111 to the upper layer wiring, one via formation region 113b is required for each source / drain electrode, and the drain electrode 111 becomes larger. A CMOS circuit using such a planarly configured MOS transistor requires two large-area source / drain electrodes 111 and one channel region for each of the nMOS transistor and the pMOS transistor. Compared to it, it is difficult to reduce the element area.

  Further, a third conventional semiconductor device that constitutes a CMOS circuit using vertical nanowire transistors is disclosed. (For example, refer to Patent Document 3).

  With reference to FIG. 20C, a conventional MOS transistor of a third semiconductor device will be described along the manufacturing process thereof.

First, a high concentration impurity region 129a is formed on the upper surface of the semiconductor substrate 121, and a silicide film 129 grown epitaxially is formed on the upper surface. Next, a SiO ₂ insulating film 122 and a Si ₃ N ₄ insulating film 124 are deposited on the upper surface of the semiconductor substrate 121, and an opening 131 is formed through the insulating films 122 and 124 to expose the high-concentration impurity region 129a. Next, an insulating film that covers the surface of the opening 131 including the bottom surface of the opening 131 is deposited to form a nanotube growth mask 122a in which a plurality of openings are formed. Next, a catalytic metal is placed in the opening of the mask 122a, and silicon is epitaxially grown using the catalytic metal as a catalyst, for example, by epitaxial growth of silicon by a CVD method (chemical vapor deposition method), so that the opening is perpendicular to the opening of the mask 122a. The silicon nanowire 120 to be erected is formed.

  Next, a gate insulating film 123 covering the inner surface of the opening 131 and the exposed surface of the nanowire 120 is deposited. Next, a gate electrode 124 is formed around the nanowire 120 so as to fill the middle of the opening 131.

  Next, an insulating film 130 that covers the gate electrode 124 and fills the opening 131 is deposited and planarized to expose the upper end of the nanowire 120, and a silicide film 127 to be a source / drain electrode is formed on the upper end of the nanowire 120. Further, a via hole 126 a connected to the gate electrode 124 is formed in the insulating film 130. Next, a drain electrode wiring connected to the silicide film 127 and a gate electrode wiring 126 connected to the gate electrode 124 through the via hole 126a are formed on the insulating film 130. Through the above process, a vertical nanowire transistor is manufactured.

  In order to construct a CMOS inverter circuit with this conventional third semiconductor device, two p-type and n-type MOS transistors must be manufactured in independent element formation regions and connected using wiring. Don't be. For example, in the CMOS inverter circuit shown in FIG. 19A, the drain electrodes of both the transistors Tr1 and Tr2 are formed on the insulating films 125 and 130 in order to connect the drain of the pMOS transistor Tr1 and the drain of the nMOS transistor Tr2. The drain electrode wiring 128 is connected. Further, in order to transmit the input signal to the gate electrodes 124 of both transistors Tr1 and Tr2, the gate electrodes 124 of both transistors Tr1 and Tr2 are connected by a gate electrode wiring 126. In addition, in order to connect the sources of these transistors Tr1 and Tr2 to the circuit power supply Vdd and the circuit ground Vss, vias (contact holes) are formed which penetrate the insulating film 125 and connect to the silicide film 129 formed on the surface of the semiconductor substrate 121. ) Must be provided.

That is, in each of the pMOS and nMOS transistors Tr1 and Tr2, at least one contact hole connected to the source, at least one via hole connected to the source / drain region and the gate electrode for standing at least one nanowire. A region for forming 126a is provided. The minimum area Δ of the region necessary for forming these contact holes, via holes 126a, or nanowires is limited by the limit of lithography, and it is difficult to make it smaller than this. For this reason, the area of the CMOS circuit of the conventional third semiconductor device cannot be made smaller than the area obtained by adding 3Δ for each of the pMOS and nMOS transistors Tr1 and Tr2, that is, 6Δ for the CMOS inverter circuit, plus the area of isolation. Can not.
JP 2002-110977 A JP 2006-140293 A Japanese Patent Laid-Open No. 2006-332662

  As described above, in the first conventional semiconductor device using the vertical nanotube nMOS transistor as a switching element, the element area can be reduced to the extent of the drain region, but a CMOS circuit with low power consumption cannot be configured. .

  Further, when the pMOS and nMOS transistors are formed in a planar manner as in the conventional second semiconductor device, the drain electrode, the source electrode, and the channel region (nanowire forming region) are disposed in a planar manner, which limits the lithography. Therefore, reduction of the element area is restricted.

    Furthermore, in the conventional third semiconductor device, the two vertical nanowire transistors constituting the pMOS and nMOS transistors are formed in separate element formation regions, which are isolated from each other. An area is required and it is difficult to sufficiently miniaturize the element. Further, in order to construct a CMOS inverter circuit composed of p-type and n-type transistors connected in series with the source electrode connected to the circuit power supply Vdd and the circuit ground Vss and the gate electrode connected in common, contact is made on the source electrode. A via hole must be formed for each transistor in the hole and on the gate electrode wiring, and the area of the formation region of the CMOS inverter circuit cannot be sufficiently reduced.

  In the first conventional semiconductor device, even if an nMOS and a pMOS are manufactured in the same manner to form a CMOS circuit, a contact hole is formed in the drain electrode and a via hole is formed in the gate electrode wiring. Therefore, it is necessary to add an area for each transistor, and the reduction of the area of the CMOS inverter circuit is restricted as in the conventional third semiconductor device.

  An object of the present invention is to provide a semiconductor device including a CMOS inverter circuit using a vertical MOS transistor having a nanowire or a nanotube as a channel region and having a small circuit formation area of the CMOS inverter circuit and a method for manufacturing the same. .

A semiconductor device according to a first configuration of the present invention for solving the above problem is a CMOS comprising a series connection of an nMOS transistor and a pMOS transistor in which a gate electrode is provided around a nanowire or a nanotube via a gate insulating film. Regarding a semiconductor device provided with an inverter circuit,
The drains of the nMOS and pMOS transistors consist of n-type and p-type impurity regions formed on the surface of the semiconductor substrate that are ohmic-connected through the connection region, and the nanowire or nanotube in which the channel is formed is an n-type or p-type impurity. Each is erected on the area.

  The source is formed at the upper end of the nanowire or nanotube, and the gate electrodes of the nMOS and pMOS transistors are connected to each other by a gate electrode wiring. This gate electrode wiring is formed on, for example, a buried insulating film that embeds the lower part of the nanowire or nanotube.

  In the CMOS inverter circuit of the semiconductor device, the n-type and p-type impurity region types constituting the drains of the nMOS and pMOS transistors are ohmically connected through the connection region, and the drains of these transistors are not insulated and separated. Therefore, these n-type and p-type impurity region types can be formed in the same element formation region. As described above, since it is not necessary to isolate and isolate the element formation regions of the nMOS and pMOS transistors in one element formation region, the conventional method of forming the nMOS and pMOS transistors in the individual element formation regions, respectively. Compared with, the circuit formation area of the CMOS inverter circuit can be reduced. Note that an element formation region in this specification refers to a region on the surface of a semiconductor substrate that is insulated and separated by an insulating separation band.

  In addition, since the n-type and p-type impurity region types constituting the drains of the nMOS and pMOS transistors are ohmically connected to each other, it is necessary to provide a contact hole forming region to connect between the drains of the nMOS and pMOS transistors. There is no. Therefore, the area of the drain or drain electrode can be reduced as compared with a conventional semiconductor device that requires a contact hole for connection between drains.

  As described above, according to the semiconductor device having the first configuration including the CMOS inverter circuit of the present invention, the minimum area in which two drains are formed in one element formation region and the drain or drain electrode forms the nanowire. Therefore, the CMOS circuit formation region can be made smaller than the conventional semiconductor device in which each transistor is formed in an individual element formation region.

  The second configuration of the present invention relates to a semiconductor device having a flip-flop circuit formed by “shaping” two CMOS inverter circuits. Note that “shaking of inverter circuits” refers to wiring that connects the outputs of one inverter to the other input.

  In the second configuration, the CMOS inverter circuit having the second configuration is used as the CMOS inverter circuit configuring the flip-flop circuit.

  In the two element formation regions constituting the two CMOS inverter circuits, n-type and p-type impurity regions and connection regions for ohmic connection thereof are provided, respectively, and contact hole formation regions are provided respectively. It is done. This contact hole formation region is a region in which the connection region extends over the element formation region.

  Further, a buried insulating film is formed on the element formation region so as to bury the roots of the standing nanowire or nanotube. A contact hole that exposes the connection region is formed in the buried insulating film.

  On this buried insulating film, a gate electrode wiring is formed which connects between the gate electrodes of the pMOS and nMOS transistors formed in one element formation region and connects to the connection region through a contact hole. One of the gate electrode wirings connects between the gate electrodes of the pMOS and nMOS transistors formed in one element formation region, and is connected to another element formation region formed adjacently, that is, another element. It is ohmically connected to the drains of the pMOS and nMOS transistors formed in the formation region.

  Similarly, the other gate electrode wiring connects between the gate electrodes of the pMOS and nMOS transistors formed in the other element formation regions, and is connected to the one element formation region formed adjacently, that is, Ohmic connection is made to the drains of the pMOS and nMOS transistors formed in one element formation region.

  These connection regions form the output end of the CMOS inverter circuit, and the gate electrode wiring forms the input end. Accordingly, the two CMOS inverter circuits are connected to each other by the gate electrode wiring to form a CMOS flip-flop circuit.

  In the second configuration of the present invention, the area for forming the CMOS flip-flop circuit is sufficient if it has an area for forming two contact holes in addition to two nMOS transistors and two pMOS transistors. That is, a flip-flop circuit can be formed by increasing the formation area of two CMOS inverters by one contact hole.

  Note that a via connected to the wiring serving as the input / output terminal of the flip-flop circuit may be formed on the upper surface of the gate electrode wiring immediately above the contact hole. As a result, it is not necessary to add a via formation area for input / output of the flip-flop circuit, and a small-area flip-flop circuit can be realized.

  The third configuration of the present invention relates to a semiconductor device using the CMOS flip-flop circuit of the second configuration of the present invention as an SRAM memory cell.

  The semiconductor device having the third configuration includes a memory cell in which a pair of bit lines are connected to each of two nodes of a CMOS flip-flop circuit connected to an input / output terminal through an access transistor. The gate of this access transistor is connected to the word line.

  The access transistor has an n-type or p-type impurity region serving as a source / drain in each element formation region of the two CMOS inverter circuits constituting the flip-flop circuit, and a nanowire standing on the impurity region Alternatively, a gate electrode provided with a nanotube as a drain and a gate insulating film around the nanowire or the nanotube is provided. The gate electrode is connected to an upper word line through a word line connection wiring disposed on the buried insulating film and vias formed on the word line connection wiring.

  In the third configuration of the present invention, since the access transistor is also disposed in the element formation region of the CMOS inverter circuit, the drain formation region of the access transistor and the word line connection wiring are added to the CMOS flip-flop circuit of the second configuration of the present invention. An SRAM memory cell can be configured simply by adding a via formation region for connection to the memory cell. For this reason, a memory cell having a very small area can be realized as compared with a memory cell using a conventional independent transistor.

  The fourth configuration of the present invention relates to the method of manufacturing the semiconductor device having the first to third configurations of the present invention described above, and forms nanowires or nanotubes using a selective growth mask (insulating film) in the element formation region. After that, a gate insulating film and a silicon film are sequentially formed so as to cover the nanowire or the nanotube and the mask upper surface, and the silicon film and the gate insulating film are selectively etched, for example, by silicon. Etch with

  As a result, the gate insulating film around the nanowire or nanotube and the silicon film around the nanowire or nanotube are left, and the other silicon film and gate insulating film are removed. At this time, the silicon film around the upper end of the nanowire or nanotube is also removed. As a result, the gate electrode is formed at a position lower than the upper end of the nanowire or nanotube. Note that the gate insulating film is exposed in the removed portion.

  Next, the mask is etched by isotropic etching using nanowires or nanotubes, a silicon film, and a gate insulating film as an etching mask. As a result, the mask on the region where the nanowire or the nanotube is not formed is removed, and the surface of the semiconductor substrate is exposed.

  Next, a silicide film is formed on the upper end of the nanowire or nanotube, the silicon film, and the exposed surface of the semiconductor substrate by, for example, a salicide method (self-aligned silicide formation). As a result, a pMOS and an nMOS transistor are formed in which the upper end of the nanowire or nanotube is the source electrode, the surrounding silicide film is the gate electrode, the nanowire or nanotube is the channel, and the p-type and n-type impurity regions are the drains, respectively. At the same time, the silicide film formed on the surface of the semiconductor substrate becomes a connection region for ohmic connection between the p-type and n-type impurity regions.

  In the fourth configuration, the silicon film and the gate insulating film are etched using selective anisotropic etching of silicon. As a result, the silicon film in the vicinity of the peripheral tip of the nanowire or nanotube is removed leaving the gate insulating film, so that the silicide film formed on the top and the periphery of the nanowire or nanotube by the subsequent salicide method, that is, the source electrode and the gate electrode , Short circuit can be avoided.

  Also, since the surface of the semiconductor substrate in the region where the nanowire or nanotube is not formed is self-aligned and silicidized simultaneously with the upper end of the nanowire or nanotube and the silicon film, a special process for forming the connection region is added. The connection region can be formed without any problem.

In the method for manufacturing a semiconductor device having the fourth structure according to the present invention,
After the step of forming the connection region, a buried insulating film is formed that embeds the lower part of the nanowires or nanotubes constituting the p-type and n-type MOS transistors, and the gates of the p-type and n-type MOS transistors are formed on the buried insulating film. You may form the gate electrode wiring which connects between electrodes.

  In this method, since the gate electrode wiring is disposed on the buried insulating film, the parasitic capacitance of the gate electrode wiring can be reduced. The buried insulating film can be easily formed by depositing the nanowire or nanotube until they are covered and then flattening and then etching back the entire surface. Alternatively, the embedded insulating film may be deposited on the semiconductor substrate exposed between the upper ends of the nanowires or nanotubes and the nanowires or nanotubes using a highly directional deposition method. According to this method, after the conductive film is embedded and similarly deposited on the insulating film, the conductive film deposited on the upper end of the nanowire or nanotube can be removed by lift-off. For this reason, it is easy to form a gate electrode wiring made of a conductive film.

  According to the present invention, an nMOS transistor and a pMOS transistor having a nanowire or a nanotube provided vertically as a channel are formed in the same element formation region with the source region being in ohmic contact with each other. The formation area of the circuit including the CMOS inverter configured as described above can be made smaller than the configuration using a MOS transistor formed in a plane or a MOS transistor formed in an individual element formation region.

  The first embodiment of the present invention relates to a semiconductor device including the CMOS inverter circuit shown in FIG.

  FIG. 1 is a structural diagram of a CMOS inverter circuit according to a first embodiment of the present invention, and shows a cell structure of a semiconductor device having a CMOS inverter circuit as a cell. Here, FIG. 1A is a vertical sectional view taken along line BB ′ in FIG. 1B, FIG. 1B is a horizontal sectional view taken along line AA ′ in FIG. 1A, and FIG. It is a perspective view showing arrangement | positioning of a via | veer. Note that FIG. 1C is drawn excluding various insulating films for the sake of clarity.

  Referring to FIGS. 1A to 1C, a rectangular CMOS inverter circuit cell 10 is provided in a matrix on a semiconductor substrate 1 made of a semiconductor, for example, silicon, and is defined by an insulating separation band 2 therein. The formed element formation region 5 is formed. The element formation region 5 is arranged leaving a size that allows the via 17 to be formed at one end thereof. The insulating separator 2 is formed by, for example, LOCOS or shallow trench (STI).

  N-type and p-type impurity regions 1n and 1p are formed on the surface of the semiconductor substrate 1 in the element formation region 5, and channels of nMOS and pMOS transistors Tr2 and Tr1 are formed on the impurity regions 1n and 1p, respectively. A semiconductor, for example, silicon nanowire 3 is erected.

  A mask 11 made of an insulating film (a part of the growth mask 11) is left around the bottom of the nanowire 3, and a gate insulating film 12 is provided around the nanowire 3 thereabove. Further, a gate electrode 13 made of a conductive film, for example, a gate electrode 13 made of a silicide film or a polycide film is formed on the gate insulating film 12. The gate electrode 13 is not provided on the upper end portion of the nanowire 3. Thereby, a short circuit with the source electrode 14 formed at the upper end of the nanowire 3 is prevented. In addition, since the lower end of the gate electrode 13 is formed on the mask 11, a short circuit between the connection region 4 formed on the surface of the element formation region 5 and the gate electrode 13 is prevented.

  The surface of the element formation region 5 is covered with a connection region 4 made of a silicide film formed on the surfaces of the impurity regions 1n and 1p except for the portion directly below the mask 11 and the portion directly below the nanowire 3 remaining around the bottom of the nanowire 3. . Here, in order to reduce the drain resistance, it is preferable that the bottom end of the nanowire 3 is doped with the impurity element diffused from the impurity regions 1n and 1p to form a part of the drain region. Note that even if the impurity regions 1n and 1p are not present under the connection region 4, it does not matter if the ohmic resistance at the junction with these regions is low.

  The upper end of the nanowire 3 is a source electrode 14 made of a silicide film.

  A buried insulating film 6 and an insulating film 7 are provided in this order on the semiconductor substrate 1 so as to bury the nanowire 3 up to the upper surface of the source electrode 14, and an interlayer insulating film 8 is further provided thereon. The interlayer insulating film 8 can be omitted. The buried insulating film 6 has a thickness for embedding the bottom of the gate electrode 13, on which two gate electrodes 13 are connected, and a gate electrode wiring 15 extending on the element isolation band 2 is provided. By disposing the buried insulating film 6 in this way, the parasitic capacitance between the gate electrode wiring 15 and the semiconductor substrate 1 can be reduced.

  The nMOS transistor Tr2 and the source electrode 14 of the pMOS transistor Tr1 formed in the n-type and p-type impurity regions 1n and 1p, respectively, are connected to the interlayer insulating film 8 via vias 18 and 19 formed in the interlayer insulating film 8, respectively. The circuit ground Vss and the circuit power supply Vdd provided above are connected to the low voltage wiring 22 and the high voltage wiring 23 supplied thereto.

  Further, a contact hole penetrating the interlayer insulating film 8, the insulating film 7, and the buried insulating film 6 is provided, and connected to the output wiring 21 provided on the interlayer insulating film 8 through the via 16 filling the contact hole. Area 4 (node N in FIG. 19) is connected.

  Further, the input wiring disposed on the gate electrode wiring 15 and the interlayer insulating film 8 via the interlayer insulating film 8 and the via 17 penetrating the insulating film 7 on the gate electrode wiring 15 extending on the element isolation band 2. 24 is connected.

  Referring to FIGS. 1B and 1C, the via 16, the two source electrodes 14 of the nMOS and pMOS transistors Tr2 and Tr1, and the via 17 are arranged along the long side of the cell 10 in this order. Arranged in a row. Therefore, if the minimum area of the formation region of the vias 16 and 17 and the two nanowires 3 (that is, the channel formation regions of the transistors Tr1 and Tr2) is Δ, the minimum area of the formation region of the CMOS inverter circuit according to the first embodiment. Becomes 4Δ. This is reduced to 2/3 compared with the minimum area 6Δ of the CMOS inverter circuit forming region of the conventional first semiconductor device. Note that the reduction ratio is further reduced in consideration of the conventionally required insulation separation band for separating the transistors Tr1 and Tr2.

  Next, the manufacturing process of the semiconductor device of the first embodiment will be described.

  2 to 4 are manufacturing process diagrams of the first embodiment of the present invention, and show the manufacturing process of the CMOS inverter circuit. Here, FIGS. 2A to 4G show the plane of the CMOS inverter circuit cell, and FIGS. 2A-1 to 4G-1 show the straight line BB ′ in FIG. 2A. It represents a vertical section along.

  2A and 2A-1, first, a rectangular CMOS inverter circuit having a short side of 50 nm and a long side of 150 nm, for example, is formed on the upper surface of a semiconductor substrate 1 whose main surface is a semiconductor such as silicon (111). A cell 10 is defined, and a rectangular element forming region 5 having a short side of 30 nm and a long side of 100 nm, for example, defined by the insulating separation band 2 is formed in the cell 10.

  Next, an n-type impurity region 1n is formed by ion-implanting an n-type impurity in a region from the left end of the element formation region 5 to about 65 nm. Further, p-type impurity regions 1p are formed by ion-implanting p-type impurities into the remaining region on the right side of the element formation region. These impurity regions need only be formed in the standing region of the nanowire 3 described later, and do not necessarily have to be formed on the entire surface of the element formation region 5.

  Next, referring to FIGS. 2B and 2B-1, an amorphous silicon oxide film having a thickness of 10 nm to 20 nm, for example, is deposited. Thereafter, openings 11a and 11b having a diameter of approximately 20 nm that expose the n-type and p-type impurity regions 1n and 1p, respectively, are opened in the silicon oxide film, and a selective growth mask 11 made of an amorphous silicon oxide film is formed. . These openings 1 a and 1 b are arranged adjacent to the approximate center of the cell 10.

  Next, referring to FIGS. 2C and 2C-1, by selective growth using the mask 11, a semiconductor such as a silicon crystal is exposed from the surface of the semiconductor substrate 1 exposed on the bottom surfaces of the openings 11 a and 11 b. Is grown epitaxially to form a cylindrical nanowire 3 having a diameter of approximately 20 nm and a height of 100 nm that stands upright with the opening 11a and the opening 11b as bottom surfaces.

  Next, a gate insulating film 12 and a silicon film 13 a are sequentially deposited on the entire surface of the semiconductor substrate 1 so as to cover the exposed surface of the nanowire 3. The gate insulating film 12 is formed of, for example, a silicon thermal oxide film formed by thermal oxidation, a silicon oxide film formed by a CVD method, a silicon nitride film, or other high dielectric film (for example, Hf, Al, or La). Including oxides, silicates or nitrides). The silicon film 13a is made of a polysilicon film or an amorphous silicon film, and can be formed by, for example, a CVD method.

  Next, the entire surface of the silicon film 13 a is etched using anisotropic ion etching that selectively etches silicon with respect to the gate insulating film 12. In this anisotropic ion etching step, first, the silicon film 13a is etched flat until the gate insulating film 12 on the upper surface of the nanowire 3 is exposed. Next, while the gate insulating film 12 exposed on the upper surface of the nanowire 3 is etched and removed, the silicon film 3 a extending around the nanowire 3 is etched flatly to a position slightly lower than the upper surface of the nanowire 3. This is because the silicon film 13a is etched (selectively) earlier than the gate insulating film 12.

  Further, referring to FIG. 3D and FIG. 3D-1, the above-described anisotropic ion etching is continued, and the gate insulating film 12 extending on the upper surface of the mask 11 outside the nanowire 3 is exposed. The silicon film 13a is removed until the gate insulating film is etched until the mask 11 is exposed or a part of the surface is etched. At the same time, the nanowire 3 is also etched at substantially the same speed as that of the silicon film 13a, so that the nanowire 3 has a height of about 70 nm.

  A gate insulating film 12 is left around the nanowire 3. Then, a side wall made of the silicon film 13 a is formed on the gate insulating film 12. The upper end of the silicon film 13a is etched by anisotropic ion etching, and the silicon film 13a is not formed at a distance within 20 nm from the upper end of the nanowire 3, for example. The distance at which the silicon film 13a is not formed can be controlled by selecting the selectivity of anisotropic ion etching.

  Next, isotropic etching using the nanowire 3, the gate insulating film 12 and the silicon film 13a as an etching mask is used to etch the mask 11 to expose the surface of the semiconductor substrate 1 (the surface of the element formation region 5). By over-etching the mask 11, the distance between the exposed surface of the semiconductor substrate 1 and the nanowire 3 can be controlled.

  Next, referring to FIGS. 3E and 3E-1, a so-called salicide process is performed in which a metal film, for example, a Ni film is deposited on the entire surface of the substrate, and the unreacted metal film is removed after the silicidation heat treatment. Then, a silicide film (for example, a Ni silicide film) serving as the source electrode 14, the gate electrode 13, and the connection region 4, respectively, is formed on the upper end of the nanowire 3, the silicon 13 a formed around the nanowire 3 and the exposed surface of the element formation region 5. Form.

  As a result, an nMOS transistor Tr2 having the nanowire 3 on the n-type impurity region 1n as a channel region and a pMOS transistor tr1 having the nanowire 3 on the p-type impurity region 1p as a channel region are manufactured. Note that the drains (respectively, n-type and p-type impurity regions 1n and 1p) of these transistors Tr2 and Tr1 are connected to each other via a connection region 4 that is in ohmic connection.

  The gate electrode 13 thus formed is formed from the surface of the semiconductor substrate 1 with the mask 11 and the gate insulating film being separated from each other, and the polysilicon film 13a at the upper end of the nanowire 3 is formed from the source electrode 14. It is formed at a distance that is not. Since these thicknesses and distances can be precisely controlled, vertical nanowire MOS transistors Tr1 and Tr2 in which the distance between the gate and the source / drain is precisely controlled are formed.

  It should be noted that the gate electrode 13 according to one embodiment of the present application may be entirely made of silicide, or may have a polycide structure in which only the surface is made of silicide.

  Next, referring to FIG. 4F and FIG. 4F-1, an embedded insulating film 6 made of, for example, a 30 nm-thickness silicon oxide film that fills the periphery of the bottom of the nanowire 3 is formed. The buried insulating film 6 is formed by depositing a silicon oxide film having a thickness of, for example, 30 nm on the entire surface of the semiconductor substrate 1 by a highly directional deposition method from above, for example, collimated sputtering, vapor deposition, or plasma chemical vapor deposition (PECVD). It is formed by depositing.

  At this time, a portion of the silicon oxide film that is deposited outside the nanowire 3 and becomes a buried insulating film is formed by being separated from the silicon oxide film deposited on the upper end of the nanowire 3 by a step formed by the height of the nanowire 3. Further, the silicon oxide film is isotropically etched in a small amount to remove the thin silicon oxide film attached around the nanowire 3 (the surface of the gate electrode 13). Thereby, the surface of the gate electrode 13 is exposed, and separation between the buried insulating film 6 and the silicon oxide film on the upper surface of the nanowire 3 can be ensured.

  Next, a conductive film, for example, an Al film having a thickness of 26 nm is deposited on the entire surface of the semiconductor substrate 1 by using a deposition method with high directivity from above. At this time, separated conductive films are formed on the outer side of the nanowire 3 and on the upper end of the nanowire 3, respectively. Next, the conductive film is patterned using photolithography to form a gate electrode wiring 15 made of the conductive film. The gate electrode wiring 15 is patterned so as to surround the nanowire 3 and to extend on the insulating separation band 2 at the right end of the cell 10.

  After the formation of the gate electrode wiring 15, the silicon oxide film deposited on the upper end of the nanowire is removed by etching, and at the same time, the conductive film thereon is lifted off and removed.

  Next, an insulating film 7 for embedding the nanowire 3 up to the upper end (upper surface of the source electrode 14) is deposited, and an interlayer insulating film 8 is deposited thereon. Next, vias 18 and 19 that pass through the interlayer insulating film 8 and connect to the source electrode 14 are formed. Further, simultaneously with the formation of the vias 18 and 19, the via 16 connected to the connection region 4 through the interlayer insulating film 7 and the buried insulating film 6 at the left end of the element formation region 5, and the interlayer insulation at the right end of the gate electrode wiring 15. A via 17 penetrating the film 7 is formed.

  Next, the low voltage wiring 22 and the high voltage wiring 23 are formed on the vias 18 and 19, respectively, and the output wiring 21 and the input wiring 24 are formed on the vias 16 and 17, respectively, thereby forming a CMOS inverter circuit. Thereafter, the semiconductor device of the first embodiment is manufactured through a necessary circuit manufacturing process.

  In the first embodiment described above, a silicon substrate is used as the semiconductor substrate 1, but a Ge substrate or a compound semiconductor substrate such as a III-V compound semiconductor substrate or an II-VI compound semiconductor substrate can also be used. In addition to silicon nanowires, nanowires made of compound semiconductors and carbon nanotubes can also be used. As is well known, these nanowires and nanotubes can be formed using a catalyst in addition to selective growth.

  The second embodiment of the present invention relates to a semiconductor device including a flip-flop circuit as a cell array.

  The semiconductor device of the second embodiment includes a CMOS flip-flop circuit shown in FIG. 19B as a cell. This flip-flop circuit is composed of two CMOS inverter circuits wired to each other.

  FIG. 5 is a structural diagram of a flip-flop circuit cell according to a second embodiment of the present invention. FIG. 5 (a) is a vertical sectional view and FIG. 5 (b) is a plan view. FIG. 5A shows a CC ′ cross section in FIG.

  In the second embodiment, referring to FIG. 5, a rectangular cell 30 is defined on the semiconductor substrate 1 as a flip-flop circuit formation region. In order to simplify the description, the cell 30 will be described by dividing it into six sections of two rows in the vertical direction and three columns in the left and right directions within the plane of FIG.

  5B, an element forming region 5A is provided which is connected to the upper left and lower two sections and the upper central section in the cell 30, and further to the right upper and lower two sections and the lower central section in the cell 30. A continuous element formation region 5B is provided.

  A p-type impurity region 1p is formed on the surface of the semiconductor substrate 1 in the upper half (upper partition portion) of the element formation regions 5A and 5B, and an n-type impurity region 1n is formed in the lower half. As in the first embodiment, the surfaces of the element formation regions 5A and 5B are formed with a connection region 4 made of a silicide film on the entire surface except for the nanowire (and mask 11) formation region.

  The nanowire 3 is erected in the section occupying the four corners of the cell 30, and the lower end thereof is in contact with the n-type or p-type impurity region 1p. As for these nanowires 3, referring to FIG. 19B as well, the upper left corner is the pMOS transistor Tr 1 of the first CMOS inverter circuit, and the lower left corner is the nMOS transistor Tr 2 of the first CMOS inverter circuit. It is composed. The upper right corner constitutes the pMOS transistor Tr3 of the second CMOS inverter circuit, and the lower right corner constitutes the nMOS transistor Tr4 of the second CMOS inverter circuit. That is, the transistors Tr1 and Tr2 constituting the first CMOS inverter circuit are provided in the element formation region 5A, and the transistors Tr3 and Tr4 constituting the second CMOS inverter circuit are provided in the element formation region 5B. The structures of these MOS transistors Tr1 to Tr4, for example, the structures of the drains (impurity regions 1p and 1n), the source electrode 14 and the gate electrode 13 are the same as those of the MOS transistors Tr1 and Tr2 of the first embodiment described above.

  Further, as in the first embodiment, a buried insulating film 6 that embeds the bottom of the nanowire 3 and a gate electrode wiring 15 formed on the buried insulating film 6 are provided.

  In the second embodiment, a contact hole 31a that exposes the connection region 4 is formed in the buried insulating film 6, and the gate electrode wiring 15 is connected to the connection region 4 through a via 31 that fills the contact hole 31a. .

  Two gate electrode wirings 15 are arranged, one of which is connected to the gate electrodes 13 of the pMOS and nMOS transistors Tr1 and Tr2 constituting the first CMOS inverter circuit, and further the element formation region of the second CMOS inverter circuit. A connection region 4 formed in 5B is connected via a via 31. This connection region 4 in the element formation region 5B constitutes a node N2 in FIG. The single gate electrode wiring 15 is formed as a Γ-shaped pattern extending to two sections on the left side of the cell 30 and one section on the upper center.

  The other gate electrode wiring 15 connects the gate electrodes 13 of the pMOS and nMOS transistors Tr3 and Tr4 constituting the second CMOS inverter circuit, and further, a connection region formed in the element formation region 5A of the first CMOS inverter circuit. 4 through a via 31. The connection region 4 in the element formation region 5A constitutes the node N1 in FIG. The other gate electrode wiring 15 is formed as a pattern obtained by rotating the Γ-shape extending to two sections on the left side of the cell 30 and one section on the upper center by 180 degrees.

  Furthermore, an insulating film 7 is formed on the semiconductor substrate 1 so as to cover the gate electrode wiring 15 and expose the source electrode 14 to bury the nanowire 3 flatly to the upper end thereof. In the second embodiment, a via 32 that penetrates the insulating film 7 and is connected to the upper surface of the gate electrode wiring 15 is formed. The via 32 is disposed immediately above the via 31. Therefore, even if the via 32 is provided, the cell area does not increase.

  The vias 32 described above are connected to the nodes N1 and N2, respectively, and are connected to the input terminal 201 and the output terminal 203 of the CMOS flip-flop circuit, respectively. The source electrodes 14 of the pMOS transistors Tr1 and Tr3 are connected to the high voltage wiring 23 to which the circuit power supply Vdd is applied, and the source electrodes 14 of the nMOS transistors Tr2 and Tr4 are connected to the low voltage wiring 22 connected to the circuit ground. The

  The cell area of the CMOS flip circuit of the second embodiment is 6Δ, where each section is the minimum area Δ required for forming the nanowire 3 or the vias 31 and 32. This is reduced to ½ of the cell area 12Δ of a conventional CMOS flip circuit requiring 3Δ for each transistor.

  Next, a manufacturing process of the semiconductor device according to the second embodiment described above will be described.

  FIG. 6 is a sectional view of a manufacturing process according to the second embodiment of the present invention, and FIG. 7 is a plan view of the manufacturing process of the second embodiment of the present invention. FIG. 6 shows a DD ′ vertical section in FIG.

  With reference to FIGS. 6A and 7A, two element forming regions 5A and 5B separated by the insulating separation band 2 are formed in a cell 30 defined on the surface of the semiconductor substrate 1. The element formation region 5A is formed so as to cover the left side and the lower center of the cell, and the element formation region 5B is formed so as to cover the right side and the upper center of the cell.

  Of the element formation regions 5A and 5B, the p-type impurity region 1p is formed by ion implantation in the portion occupying the upper half of the cell 30, and the n-type impurity region 1n is formed in the portion occupying the lower half.

  Nanowires 3 forming pMOS transistors Tr1 and Tr3 are formed at the left and right ends of the p-type impurity region 1p, and nanowires 3 forming nMOS transistors Tr2 and Tr4 are formed at the left and right ends of the n-type impurity region 1n, respectively. Further, the gate insulating film 12, the gate electrode 13, and the source electrode 14 are formed. Further, the connection region 4 is formed on the exposed surface of the element formation regions 5A and 5B. These manufacturing steps are performed in the same manner as the manufacturing steps of the first embodiment described above.

  Next, referring to FIG. 6B and FIG. 7B, as in the first embodiment, the buried insulating film 6 is deposited on the entire surface of the semiconductor substrate 1 using a highly directional deposition method. At this time, the insulating film 6 deposited on the upper end of the nanowire 3 is separated from the insulating film 6 formed on the surface of the semiconductor substrate 1.

  Next, a contact hole 31a that exposes the connection region is formed on the element formation regions 5A and 5B located at the upper and lower central portions of the cell 30 by photolithography.

  Next, referring to FIGS. 6C and 7C, a conductive film is deposited on the entire surface of the semiconductor substrate 1 by a highly directional deposition method, and the embedded insulating film 6 on the upper end of the nanowire 3 is removed to remove the conductive film. The conductive film is lifted off. Thereafter, the conductive film is patterned to form the gate electrode wiring 15.

  One gate electrode wiring 15 connects the gate electrodes 13 of the p-type MOS transistor Tr1 and the n-type MOS transistor Tr2 formed in the element formation region 5A, and further embeds and connects the contact hole 31a opened in the element formation region 5B. Patterned to connect to region 4. The other gate electrode wiring 15 connects the gate electrodes 13 of the p-type MOS transistor Tr3 and the n-type MOS transistor Tr4 formed in the element formation region 5B, and further embeds and connects the contact hole 31a opened in the element formation region 5A. Patterned to connect to region 4.

  After that, referring to FIG. 5, the insulating film 7 for embedding the nanowire 3 is formed, and a via 32 that penetrates the insulating film 7 and is connected to the upper surface of the gate electrode wiring 15 is formed immediately above the via 31. Next, the wiring connected to the input / output terminals 201 and 203, the high potential wiring 23, and the low potential wiring 22 are formed using normal multilayer wiring, and a semiconductor device including a CMOS flip-flop circuit is manufactured.

  FIG. 8 is a cross-sectional view of the manufacturing process of the second embodiment modification of the present invention, and shows another manufacturing method of the buried insulating film 6 and the gate electrode wiring 15 of the second embodiment.

  Referring to FIG. 8, after the steps shown in FIGS. 6A and 7A, an insulating film 6a having a flat surface covering nanowire 3 is formed on the entire surface of semiconductor substrate 1. Next, an etching mask 6b having an opening 31b is formed on the insulating film 6a. The opening 31 b is provided immediately above the contact hole 31 a to be formed in the buried insulating film 6. Further, by providing an inclined surface at the upper end of the opening 31b, for example, by forming the opening 31b in a funnel shape, the inclined surface can be formed on the upper portion of the contact hole 31a. Thereby, disconnection due to a step of the gate electrode wiring 15 formed thereon can be prevented.

  Next, the insulating film 6a is etched by whole surface etching using the etching mask 31b as a mask to form a buried insulating film 6 indicated by a dotted line in the drawing. A contact hole 31a is formed in the buried insulating film 6 by this one-time entire surface etching. Therefore, lithography for forming the contact hole 31a is not necessary.

  Next, as in FIG. 6C, a conductive film is deposited and patterned to form the gate electrode wiring 15. In this modification, since the insulating film 6a at the upper end of the nanowire 3 is removed, this conductive film is also deposited on the upper end of the nanowire. This conductive film can be left as part of the source electrode 14. Further, if not necessary, the insulating film 7 which embeds the nanowire 3 up to the upper end can be removed in a step of flattening. Thereafter, the semiconductor device of the modified example of the second embodiment is manufactured through the same process as that of the second embodiment.

  The third embodiment of the present invention relates to a semiconductor device including SRAM (Static Random Access Memory) cells.

  As shown in FIG. 19C, the SRAM cell circuit of the third embodiment includes a first CMOS inverter composed of a series circuit of a pMOS transistor Tr1 and an nMOS transistor Tr2, and a series circuit of a pMOS transistor Tr3 and an nMOS transistor Tr4. As a SRAM memory cell, a flip-flop circuit formed by connecting a second CMOS inverter composed of

  Then, it is connected to a pair of complementary bit lines B and / B via access transistors Tr5 and Tr6 connected to input / output nodes N1 and N2 of the flip-flop circuit, respectively. The gates of the access transistors Tr5 and Tr6 are connected to the word line W.

  9 is a cross-sectional view of the SRAM cell according to the third embodiment of the present invention, FIG. 10 is a plan view of the SRAM cell according to the third embodiment of the present invention, and FIG. 9 is a cross-section along the fold line EE ′ in FIG. 10A shows the structure of the upper wiring, and FIG. 10B shows the arrangement of the transistors and vias.

Referring to FIG. 10B, in the third embodiment, a substantially square SRAM cell 40 having a side length of 100 nm is defined on the surface of the semiconductor substrate 1.

On the left side of the cell 40, an access transistor Tr5, an nMOS transistor Tr2, and a pMOS transistor Tr1 are arranged in this order at a substantially equal interval, for example, a pitch of 30 nm, from the top to the bottom of the page. A pMOS transistor Tr3, an nMOS transistor Tr4, and an access transistor Tr6 are arranged in this order on the right side of the cell 40 from the top to the bottom of the drawing.

  Vias 32C, vias 31B, vias 31A, and vias 32D are formed on the straight line passing through the center of the cell 40 (the center line on the left and right of the cell 40) in order from the top, at substantially equal intervals, for example, at a pitch of 30 nm. . These vias 32C, 31B, 31A, and 32D will be described later. The via 31B is provided on a straight line connecting the nMOS transistor Tr2 and the pMOS transistor Tr3, and the via 31A is provided on a straight line connecting the pMOS transistor Tr1 and the nMOS transistor Tr4. Therefore, the columns of the left and right transistors Tr5, Tr2, Tr1, and Tr3, Tr4, Tr6 and the columns of the vias 32C, 31B, 31A, 32D are arranged 15 nm vertically, that is, ½ pitch apart. Yes.

  In the cell 40, two element forming regions 5A and 5B are formed. The element formation region 5A is formed so as to include the transistor columns Tr5, Tr2, Tr1 and the via 31A on the left side of the cell 40, and the element formation region 5B is formed on the transistor columns Tr3, Tr4, Tr6 and the via on the right side of the cell 40. It is formed so as to include 31B in the region.

  Referring to FIG. 9, element formation regions 5 </ b> A and 5 </ b> B that are element-isolated by insulating isolation band 2 are formed on the surface of semiconductor substrate 1. Element formation regions 5A and 5B are divided into n-type impurity region 1n and n-type impurity region 1p, and nMOS transistors Tr5, Tr2, Tr4 and Tr6 are formed on n-type impurity region 1n, and p-type impurity region 1p is formed. On the top, pMOS transistors Tr1 and Tr3 are formed.

  These transistors Tr1 to Tr6 have the same structure as the transistors of the first and second embodiments. That is, a p-type or n-type impurity region is used as a drain, a nanowire 3 standing on the drain is used as a channel formation region, and a gate electrode 13 provided around the nanowire 3 via a gate insulating film 12 is provided. As a source electrode 14, a silicide film formed on the upper end of the substrate is provided.

  Further, a connection region 4 made of a silicide film is formed on the surface of the element formation regions 5A and 5B exposed between the transistors Tr1 to Tr6. This connection region 4 is in ohmic contact with the p-type and n-type impurity regions 1p and 1n.

  Referring to FIGS. 9 and 10B, a buried insulating film 6 for embedding the base (bottom) of the nanowire 3 is provided on the entire surface of the semiconductor substrate 1 except for the nanowire 3 and the mask 11 remaining at the bottom of the nanowire 3. It is done. In the buried insulating film 6, a contact hole 31a that exposes the connection region 4 is formed at a position where the via 31A and the via 31B are formed.

  Gate electrode wirings 15 </ b> A to 15 </ b> D are provided on the buried insulating film 6. The gate electrode wiring 15A connects between the gate electrodes 13 of the pMOS transistor Tr1 and the nMOS transistor Tr2 constituting the CMOS inverter circuit formed on the element formation region 5A. Furthermore, it extends over the contact hole 31a opened on the element formation region 5B and is connected to the connection region 4 formed in the element formation region 5B through a via 31B filling the contact hole 31a. That is, the gate electrode wiring 15A connects the gate electrodes 13 of the transistors Tr1 and Tr2, and is connected to the node N2 (a node connected to the drain regions of the transistors Tr3 and Tr4).

  On the other hand, the gate electrode wiring 15B connects between the gate electrodes 13 of the pMOS transistor Tr3 and the nMOS transistor Tr4 constituting the CMOS inverter circuit formed on the element formation region 5B. Furthermore, it extends over the contact hole 31a opened on the element formation region 5A and is connected to the connection region 4 formed in the element formation region 5A via a via 31A filling the contact hole 31a. That is, the gate electrode wiring 15B connects the gate electrodes 13 of the transistors Tr3 and Tr4 and is connected to the node N1 (a node connected to the drain regions of the transistors Tr1 and Tr2). The gate electrode wirings 15A and 15B are formed by wiring two CMOS inverter circuits formed on the element formation regions 5A and 5B, thereby producing a CMOS flip-flop circuit.

  The gate electrode wiring 15C is connected to the gate electrode 13 of the nMOS access transistor Tr5 and extends onto the formation region of the via 32C. Similarly, the gate electrode wiring 15D is connected to the gate electrode 13 of the nMOS access transistor Tr6 and extends onto the formation region of the via 32C. The access transistors Tr5 and Tr6 are not limited to n-type but can be p-type. At this time, the drain becomes a p-type impurity region.

  An insulating film 7 covering the transistors Tr1 to Tr6 and having a flat upper surface is formed on the entire surface of the semiconductor substrate 1. Further, a flat interlayer insulating film 8 is formed on the insulating film 7. On the upper surface of the insulating film 7, a word line 26 (W) and a pair of bit lines 25 (B, / B) made of complementary signal lines are arranged. On the upper surface of the interlayer insulating film 8, a low voltage wiring 22 for supplying the circuit ground Vss and a high voltage wiring 23 for supplying the circuit power supply Vdd are disposed.

  Referring to FIGS. 9, 10A and 10B, vias that penetrate through the insulating film 7 and the interlayer insulating film 8 and connect the low potential wiring 22 to the source electrodes 14 of the nMOS transistors Tr2 and Tr4. 18 and a via 19 that connects the high-potential wiring 23 to the source electrodes 14 of the pMOS transistors Tr1 and Tr3 are provided. Furthermore, a via 20 is provided through the insulating film 7 to connect each of the pair of bit lines 25 (B, / B) to the source electrode 14 of the access transistors Tr5, Tr6. Also, vias 32C and 32D are provided through the insulating film 7 to connect the word line 26 to the upper surfaces of the gate electrode wirings 15C and 15D connected to the gate electrodes of the access transistors Tr5 and Tr6.

  The n-type impurity region 1n (impurity region at the lower end of the nanowire 3) constituting the drains of the access transistors Tr5 and Tr6 is connected to the impurity region 1n constituting the drains of other transistors in the same element formation region via the connection region 4. Connected to 1p. As a result, referring to FIGS. 19C and 10A, the drains of access transistors Tr5 and Tr6 are connected to nodes N1 and N2, respectively. Therefore, a pair of complementary bit lines 25 are connected to the input / output ends of the flip-flop circuit via the access transistors Tr5 and Tr6. This input / output operation is controlled by a signal on the word line 26 connected to the gate electrodes 13 of the access transistors Tr5 and Tr6.

  According to the third embodiment described above, the area of the SRAM cell can be formed by the sum 9Δ of the area 6Δ for forming six transistors and the area 3Δ for forming three vias. Here, the areas of the vias 32 </ b> C and 32 </ b> D were calculated as being shared with the cells 40 adjacent vertically. Even when the via 32C and the via 32D are provided for each cell, the cell area can be set to 9Δ by arranging the vertically adjacent cells by shifting by half the horizontal width of the cell (left and right width). it can. This is because in a conventional semiconductor device in which transistors are formed in independent element formation regions and each transistor requires an area of 3Δ, an SRAM cell using six transistors Tr1 to Tr6 requires a cell area of 18Δ at the minimum. Compared to ½, it is reduced to ½.

  Next, the manufacturing process of the semiconductor device of the third embodiment described above will be described.

  FIGS. 11 to 14 are sectional views (part 1) to (part 4) of the manufacturing process of the third embodiment of the present invention, and FIGS. No. 4), which shows the structure of the SRAM cell region being manufactured. FIGS. 11A to 14L correspond to the steps of FIGS. 15A to 18L, respectively. FIG. 11A to FIG. 14L represent vertical sections at positions along the fold line EE ′ in FIG.

  Referring to FIGS. 11A and 15A, first, two element formation regions separated by an insulating isolation band 2 inside the SRAM cell 40 defined on the surface of the semiconductor substrate 1 made of silicon. 5A and 5B are formed.

  Next, referring to FIG. 11B and FIG. 15B, p-type impurities are ion-implanted into the element formation regions 5A and 5B using an ion implantation mask 41p having an oblique Z-shaped opening 41po. A p-type impurity region 1p is formed in the pMOS transistors Tr1 and Tr3 formation region and the vias 31A and 31B formation regions 42A and 42B on the surface of the element formation regions 5A and 5B.

  Next, referring to FIG. 11C and FIG. 15C, using an ion implantation mask 41n having an opening 41no that exposes the element formation regions 5A and 5B where the p-type impurity region 1p is not formed. An n-type impurity is ion-implanted to form an n-type impurity region 1n in the formation region of the nMOS transistors Tr2 and Tr4 and the access transistors Tr5 and Tr6.

  Next, referring to FIG. 12D and FIG. 16D, a thermal oxide film having a thickness of 20 nm is formed on the surface of the element formation regions 5A and 5B. Then, an opening 11a having a diameter of 20 nm that exposes the surface of the semiconductor substrate 1 is opened in the formation region of the transistors Tr1 to Tr6 in this thermal oxide film, and a selective growth mask 11 made of a thermal oxide film is formed.

  Next, with reference to FIGS. 12E and 16E, silicon nanowires 3 are selectively epitaxially grown from the surface of the semiconductor substrate 1 exposed in the openings 11a by selective epitaxial growth of silicon using the mask 11. Then, a non-doped silicon nanowire 3 standing from the opening 11a is formed.

  At this time, the p-type and n-type silicon nanowires 3 may be simultaneously formed by providing a metal catalyst containing an n-type or p-type impurity in each opening 11a. Alternatively, p-type and n-type silicon nanowires 3 can be formed by ion-implanting p-type and n-type impurities into non-doped nanowires 3.

  12 (f) and 16 (f), a silicon oxide film or a high dielectric is formed on the entire surface of the semiconductor substrate 1 by thermal oxidation or by using a deposition method having good coverage, such as CVD. A gate insulating film 12 made of a body film is deposited so as to cover the upper and side surfaces of the nanowire 3. Further, a silicon film 13a, for example, a polysilicon film is formed on the gate insulating film 12 by using a deposition method with good coverage, for example, CVD.

  Next, the entire surface of the silicon film 13a is etched back using anisotropic ion etching that selectively etches silicon compared to the gate insulating film. As a result, referring to FIGS. 13G and 17G, the other silicon film 13a is removed while leaving the silicon film 13a around the nanowire 3. At the same time, the gate insulating film 12 on the upper end of the nanowire 3 is removed by further over-etching after the silicon film 13 is removed by etching. Subsequently, the upper end of the silicon nanowire 3 is etched to form a nanowire 3 having a height of 70 nm.

  In this whole surface anisotropic ion etching, the gate insulating film 12 formed on the mask 11 is exposed between the nanowires 3 and the gate insulating film 12 is removed until the gate insulating film 12 is further removed or removed. The process is continued until the surface layer of the mask 11 exposed below is removed.

  The silicon film 13a remaining around the nanowire 3 formed in this way is removed to about 20 nm below the upper end surface of the nanowire 3, and is formed only below the silicon film 13a. The relationship between the height of the nanowire 3, the position of the upper end of the silicon film 13 a and the removal of the gate insulating film 12 between the nanowires 3 is the selectivity of the silicon nanowire 3 and the silicon film 12 with respect to the gate insulating film 12 of anisotropic ion etching, It is controlled by adjusting the height and the etching time of the first nanowire 3.

  In order to form the nanowire 3 at a predetermined height, in addition to the above-described whole surface etching, after the silicon film 13a is formed, an insulating film covering the nanowire 3 is formed, and then CMP (chemical mechanical polishing) or the entire surface is formed. Planarization may be performed until the nanowire 3 reaches a predetermined height by etch back. Thereafter, a gate oxide film is formed on the upper end surface of the nanowire 3, the insulating film is removed, and the entire surface of the silicon film 13a is anisotropically etched to obtain the structure shown in FIGS. 13 (g) and 17 (g). In this method, since the gate insulating film at the upper end of the nanowire serves as an etch stopper, the conditions for etching selectivity are relaxed.

  Next, referring to FIGS. 13H and 17H, the surface of the semiconductor substrate 1 is exposed by isotropic etching using the nanowire 3, the gate insulating film 12 and the silicon film 13a as a mask. Etch until. As a result, the mask 11 is over-etched and remains only in the vicinity of the periphery of the nanowire 3, and the surface of the semiconductor substrate 1 is exposed outside.

  Next, referring to FIGS. 13 (i) and 17 (i), the exposed silicon surface is silicided using a known salicide method. As a result, the source electrode 14 made of a silicide film on the upper end surface of the silicon nanowire 3, the gate electrode made of the silicide film around the nanowire 3 through the gate insulating film 12, and the semiconductor substrate exposed between the masks 11. A connection region 4 made of a silicon film is formed on one surface. The gate electrode 13 can also have a polycide structure composed of two layers of silicon and silicide.

  More specifically, a metal film such as a Ni film is deposited on the entire surface of the semiconductor substrate 1. Next, heat treatment is performed to react the Ni film in contact with the exposed surface of the silicon, thereby forming a silicide film. Thereafter, the unreacted Ni film is removed by etching, whereby the source electrode 14, the gate electrode 13, and the connection region 4 are formed.

  14 (j) and 18 (j), an insulating film 6a made of a silicon oxide film for embedding the nanowire 3 is deposited on the entire surface of the semiconductor substrate 1 by the CVD method. Next, an etching mask 6b having an opening 31b is formed on the insulating film 6a. The opening 31b is formed immediately above the via formation regions 42A and 42B provided in the element formation regions 5A and 5B, respectively, and is a two-stage opening having a wide upper portion and a narrow lower portion.

  Note that the opening 31b of the etching mask 6b is not limited to a circle, and may be, for example, rectangular or asymmetric. In particular, it is desirable to make the wall surface of the opening 31b close to the insulating separator 2 into a two-step wide step surface or a loosely inclined section and to make the opposite wall surface steep. A part (wide step surface) of the opening can be formed on the insulating separator 2 by making the cross section of the opening 31b into such an asymmetric cross sectional shape. For this reason, since the insulation separation body 2 can be formed widely, the short circuit between element formation area 5A, 5B is prevented. Such an etching mask 6b can be easily formed by an imprint method using a mold.

  Next, referring to FIGS. 14K and 18K, the insulating film 6a is etched by anisotropic ion etching, and the shape of the etching mask 6b is transferred to the insulating film 6a, and the insulating film is thickened. The buried insulating film 6 is formed by reducing the thickness to 30 nm. If the parasitic capacitance between the gate electrode wirings 15 </ b> A to 15 </ b> D and the semiconductor substrate 1 is large, the buried insulating film 6 can be made as thick as the mask 11. In the buried insulating film 6, openings 31a for exposing the connection regions 4 are formed in the via formation regions 42A and 42B, respectively. The opening 31a to which the opening 31b is transferred is a two-stage opening having a wide upper portion and a narrow lower portion, for example, an opening having a diameter of 30 nm and a lower portion having a diameter of 20 nm.

  Next, referring to FIGS. 14K and 18K, an Al film having a thickness of 15 nm is deposited on the entire surface of the semiconductor substrate 1 by a highly directional deposition method, for example, a collimated vapor deposition method. Patterning is performed by lithography to form gate electrode wirings 15A to 15D. The Al film that is simultaneously formed and fills the opening 31a forms a via 31 that connects the gate electrode wirings 15A to 15D to the connection region. By this patterning, the Al film deposited on the upper end surface of the nanowire 3 (upper surface of the source electrode 14) is etched and removed. Of course, the Al film may be left on the source electrode 14 to be a part of the source electrode 14.

  The buried insulating film 6 and the gate electrode wirings 15A to 15D described above can also be formed by the manufacturing process of the second embodiment, the method described with reference to FIGS. 6B to 6C. That is, referring to FIG. 13 (i), after forming the source electrode 14, the gate electrode 13 and the connection region 4 made of a silicide film, the following steps are performed instead of the steps of FIGS. 14 (j) to 14 (l). The buried insulating film 6 and the gate electrode wirings 15A to 15D are formed by the process.

  First, after the step shown in FIG. 13I, an insulating film having a thickness of 30 nm is deposited on the entire surface of the semiconductor substrate 1 by a highly directional deposition method. As a result, referring to FIG. 14 (k), a buried insulating film 6 having a thickness of 30 nm is formed to bury the base of nanowire 3, and at the same time, the insulating film has the same thickness on the upper end (source electrode 14) of nanowire 3. Formed. Next, the insulating film is slightly etched to remove the insulating film that is thinly deposited on the gate electrode 12.

Next, an opening 31a is formed in the insulating film using photolithography, and the buried insulating film 6 made of the insulating film is formed. As is well known, the two-stage opening 31a can be formed using an etching mask having the two-stage opening 31b shown in FIG. 14 (j). Next, a conductive film, For example, an Al film having a thickness of 15 nm is deposited using a highly directional deposition method. Next, the insulating film on the upper end of the nanowire 3 is removed by etching, and at the same time, the conductive film deposited on the upper end of the nanowire 3 is removed by lift-off. Next, the conductive film deposited on the buried insulating film 6 is patterned to form gate electrode wirings 15A to 15D made of the conductive film. Through the above steps, the buried insulating film 6 and the gate electrode wirings 15A to 15D can be formed.

  The gate electrode wiring 15A described above is connected between the gate electrodes 13 of the pMOS and nMOS transistors Tr1 and Tr2 constituting the CMOS inverter circuit formed in the element formation region 5A, and is formed in the other element formation region 5B. Patterning is performed so as to connect to the connection region 4 (node N2) through the via 31B. On the other hand, the gate electrode wiring 15B connects between the gate electrodes 13 of the pMOS and nMOS transistors Tr3 and Tr4 constituting the CMOS inverter circuit formed in the element formation region 5B, and further, a via 31A formed in the element formation region 5A. To be connected to the connection region 4 (node N1) via

  9 and 10, an insulating film 7 is formed on the entire surface of the semiconductor substrate 1, and openings (via holes) for exposing the source electrodes 14 of the transistors Tr1 to Tr6 are formed. Further, openings (via holes) for exposing the gate electrode wirings 15C and 15D are formed in the formation regions of the vias 32C and 32D. Next, vias 18 to 20, 32 </ b> C, and 32 </ b> D filling these openings (via holes) are formed.

  Next, via vias 18 and 19 connected to the source electrodes 14 of the transistors Tr1 to Tr4 constituting the CMOS inverter circuit are formed as via relays for leading to the upper layer. In addition, bit lines 25 (B, / B) that are connected to the vias 20 connected to the source electrodes 14 of the access transistors Tr5 and Tr6 and extend on the insulating film 7 are formed. At the same time, a word line 26 (W) is formed which is connected to the vias 32 C and 32 D connected to the gate electrode wirings 15 C and 15 D and extends on the insulating film 7.

  Next, an interlayer insulating film 8 is formed on the entire surface of the semiconductor substrate 1 and vias connected to the vias 18 and 19 are formed. Further, a low potential wiring 22 and a high potential wiring 23 connected to these vias are formed on the interlayer insulating film 8. The semiconductor device according to the third embodiment is manufactured through the above steps.

  In the first to third embodiments described above, the semiconductor substrate 1 may be a semiconductor substrate other than silicon, for example, a III-V group or II-VI group compound semiconductor. The same applies to nanowires. Further, carbon nanotubes may be used instead of nanowires.

  Further, the connection region 4 may be formed deeper than the p-type and n-type impurity regions 1p and 1n. Since the p-type and n-type impurity regions 1p and 1n are ohmic-bonded to each other by the connection region 4, it is not necessary to arrange them in contact with each other.

As described above, the present invention disclosed in the following supplementary notes is disclosed in this specification.
(Appendix 1) A semiconductor device comprising a CMOS inverter circuit comprising a series connection of an nMOS transistor and a pMOS transistor in which a nanowire or nanotube is used as a channel and a gate electrode is provided around the nanowire or nanotube via a gate insulating film In
The drains of the nMOS and pMOS transistors are n-type and p-type impurity regions formed on the surface of the semiconductor substrate, respectively.
The n-type and p-type impurity regions are ohmically connected via a connection region that is ohmically connected to the n-type and p-type impurity regions,
The nanowires or nanotubes are respectively erected on the n-type and p-type impurity regions,
The sources of the nMOS and pMOS transistors are formed at the top of the nanowire or nanotube,
A gate electrode of the nMOS and the pMOS transistor is connected by a gate electrode wiring.
(Supplementary Note 2) A flip-flop circuit having the first and second CMOS inverter circuits and having one input terminal and the other output terminal of the first and second CMOS inverter circuits connected to each other is provided. In the semiconductor device described in Appendix 1,
The gate electrode wiring is formed on a buried insulating film that embeds the bottom end of the nanowire or nanotube,
The buried insulating film has a contact hole that exposes the connection region,
The gate electrode wiring constituting one of the first and second CMOS inverters is connected to the connection region constituting the other of the first and second CMOS inverters through the contact hole. Semiconductor device.
(Appendix 3) In the semiconductor device described in Appendix 2,
The flip-flop circuit is formed in a rectangular flip-flop circuit formation region,
The nMOS transistor constituting the first CMOS inverter circuit is arranged at the upper left corner of the flip-flop circuit formation region,
The pMOS transistor constituting the first CMOS inverter circuit is arranged at the lower left corner of the flip-flop circuit formation region,
The nMOS transistors constituting the two CMOS inverter circuits are arranged in the upper right corner of the flip-flop circuit formation region,
The pMOS transistor constituting the second CMOS inverter circuit is disposed at the lower right corner of the flip-flop circuit formation region,
2. A semiconductor device according to claim 1, wherein the contact holes are formed between the nMOS transistors and between the pMOS transistors to expose connection regions of the first and second CMOS inverters, respectively.
(Supplementary Note 4) In the semiconductor device according to Supplementary Note 2, wherein the flip-flop circuit is provided in an SRAM memory cell.
Comprising an access transistor inserted between the connection region and the bit line;
The access transistor is formed on the surface of the semiconductor substrate and is ohmic-connected to the connection region, an access transistor n-type impurity region;
A nanowire or a nanotube for an access transistor standing on the n-type impurity region for the access transistor;
An electrode formed on an upper end of the access transistor nanowire or nanotube, and connected to the bit line;
A semiconductor device comprising an access transistor gate electrode provided around a nanowire or nanotube for an access transistor via a gate insulating film and connected to a word line.
(Appendix 5) In the semiconductor device according to Appendix 4,
The SRAM memory cell is formed in a rectangular memory cell formation region,
In the first direction along one side of the memory cell formation region, the access transistor, the nMOS transistor, and the pMOS transistor constituting the first CMOS inverter circuit are arranged in this order,
The access transistor, the nMOS transistor, and the pMOS transistor that constitute the second CMOS inverter circuit are arranged in this order in a direction opposite to the first direction along a side opposite to the one side of the memory cell formation region. And
The contact hole that exposes the connection region of the first CMOS inverter circuit includes the pMOS transistor that constitutes the first CMOS inverter circuit and the nMOS transistor that constitutes the second CMOS inverter circuit. Placed between
The contact hole that exposes the connection region of the second CMOS inverter circuit includes the pMOS transistor that constitutes the second CMOS inverter circuit and the nMOS transistor that constitutes the first CMOS inverter circuit. A semiconductor device characterized by being disposed between.
(Supplementary note 6) The semiconductor device according to any one of supplementary notes 1 to 5, wherein the nanowire is a semiconductor nanowire formed by selective growth using a mask.
(Supplementary note 7) The semiconductor device according to supplementary note 6, wherein the semiconductor nanowire is doped with a p-type or n-type impurity.
(Supplementary note 8) The semiconductor device according to any one of supplementary notes 1 to 5, wherein the nanowire is a carbon nanotube.
(Supplementary Note 9) A step of forming a p-type impurity region and an n-type impurity region in an element forming region isolated by an insulating isolation band formed on the surface of a semiconductor substrate;
Forming an insulating film having first and second openings for exposing the p-type and n-type impurity regions on the semiconductor substrate;
Forming a nanowire or a nanotube composed of semiconductor pillars erected in the first and second openings by chemical vapor deposition;
A step of sequentially forming a gate insulating film and a silicon film covering the nanowires or nanotubes and the insulating film upper surface;
The gate insulating film is left around the nanowire or the nanotube, and the silicon film whose upper end is lower than the upper end surface of the nanowire or the nanotube is left around the nanowire or the nanotube, and the other silicon film and the gate Removing the insulating film;
Removing the insulating film in a region where the nanowires or nanotubes are not formed to expose the semiconductor substrate surface;
Next, a silicide film is formed on the upper end of the nanowire or nanotube, the silicon film, and the exposed surface of the semiconductor substrate, and the upper end of the nanowire or nanotube and the surrounding silicide film are used as a source electrode and a gate electrode, respectively. And pMOS and nMOS transistors having the p-type and n-type impurity regions as drains, respectively, and at the same time ohmic between the p-type and n-type impurity regions comprising the silicide film formed on the surface of the semiconductor substrate. And a step of forming a connection region to be connected.
(Supplementary note 10) In the method for manufacturing a semiconductor device according to supplementary note 9,
After the step of forming the connection region,
Forming a buried insulating film filling the lower part of the nanowire or nanotube constituting the p-type and n-type MOS transistor;
And forming a gate electrode wiring connecting the gate electrodes of the p-type and n-type MOS transistors formed around the nanowire or the nanotube on the buried insulating film. A method for manufacturing a semiconductor device.
(Additional remark 11) In the manufacturing method of the semiconductor device of Additional remark 10,
Forming the pMOS and nMOS transistors in each of the first and second element formation regions;
A first contact hole that exposes the connection region formed in the first element formation region and a second contact region that exposes the connection region formed in the second element formation region are formed in the buried insulating film. Forming a contact hole of
In the step of forming the gate electrode wiring, the conductive film deposited on the buried insulating film and in the contact hole is patterned so that the gate electrode wiring formed on the first element formation region is the second electrode Forming the gate electrode wiring such that a gate electrode wiring connected to the connection region through a contact hole and connected to the connection region through the first contact hole is connected to the connection region; A method of manufacturing a semiconductor device.
(Appendix 12) In the method for manufacturing a semiconductor device according to Appendix 11,
The step of forming the buried insulating film and the contact hole includes:
Depositing an insulating film covering the top surface of the nanowire or nanotube flatly;
On the insulating film, forming an etching mask in which the contact hole forming region is formed thinner than other regions;
And a step of etching the insulating film by anisotropic etching using the etching mask to form the buried insulating film in which the contact hole is formed.
(Appendix 13) A step of depositing the buried insulating film on the entire surface of the semiconductor substrate using a highly directional deposition method;
Then, depositing the conductive film on the entire surface of the semiconductor substrate using a highly directional deposition method;
12. The method of manufacturing a semiconductor device according to claim 10, further comprising a step of etching off the buried insulating film deposited on the upper end surface of the nanowire and lifting off the conductive film deposited on the upper end surface of the nanowire. Method.
(Additional remark 14) The said whole surface anisotropic ion etching is an etching which etches silicon and silicon selectively with respect to the said gate insulating film,
Any one of appendices 9 to 13, wherein the nanowire is etched from the upper end to a predetermined height by the step of etching the silicon film and the gate insulating film using the whole surface anisotropic ion etching. The manufacturing method of the semiconductor device as described in any one of Claims 1-3.
(Supplementary note 15) The nanowire is formed in a predetermined length,
14. The method of manufacturing a semiconductor device according to any one of appendices 9 to 13, wherein the whole surface anisotropic ion etching for selectively etching silicon is etching using a gate insulating film as a stopper.
(Supplementary note 16) The method of manufacturing a semiconductor device according to supplementary notes 9 to 15, further comprising a step of doping the nanowire with a p-type impurity or an n-type impurity using an ion implantation mask after the nanowire is formed.

  According to the present invention, a CMOS inverter circuit configured using vertical MOS transistors can be formed in a small area cell, and a semiconductor device including the CMOS inverter circuit is formed on a small area semiconductor substrate. can do.

First Embodiment CMOS Inverter Circuit Structure Diagram of the First Embodiment First Embodiment Manufacturing Process Diagram (Part 1) First Embodiment Manufacturing Process Diagram (Part 2) First Embodiment Manufacturing Process Diagram of the Present Invention (Part 3) Flip-flop circuit cell structure diagram of the second embodiment of the present invention Sectional view of manufacturing process of second embodiment of the present invention Second embodiment manufacturing process plan view of the present invention Manufacturing process sectional drawing of 2nd Embodiment modification of this invention Third Embodiment SRAM Cell Cross Section of the Present Invention Third Embodiment SRAM Cell Cross Section of the Present Invention Third embodiment manufacturing process sectional view of the present invention (Part 1) Third embodiment manufacturing process sectional view of the present invention (Part 2) Third Embodiment Manufacturing Process Cross Section View (Part 3) Third embodiment manufacturing process sectional view of the present invention (Part 4) Third embodiment manufacturing process plan view of the present invention (Part 1) Third Embodiment Manufacturing Process Plan View of the Present Invention (Part 2) Third embodiment manufacturing process plan view of the present invention (No. 3) Third embodiment manufacturing process plan view of the present invention (Part 4) CMOS cell circuit diagram Cross-sectional view of conventional semiconductor device

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 1n n-type impurity region 1p p-type impurity region 2 Insulation isolation band 3 Nanowire 4 Connection region 5, 5A, 5B Element formation region 6 Embedded insulating film 6a Insulating film 6b Etching mask 7 Insulating film 8 Interlayer insulating film 10, 30 , 40 cell 11 mask 12 gate insulating film 13 gate electrode 14 source electrode 15, 15A, 15B, 15C, 15D gate electrode wiring 16, 17, 18, 19, 20 via 21 input wiring 22 low voltage wiring (Vss wiring)
23 High voltage wiring (Vdd wiring)
24 output wiring 25 bit line (B, / B)
26 Word line (W)
31, 31A, 31B, 32, 32C, 32D Via 31a Contact hole 31b Opening 41n, 41p Ion implantation mask 41no, 41po Opening 42A, 42B Via formation region 101 Substrate 102, 114, 122, 125, 130 Insulating film 102a Small hole 103 Source electrode 104 Drain electrode 105, 115, 124 Gate electrode 106 Nonconductive thin film 107 Nanotube 110n nMOS transistor 110p pMOS transistor 111 Source / drain electrode 112, 120 Nanowire 113 Catalyst ball 121 Semiconductor substrate 123 Gate insulating film 126 Gate electrode wiring 126a Via hole 127 129 Silicide film 128 Drain electrode wiring 129a Impurity region 131 Opening 201 Input end 202, 203 Output end Tr1, Tr3 pMOS transistor Tr2, Tr4 nMOS transistor Tr5, Tr6 Access transistor N, N1, N2 Node Vdd Circuit power supply Vss Circuit ground

Claims (6)

In a semiconductor device comprising a CMOS inverter circuit comprising a series connection of an nMOS transistor and a pMOS transistor in which a nanowire or nanotube is used as a channel, and a gate electrode is provided around the nanowire or nanotube via a gate insulating film,
The drains of the nMOS and pMOS transistors are n-type and p-type impurity regions formed on the surface of the semiconductor substrate, respectively.
The n-type and p-type impurity regions are ohmically connected via a connection region that is ohmically connected to the n-type and p-type impurity regions,
The nanowires or nanotubes are respectively erected on the n-type and p-type impurity regions,
The sources of the nMOS and pMOS transistors are formed at the top of the nanowire or nanotube,
A gate electrode of the nMOS and the pMOS transistor is connected by a gate electrode wiring. 2. A flip-flop circuit comprising first and second CMOS inverter circuits, wherein one input terminal and the other output terminal of the first and second CMOS inverter circuits are connected to each other. In the described semiconductor device,
The gate electrode wiring is formed on a buried insulating film that embeds the bottom end of the nanowire or nanotube,
The buried insulating film has a contact hole that exposes the connection region,
The gate electrode wiring constituting one of the first and second CMOS inverters is connected to the connection region constituting the other of the first and second CMOS inverters through the contact hole. Semiconductor device. The semiconductor device according to claim 2,
The flip-flop circuit is formed in a rectangular flip-flop circuit formation region,
The nMOS transistor constituting the first CMOS inverter circuit is arranged at the upper left corner of the flip-flop circuit formation region,
The pMOS transistor constituting the first CMOS inverter circuit is arranged at the lower left corner of the flip-flop circuit formation region,
The nMOS transistor constituting the second CMOS inverter circuit is arranged in the upper right corner of the flip-flop circuit formation region,
The pMOS transistor constituting the second CMOS inverter circuit is disposed at the lower right corner of the flip-flop circuit formation region,
2. A semiconductor device according to claim 1, wherein the contact holes are formed between the nMOS transistors and between the pMOS transistors to expose connection regions of the first and second CMOS inverters, respectively. The semiconductor device according to claim 2, wherein the flip-flop circuit is provided in an SRAM memory cell.
Comprising an access transistor inserted between the connection region and the bit line;
The access transistor is formed on the surface of the semiconductor substrate and is ohmic-connected to the connection region, and an access transistor n-type impurity region;
A nanowire or a nanotube for an access transistor standing on the n-type impurity region for the access transistor;
An electrode formed on an upper end of the access transistor nanowire or nanotube, and connected to the bit line;
A semiconductor device comprising an access transistor gate electrode provided around a nanowire or nanotube for an access transistor via a gate insulating film and connected to a word line. The semiconductor device according to claim 4.
The SRAM memory cell is formed in a rectangular memory cell formation region,
In the first direction along one side of the memory cell formation region, the access transistor, the nMOS transistor, and the pMOS transistor constituting the first CMOS inverter circuit are arranged in this order,
The access transistor, the nMOS transistor, and the pMOS transistor that constitute the second CMOS inverter circuit are arranged in this order in a direction opposite to the first direction along a side opposite to the one side of the memory cell formation region. And
The contact hole that exposes the connection region of the first CMOS inverter circuit includes the pMOS transistor that constitutes the first CMOS inverter circuit and the nMOS transistor that constitutes the second CMOS inverter circuit. Placed between
The contact hole that exposes the connection region of the second CMOS inverter circuit includes the pMOS transistor that constitutes the second CMOS inverter circuit and the nMOS transistor that constitutes the first CMOS inverter circuit. A semiconductor device characterized by being disposed between. Forming a p-type impurity region and an n-type impurity region in an element formation region isolated by an isolation band formed on the surface of the semiconductor substrate;
Forming an insulating film having first and second openings for exposing the p-type and n-type impurity regions on the semiconductor substrate;
Forming a nanowire or a nanotube composed of semiconductor pillars erected in the first and second openings by chemical vapor deposition;
A step of sequentially forming a gate insulating film and a silicon film covering the nanowires or nanotubes and the insulating film upper surface;
The gate insulating film is left around the nanowire or the nanotube, and the silicon film whose upper end is lower than the upper end surface of the nanowire or the nanotube is left around the nanowire or the nanotube, and the other silicon film and the gate Removing the insulating film;
Removing the insulating film in a region where the nanowires or nanotubes are not formed to expose the semiconductor substrate surface;
Next, a silicide film is formed on the upper end of the nanowire or nanotube, the silicon film, and the exposed surface of the semiconductor substrate, and the upper end of the nanowire or nanotube and the surrounding silicide film are used as a source electrode and a gate electrode, respectively. And pMOS and nMOS transistors having the p-type and n-type impurity regions as drains, respectively, and at the same time ohmic between the p-type and n-type impurity regions comprising the silicide film formed on the surface of the semiconductor substrate. And a step of forming a connection region to be connected.

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