JP5395601B2 - Semiconductor integrated circuit - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit using a field effect transistor.

  In a circuit using a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), it is rare that the gate-source threshold voltage Vthn of the N-channel MOSFET and the gate-source threshold voltage Vthp of the P-channel MOSFET coincide with each other. Due to manufacturing process variations (hereinafter referred to as process variations), Vthn and Vthp often differ from device to device, from wafer to wafer, and from lot to lot. Such imbalance between the threshold voltages Vthn and Vthp affects the circuit operation in a state where the power supply voltage Vdd is lowered (a reduced voltage state).

  This problem will be described with reference to FIG. FIGS. 1A and 1B are a circuit diagram showing a configuration of a feedforward class AB output circuit and its operating characteristics. The output circuit 200 includes output transistors MO1 and MO2 connected in a push-pull manner, and a bias circuit 202. A differential amplifier (not shown) is connected to the front stage of the output circuit 200 as an input stage, but is omitted for simplification of explanation and easy understanding. The bias circuit 202 includes MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) (hereinafter simply referred to as transistors) M11 to M16, upper current sources 204 and 206, and lower current sources 208 and 210.

  The upper current source 204 is provided on the power supply terminal side, and generates an upper bias current Ip1. The upper bias current Ip1 is a unit current I in an ideal state. The transistors M11 and M16 form a current mirror circuit, and the transistor M16 is biased so that the unit current I generated by the upper current source 204 flows. The transistor M13 is provided in association with the output transistor MO2 in order to balance the source potential of the transistor M11 and the source potential of the transistor M16.

  The lower current source 208 is provided on the ground terminal side and generates a lower bias current In1. The lower bias current In1 is also the unit current I in the ideal state. The transistors M12 and M15 form a current mirror circuit, and the transistor M15 is biased so that the unit current I generated by the lower current source 208 flows. The transistor M14 is provided in association with the output transistor MO1 in order to balance the source potential of the transistor M12 and the source potential of the transistor M15.

The upper bias current Ip2 generated by the upper current source 206 and the lower bias current In2 generated by the lower current source 210 are both twice (2I) the unit current I in the ideal state, and the transistors M15 and M16 are united. Each current I is distributed. The above is the configuration of the output circuit 200. The output circuit 200
Ip1: In1: Ip2: In2 = 1: 1: 2: 2
Operates normally when In general, since the upper current sources 204 and 206 are formed using a current mirror circuit, Ip1: Ip2 = 1: 2 is established unconditionally. For the same reason, In1: In2 = 1: 2 is It may be considered that it is established unconditionally.

JP-A-9-130166

Consider the operating voltage range of the output circuit 200 of FIG. The upper current source 204 and the transistors M11 and M12 are
2 × Vthn + Vds _SAT <Vdd (1)
It operates normally in the area. Vds _SAT is a lower limit value (saturation voltage) of the voltage between both ends at which the upper current source 204 can generate the unit current I. Similarly, the lower current source 208 and the transistors M13 and M14 are
2 × Vthp + Vds _SAT <Vdd (2)
It operates normally in the area. Here, Vds _SAT is a lower limit value (saturation voltage) of the voltage between both ends at which the lower current source 208 can generate the unit current I.

  Here, consider a situation where Vthn <Vthp due to process variations or the like. In the region (I) where the power supply voltage Vdd is sufficiently high, both the bias currents Ip1 and In1 are kept at the unit current I. When the power supply voltage Vdd decreases (region (II)), the formula (1) is satisfied, but the formula (2) is not satisfied. Therefore, only the bias current In1 is maintained at the unit current I, and the bias current Ip Is smaller than the unit current I. When the power supply voltage further decreases (region (III)), equation (1) does not hold and the bias current In becomes smaller than the unit current I.

  In region (II), the bias state of the output circuit 200 is completely unbalanced, causing a problem in circuit operation.

  Such a problem may occur not only in the output circuit 200 of FIG. 1A but also in various circuits that require symmetry between the upper bias current Ip and the lower bias current In.

  The present invention has been made in such a situation, and one of exemplary objects of an embodiment thereof is to provide a semiconductor integrated circuit having improved operation in a reduced voltage state.

  One embodiment of the present invention relates to a semiconductor integrated circuit. The semiconductor integrated circuit includes an upper bias current and a lower bias current, a main circuit configured to perform predetermined signal processing in a balanced state, a first reference current, and an adjusted second reference A reference current adjusting unit for generating a current; provided on the power supply terminal side of the main circuit; provided on the ground terminal side of the main circuit; and an upper current source for supplying an upper bias current corresponding to the second reference current to the main circuit. And a lower current source for supplying a lower bias current corresponding to the second reference current to the main circuit. The reference current adjustment unit generates the second reference current so that the upper bias current and the lower bias current are equal.

  According to this aspect, the balance between the upper bias current and the lower bias current can be maintained even in the reduced voltage state, and the main circuit can be operated stably.

  Another embodiment of the present invention is also a semiconductor integrated circuit. This semiconductor integrated circuit is a main circuit configured to receive an upper side bias current and a lower side bias current and perform predetermined signal processing in a state where they are balanced, and at least a path through which the upper side bias current is supplied An M channel (M is a natural number) N-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor) connected between the gate and the source, and a path to which the lower bias current is supplied. A main circuit including M P-channel MOSFETs connected to each other, a first current mirror circuit including a pair of first conductive MOSFETs and copying a first reference current having a predetermined current value; And a second reference current output circuit that copies the output current of the first current mirror circuit and outputs a second reference current. (M-1) first conductive MOSFETs provided on the same path as the input-side MOSFETs of the current mirror circuit and the first current mirror circuit and connected between the gate and the source, and the second current mirror (M-1) second conductive MOSFETs provided on the same path as the MOSFET on the input side of the circuit and connected between the gate and source, and provided on the power supply terminal side of the main circuit. An upper current source that supplies an upper bias current corresponding to the second reference current; a lower current source that is provided on the ground terminal side of the main circuit and supplies a lower bias current corresponding to the second reference current to the main circuit; .

  According to this aspect, the balance between the upper bias current and the lower bias current can be maintained even in the reduced voltage state, and the main circuit can be operated stably.

  Note that any combination of the above-described components, or a conversion of the expression of the present invention between methods, apparatuses, and the like is also effective as an aspect of the present invention.

  According to an aspect of the present invention, the operation in the reduced voltage state can be improved.

FIGS. 1A and 1B are a circuit diagram showing a configuration of a feedforward class AB output circuit and its operating characteristics. 1 is a block diagram showing a configuration of a semiconductor integrated circuit according to an embodiment. 3A and 3B are diagrams showing the power supply voltage dependence of the second reference current of the semiconductor integrated circuit of FIG. 4A and 4B are circuit diagrams illustrating a configuration example of the reference current adjusting unit. FIGS. 5A and 5B are circuit diagrams showing specific configuration examples of the upper current source and the lower current source.

  The present invention will be described below based on preferred embodiments with reference to the drawings. The same or equivalent components, members, and processes shown in the drawings are denoted by the same reference numerals, and repeated descriptions are omitted as appropriate. The embodiments do not limit the invention but are exemplifications, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

In this specification, “the state in which the member A is connected to the member B” means that the member A and the member B are electrically connected in addition to the case where the member A and the member B are physically directly connected. It includes the case of being indirectly connected through another member that does not affect the connection state.
Similarly, “the state in which the member C is provided between the member A and the member B” refers to the case where the member A and the member C or the member B and the member C are directly connected, as well as an electrical condition. It includes the case of being indirectly connected through another member that does not affect the connection state.

  FIG. 2 is a block diagram showing a configuration of the semiconductor integrated circuit 100 according to the embodiment. The semiconductor integrated circuit 100 includes a main circuit 10, an upper current source 20H, a lower current source 20L, and a reference current adjusting unit 30.

  The main circuit 10 is configured to receive the upper bias current Ip and the lower bias current In and perform predetermined signal processing in a state where they are balanced. When an imbalance occurs in the bias currents Ip and In, the main circuit 10 becomes inoperable or its characteristics deteriorate. For example, the main circuit 10 is an operational amplifier, and linearity, distortion characteristics, and the like are deteriorated due to imbalance of the bias current. The configuration of the main circuit 10 is not particularly limited, but preferred specific examples include, for example, the feedforward class AB output circuit of FIG. 1 and a rail-rail amplifier.

The reference current adjusting unit 30 receives the first reference current I _BO and generates the adjusted second reference current I _B.

Upper current source 20H is provided to the power supply terminal side of the main circuit 10, and supplies the upper bias current Ip corresponding to the second reference current I _B in the main circuit 10. Lower current source 20L is provided on the ground terminal side of the main circuit 10 supplies a lower bias current In corresponding to the second reference current I _B in the main circuit 10.

For example, the main circuit 10 includes a first circuit 10_1 provided at the supply destination of the upper bias current Ip and a second circuit 10_2 provided at the supply destination of the lower bias current In.
In order for the upper current source 20H to generate the predetermined upper bias current Ip, the voltage between both ends thereof must be larger than the saturation voltage V _SAT H. When the voltage across the first circuit 10_1 (referred to as the first threshold voltage) is written as Vth1, the upper bias current Ip is
Vdd> Vth1 + _VSAT H (3)
Is normally generated when When the power supply voltage Vdd is less than the upper bias current Ip is smaller than the target value corresponding to the reference current I _B.

Similarly, in order for the lower current source 20L to generate a predetermined lower bias current In, the voltage between both ends thereof must be larger than the saturation voltage V _SAT L. When the voltage across the second circuit 10_2 (referred to as the second threshold voltage) is written as Vth2, the lower bias current In is
Vdd> Vth2 + V _SAT L (4)
Is normally generated when When the power supply voltage Vdd is less than, smaller than the target value corresponding to the lower bias current In reference current I _B. In the following, it is assumed that V _SAT H≈V _SAT L holds for the sake of simplification of explanation and easy understanding.

Reference current adjusting unit 30, so that the upper bias current Ip and a lower bias current In becomes equal, for generating a second reference current I _B. Specifically, the second reference current I _B has the following properties. Figure 3 (a), (b) is a diagram showing the power supply voltage dependency of the second reference current _{I B} of the semiconductor integrated circuit 100 of FIG. 3A shows the characteristics when Vth1> Vth2, and FIG. 3B shows the characteristics when Vth1 <Vth2.

(1) When Vth1> Vth2 Referring to FIG. When the provisionally changed the second reference current I _B power supply voltage at a fixed state Vdd, the power supply voltage Vdd is high enough the first region (I), the upper bias current Ip, to the lower bias current In both target value Kept.

When the power supply voltage Vdd is lowered and becomes lower than Vth1 + _VSAT H, the upper bias current Ip starts to decrease (second region (II)). Further, when the value of the power supply voltage Vdd becomes lower than Vth2 + _VSAT L, the lower bias current In starts to decrease.

In this case, the reference current adjusting unit 30, as dependent on the power supply voltage Vdd of the second reference current I _B becomes equal to the dependency on the power supply voltage Vdd of the upper bias current Ip, generating a second reference current I _B To do. As shown in FIG. 3 (a), the second reference current I _B is preferably slightly smaller than the upper bias current Ip in the case of fixing the second reference current I _B. In this case, the balance between an upper side bias current Ip and a lower side bias current In which will be described later can be most improved. However the second reference current I _B may be exactly match the upper bias current Ip in the case of fixing the second reference current I _B, it may be slightly larger than the upper bias current Ip.

(2) When Vth1 <Vth2 Referring to FIG. Gradually reduce the power supply voltage Vdd in a state of fixing the bias current _{I B,} when the value is lower than Vth2 _{+ V SAT} L, the lower bias current In starts to decrease (the third region (III)). Further, when the value of the power supply voltage Vdd becomes lower than Vth1 _{+ V SAT} H, the upper bias current Ip starts to decrease.

In this case, the reference current adjusting unit 30 is dependent on the power supply voltage Vdd of the second reference current I _B is to be equal with the dependency on the power supply voltage Vdd of the lower bias current In, the second reference current I _B Generate.

The magnitude relationship between Vth1 and Vth2 may change due to process variations and temperature fluctuations. Reference current adjusting unit 30, Vth1> Vth2, Vth1 <In either situation the Vth2, generates the appropriate second reference current _{I B.} Minimum there From the perspective, the reference current adjusting unit 30, FIG. 3 (a), set to a second reference current I _B the smaller of the upper bias current Ip and a lower bias current In shown in (b) It can also be understood as a value selection circuit.

  The above is the configuration of the semiconductor integrated circuit 100. Next, the operation will be described.

(1) When Vth1> Vth2 In the first region (I), both the upper current source 20H and the lower current source 20L operate normally, and the balance between the upper bias current Ip and the lower bias current In is maintained. .

In the second region (II), the upper current source 20H does not operate normally, and an upper bias current Ip smaller than the target value is generated. On the other hand, the lower current source 20L to operate normally, the second reference current I _B is to reduce, comparable to the upper bias current Ip, the target small lower bias current In from the value is generated. As a result, the balance between the upper bias current Ip and the lower bias current In is maintained.

(2) When Vth1 <Vth2 In the first region (I), both the upper current source 20H and the lower current source 20L operate normally, and the balance between the upper bias current Ip and the lower bias current In is maintained. .

In the third region (III), the lower current source 20L does not operate normally, and a lower bias current In smaller than the target value is generated. On the other hand, the upper current source 20H to work properly, because the second reference current I _B is reduced, the same level as the lower bias current In, small upper bias current Ip than the target value is generated. As a result, the balance between the upper bias current Ip and the lower bias current In is maintained.

  As described above, according to the semiconductor integrated circuit 100 of FIG. 2, the upper bias current Ip is applied not only in the first region (I) but also in the second region (II) and the third region (III) in a reduced voltage state. And the lower bias current In can be balanced, and the circuit operation of the main circuit 10 can be stabilized.

  4A and 4B are circuit diagrams illustrating a configuration example of the reference current adjustment unit 30. FIG.

Reference is made to FIG. The first circuit 10_1 of the main circuit 10a includes one N-channel MOSFET (M21) whose source is grounded and whose gate and drain are connected. The first threshold voltage Vth1 at this time is
Vth1 = Vthn
It is. Vthn is a gate-source threshold voltage of the transistor M21.

The second circuit 10_2 includes one P-channel MOSFET (M22) whose source is grounded and whose gate and drain are connected. The second threshold voltage Vth2 at this time is
Vth2 = Vthp
It is. Vthp is a gate-source threshold voltage of the transistor M22.

  For example, the transistors M21 and M22 may be input side transistors of a current mirror circuit that copies the bias currents Ip and In.

The reference current adjustment unit 30a corresponding to the main circuit 10a includes a first current mirror circuit 32 and a second current mirror circuit 34. The first current mirror circuit 32 copies the first reference current I _BO . The second current mirror circuit 34, the output current of the first current mirror circuit 32 copies, and outputs a second reference current I _B.

  One of the first current mirror circuit 32 and the second current mirror circuit 34 (here, the first current mirror circuit 32) includes an N-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor) pair M41 and M42. The other (here, the second current mirror circuit 34) includes a pair of P-channel MOSFETs M43 and M44.

  The W / L of the MOSFET constituting the reference current adjusting unit 30a is designed to be smaller than the W / L of a current mirror circuit (not shown) in the main circuit 10a. W is the gate width and L is the gate length. That is, the current drive capability of the reference current adjusting unit 30a is intentionally designed to be lower than the current drive capability of the current mirror circuit in the main circuit 10a.

  The operation principle of the reference current adjusting unit 30a will be described.

(1) When Vth1> Vth2 (that is, Vthn> Vthp) The reference current adjusting unit 30a
Vthn + V _SAT H <Vdd
And Vthp + _VSAT L <Vdd
When the condition is satisfied, the second reference current I _B proportional to the first reference current I _BO can be output.

The power supply voltage Vdd is Vthp + _VSAT L <Vdd <Vthn + _VSAT H
2, the second current mirror circuit 34 operates normally, but the first current mirror circuit 32 does not operate normally, and a second reference current I _B smaller than the first reference current I _BO is generated. The Supply voltage Vdd dependence of the second reference current I _B at this time is equal to the dependency on the power supply voltage Vdd of the upper bias current Ip.

(2) When Vth1 <Vth2 (that is, Vthn <Vthp) The reference current adjusting unit 30a
Vthn + V _SAT H <Vdd
And Vthp + _VSAT L <Vdd
When the condition is satisfied, the second reference current I _B proportional to the first reference current I _BO can be output.

The power supply voltage Vdd is Vthn + _VSAT H <Vdd <Vthp + _VSAT L
The first current mirror circuit 32 operates normally, but the second current mirror circuit 34 does not operate normally, and a second reference current I _B smaller than the first reference current I _BO is generated. The Supply voltage Vdd dependence of the second reference current I _B at this time is equal to the dependency on the power supply voltage Vdd of the lower bias current In.

As a result, according to the reference current adjusting unit 30a of FIG. 4A, in any situation of Vth1> Vth2 and Vth1 <Vth2, the appropriate second reference current shown in FIGS. it can generate I _B.

  Supplementally, it can be said that the transistor M41 is associated with M21, and the path including the transistor M41 between the power supply terminal and the ground terminal simulates the characteristics of the path including the upper current source 20H and the transistor M21. Similarly, the transistor M43 is associated with M22, and the path including the transistor M43 between the power supply terminal and the ground terminal can be said to simulate the characteristics of the path including the lower current source 20L and the transistor M22.

Reference is made to FIG. The first circuit 10_1 of the main circuit 10b includes two N-channel MOSFETs (M21 and M23) whose source is grounded and whose gate and drain are connected. The first threshold voltage Vth1 at this time is
Vth1 = 2 × Vthn
It is.

The second circuit 10_2 includes two P-channel MOSFETs (M22, M24) whose source is grounded and whose gate and drain are connected. The second threshold voltage Vth2 at this time is
Vth2 = 2 × Vthp
It is.

  For example, the transistors M21 and M22 may be input side transistors of a current mirror circuit that copies the bias currents Ip and In.

  The main circuit 10b in FIG. 4A may be the output circuit 200 in FIG. In this case, the transistors M21 to M24 in FIG. 4B correspond to the transistors M11 to M14 in FIG.

The reference current adjustment unit 30b corresponding to the main circuit 10b includes a first current mirror circuit 32 and a second current mirror circuit 34. The first current mirror circuit 32 copies the first reference current I _BO . The second current mirror circuit 34, the output current of the first current mirror circuit 32 copies, and outputs a second reference current I _B.

  The transistor M45 is provided on the same path as the MOSFET (M41) on the input side of the first current mirror circuit 32, and its gate and source are connected. The transistor M45 has the same conductivity type as the transistors M23 and M21 included in the first circuit 10_1.

  Similarly, the transistor M46 is provided on the same path as the MOSFET (M43) on the input side of the second current mirror circuit 34, and its gate and source are connected. The transistor M46 has the same conductivity type as the transistors M24 and M22 that form the second circuit 10_2.

  That is, the transistors M41 and M45 are associated with the transistors M21 and M23, and the path including the transistors M41 and M45 between the power supply terminal and the ground terminal simulates the characteristics of the path including the upper current source 20H and the transistors M21 and M23. It can be said that. Similarly, the transistors M43 and M46 are associated with the transistors M22 and M24, and the path including the transistors M43 and M46 between the power supply terminal and the ground terminal has characteristics of the path including the lower current source 20L and the transistors M22 and M24. It can be said that it is simulated.

  The W / L of the MOSFET constituting the reference current adjusting unit 30b is designed to be smaller than the W / L of a current mirror circuit (not shown) in the main circuit 10b. That is, the current drive capability of the reference current adjusting unit 30b is intentionally designed to be lower than the current drive capability of the current mirror circuit in the main circuit 10b.

(1) When Vth1> Vth2 (that is, Vthn> Vthp) The reference current adjusting unit 30b is
2 × Vthn + V _SAT H <Vdd
And 2 × Vthp + V _SAT L <Vdd
When the condition is satisfied, the second reference current I _B proportional to the first reference current I _BO can be output.

The power supply voltage Vdd is 2 × Vthp + V _SAT L <Vdd <2 × Vthn + V _SAT H
2, the second current mirror circuit 34 operates normally, but the first current mirror circuit 32 does not operate normally, and a second reference current I _B smaller than the first reference current I _BO is generated. The Supply voltage Vdd dependence of the second reference current I _B at this time is equal to the dependency on the power supply voltage Vdd of the upper bias current Ip.

(2) When Vth1 <Vth2 (that is, Vthn <Vthp) The reference current adjusting unit 30b is
2 × Vthn + V _SAT H <Vdd
And 2 × Vthp + V _SAT L <Vdd
When the condition is satisfied, the second reference current I _B proportional to the first reference current I _BO can be output.

The power supply voltage Vdd is 2 × Vthn + _VSAT H <Vdd <2 × Vthp + _VSAT L
The first current mirror circuit 32 operates normally, but the second current mirror circuit 34 does not operate normally, and a second reference current I _B smaller than the first reference current I _BO is generated. The Supply voltage Vdd dependence of the second reference current I _B at this time is equal to the dependency on the power supply voltage Vdd of the lower bias current In.

Thus, according to the reference current adjusting portion 30a in Fig. 4 (a), Vth1> Vth2 , Vth1 < In either situation the Vth2, it is possible to generate an appropriate second reference current _{I B.}

When the reference current adjusting units 30a and 30b in FIGS. 4A and 4B are generalized, it can be grasped as follows.
The main circuit 10 includes a first circuit 10_1 provided in series with the upper current source 20H between the power supply terminal and the ground terminal, and a second circuit provided in series with the lower current source 20L between the power supply terminal and the ground terminal. Including the circuit 10_2. The first circuit 10_1 includes M (M is a natural number) N-channel MOSFETs whose source and drain are connected. Similarly, the second circuit 10_2 includes M P-channel MOSFETs whose source and drain are connected.

The reference current adjusting unit 30 includes a first conductive MOSFET pair, includes a first current mirror circuit 32 that copies the first reference current I _BO , and a second conductive MOSFET pair, copy the output current of the current mirror circuit 32, a second current mirror circuit 34 for outputting a second reference current I _B, provided on the same path on the input side of the MOSFET of the first current mirror circuit 32, the gate-source Are connected on the same path as the (M−1) first conductive MOSFETs connected to the MOSFET and the MOSFET on the input side of the second current mirror circuit 34 (M−1). ) Second conductive MOSFETs.

A reference current adjusting unit 30 and the main circuit 10 by constituting thus associated, it is possible to generate an appropriate second reference current I _B.

  5A and 5B are circuit diagrams showing specific configuration examples of the upper current source 20H and the lower current source 20L. The upper current source 20H and the lower current source 20L in FIG. 5A are configured by cascode type current mirror circuits. The upper current source 20H and the lower current source 20L in FIG. 5B are configured by a single stage current mirror circuit.

  Although the present invention has been described using specific terms based on the embodiments, the embodiments only illustrate the principles and applications of the present invention, and the embodiments are defined in the claims. Many modifications and arrangements can be made without departing from the spirit of the present invention.

DESCRIPTION OF SYMBOLS 100 ... Semiconductor integrated circuit, 10 ... Main circuit, 20H ... Upper side current source, 20L ... Lower side current source, 30 ... Reference current adjustment part, Ip ... Upper side bias current, In ... Lower side bias current, 32 ... First current mirror Circuit 34 ... second current mirror circuit.

Claims (9)

A main circuit configured to receive an upper bias current and a lower bias current and to perform predetermined signal processing in a state where they are balanced;
A reference current adjusting unit that receives the first reference current and generates a regulated second reference current;
An upper current source that is provided on the power supply terminal side of the main circuit and supplies the upper bias current to the main circuit with an amount corresponding to the second reference current as a target value;
A lower current source that is provided on the ground terminal side of the main circuit and supplies the lower bias current to the main circuit with the amount corresponding to the second reference current as a target value;
Bei to give a,
The reference current adjustment unit is configured such that (i) the dependency of the second reference current on the power supply voltage is a power supply of the upper bias current in a state where the upper current source cannot generate the upper bias current of the target value. A second reference current is generated so as to be equal to the dependence on the voltage; and (ii) in a state where the lower current source cannot generate the lower bias current of the target value. A semiconductor integrated circuit , wherein the second reference current is generated so that the dependency on the power supply voltage is equal to the dependency on the power supply voltage of the lower bias current .   A main circuit configured to receive an upper bias current and a lower bias current and to perform predetermined signal processing in a state where they are balanced;
  A reference current adjusting unit that receives the first reference current and generates a regulated second reference current;
  An upper current source that is provided on the power supply terminal side of the main circuit and supplies the upper bias current to the main circuit with an amount corresponding to the second reference current as a target value;
  A lower current source that is provided on the ground terminal side of the main circuit and supplies the lower bias current to the main circuit with the amount corresponding to the second reference current as a target value;
  With
  The reference current adjustment unit is configured to (i) the lower bias current generated by the lower current source after the decrease in a state where the upper current source cannot generate the upper bias current of the target value. The second reference current is decreased so as to be equal to the amount of current of the upper bias current, and (ii) in a state where the lower current source cannot generate the lower bias current of the target value. The second reference current is decreased so that the upper bias current generated by the source is equal to the amount of the lower bias current after the decrease, thereby reducing the upper bias current and the lower bias current. A semiconductor integrated circuit characterized by being configured to keep equal. The reference current adjuster is
A first current mirror circuit for copying the first reference current;
A second current mirror circuit that copies the output current of the first current mirror circuit and outputs the second reference current;
Including
Wherein one of the first and second current mirror circuit includes a pair of N-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor ), the other according to claim 1 or 2, characterized in that it comprises a pair of P-channel MOSFET Semiconductor integrated circuit. The main circuit is
M (Metal Oxide Semiconductor Field Effect Transistor) N-channel MOSFETs (M is a natural number) provided in series with the upper current source between the power supply terminal and the ground terminal and connected between the source and drain;
M (M is a natural number) P-channel MOSFETs provided in series with the lower current source between the power supply terminal and the ground terminal and connected between the source and drain;
Including
The reference current adjuster is
A first current mirror circuit including a pair of first conductive MOSFETs for copying the first reference current;
A second current mirror circuit including a pair of second conductive MOSFETs, copying the output current of the first current mirror circuit, and outputting the second reference current;
(M-1) first conductive MOSFETs provided on the same path as the MOSFET on the input side of the first current mirror circuit and connected between the gate and source;
(M−1) second conductive MOSFETs provided on the same path as the MOSFET on the input side of the second current mirror circuit and connected between the gate and the source;
The semiconductor integrated circuit according to claim 1 or 2, characterized in that it comprises a. The W / L (gate width / gate length) of the MOSFET constituting the first and second current mirror circuits is smaller than the W / L of the MOSFET constituting the current mirror circuit in the main circuit. The semiconductor integrated circuit according to claim 3 or 4 . The main circuit is a semiconductor integrated circuit according to any one of claims 1 to 5, characterized in that the feed-forward class AB output circuit. A main circuit configured to receive an upper bias current and a lower bias current and perform predetermined signal processing in a state where they are balanced, provided at least on a path to which the upper bias current is supplied, M (M is a natural number) N-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor) connected between the gate and the source and a path to which the lower bias current is supplied are connected between the gate and source. A main circuit including M P-channel MOSFETs;
A first current mirror circuit including a first conductive MOSFET pair and copying a first reference current having a predetermined current value;
A second current mirror circuit including a pair of second conductive MOSFETs, copying the output current of the first current mirror circuit and outputting a second reference current;
(M-1) first conductive MOSFETs provided on the same path as the MOSFET on the input side of the first current mirror circuit and connected between the gate and source;
(M−1) second conductive MOSFETs provided on the same path as the MOSFET on the input side of the second current mirror circuit and connected between the gate and the source;
An upper current source that is provided on the power supply terminal side of the main circuit and supplies the upper bias current according to the second reference current to the main circuit;
A lower current source that is provided on the ground terminal side of the main circuit and supplies the lower bias current according to the second reference current to the main circuit;
A semiconductor integrated circuit comprising:   The W / L (gate width / gate length) of the MOSFET constituting the first and second current mirror circuits is smaller than the W / L of the MOSFET constituting the current mirror circuit in the main circuit. The semiconductor integrated circuit according to claim 7. 9. The semiconductor integrated circuit according to claim 7 , wherein the main circuit is a feedforward class AB output circuit.

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