JP5192359B2 - High voltage output driver and piezoelectric pump - Google Patents

Description

  The present invention relates to a high-voltage output driver that outputs a drive signal to a load, and a piezoelectric pump using the same.

  Conventionally, a diaphragm pump using a piezoelectric element has been proposed. This pump is called a piezoelectric pump, and is driven by reciprocating the piezoelectric element and reciprocating the diaphragm by sequentially changing the direction of voltage application to the piezoelectric element.

  Such a piezoelectric pump requires a drive circuit that outputs a drive signal for the piezoelectric element, and this drive signal is composed of, for example, a pair of complementary sine waves.

JP-A-6-109068 JP-A-8-205563 Japanese Patent Laid-Open No. 2000-60847

  Here, a drive signal for a load such as a piezoelectric element has a relatively high voltage, and there may be a large shock if the drive signal in the opposite phase is suddenly stopped when the power supply falls.

  The present invention is a high-voltage output driver for driving a load, which boosts an output of a low-voltage power source to generate a high-voltage driving power source, and uses the driving power source from the boosting circuit as a power source, An output circuit for outputting a pair of complementary drive signals for driving the two, and at the time of falling of the drive power supply to stop the output, both of the drives are driven from the time when the potential difference between the pair of drive signals is substantially zero. It is characterized by changing the signals together to the ground level.

  The output circuit includes drive waveform generation means for generating a drive waveform of the load using the low-voltage power supply as a power supply, and an amplifier circuit for amplifying the drive waveform using the drive power supply as a power supply, Preferably, the drive waveform generation means generates a pair of drive waveforms corresponding to the pair of drive signals.

  Further, it is preferable that the pair of drive signals are controlled by the drive waveform until reaching the lowest level together at the time of the fall of the drive power supply, and thereafter reach the ground level by natural discharge.

  The present invention also includes a load driven by the above-described high-voltage output driver and a drive signal that is an output of the high-voltage output driver, the load being a piezoelectric element, and reciprocating a diaphragm using the piezoelectric element. The present invention relates to a piezoelectric pump driven by movement.

  It is possible to effectively prevent the occurrence of shock when the power is turned on.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

"Configuration of piezoelectric pump"
A configuration of a diaphragm pump (piezoelectric pump) using a piezoelectric element will be described with reference to FIG. Inside the pump casing 10, a diaphragm 12 whose periphery is fixed to the inner wall of the pump casing 10 and whose center side moves up and down is disposed, and a pump chamber 14 is formed on one side of the diaphragm 12. The pump chamber 14 is provided with an inlet 18 connected to the inflow passage 16 and an outlet 22 connected to the outflow passage 20. Between the inflow passage 16 and the inlet 18, a check valve 24 on the inflow side is provided. A check valve 26 on the outflow side is provided between the outflow passage 20 and the outflow port 22.

  Here, the diaphragm 12 has a structure in which piezoelectric elements PZ1 and PZ2 having electrodes on both surfaces are bonded to both the front and back surfaces of a thin metal plate M as shown in FIG. Then, an AC voltage of one phase (sine wave-like drive signal) is applied between the upper electrode of the piezoelectric element PZ1 and the lower electrode of the piezoelectric element PZ2, and the middle between the piezoelectric elements PZ1 and PZ2 An AC voltage (a sine wave-like drive signal having an opposite phase) having an opposite phase (180 degrees different) is applied to the metal plate M. As a result, the two piezoelectric elements PZ1 and PZ2 warp greatly when the applied voltage is large, and as shown in FIGS. 1 and 2, the diaphragm 12 vibrates up and down with the peripheral portion as a fulcrum and the center as the maximum amplitude. It will be.

  The check valve 24 on the inflow side allows the flow of fluid in the direction of flowing into the pump chamber 14 and blocks the opposite flow. On the other hand, the check valve 26 on the outflow side allows the flow of fluid in the direction of flowing out from the pump chamber 14 and blocks the opposite flow. Therefore, as shown in FIG. 1, the fluid in the inflow passage 16 is pushed out to the outflow passage 20 through the pump chamber 14 in accordance with the volume change of the pump chamber 14 accompanying the vibration of the diaphragm 12.

"Drive signal output circuit"
FIG. 3 shows a configuration of a drive signal output circuit that outputs a drive signal to the piezoelectric element PZ. The R-side input signal that is one drive waveform (sine wave-like AC waveform) is input to the positive input terminal of the buffer amplifier BF1. The output of the buffer amplifier BF1 is connected to the negative input terminal, and the R-side input signal is output as it is. The output of the buffer amplifier BF1 is input to the positive input terminal of the comparator (error amplifier) CP1. A feedback signal is input to the negative input terminal of the comparator CP1, and an error signal of both signals is obtained as an output of the comparator CP1. The obtained error signal is supplied to the output amplifier AP1 driven by a high power supply voltage, and the output of the output amplifier AP1 is supplied to the output terminal T1. An electrode on one side of the piezoelectric element PZ is connected to the output terminal T1, and is connected to the ground via the voltage dividing resistors R1 and R2. The midpoint of the voltage dividing resistors R1 and R2 is connected to the negative input terminal of the comparator CP1 via the terminal T2, and the voltage obtained by dividing the output voltage is negatively fed back to the comparator CP1.

  Therefore, the comparator CP1 operates so that the output voltage of the voltage dividing resistors R1 and R2, which are feedback signals, coincides with the R-side input signal. Accordingly, the drive signal ROUT from the output terminal T1 is input to the R-side input. Depending on the signal.

  The F-side input signal is a signal (complementary signal) that is 180 degrees out of phase with the R-side input signal, and the F-side input signal is input to the F-side via the buffer amplifier BF2, the comparator CP2, and the output amplifier AP2. A high-voltage drive signal corresponding to the signal is supplied to the output terminal T3. The output terminal T3 is connected to the other electrode of the piezoelectric element PZ and connected to the ground via the voltage dividing resistors R3 and R4, and the midpoint voltage of the voltage dividing resistors R3 and R4 is negative to the comparator CP2. It has been returned. Therefore, the drive signal FOUT output from the output terminal T3 has a polarity opposite to that of the drive signal ROUT from the output terminal T1, and a pair of drive signals ROUT and FOUT whose phases are 180 degrees different from the electrodes on both surfaces of the piezoelectric element PZ. Will be applied. This piezoelectric element PZ constitutes the diaphragm 12 of the above-described piezoelectric pump, and the diaphragm 12 reciprocates. The piezoelectric pump described above has two piezoelectric elements PZ1 and PZ2. However, the piezoelectric element PZ may correspond to one of them, and the diaphragm 12 is configured by one piezoelectric element PZ. May be.

  Next, the drive power supply control signal is input to the positive input terminal of the comparator CP3. A feedback signal is input to the negative input terminal of the comparator CP3. The output of the comparator CP3 is input to the negative input terminal of the comparator CP4. A preset triangular wave is supplied to the positive input terminal of the comparator CP4. Therefore, a PWM signal having a duty ratio corresponding to the output voltage of the comparator CP3 is obtained at the output of the comparator CP4. That is, if the drive power supply control signal is higher than the feedback signal, the output voltage of the comparator CP3 increases, and a PWM signal with a low duty ratio (H level period) is output from the comparator CP4. The drive power supply control signal is generated based on a control power supply voltage VCC for controlling the drive of the piezoelectric element PZ, as will be described later.

  The output of the comparator CP4 is supplied to the gates of the p-channel transistor Q1 and the n-channel transistor Q2. The transistor Q1 has a source connected to the terminal T5, a drain connected to the drain of the transistor Q2, and a source of the transistor Q2 connected to the ground. The connection point between the drains of the transistors Q1 and Q2 is connected to the terminal T6.

  The terminal T5 is connected to the anode of an external diode D1 via an external coil Lvs, and the cathode of the diode D1 is connected to the ground via an external capacitor C1. Further, the gate of the n-channel transistor Q3 is connected to the terminal T6, the drain of the transistor Q3 is connected to the connection point of the coil Lvs and the diode D1, and the source is connected to the ground.

  Therefore, when the PWM signal output from the comparator CP4 is at the H level, the transistor Q2 is turned on and the terminal T6 is at the L level, the transistor Q3 is turned off. When the PWM signal is at the L level, the transistor Q2 is turned off and the terminal T6 is turned on. Becomes H level and the transistor Q3 is turned on. When the transistor Q3 is turned on, energy is accumulated in the coil Lvs, and when the transistor Q3 is turned off, the capacitor C1 is charged according to the energy accumulated in the coil Lvs. Therefore, the longer the L level period in the output from the comparator CP4, the larger the charge amount to the capacitor C1, and the higher the drive power supply voltage that is the output from the capacitor C1. If a transistor is provided in parallel with the diode D1, it becomes easy to lower the drive power supply voltage by switching.

  The upper side of the capacitor C1 (electrode connected to the cathode of the diode D1) is connected to a terminal T7, and this terminal T7 is supplied to the output amplifiers AP1 and AP2 as a drive power supply voltage. The upper side of the capacitor C1 is connected to the ground through external voltage dividing resistors R5 and R6. The midpoint of the voltage dividing resistors R5 and R6 is connected to a terminal T8 via an external resistor R7 and a capacitor C2. The terminal T8 is connected to the negative input terminal of the comparator CP4. The resistor R7 and the capacitor C2 constitute a high-pass filter, which removes the high frequency component of the drive power supply voltage output. Further, the midpoint of the voltage dividing resistors R5 and R6 is connected to the terminal T9, and this terminal T9 is connected to the negative input terminal of the comparator CP3. Therefore, a voltage obtained by dividing the drive power supply voltage by the voltage dividing resistors R5 and R6 becomes a feedback signal (feedback signal) to be compared with the drive power supply control signal so that the voltage of the feedback signal matches the voltage of the drive power supply control signal. The drive power supply voltage is controlled.

  In this way, the drive power supply voltage can be arbitrarily controlled by the drive power supply control signal. As a result, the amplitudes of the drive signals ROUT and FOUT, which are outputs from the terminals T1 and T3, are controlled. As will be described later, the drive power control signal is supplied to the driver from the outside as the power supply voltage VCC.

  FIG. 4 shows the states of the drive signals ROUT and FOUT. By reducing the drive power supply voltage output, the amplitudes of ROUT and FOUT are reduced. Thereby, the movement of the piezoelectric element PZ is controlled, and the amplitude of the diaphragm of the piezoelectric pump is controlled, so that the discharge amount of the pump can be controlled.

"Configuration of output amplifier AP"
5 and 6 show configuration examples of the output amplifier AP. A constant current is supplied from ICOM, which is supplied to the drain and gate of n-channel transistor Q11. The source of the transistor Q11 is connected to the ground (PGND). The gates of the transistors Q11 are commonly connected to the gates of n-channel transistors Q12, Q13, Q14 whose sources are connected to the ground (PGND). Therefore, the transistors Q12, Q13, Q14 form a current mirror with respect to the transistor Q11, and the same constant current flows through these transistors Q11-Q14.

  The drain of the transistor Q12 is connected to the drain of the p-channel transistor Q15, and the source of the transistor Q15 is connected to the drive power supply VS. The drain and gate of the transistor Q15 are short-circuited, and the gates of p-channel transistors Q16 and Q17 whose sources are connected to VS are connected to this gate. Therefore, the same constant current flows through these transistors Q16 and Q17 as those flowing through the transistor Q11.

  The drain of the transistor Q13 is connected to the drive power supply VS via the p-channel transistors Q18 and Q19 whose two drains and gates are short-circuited, and the drains of the transistors Q13 and Q18 are connected to the gate of the p-channel transistor Q20. Has been. The drain of the transistor Q17 is connected to a terminal RF connected to an external ground via n-channel transistors Q21 and Q22 in which the two drains and gates are short-circuited. A connection point between the transistors Q17 and Q21 is connected to the gate of the n-channel transistor Q23.

  The source of the transistor Q20 and the drain of the transistor Q23 are connected in common to the drain of the transistor Q16 and to the gate of the p-channel transistor Q24. Further, the drain of the transistor Q20 and the source of the transistor Q23 are connected in common to the drain of the transistor Q14 and to the gate of the n-channel transistor Q25. The drive current Idr is supplied from the ICTLF terminal to the drain of the transistor Q20, the source of the transistor Q23, the drain of the transistor Q14, and the gate of the n-channel transistor Q25. That is, the ICTLF terminal is connected to the output of the comparator CP1 (or the comparator CP2).

  The source of the transistor Q24 is connected to the drive power supply VS, the drain is connected to the drain of the transistor Q25 and the output terminal OUT (T1 or T3), and the source of the transistor Q25 is connected to the terminal RF. Yes.

  In such a circuit, a current obtained by dividing the constant current flowing through the transistor Q16 flows through the transistor Q20 and the transistor Q23. In addition, a constant current flowing through the transistor Q13 flows through the transistors Q19 and Q18, and a current flowing through the transistor Q17 flows through the transistors Q21 and Q22. Therefore, normally, the currents flowing through the transistors Q20 and Q23 are equal.

  When the drive current Idr is a current Idr + flowing toward the gate of the transistor Q25, as shown in FIG. 5, the transistor Q25 is turned on, a current flows in a direction of drawing a current from the output terminal OUT, and the output terminal OUT Move to the L level. At this time, since the sum of the currents flowing through the transistors Q20 and Q23 is equal to the constant current flowing through the transistor Q14, the transistor Q24 is off.

  On the other hand, if the drive current Idr is the current Idr− that flows in the direction of pulling out from the gate of the transistor Q25, the drain current of the transistor Q23 increases as shown in FIG. 6, the transistor Q24 is turned on, and the output terminal OUT Current flows in the direction of discharging current, and the output terminal OUT moves to the H level side.

  In this way, the output transistors Q24 and Q25 are controlled according to the current flowing through the ICTLF, and the output from the output terminal OUT is controlled. The output amplifier AP functions as a high withstand voltage output unit that obtains an output by power from the drive power supply VS. Therefore, the amplifiers shown in FIGS. 5 and 6 are prepared as the output amplifiers AP1 and AP2 in FIG. 3, and the outputs of the comparators CP1 and CP2 are input to the ICTLF of the respective amplifiers. ROUT and FOUT can be obtained respectively.

  The power supply voltage of the signal system is, for example, about 5V, and the drive power supply VS is, for example, about 200V.

“Configuration of VCC-linked DAC”
In a conventional apparatus, there is a case in which a circuit that can output a power supply voltage VCC that is a control power supply voltage for controlling fan driving is already prepared for fan drive control. In this case, it is preferable to generate a signal for controlling the piezoelectric element PZ in accordance with the power supply voltage VCC.

  FIG. 7 shows a configuration suitable for such a case. A terminal T11 to which a power supply VCC whose voltage inputted from the outside is appropriately changed according to the drive request of the pump is connected to the ground via a voltage dividing resistor composed of resistors R11 and R12 connected in series. The middle point of the voltage dividing resistors R11 and R12 is input to the positive input terminal of the buffer amplifier BF11 whose output is short-circuited to the negative input terminal, and this output is the power supply VDAC of the D / A converter 30.

  In this example, the reference V1 is input to the positive input terminal, the middle point of the voltage dividing resistors R11 and R12 is connected to the negative input terminal, and the middle point of the voltage dividing resistors R11 and R12 is output via the diode D11. And the reference V2 is input to the positive input terminal, the midpoint of the voltage dividing resistors R11 and R12 is connected to the negative input terminal, and the output of the voltage dividing resistors R11 and R12 is connected via the diode D12. And a comparator CP12 connected to the midpoint. The diode D11 passes only the current flowing from the middle point of the voltage dividing resistors R11 and R12 toward the output of the comparator CP11, and the diode D12 flows from the output of the comparator CP11 toward the middle point of the voltage dividing resistors R11 and R12. Only shed. Therefore, the midpoint voltage of the voltage dividing resistors R11 and R12 is clipped by the reference voltages V1 and V2. Therefore, the power supply VDAC changes as shown in FIG. 8 as the power supply voltage VCC changes. That is, the power supply VDAC linearly changes from V2 to V1 when the power supply voltage VCC is 0 to V2 (R11 + R12) / R12, and between V2 (R11 + R12) / R12 to V1 (R11 + R12) / R12, V1 At (R11 + R12) / R12 or higher, it is fixed at V1.

  FIG. 9 shows the configuration of the D / A converter 30. A resistor corresponding to the number of bits of the input digital signal is connected in series between the power supply VDAC and the ground. Two switches are provided corresponding to the connection points between the resistors, and the ends of the R-side switch group SWr on one side that are not on the resistance side are commonly connected to output the R-side signal and the other side. The ends of the F-side switch group SWf that are not on the resistance side are commonly connected to output an F-side signal.

  A counter circuit 32 is provided to control the R side and F side switch groups. The counter 32 repeats up-counting and down-counting a predetermined clock. For example, the 512-stage count value is repeatedly output in order of 0 → 511 → 0 → 511. The outputs of these counters are associated with each other so that the R-side switch group SWr and the F-side switch group SWf have the opposite outputs. That is, the output of the F-side switch group SWf is set to 511 if the output of the R-side switch group SWr is 0 when the output of the counter 32 is 0.

  Accordingly, the R side signal and the F side signal become complementary sine curves that sequentially change with respect to one clock, as shown in the figure. As the power supply VDAC changes, the amplitudes of the R side signal and the F side signal change in conjunction with each other. Therefore, an R-side signal and an F-side signal whose amplitude changes according to the power supply VCC are obtained at the output of the D / A converter 30. Further, the maximum output of the D / A converter 30 is output as a drive power supply control signal.

  9 is input to the buffer amplifiers BF1 and BF2 and the comparator CP3 in FIG. Then, by appropriately setting the ratio of the voltage dividing resistors R1, R2, R3, R4, R5, and R6, the discharge amount of the piezoelectric pump can be controlled to the target value according to the input VCC. Become.

  In FIG. 9, the R-side signal and the F-side signal are output from the D / A converter 30 as they are. However, the R side signal and the F side signal are vertically symmetrical. Accordingly, only half (180 degrees) of output can be output from the D / A converter 30, and the output of the other half can be inverted. As a result, the resistor string in the D / A converter 30 can be halved.

"Processing at startup"
FIG. 10 shows the waveforms of the drive power supply voltage and the drive signals ROUT and FOUT when the power supply rises.

  In this way, after the drive power supply is turned on, ROUT and FOUT change with the same phase for a predetermined period. In this example, ROUT and FOUT change together from voltage 0 to the first midpoint voltage of amplitude. From the point of time when the midpoint voltage is reached, the output becomes the original ROUT and FOUT. In this example, the phase of FOUT is inverted until the midpoint voltage is reached, and when the midpoint voltage is reached, the phase is inverted.

  In this way, at the start of driving, ROUT and FOUT are maintained at the same value (voltage difference is 0) for a predetermined period, and then a normal voltage is applied so that a large voltage is suddenly applied to the piezoelectric element. It is possible to reduce the shock at the start-up.

  FIG. 11 shows another example. In this example, after the drive power supply is started, both ROUT and FOUT are changed together from the voltage 0v to the maximum voltage. Thereafter, the FOUT shifts to a normal change as a sine wave, but a constant value is maintained for ROUT. Then, when the time of 180 degrees has passed, the ROUT change is started. That is, at the stage advanced by 180 degrees, FOUT is at the minimum voltage, and ROUT is at the maximum voltage, so the change of ROUT is started after waiting here.

  Also by this, a voltage difference is gradually generated from the same voltage in ROUT and FOUT, and sudden application of a large voltage to the piezoelectric element can be prevented.

  Furthermore, FIG. 12 shows still another example. In this example, after the drive power supply is turned on, both ROUT and FOUT are maintained at the voltage 0v at a minimum voltage for a certain period (a period of 180 degrees). Then, the change is started with FOUT as a normal sine wave from the lowest voltage. On the other hand, ROUT maintains the minimum voltage for a period of 180 degrees later, and when ROUT reaches the maximum voltage, the ROUT change starts from the minimum voltage. That is, at the stage advanced by 180 degrees, FOUT is at the maximum voltage, and ROUT becomes the minimum voltage, so the change of ROUT is started after waiting here.

  Also by this, a voltage difference is gradually generated from the same voltage in ROUT and FOUT, and sudden application of a large voltage to the piezoelectric element can be prevented.

  The generation of the drive signals ROUT and FOUT as described above is preferably performed by adjusting the R side signal and the F side signal generated in the D / A converter 30 shown in FIG. In order to output the waveforms as shown in FIGS. 10 to 12, the switching of the switches in the D / A converter 30 may be controlled by the output from the counter 32. For example, in order to obtain a waveform as shown in FIG. 10, it is only necessary to turn on the switch for obtaining the R-side signal and the F-side signal at the same position and return to the original switching from the position of the midpoint voltage. In order to obtain waveforms as shown in FIGS. 11 and 12, the R-side signal switch may be turned on so that the uppermost or lowermost switch is turned on for a period of 180 degrees, and then normal switching is performed.

"Processing at the time of falling"
FIG. 13 is a diagram showing waveforms of the drive power supply voltage and the drive signals ROUT and FOUT when the power supply falls. When an abnormality is detected or the power switch is turned off, the operation of the booster circuit is stopped, the drive power supply output is turned off, and the drive signals ROUT and FOUT are also stopped.

  Here, when the output of the drive signal is stopped, as shown in FIG. 13, the waveform of FOUT is made the same as ROUT from the time when the drive signals ROUT and FOUT reach the same middle point. When the lowest point is reached, the output is stopped.

  Such control is performed by controlling the drive waveform output from the D / A converter 30 shown in FIG. In the example of FIG. 13, the drive waveform corresponding to the drive signal FOUT may be a waveform that rises to the middle point and then decreases to the lowest point.

  As a result, when the applied voltage to the piezoelectric element is 0 V, the voltages of both electrodes of the piezoelectric element are lowered together, and the driving can be stopped in a state where no shock is applied to the piezoelectric element.

  Note that the drive power supply voltage is decreased by stopping the boosting and discharging the charge charged in the external capacitor C1 through the resistors R5 and R6. Also, the output of the drive signals ROUT and FOUT is stopped when the minimum voltage is reached, and thereafter the electrode voltage is lowered to the ground level by the discharge through the resistors R1, R2, R3, and R4.

"Control of drive power supply voltage"
As described above, in this embodiment, the drive power supply control signal is generated according to the power supply voltage VCC to control the boosting. Here, the drive power supply voltage needs to be larger than the drive signals ROUT and FOUT, but need not be constant. Therefore, it is preferable to change the drive power supply control signal in accordance with the waveform of the drive signal as shown in FIG. That is, as shown in FIG. 14, a switch 34 is provided to generate a signal that takes the larger of the R-side signal and the F-side signal (a signal that continues only on the peak side) and uses this as a drive power control signal. This drive control signal is supplied to the booster circuit in FIG. For this reason, as shown in FIG. 15, only the peaks where the drive power supply voltage is slightly higher than the envelopes of the drive signals ROUT and FOUT are obtained. As a result, loss in the output transistor in driving the piezoelectric element can be reduced and efficient driving of the piezoelectric element can be achieved.

  FIG. 16 shows the R-side signal and the F-side signal, which are the outputs of FIG. In this way, complementary R-side signals and F-side signals are obtained as outputs of the D / A converter 30, and when the power supply is turned off, the R-side signals and the F-side signals are reduced. Further, in this example, the drive power control signal is a signal that is offset by a predetermined value higher than the R side signal and the F side signal. This offset may be offset by a predetermined offset power source, but it is also preferable to offset the output of the D / A converter 30 itself. That is, the D / A converter 30 has a margin for creating the R side signal and the F side signal, and the R side signal and the F side signal are lower than the maximum output value of the D / A converter 30 by a predetermined value or more. The drive power control signal may be output as a value higher by a predetermined value than the higher of the R side signal and the F side signal. As a result, a drive power control signal as shown in FIG. 16 can be obtained. When the R side signal and the F side signal have the same value, the drive power control signal is set to 0V, and then the R side signal and the F side signal are moved to 0V. In this way, by using the output as shown in FIG. 16, the waveform as shown in FIG. 15 is obtained as the drive signal and the drive power supply voltage.

  It is preferable to obtain the R-side signal and the F-side signal at the time of rising at the output of the D / A converter 30 even at the time of rising, but the R-side signal and the F-side signal are similarly applied to the drive power control signal. It is preferable to set a signal higher than the envelope by a predetermined value.

It is a figure which shows the structure of a piezoelectric pump. It is a figure which shows the structure of the diaphragm of a piezoelectric pump. It is a figure which shows the structure of the output part of a high voltage output driver. It is a figure which shows the waveform of a drive signal. It is a figure which shows the structure of an output amplifier. It is a figure which shows the structure of an output amplifier. It is a figure which shows the structure for the output of power supply VDAC. It is a figure which shows the characteristic with respect to the power supply VCC of the power supply VDAC. It is a figure which shows the structure of the D / A converter which obtains the output of the output amplitude according to power supply VDAC. It is a figure which shows an example of the waveform of the drive signal at the time of rising. It is a figure which shows the other example of the waveform of the drive signal at the time of rising. It is a figure which shows the further another example of the waveform of the drive signal at the time of rising. It is a figure which shows an example of the waveform of the drive signal at the time of a fall. It is a figure which shows the structure of the D / A converter which outputs a R side signal, a F side signal, and a drive power supply control signal. It is a figure which shows an example of the waveform of the drive signal at the time of a fall. It is a figure which shows an example of the waveform of the R side signal at the time of a fall, an F side signal, and a drive power supply control signal.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 Pump casing, 12 Diaphragm, 14 Pump chamber, 16 Inlet part, 18 Inlet part, 20 Outlet part, 22 Outlet part, 24,26 Check valve, 30 Converter, 32 Counter circuit, AP1, AP2 Output amplifier, BF1, BF2 , BF11 buffer amplifier, C1, C2 capacitors, CP1, CP2, CP3, CP4, CP11, CP12 comparators, D1, D11, D12 diodes, Q1-Q3, Q11-Q25 transistors, R1-R7, R11, R12 resistors.

Claims (4)

A high voltage output driver for driving a load,
A booster circuit that boosts the output of the low-voltage power supply to generate a high-voltage drive power supply;
An output circuit that outputs a pair of complementary drive signals for driving the load, using the drive power supply from the booster circuit as a power supply;
Have
A high-voltage output driver characterized in that both drive signals are changed together to the ground level from the time when the potential difference between the pair of drive signals is substantially zero at the fall of the drive power supply for stopping output. The high voltage output driver according to claim 1,
The output circuit is
Drive waveform generating means for generating a drive waveform of the load using the low-voltage power supply as a power supply;
An amplification circuit that amplifies the drive waveform using the drive power supply as a power supply;
Have
A high voltage output driver characterized in that the drive waveform generating means generates a pair of drive waveforms corresponding to a pair of drive signals. The high voltage output driver according to claim 2,
A high-voltage output driver characterized in that, when the drive power supply falls, the pair of drive signals are controlled by the drive waveform until reaching the lowest level together, and then reach the ground level by natural discharge. A load driven by a high-voltage output driver according to any one of claims 1 to 3 and a drive signal that is an output of the high-voltage output driver,
The piezoelectric pump, wherein the load is a piezoelectric element, and is driven by reciprocating a diaphragm using the piezoelectric element.

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