JP5276824B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP5276824B2 JP5276824B2 JP2007270744A JP2007270744A JP5276824B2 JP 5276824 B2 JP5276824 B2 JP 5276824B2 JP 2007270744 A JP2007270744 A JP 2007270744A JP 2007270744 A JP2007270744 A JP 2007270744A JP 5276824 B2 JP5276824 B2 JP 5276824B2
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 35
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 33
- 238000005530 etching Methods 0.000 claims abstract description 98
- 230000008033 biological extinction Effects 0.000 claims abstract description 60
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 56
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 56
- 239000010703 silicon Substances 0.000 claims abstract description 56
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 claims abstract description 34
- 229910001882 dioxygen Inorganic materials 0.000 claims abstract description 34
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 239000010410 layer Substances 0.000 claims description 51
- 239000011229 interlayer Substances 0.000 claims description 40
- 229910052751 metal Inorganic materials 0.000 claims description 22
- 239000002184 metal Substances 0.000 claims description 22
- 239000007789 gas Substances 0.000 claims description 13
- 238000003860 storage Methods 0.000 claims description 8
- 150000004767 nitrides Chemical class 0.000 claims description 4
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 claims description 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 3
- 239000011737 fluorine Substances 0.000 claims description 3
- 229910052731 fluorine Inorganic materials 0.000 claims description 3
- 239000001257 hydrogen Substances 0.000 claims description 3
- 229910052739 hydrogen Inorganic materials 0.000 claims description 3
- 238000000034 method Methods 0.000 abstract description 24
- 230000005855 radiation Effects 0.000 abstract 4
- 238000010521 absorption reaction Methods 0.000 description 21
- 230000000052 comparative effect Effects 0.000 description 15
- 229910052814 silicon oxide Inorganic materials 0.000 description 11
- 230000015572 biosynthetic process Effects 0.000 description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 238000001020 plasma etching Methods 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 4
- 239000005380 borophosphosilicate glass Substances 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 229910052786 argon Inorganic materials 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910018557 Si O Inorganic materials 0.000 description 1
- 229910007991 Si-N Chemical group 0.000 description 1
- 229910006294 Si—N Chemical group 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- -1 arsenic ions Chemical class 0.000 description 1
- 230000002354 daily effect Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000003203 everyday effect Effects 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Inorganic materials [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/942—Masking
- Y10S438/948—Radiation resist
- Y10S438/952—Utilizing antireflective layer
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Semiconductor Memories (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Drying Of Semiconductors (AREA)
- Non-Volatile Memory (AREA)
Description
12 ビットライン
14 トンネル絶縁膜
16 電荷蓄積層
18 トップ絶縁膜
20 ONO膜
22 ワードライン
24 層間絶縁膜
26 紫外線吸収膜
28 反射防止膜
30 キャップ層
32 プラグ金属
34 フォトレジスト
36 第1開口部
38 第2開口部
42 配線層
44 層間絶縁膜
46 キャップ層
48 反射防止膜
50 第1開口部
52 第2開口部
54 プラグ金属
Claims (9)
- シリコンリッチな酸化膜およびシリコンリッチな窒化膜の少なくとも一方を含むシリコンリッチ膜を半導体基板上に形成する工程と、
前記シリコンリッチ膜の紫外線に対する消衰係数を測定する工程と、
前記消衰係数に対応した酸素ガス流量を用いたエッチング条件により、前記シリコンリッチ膜をエッチングする工程と、を有することを特徴とする半導体装置の製造方法。 - 前記半導体基板と前記シリコンリッチ膜との間に第1絶縁膜を形成する工程と、
前記消衰係数に対応した酸素ガス流量を用いたエッチング条件により、前記シリコンリッチ膜をエッチングした領域下の前記第1絶縁膜の一部をエッチングして、第1開口部を形成する工程と、
所定の酸素ガス流量を用いたエッチング条件により、前記第1開口部下の前記第1絶縁膜をエッチングして、第2開口部を形成する工程と、を有することを特徴とする請求項1記載の半導体装置の製造方法。 - 前記第1絶縁膜は酸化膜であることを特徴とする請求項2記載の半導体装置の製造方法。
- 前記半導体基板内を延伸するようにビットラインを形成する工程を有し、
前記第1開口部を形成する工程は、前記ビットライン上に形成されるように、前記第1開口部を形成する工程を含み、
前記第2開口部を形成する工程は、前記第1開口部下の前記第1絶縁膜をエッチングして、前記シリコンリッチ膜と前記第1絶縁膜とを貫通し、前記ビットラインが露出するように、前記第2開口部を形成する工程を含むことを特徴とする請求項2または3記載の半導体装置の製造方法。 - 前記半導体基板と前記第1絶縁膜との間に電荷蓄積層を含むONO膜を形成する工程と、
前記シリコンリッチ膜上に反射防止膜を形成する工程と、を有し、
前記シリコンリッチ膜は紫外線を吸収する紫外線吸収膜であり、前記第1絶縁膜は層間絶縁膜であり、
前記第1開口部を形成する工程は、前記反射防止膜、前記紫外線吸収膜および前記層間絶縁膜の一部をエッチングして、前記第1開口部を形成する工程を含み、
前記第2開口部を形成する工程は、前記第1開口部下の前記層間絶縁膜および前記ONO膜をエッチングして、前記反射防止膜、前記紫外線吸収膜、前記層間絶縁膜および前記ONO膜を貫通し、前記ビットラインが露出するように、前記第2開口部を形成する工程を含むことを特徴とする請求項4記載の半導体装置の製造方法。 - 前記半導体基板と前記第1絶縁膜との間に配線層を形成する工程を有し、
前記第1開口部を形成する工程は、前記配線上に形成されるように、前記第1開口部を形成する工程を含み、
前記第2開口部を形成する工程は、前記第1開口部下の前記第1絶縁膜をエッチングして、前記シリコンリッチ膜と前記第1絶縁膜とを貫通し、前記配線層が露出するように、前記第2開口部を形成する工程を含むことを特徴とする請求項2または3記載の半導体装置の製造方法。 - 前記シリコンリッチ膜は反射防止膜であることを特徴とする請求項6記載の半導体装置の製造方法。
- 前記第2開口部に金属を埋め込むことにより、プラグ金属を形成する工程を有することを特徴とする請求項4から7のいずれか一項記載の半導体装置の製造方法。
- 前記シリコンリッチ膜をエッチングする工程は、水素とフッ素とを含んだガスを用いることを特徴とする請求項1から8のいずれか一項記載の半導体装置の製造方法。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007270744A JP5276824B2 (ja) | 2007-10-17 | 2007-10-17 | 半導体装置の製造方法 |
US12/253,035 US7781320B2 (en) | 2007-10-17 | 2008-10-16 | Method for fabricating a semiconductor device by considering the extinction coefficient during etching of an interlayer insulating film |
US12/840,063 US8440557B2 (en) | 2007-10-17 | 2010-07-20 | Method for fabricating a semiconductor device by considering the extinction coefficient during etching of an interlayer insulating film |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007270744A JP5276824B2 (ja) | 2007-10-17 | 2007-10-17 | 半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2009099813A JP2009099813A (ja) | 2009-05-07 |
JP5276824B2 true JP5276824B2 (ja) | 2013-08-28 |
Family
ID=40702526
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007270744A Expired - Fee Related JP5276824B2 (ja) | 2007-10-17 | 2007-10-17 | 半導体装置の製造方法 |
Country Status (2)
Country | Link |
---|---|
US (2) | US7781320B2 (ja) |
JP (1) | JP5276824B2 (ja) |
Family Cites Families (26)
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US4690728A (en) * | 1986-10-23 | 1987-09-01 | Intel Corporation | Pattern delineation of vertical load resistor |
EP0265584A3 (en) * | 1986-10-30 | 1989-12-06 | International Business Machines Corporation | Method and materials for etching silicon dioxide using silicon nitride or silicon rich dioxide as an etch barrier |
US5382545A (en) * | 1993-11-29 | 1995-01-17 | United Microelectronics Corporation | Interconnection process with self-aligned via plug |
JPH08153708A (ja) * | 1994-11-29 | 1996-06-11 | Nec Corp | エッチング装置およびエッチング方法 |
US5897372A (en) * | 1995-11-01 | 1999-04-27 | Micron Technology, Inc. | Formation of a self-aligned integrated circuit structure using silicon-rich nitride as a protective layer |
JPH11214507A (ja) * | 1998-01-21 | 1999-08-06 | Nec Corp | 半導体装置の配線構造およびその製造方法 |
US6045954A (en) * | 1998-06-12 | 2000-04-04 | Industrial Technology Research Institute | Formation of silicon nitride film for a phase shift mask at 193 nm |
TW415060B (en) * | 1998-08-31 | 2000-12-11 | United Microelectronics Corp | Manufacturing method of self-aligned via hole in the multilevel interconnects |
US6255717B1 (en) * | 1998-11-25 | 2001-07-03 | Advanced Micro Devices, Inc. | Shallow trench isolation using antireflection layer |
US7061075B1 (en) * | 1998-11-25 | 2006-06-13 | Advanced Micro Devices, Inc. | Shallow trench isolation using antireflection layer |
US6235653B1 (en) * | 1999-06-04 | 2001-05-22 | Taiwan Semiconductor Manufacturing Company | Ar-based si-rich oxynitride film for dual damascene and/or contact etch stop layer |
US6207556B1 (en) * | 1999-07-09 | 2001-03-27 | United Microelectronics Corp. | Method of fabricating metal interconnect |
US6326301B1 (en) * | 1999-07-13 | 2001-12-04 | Motorola, Inc. | Method for forming a dual inlaid copper interconnect structure |
US6383874B1 (en) * | 2001-03-07 | 2002-05-07 | Advanced Micro Devices, Inc. | In-situ stack for high volume production of isolation regions |
JP2002269328A (ja) * | 2001-03-12 | 2002-09-20 | Pioneer Electronic Corp | 予算管理システムおよび方法ならびに予算管理用記録媒体 |
US20020197835A1 (en) * | 2001-06-06 | 2002-12-26 | Sey-Ping Sun | Anti-reflective coating and methods of making the same |
JP2003060031A (ja) * | 2001-08-14 | 2003-02-28 | Oki Electric Ind Co Ltd | 半導体装置及びその製造方法。 |
US6790772B2 (en) * | 2002-05-09 | 2004-09-14 | Macronix International Co., Ltd. | Dual damascene processing method using silicon rich oxide layer thereof and its structure |
US6774432B1 (en) * | 2003-02-05 | 2004-08-10 | Advanced Micro Devices, Inc. | UV-blocking layer for reducing UV-induced charging of SONOS dual-bit flash memory devices in BEOL |
US7916986B2 (en) * | 2004-03-15 | 2011-03-29 | Sharp Laboratories Of America, Inc. | Erbium-doped silicon nanocrystalline embedded silicon oxide waveguide |
JP4813778B2 (ja) * | 2004-06-30 | 2011-11-09 | 富士通セミコンダクター株式会社 | 半導体装置 |
JP2006202841A (ja) * | 2005-01-18 | 2006-08-03 | Alps Electric Co Ltd | シリコン基板の加工方法 |
JP2007158289A (ja) * | 2005-11-11 | 2007-06-21 | Matsushita Electric Ind Co Ltd | 半導体記憶装置およびその製造方法 |
US7602067B2 (en) * | 2007-12-17 | 2009-10-13 | Spansion Llc | Hetero-structure variable silicon rich nitride for multiple level memory flash memory device |
US20100051096A1 (en) * | 2008-08-26 | 2010-03-04 | Sixtron Advanced Materials, Inc. | Silicon carbonitride antireflective coating |
US8158335B2 (en) * | 2008-09-15 | 2012-04-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | High etch resistant material for double patterning |
-
2007
- 2007-10-17 JP JP2007270744A patent/JP5276824B2/ja not_active Expired - Fee Related
-
2008
- 2008-10-16 US US12/253,035 patent/US7781320B2/en not_active Expired - Fee Related
-
2010
- 2010-07-20 US US12/840,063 patent/US8440557B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP2009099813A (ja) | 2009-05-07 |
US7781320B2 (en) | 2010-08-24 |
US8440557B2 (en) | 2013-05-14 |
US20090269864A1 (en) | 2009-10-29 |
US20100279441A1 (en) | 2010-11-04 |
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