JP4810958B2 - ハイブリット回路装置 - Google Patents
ハイブリット回路装置 Download PDFInfo
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- JP4810958B2 JP4810958B2 JP2005296735A JP2005296735A JP4810958B2 JP 4810958 B2 JP4810958 B2 JP 4810958B2 JP 2005296735 A JP2005296735 A JP 2005296735A JP 2005296735 A JP2005296735 A JP 2005296735A JP 4810958 B2 JP4810958 B2 JP 4810958B2
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
- H01L2224/24195—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being a discrete passive component
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Optical Couplings Of Light Guides (AREA)
- Optical Integrated Circuits (AREA)
Description
Claims (3)
- 貫通開口部からなる複数個の部品装填開口部を形成したシリコン基板と、上記各部品装填開口部内に、それぞれの入出力部形成面が上記シリコン基板の第1主面と略同一面を構成して装填され、少なくとも1個が光学素子である複数個の実装部品と、上記各部品装填開口部にそれぞれ充填された封止材によって形成され、上記各実装部品をそれぞれの上記入出力部形成面を上記シリコン基板の第1主面に露出させた状態で上記各部品装填開口部内に埋め込んで固定する封止層と、上記シリコン基板の上記第1主面上に形成され、この第1主面に露出された上記各実装部品の上記各入出力部形成面に設けられた入出力部と接続される配線パターンを有する配線層とから構成され、光透過性を有する絶縁樹脂によって絶縁層を形成するとともに、上記光学素子の光学信号入出力部と対向する部位を厚み方向の全域に亘って上記配線パターンの非形成領域として上記配線層内に設けられて光学信号を透過する光学信号伝送路と、上記配線層の表面側に、一端部を上記光学信号伝送路と対向されるとともに他端部を側方側に引き出されて設けられた光導波路部材とによって構成され、上記光学素子の光学信号入出力部と対向する上記シリコン基板の上記第1主面上と、上記配線層内と、上記配線層の表面上の少なくともいずれか1箇所に、光学信号を伝送する光学信号伝送路手段が設けられ、上記シリコン基板の第2主面の全面に、上記各部品装填開口部の開口部を閉塞して高熱伝導率特性を有する金属板からなる補強板部材が接合され、この補強板部材が補強機能と上記各実装部品から発生した熱を放熱する放熱機能とを奏する第1のハイブリットモジュールと、
貫通開口部からなる複数個の部品装填開口部を形成したシリコン基板と、上記各部品装填開口部内に、それぞれの入出力部形成面が上記シリコン基板の第1主面と略同一面を構成して装填され、少なくとも1個が光学素子である複数個の実装部品と、上記各部品装填開口部にそれぞれ充填された封止材によって形成され、上記各実装部品をそれぞれの上記入出力部形成面を上記シリコン基板の第1主面に露出させた状態で上記各部品装填開口部内に埋め込んで固定する封止層と、上記シリコン基板の上記第1主面上に形成され、この第1主面に露出された上記各実装部品の上記各入出力部形成面に設けられた入出力部と接続される配線パターンを有する配線層とから構成され、光透過性を有する絶縁樹脂によって絶縁層を形成するとともに、上記光学素子の光学信号入出力部と対向する部位を厚み方向の全域に亘って上記配線パターンの非形成領域として上記配線層内に設けられて光学信号を透過する光学信号伝送路と、上記配線層の表面側に、一端部を上記光学信号伝送路と対向されるとともに他端部を側方側に引き出されて設けられた光導波路部材とによって構成され、上記光学素子の光学信号入出力部と対向する上記シリコン基板の上記第1主面上と、上記配線層内と、上記配線層の表面上の少なくともいずれか1箇所に、光学信号を伝送する光学信号伝送路手段が設けられ、上記シリコン基板の第2主面の全面に、上記各部品装填開口部の開口部を閉塞して高熱伝導率特性を有する金属板からなる補強板部材が接合され、この補強板部材が補強機能と上記各実装部品から発生した熱を放熱する放熱機能とを奏する第2のハイブリットモジュールと、
上記第1のハイブリットモジュールと第2のハイブリットモジュールを、上記配線層の表面に形成したバンプを介して第1主面上に実装する配線基板とを備え、
上記配線基板に、上記光学素子として発光素子を実装した第1ハイブリットモジュールと上記光学素子として受光素子を実装した第2ハイブリットモジュールとが実装されるとともに、上記第1ハイブリットモジュールの上記発光素子の光学信号出力部と対向する光学信号伝送路と上記第2ハイブリットモジュールの上記受光素子の光学信号入力部と対向する光学信号伝送路とに相対する端部が対向されて光導波路部材が設けられたハイブリット回路装置。 - 上記配線基板には、上記光学素子の光学信号入出力部と対向する部位に厚み方向に貫通して形成されて光学信号を透過させる光学信号伝送路を構成するスルーホールが形成され、当該配線基板の第2主面に、一端部を上記スルーホールに対向されるとともに他端部を側方側に引き出された光導波路部材が配された請求項1に記載のハイブリット回路装置。
- 上記配線基板に形成した上記スルーホールに光学レンズが嵌め込まれた請求項2に記載のハイブリット回路装置。
Priority Applications (1)
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JP2005296735A JP4810958B2 (ja) | 2005-02-28 | 2005-10-11 | ハイブリット回路装置 |
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JP2005054848 | 2005-02-28 | ||
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JP2005296735A JP4810958B2 (ja) | 2005-02-28 | 2005-10-11 | ハイブリット回路装置 |
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JP2006270037A JP2006270037A (ja) | 2006-10-05 |
JP4810958B2 true JP4810958B2 (ja) | 2011-11-09 |
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Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
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JP5384819B2 (ja) * | 2007-12-07 | 2014-01-08 | 日本特殊陶業株式会社 | 光電気混載パッケージ、光電気混載モジュール |
JP5380903B2 (ja) * | 2008-05-14 | 2014-01-08 | 凸版印刷株式会社 | 光基板の製造方法 |
JP2010211179A (ja) * | 2009-02-13 | 2010-09-24 | Hitachi Ltd | 光電気複合配線モジュールおよびその製造方法 |
JP5877673B2 (ja) | 2011-09-07 | 2016-03-08 | 新光電気工業株式会社 | 配線基板及びその製造方法、半導体パッケージ |
JP5882720B2 (ja) * | 2011-12-21 | 2016-03-09 | 京セラ株式会社 | 受発光素子モジュールおよびこれを用いたセンサ装置 |
JP6592948B2 (ja) * | 2015-04-21 | 2019-10-23 | 富士通株式会社 | 半導体装置の製造方法 |
JP6959731B2 (ja) | 2016-11-30 | 2021-11-05 | 日東電工株式会社 | 光電気混載基板 |
JP7176842B2 (ja) * | 2017-12-12 | 2022-11-22 | 日東電工株式会社 | 光電気混載基板 |
JP2019179782A (ja) * | 2018-03-30 | 2019-10-17 | ソニーセミコンダクタソリューションズ株式会社 | 半導体装置および半導体装置の製造方法 |
JPWO2021162108A1 (ja) * | 2020-02-12 | 2021-08-19 | ||
JP2022115723A (ja) | 2021-01-28 | 2022-08-09 | アイオーコア株式会社 | 光電気モジュール |
CN114512589B (zh) * | 2022-04-21 | 2022-06-17 | 威海三维曲板智能装备有限公司 | 一种光电混合封装结构及其制造方法 |
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US4630096A (en) * | 1984-05-30 | 1986-12-16 | Motorola, Inc. | High density IC module assembly |
JP2002006161A (ja) * | 2000-06-19 | 2002-01-09 | Sony Corp | 光配線基板および光配線モジュール並びにそれらの製造方法 |
JP4036644B2 (ja) * | 2000-12-22 | 2008-01-23 | イビデン株式会社 | Icチップ実装用基板、icチップ実装用基板の製造方法、および、光通信用デバイス |
JP2003110121A (ja) * | 2001-09-28 | 2003-04-11 | Ibiden Co Ltd | 光学素子実装用基板の製造方法及び光学素子実装用基板 |
JP2004079736A (ja) * | 2002-08-15 | 2004-03-11 | Sony Corp | チップ内蔵基板装置及びその製造方法 |
JP4042555B2 (ja) * | 2002-12-09 | 2008-02-06 | ソニー株式会社 | 半導体回路素子・光学素子混載ハイブリットモジュール及びその製造方法 |
JP2004327516A (ja) * | 2003-04-22 | 2004-11-18 | Toppan Printing Co Ltd | 多層光電気混載基板およびその製造方法 |
EP1487019A1 (en) * | 2003-06-12 | 2004-12-15 | Koninklijke Philips Electronics N.V. | Electronic device and method of manufacturing thereof |
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