JP4797791B2 - Integrated circuit device and electronic apparatus - Google Patents

Description

  The present invention relates to an integrated circuit device and an electronic apparatus.

  There is a display driver (LCD driver) as an integrated circuit device for driving a display panel such as a liquid crystal panel. This display driver is required to reduce the chip size in order to reduce the cost.

  However, the size of a display panel incorporated in a mobile phone or the like is almost constant. Therefore, if a fine process is adopted and the integrated circuit device of the display driver is simply shrunk to reduce the chip size, problems such as difficulty in mounting are caused.

  There are various display panel types (amorphous TFT, low-temperature polysilicon TFT) and display pixel numbers (QCIF, QVGA, VGA). Therefore, it is necessary to provide a user with a model corresponding to such various types of display panels.

Further, when the layout of the circuit block of the integrated circuit device is changed, if the influence extends to other circuit blocks, problems such as inefficiency of design and prolongation of the development period are caused.
JP 2001-222249 A

  The present invention has been made in view of the above technical problems, and an object of the present invention is to provide an integrated circuit device capable of reducing a circuit area and improving design efficiency and an electronic apparatus including the integrated circuit device. There is to do.

  In the present invention, the direction from the first side, which is the short side of the integrated circuit device, to the third side facing the first side is the first direction, and the second side, which is the long side of the integrated circuit device, faces the second side. 4 includes first to Nth circuit blocks (N is an integer greater than or equal to 2) arranged along the first direction, where the direction toward the side 4 is the second direction. The Nth circuit block stores a scan driver block for driving a scan line, a power supply circuit block for generating a power supply voltage, at least one data driver block for driving a data line, and image data. At least one memory block, and the data driver block and the memory block are arranged adjacent to each other in the first direction, and the power supply circuit block includes the scan driver block, the data driver block, and the data driver block. Related to integrated circuit device is disposed between the driver block and the memory block.

  In the present invention, the first to Nth circuit blocks are arranged along the first direction, and the first to Nth circuit blocks include at least a scan driver block, a power supply circuit block, at least one data driver block, and at least one data driver block. Contains one memory block. In the present invention, the power supply circuit block is disposed between the scan driver block, the data driver block, and the memory block. Therefore, for example, the wiring using the empty space on the second direction side or the fourth direction side of the power supply circuit block becomes possible, and the wiring efficiency can be improved. In the present invention, the memory block and the data driver block are arranged adjacent to each other along the first direction. Therefore, the width of the integrated circuit device in the second direction can be reduced as compared with the method in which the memory block and the data driver block are arranged along the second direction, and a slim and elongated integrated circuit device can be provided. Further, even when the circuit configuration or the like of one of the circuit blocks arranged along the first direction changes, the influence can be prevented from reaching the other circuit block, and the design can be made more efficient.

  In the present invention, a first scan driver block is disposed as a first circuit block of the first to Nth circuit blocks, and an Nth circuit block of the first to Nth circuit blocks. As a second scan driver block, and at least one data driver block and at least one memory block between the first scan driver block and the power supply circuit block and the second scan driver block. May be arranged.

  In this way, the scanning lines can be driven by the first and second scanning driver blocks disposed at both ends of the integrated circuit device, so that the mounting efficiency can be improved. In addition, it is possible to perform wiring using free space on the power circuit block on the second direction side or the fourth direction side, for example, and wiring efficiency can be improved.

  In the present invention, the scan driver block is disposed as a first circuit block among the first to Nth circuit blocks, and at least on the first direction side of the scan driver block and the power supply circuit block, One data driver block and at least one memory block may be arranged.

  In this way, since the scanning line can be driven by the scanning driver block arranged at either the left end or the right end of the integrated circuit device, the mounting efficiency can be improved. In addition, it is possible to perform wiring using free space on the power circuit block on the second direction side or the fourth direction side, for example, and wiring efficiency can be improved.

  In the present invention, the first to N-th circuit blocks may include the first to I-th memory blocks (I is an integer of 2 or more) and the first to I-th memory blocks, respectively. You may make it include the 1st-1st I data driver block each arrange | positioned adjacently along a 1st direction.

  In this way, it is possible to arrange the first to I-th memory blocks having the optimal number of blocks according to the number of bits of image data to be stored and the corresponding first to I-th data driver blocks. It becomes possible. In addition, the width in the second direction and the length in the first direction of the integrated circuit device can be adjusted by the number of blocks, and the width in the second direction can be particularly reduced.

  In the present invention, when the direction opposite to the first direction is the third direction, the Jth memory block (1 ≦ J <I) of the first to Ith memory blocks is selected. The J-th data driver block among the first to I-th data driver blocks is adjacently disposed on the third direction side, and the first direction side of the J-th memory block is disposed on the first direction side. The J + 1th memory block among the Ith memory blocks is arranged adjacent to the first memory block, and the J + 1th memory driver block among the first to Ith data driver blocks is arranged on the first direction side of the J + 1th memory block. J + 1 data driver blocks may be arranged adjacent to each other.

  In this way, for example, the column address decoder can be shared between the Jth memory block and the J + 1th memory block, and the circuit can be further reduced in scale.

  In the present invention, when the direction opposite to the first direction is the third direction, the Jth memory block (1 ≦ J <I) of the first to Ith memory blocks is selected. The J-th data driver block among the first to I-th data driver blocks is adjacently disposed on the third direction side, and the first direction side of the J-th memory block is disposed on the first direction side. A J + 1th data driver block among the first to Ith data driver blocks is arranged, and the J + 1th data block among the first to Ith memory blocks is arranged on the first direction side of the J + 1th data driver block. These memory blocks may be arranged adjacent to each other.

  In this way, the pitch of the data signal output lines from the first to I data driver blocks can be made uniform.

  In the present invention, word lines connected to the memory cells of the memory block are wired along the second direction in the memory block, and image data stored in the memory block is supplied to the data driver block. The bit line output to the memory block may be routed along the first direction in the memory block.

  In this way, it is possible to reduce the length of the word line and optimize signal delay on the word line.

  In the present invention, the image data stored in the memory block may be read from the memory block to the data driver block a plurality of times in one horizontal scanning period.

  This reduces the number of memory cells in the second direction of the memory block, so that the width of the memory block in the second direction can be reduced, and the width of the integrated circuit device in the second direction is also reduced. It becomes possible.

  In the present invention, the data driver block may include a plurality of data drivers arranged in a stack along the first direction.

  In this way, data drivers of various configurations and types can be efficiently arranged.

  In the present invention, a first data driver of the plurality of data drivers latches image data read from the memory block for the first time in a first horizontal scanning period, and stores the latched image data. D / A conversion is performed, a data signal obtained by the D / A conversion is output to a data signal output line, and a second data driver of the plurality of data drivers is connected to the first horizontal from the memory block. The image data read for the second time in the scanning period is latched, D / A conversion of the latched image data is performed, and a data signal obtained by the D / A conversion is output to the data signal output line. Also good.

  In this way, each of the first and second data drivers need only latch the image data read for the first time and the second time and perform D / A conversion. Therefore, it is possible to prevent a situation in which the width of the integrated circuit device in the second direction becomes large due to the large scale of the first and second data drivers.

  According to the present invention, each of the first and second data drivers of the plurality of data drivers includes a first circuit region in which a circuit operating with a power supply of a first voltage level is disposed, and the first And a second circuit region in which a circuit operating with a power supply of a second voltage level higher than the first voltage level is arranged, and the first and second data drivers are One circuit area may be adjacent to the first memory block, and the first circuit area of the second data driver may be adjacent to the second memory block.

  In this way, the first and second memory blocks that operate with the power supply of the first voltage level and the first circuit areas of the first and second data drivers are arranged adjacent to each other. Therefore, layout efficiency can be improved.

  In the present invention, each of the data drivers included in the data driver block outputs a data signal corresponding to image data for one pixel, and includes Q driver cells arranged along the second direction. Also good.

  If a plurality of driver cells are arranged along the second direction in this way, image data signals from other circuit blocks arranged along the first direction can be efficiently input to these driver cells. it can.

  In the present invention, HPN is the number of pixels in the horizontal scanning direction of the display panel, DBN is the number of data driver blocks, and IN is the number of times image data is input to the driver cell in one horizontal scanning period. In this case, the number Q of the driver cells arranged along the second direction may be Q = HPN / (DBN × IN).

  In this way, the width of the first to Nth circuit blocks in the second direction can be set to an optimum width according to the number of data driver blocks and the number of times image data is input.

  In the present invention, the number of pixels in the horizontal scanning direction of the display panel is HPN, the number of bits of image data for one pixel is PDB, the number of memory blocks is MBN, and data is read from the memory block in one horizontal scanning period. When the number of read times of image data is RN, the sense amplifier block of the memory block includes P sense amplifiers arranged in the second direction, and the number P of sense amplifiers is P = (HPN × PDB) / (MBN × RN).

  In this way, it is possible to set the width in the second direction of the first to Nth circuit blocks to an optimum width according to the number of blocks MBN of the memory block and the number of image data readings RN. Become.

  In the present invention, in the sense amplifier block of the memory block, a plurality of sense amplifiers may be stacked in the first direction.

  In this way, since the output pitch of the image data supply line from the memory block in the second direction can be narrowed, the width of the memory block in the second direction can be reduced.

  In the present invention, the memory cell column in the upper row of the two memory cell columns arranged along the first direction on the first direction side of the first and second sense amplifiers arranged in a stack. These bit lines may be connected to the first sense amplifier, and the bit lines of the memory cell column in the lower row may be connected to the second sense amplifier.

  In this way, a cell having a narrow width in the second direction can be used as the memory cell, and the memory block can be highly integrated.

  In the present invention, a data driver pad for electrically connecting the output line of the data driver block and the data line is disposed on the second direction side of the data driver block, and the memory A scan driver pad disposed on the second direction side of the block and electrically connecting the output line of the scan driver block and the scan line is provided on the second direction side of the power supply circuit block. It may be arranged.

  In this way, it is possible to arrange the data driver pads by effectively using the empty area on the second direction side of the memory block, and to effectively use the empty area on the second direction side of the power circuit block, Scan driver pads can be arranged.

  In the present invention, a global line for power supply for supplying the power supply voltage generated by the power supply circuit block to the data driver block is disposed on the circuit block interposed between the power supply circuit block and the data driver block. Wiring may be performed along the first direction.

  In this way, since the power supply line can be wired by the global line, the internal circuit of the data driver block can be operated by the power supplied from the global line. In addition, an increase in power supply impedance can be minimized, and stable power supply can be achieved.

  In the present invention, a scan driver global line that is an output line of the scan driver block may be wired on the power supply circuit block from the scan driver block to the scan driver pad.

  In this way, the global area for the scan driver can be wired by effectively utilizing the area of the power supply circuit block, and the width of the integrated circuit device in the second direction can be reduced.

  In the present invention, in the power supply circuit block, a shield line may be wired under the scan driver global line.

  In this way, since noise from the scan driver global line can be removed by the shield line, it is possible to prevent malfunction of the circuit in the power circuit block below the global line.

  In the present invention, the data driver block includes a plurality of subpixel driver cells each outputting a data signal corresponding to image data for one subpixel, and an output signal extraction line of the subpixel driver cell is provided. A rearrangement wiring area for rearranging the arrangement order may be provided in the arrangement area of the subpixel driver cells.

  If the rearrangement wiring region is provided in the subpixel driver cell arrangement region in this way, switching of the wiring layer in the wiring region between the pad and the data driver block can be minimized, and the first wiring region can be changed. The width in the direction 2 can be reduced.

  In the present invention, the data driver block includes a plurality of subpixel driver cells each outputting a data signal corresponding to image data for one subpixel, and the image data from the memory block is transferred to the subpixel driver. An image data supply line for supplying to the cell may be wired along the first direction across the plurality of subpixel driver cells.

  In this way, the image data from the memory block can be efficiently supplied to a plurality of subpixel driver cells using the image data supply line.

  According to the present invention, the subpixel driver cell includes a D / A converter that performs D / A conversion of image data using a gradation voltage, and supplies the gradation voltage to the D / A converter. For this purpose, a gray voltage supply line may be wired along the second direction across the plurality of subpixel driver cells.

  According to this configuration, the gradation voltage supply line wired along the second direction is used for the D / A converters of the plurality of subpixel driver cells arranged along the second direction. The regulated voltage can be supplied efficiently and the layout efficiency can be improved. In addition, the gradation voltage supply line can be wired by effectively utilizing the empty wiring area of the extraction line.

  According to the present invention, a first interface region provided along the fourth side on the second direction side of the first to Nth circuit blocks and a direction opposite to the second direction are set to a fourth direction. And the second interface region provided along the second side on the fourth direction side of the first to Nth circuit blocks.

  The present invention also relates to an electronic apparatus including any one of the integrated circuit devices described above and a display panel driven by the integrated circuit device.

  Hereinafter, preferred embodiments of the present invention will be described in detail. The present embodiment described below does not unduly limit the contents of the present invention described in the claims, and all the configurations described in the present embodiment are indispensable as means for solving the present invention. Not necessarily.

1. Comparative Example FIG. 1A shows an integrated circuit device 500 as a comparative example of the present embodiment. The integrated circuit device 500 of FIG. 1A includes a memory block MB (display data RAM) and a data driver block DB. The memory block MB and the data driver block DB are arranged along the direction D2. Further, the memory block MB and the data driver block DB are ultra flat blocks whose length along the D1 direction is longer than the width in the D2 direction.

  Image data from the host side is written in the memory block MB. The data driver block DB converts the digital image data written in the memory block MB into an analog data voltage and drives the data lines of the display panel. Thus, in FIG. 1A, the signal flow of the image data is in the direction D2. For this reason, in the comparative example of FIG. 1A, the memory block MB and the data driver block DB are arranged along the direction D2 in accordance with the flow of this signal. By doing so, a short path is formed between the input and the output, the signal delay can be optimized, and efficient signal transmission becomes possible.

  However, the comparative example of FIG. 1A has the following problems.

  First, in an integrated circuit device such as a display driver, a reduction in chip size is required for cost reduction. However, when a fine process is employed and the integrated circuit device 500 is simply shrunk to reduce the chip size, not only the short side direction but also the long side direction is reduced. Therefore, as shown in FIG. 2A, there is a problem of difficulty in mounting. That is, the output pitch is desirably 22 μm or more, for example, but a simple shrink as shown in FIG. 2A has a pitch of 17 μm, for example, which makes mounting difficult due to the narrow pitch. Moreover, the frame of the glass of the display panel is widened, the number of pieces of glass is reduced, and the cost is increased.

  Secondly, in the display driver, the configuration of the memory and data driver varies depending on the type of display panel (amorphous TFT, low-temperature polysilicon TFT), the number of pixels (QCIF, QVGA, VGA), product specifications, and the like. Therefore, in the comparative example of FIG. 1A, in some products, as shown in FIG. 1B, even if the pad pitch, the memory cell pitch, and the data driver cell pitch match, the configuration of the memory and data driver changes. As shown in FIG. 1C, these pitches do not match. If the pitches do not match as shown in FIG. 1C, a useless wiring region for absorbing the pitch mismatch must be formed between the circuit blocks. In particular, in the comparative example of FIG. 1A in which the block is flat in the D1 direction, a useless wiring area for absorbing the pitch mismatch becomes large. As a result, the width W of the integrated circuit device 500 in the D2 direction is increased, the chip area is increased, and the cost is increased.

  On the other hand, in order to avoid such a situation, if the layout of the memory or data driver is changed so that the pad pitch and the cell pitch are aligned, the development period becomes longer, resulting in an increase in cost. That is, in the comparative example of FIG. 1A, the circuit configuration and layout of each circuit block are individually designed, and then the pitch and the like are adjusted, resulting in useless empty areas and inefficient design. Problems arise.

2. Configuration of Integrated Circuit Device FIG. 3 shows a configuration example of the integrated circuit device 10 of the present embodiment that can solve the above problems. In the present embodiment, the direction from the first side SD1 which is the short side of the integrated circuit device 10 to the third side SD3 facing the first direction D1 is defined as a first direction D1, and the opposite direction of D1 is defined as a third direction D3. Yes. The direction from the second side SD2 which is the long side of the integrated circuit device 10 to the fourth side SD4 facing the second side D2 is a second direction D2, and the opposite direction of D2 is a fourth direction D4. In FIG. 3, the left side of the integrated circuit device 10 is the first side SD1 and the right side is the third side SD3. However, the left side is the third side SD3 and the right side is the first side SD1. May be.

  As shown in FIG. 3, the integrated circuit device 10 of this embodiment includes first to Nth circuit blocks CB1 to CBN (N is an integer of 2 or more) arranged along the direction D1. That is, in the comparative example of FIG. 1A, the circuit blocks are arranged in the D2 direction, but in this embodiment, the circuit blocks CB1 to CBN are arranged in the D1 direction. Further, each circuit block is not a very flat block as in the comparative example of FIG. 1A, but is a relatively square block.

  The integrated circuit device 10 also includes an output-side I / F region 12 (first interface region in a broad sense) provided along the side SD4 on the D2 direction side of the first to Nth circuit blocks CB1 to CBN. Further, it includes an input-side I / F area 14 (second interface area in a broad sense) provided along the side SD2 on the D4 direction side of the first to Nth circuit blocks CB1 to CBN. More specifically, the output-side I / F region 12 (first I / O region) is arranged on the D2 direction side of the circuit blocks CB1 to CBN without using, for example, other circuit blocks. The input-side I / F area 14 (second I / O area) is arranged on the D4 direction side of the circuit blocks CB1 to CBN, for example, without passing through other circuit blocks. That is, at least in the portion where the data driver block exists, there is only one circuit block (data driver block) in the direction D2. When the integrated circuit device 10 is used as an IP (Intellectual Property) core and incorporated in another integrated circuit device, etc., it may be configured such that at least one of the I / F regions 12 and 14 is not provided.

  The output side (display panel side) I / F area 12 is an area serving as an interface with the display panel, and includes various elements such as a pad, an output transistor connected to the pad, and a protection element. Specifically, it includes an output transistor for outputting a data signal to the data line and a scanning signal to the scanning line. In the case where the display panel is a touch panel, an input transistor may be included.

  The input side (host side) I / F area 14 is an area serving as an interface with a host (MPU, image processing controller, baseband engine), and is a pad or an input (input / output) transistor connected to the pad. Various elements such as an output transistor and a protection element can be included. Specifically, an input transistor for inputting a signal (digital signal) from the host, an output transistor for outputting a signal to the host, and the like are included.

  Note that an output-side or input-side I / F area along the short sides SD1 and SD3 may be provided. Further, bumps or the like serving as external connection terminals may be provided in the I / F (interface) regions 12 and 14, or may be provided in other regions (first to Nth circuit blocks CB1 to CBN). In the case where it is provided in a region other than the I / F regions 12 and 14, it is realized by using a small bump technology (such as a bump technology using a resin as a core) other than the gold bump.

  The first to Nth circuit blocks CB1 to CBN can include at least two (or three) different circuit blocks (circuit blocks having different functions). Taking the case where the integrated circuit device 10 is a display driver as an example, the circuit blocks CB1 to CBN include at least two blocks of a data driver, a memory, a scan driver, a logic circuit, a gradation voltage generation circuit, and a power supply circuit. be able to. More specifically, the circuit blocks CB1 to CBN can include at least a data driver block and a logic circuit block, and can further include a grayscale voltage generation circuit block. In the case of a built-in memory type, a memory block can be further included.

  For example, FIG. 4 shows examples of various types of display drivers and circuit blocks incorporated therein. In a display driver for an amorphous TFT (Thin Film Transistor) panel with a built-in memory (RAM), circuit blocks CB1 to CBN include a memory, a data driver (source driver), a scanning driver (gate driver), a logic circuit (gate array circuit), It includes a gradation voltage generation circuit (γ correction circuit) and a power supply circuit block. On the other hand, in a display driver for a low-temperature polysilicon (LTPS) TFT panel with a built-in memory, the scanning driver can be formed on a glass substrate, so that the scanning driver block can be omitted. Also, the memory block can be omitted for an amorphous TFT panel without a memory, and the memory and scan driver blocks can be omitted for a low-temperature polysilicon TFT panel without a memory. Further, for a color super twisted nematic (CSTN) panel and a thin film diode (TFD) panel, the block of the gradation voltage generation circuit can be omitted.

  FIGS. 5A and 5B show examples of a planar layout of the integrated circuit device 10 of the display driver of this embodiment. 5A and 5B are examples for an amorphous TFT panel with a built-in memory. FIG. 5A targets, for example, a display driver for QCIF and 32 gradations, and FIG. The display driver for gradation is targeted.

  5A and 5B, the first to Nth circuit blocks CB1 to CBN are first to fourth memory blocks MB1 to MB4 (first to Ith memory blocks in a broad sense. I is 2). Including the above integer). The first to fourth data driver blocks DB1 to DB4 (first in a broad sense, the first to fourth memory blocks MB1 to MB4) are arranged adjacent to each other along the direction D1. To I-th data driver block). Specifically, the memory block MB1 and the data driver block DB1 are arranged adjacently along the D1 direction, and the memory block MB2 and the data driver block DB2 are arranged adjacently along the D1 direction. The image data (display data) used by the data driver block DB1 to drive the data lines is stored in the adjacent memory block MB1, and the image data used by the data driver block DB2 to drive the data lines is adjacent. Memory block MB2 stores it.

  In FIG. 5A, MB1 of the memory blocks MB1 to MB4 (Jth memory block in a broad sense, 1 ≦ J <I) is placed on the D3 direction side of the data driver blocks DB1 to DB4. In a broad sense, the Jth data driver block) is arranged adjacent to each other. Further, a memory block MB2 (J + 1th memory block in a broad sense) is arranged adjacent to the D1 direction side of the memory block MB1. A data driver block DB2 (J + 1th data driver block in a broad sense) is arranged adjacent to the D1 direction side of the memory block MB2. The arrangement of the memory blocks MB3 and MB4 and the data driver blocks DB3 and DB4 is the same. In this way, in FIG. 5A, MB1, DB1, and MB2, DB2 are arranged symmetrically with respect to the boundary lines of MB1 and MB2, and MB3, DB3, and MB4 are arranged symmetrically with respect to the boundary lines of MB3 and MB4. , DB4 are arranged. In FIG. 5A, DB2 and DB3 are arranged adjacent to each other, but other circuit blocks may be arranged between them without adjoining them.

  On the other hand, in FIG. 5B, DB1 (Jth data driver block) of the data driver blocks DB1 to DB4 is on the D3 direction side of MB1 (Jth memory block) of the memory blocks MB1 to MB4. Adjacent to each other. Further, DB2 (J + 1th data driver block) is arranged on the D1 direction side of MB1. MB2 (J + 1th memory block) is arranged on the D1 direction side of DB2. DB3, MB3, DB4, and MB4 are similarly arranged. In FIG. 5B, MB1 and DB2, MB2 and DB3, and MB3 and DB4 are arranged adjacent to each other, but other circuit blocks may be arranged between them without being adjacent to each other. Good.

  5A has an advantage that the column address decoder can be shared between the memory blocks MB1 and MB2 and between the MB3 and MB4 (between the Jth and J + 1th memory blocks). On the other hand, according to the layout arrangement of FIG. 5B, there is an advantage that the wiring pitch of the data signal output lines from the data driver blocks DB1 to DB4 to the output side I / F region 12 can be made uniform, and the wiring efficiency can be improved. is there.

  The layout arrangement of the integrated circuit device 10 of the present embodiment is not limited to FIGS. For example, the number of memory blocks or data driver blocks may be 2, 3 or 5 or more, or the memory block or data driver block may be configured not to be divided into blocks. Further, a modification can be made so that the memory block and the data driver block are not adjacent to each other. In addition, a configuration in which a memory block, a scan driver block, a power supply circuit block, a gradation voltage generation circuit block, or the like is not provided may be employed. Further, a circuit block having a very narrow width in the D2 direction (elongated circuit block of WB or less) may be provided between the circuit blocks CB1 to CBN and the output-side I / F region 12 or the input-side I / F region 14. The circuit blocks CB1 to CBN may include circuit blocks in which different circuit blocks are arranged in multiple stages in the D2 direction. For example, the scan driver circuit and the power supply circuit may be configured as one circuit block.

  FIG. 6A shows an example of a cross-sectional view along the direction D2 of the integrated circuit device 10 of the present embodiment. Here, W1, WB, and W2 are the widths in the D2 direction of the output side I / F region 12, the circuit blocks CB1 to CBN, and the input side I / F region 14, respectively. W is the width of the integrated circuit device 10 in the direction D2.

  In this embodiment, as shown in FIG. 6A, in the direction D2, other circuit blocks are arranged between the circuit blocks CB1 to CBN (data driver block DB) and the output side and input side I / F regions 12 and 14. Can be configured without intervening. Therefore, W1 + WB + W2 ≦ W <W1 + 2 × WB + W2 can be satisfied, and a narrow integrated circuit device can be realized. Specifically, the width W in the D2 direction can be set to W <2 mm, and more specifically, W <1.5 mm. In consideration of chip inspection and mounting, it is desirable that W> 0.9 mm. The length LD in the long side direction can be 15 mm <LD <27 mm. The chip shape ratio SP = LD / W can be set to SP> 10, and more specifically, SP> 12.

  The widths W1, WB, and W2 in FIG. 6A are respectively the transistor formation regions (bulk region and active region) of the output side I / F region 12, circuit blocks CB1 to CBN, and input side I / F region 14. Width. That is, in the I / F regions 12 and 14, an output transistor, an input transistor, an input / output transistor, a transistor of an electrostatic protection element, and the like are formed. In the circuit blocks CB1 to CBN, transistors constituting the circuit are formed. W1, WB, and W2 are determined based on a well region, a diffusion region, or the like where such a transistor is formed. For example, in order to realize a slimmer integrated circuit device, it is desirable to form bumps (active surface bumps) also on the transistors of the circuit blocks CB1 to CBN. Specifically, a resin core bump having a core formed of a resin and a metal layer formed on the surface of the resin is formed on the transistor (active region). The bumps (external connection terminals) are connected to pads arranged in the I / F regions 12 and 14 by metal wiring. In the present embodiment, W1, WB, and W2 are not the width of the bump formation region but the width of the transistor formation region formed under the bump.

  The widths of the circuit blocks CB1 to CBN in the D2 direction can be unified to the same width, for example. In this case, the widths of the circuit blocks may be substantially the same. For example, a difference of about several μm to 20 μm (several tens μm) is within an allowable range. When circuit blocks having different widths exist in the circuit blocks CB1 to CBN, the width WB can be the maximum width among the circuit blocks CB1 to CBN. The maximum width in this case can be, for example, the width of the data driver block in the D2 direction. Alternatively, in the case of an integrated circuit device with a built-in memory, the width in the direction D2 of the memory block can be set. An empty area with a width of about 20 to 30 μm can be provided between the circuit blocks CB1 to CBN and the I / F areas 12 and 14, for example.

  In the present embodiment, the output-side I / F region 12 can be provided with pads having one or more stages in the D2 direction. Therefore, considering the pad width (for example, 0.1 mm) and the pad pitch, the width W1 in the D2 direction of the output I / F region 12 can be 0.13 mm ≦ W1 ≦ 0.4 mm. In addition, since a pad having one step in the D2 direction can be arranged in the input side I / F region 14, the width W2 of the input side I / F region 14 is set to 0.1 mm ≦ W2 ≦ 0.2 mm. be able to. In order to realize an elongated integrated circuit device, a logic signal from the logic circuit block, a gradation voltage signal from the gradation voltage generation circuit block, and a power supply wiring are arranged on the circuit blocks CB1 to CBN. These wiring widths are, for example, about 0.8 to 0.9 mm in total. Therefore, in consideration of these, the width WB of the circuit blocks CB1 to CBN can be set to 0.65 mm ≦ WB ≦ 1.2 mm.

  Even if W1 = 0.4 mm and W2 = 0.2 mm, since 0.65 mm ≦ WB ≦ 1.2 mm, WB> W1 + W2 holds. When W1, WB, and W2 are the smallest values, W1 = 0.13 mm, WB = 0.65 mm, and W2 = 0.1 mm, and the width of the integrated circuit device is about W = 0.88 mm. Therefore, W = 0.88 mm <2 × WB = 1.3 mm holds. When W1, WB, and W2 are the largest values, W1 = 0.4 mm, WB = 1.2 mm, and W2 = 0.2 mm, and the width of the integrated circuit device is about W = 1.8 mm. Therefore, W = 1.8 mm <2 × WB = 2.4 mm holds. Therefore, a relational expression of W <2 × WB is established, and an elongated integrated circuit device can be realized.

  In the comparative example of FIG. 1A, as shown in FIG. 6B, two or more circuit blocks are arranged along the direction D2. In the D2 direction, a wiring region is formed between the circuit blocks or between the circuit block and the I / F region. Therefore, the width W of the integrated circuit device 500 in the D2 direction (short side direction) becomes large, and a slim elongated chip cannot be realized. Therefore, even if the chip is shrunk using a fine process, the length LD in the D1 direction (long side direction) is also shortened as shown in FIG. Incurs difficulty in implementation.

  On the other hand, in this embodiment, as shown in FIGS. 3, 5A and 5B, a plurality of circuit blocks CB1 to CBN are arranged along the direction D1. Further, as shown in FIG. 6A, a transistor (circuit element) can be disposed under the pad (bump) (active surface bump). In addition, signal lines between circuit blocks, between circuit blocks and I / F regions, and the like can be formed by global wiring formed in a layer above the local wiring (lower layer than the pad) that is a wiring in the circuit block. Therefore, as shown in FIG. 2B, the width W in the D2 direction can be narrowed while maintaining the length LD in the D1 direction of the integrated circuit device 10, and an ultra slim slim chip can be realized. As a result, the output pitch can be maintained at, for example, 22 μm or more, and mounting can be facilitated.

  In the present embodiment, since the plurality of circuit blocks CB1 to CBN are arranged along the direction D1, it is possible to easily cope with a change in product specifications and the like. In other words, since it is possible to design products with various specifications using a common platform, the design efficiency can be improved. For example, in FIGS. 5A and 5B, even when the number of pixels and the number of gradations of the display panel increase or decrease, the number of memory blocks and data driver blocks, the number of times image data is read out in one horizontal scanning period, etc. Just increase or decrease the number. FIGS. 5A and 5B are examples for an amorphous TFT panel with a built-in memory. When developing a product for a low-temperature polysilicon TFT panel with a built-in memory, scanning is performed from among the circuit blocks CB1 to CBN. Just remove the driver block. When developing a product without a memory, the memory block can be removed. Even if the circuit block is removed in accordance with the specifications as described above, in this embodiment, the influence of the circuit block on the other circuit blocks can be minimized, so that the design efficiency can be improved.

  In the present embodiment, the width (height) of each circuit block CB1 to CBN in the D2 direction can be unified with, for example, the width (height) of the data driver block and the memory block. When the number of transistors in each circuit block increases / decreases, the design can be made more efficient because it can be adjusted by increasing / decreasing the length of each circuit block in the D1 direction. For example, in FIGS. 5A and 5B, even when the configuration of the gradation voltage generation circuit block or the power supply circuit block is changed and the number of transistors is increased or decreased, the direction of the gradation voltage generation circuit block or the power supply circuit block in the direction D1 This can be dealt with by increasing or decreasing the length.

  As a second comparative example, there is also a method in which, for example, the data driver block is elongated in the D1 direction, and other circuit blocks such as a memory block are arranged along the D1 direction on the D4 direction side of the data driver block. Conceivable. However, in the second comparative example, a data driver block having a large width is interposed between another circuit block such as a memory block and the output-side I / F region. Therefore, in the D2 direction of the integrated circuit device. The width W becomes larger, and it becomes difficult to realize a slim elongated chip. In addition, a useless wiring area is generated between the data driver block and the memory block, and the width W is further increased. Further, when the configuration of the data driver block or the memory block is changed, the pitch mismatch problem described with reference to FIGS. 1B and 1C occurs, and the design efficiency cannot be improved.

  Further, as a third comparative example of the present embodiment, a method in which only circuit blocks having the same function (for example, data driver blocks) are divided into blocks and arranged in the D1 direction is also conceivable. However, in the third comparative example, since the integrated circuit device can have only the same function (for example, the function of the data driver), various product development cannot be realized. On the other hand, in the present embodiment, the circuit blocks CB1 to CBN include circuit blocks having at least two different functions. Accordingly, as shown in FIGS. 4, 5A and 5B, there is an advantage that various types of integrated circuit devices corresponding to various types of display panels can be provided.

3. Circuit Configuration FIG. 7 shows a circuit configuration example of the integrated circuit device 10. The circuit configuration of the integrated circuit device 10 is not limited to that shown in FIG. 7, and various modifications can be made. The memory 20 (display data RAM) stores image data. The memory cell array 22 includes a plurality of memory cells and stores image data (display data) for at least one frame (one screen). In this case, one pixel is composed of, for example, three subpixels (3 dots) of R, G, and B, and image data of, for example, 6 bits (k bits) is stored for each subpixel. The row address decoder 24 (MPU / LCD row address decoder) performs a decoding process on the row address and performs a word line selection process of the memory cell array 22. A column address decoder 26 (MPU column address decoder) performs a decoding process on the column address and performs a selection process of a bit line of the memory cell array 22. The write / read circuit 28 (MPU write / read circuit) performs image data write processing to the memory cell array 22 and image data read processing from the memory cell array 22. The access area of the memory cell array 22 is defined by, for example, a rectangle having a start address and an end address as a vertex. That is, an access area is defined by the column address and row address of the start address and the column address and row address of the end address, and memory access is performed.

  The logic circuit 40 (for example, an automatic placement and routing circuit) generates a control signal for controlling display timing, a control signal for controlling data processing timing, and the like. The logic circuit 40 can be formed by automatic placement and routing such as a gate array (G / A). The control circuit 42 generates various control signals and controls the entire apparatus. Specifically, gradation characteristic (γ characteristic) adjustment data (γ correction data) is output to the gradation voltage generation circuit 110 and voltage generation of the power supply circuit 90 is controlled. Further, it controls the write / read processing to the memory using the row address decoder 24, the column address decoder 26, and the write / read circuit 28. The display timing control circuit 44 generates various control signals for controlling the display timing, and controls reading of image data from the memory to the display panel side. The host (MPU) interface circuit 46 implements a host interface that generates an internal pulse for each access from the host and accesses the memory. The RGB interface circuit 48 realizes an RGB interface that writes moving image RGB data to a memory using a dot clock. Note that only one of the host interface circuit 46 and the RGB interface circuit 48 may be provided.

  In FIG. 7, the host interface circuit 46 and the RGB interface circuit 48 access the memory 20 in units of pixels. On the other hand, to the data driver 50, image data designated by a line address and read in units of lines is sent for each line period at an internal display timing independent of the host interface circuit 46 and the RGB interface circuit 48.

  The data driver 50 is a circuit for driving the data lines of the display panel, and FIG. 8A shows a configuration example thereof. The data latch circuit 52 latches digital image data from the memory 20. The D / A conversion circuit 54 (voltage selection circuit) performs D / A conversion of the digital image data latched by the data latch circuit 52 and generates an analog data voltage. Specifically, a plurality of (for example, 64 levels) gradation voltages (reference voltages) are received from the gradation voltage generation circuit 110, and a voltage corresponding to digital image data is selected from the plurality of gradation voltages. And output as a data voltage. The output circuit 56 (drive circuit, buffer circuit) buffers the data voltage from the D / A conversion circuit 54 and outputs it to the data line of the display panel to drive the data line. Note that a part of the output circuit 56 (for example, an output stage of an operational amplifier) may not be included in the data driver 50 but may be arranged in another region.

  The scan driver 70 is a circuit for driving the scan lines of the display panel, and FIG. 8B shows a configuration example thereof. The shift register 72 includes a plurality of flip-flops sequentially connected, and sequentially shifts the enable input / output signal EIO in synchronization with the shift clock signal SCK. The level shifter 76 converts the voltage level of the signal from the shift register 72 into a high voltage level for scanning line selection. The output circuit 78 buffers the scanning voltage converted and output by the level shifter 76 and outputs it to the scanning line of the display panel to selectively drive the scanning line. Note that the scan driver 70 may have the configuration shown in FIG. In FIG. 8C, the scan address generation circuit 73 generates and outputs a scan address, and the address decoder performs a scan address decoding process. A scanning voltage is output via the level shifter 76 and the output circuit 78 to the scanning line specified by this decoding process.

  The power supply circuit 90 is a circuit that generates various power supply voltages, and FIG. The booster circuit 92 is a circuit that boosts the input power supply voltage and the internal power supply voltage by a charge pump method using a boosting capacitor and a boosting transistor, and generates a boosted voltage, and includes primary to quaternary boosting circuits and the like. be able to. The booster circuit 92 can generate a high voltage used by the scan driver 70 and the gradation voltage generation circuit 110. The regulator circuit 94 adjusts the level of the boosted voltage generated by the booster circuit 92. The VCOM generation circuit 96 generates and outputs a VCOM voltage supplied to the counter electrode of the display panel. The control circuit 98 controls the power supply circuit 90 and includes various control registers.

  A gradation voltage generation circuit (γ correction circuit) 110 is a circuit that generates a gradation voltage, and FIG. 9B shows a configuration example thereof. The selection voltage generation circuit 112 (voltage division circuit) generates selection voltages VS0 to VS255 (R selection voltages in a broad sense) based on the high voltage power supply voltages VDDH and VSSH generated by the power supply circuit 90. Output. Specifically, the selection voltage generation circuit 112 includes a ladder resistor circuit having a plurality of resistor elements connected in series. Then, voltages obtained by dividing VDDH and VSSH by the ladder resistor circuit are output as selection voltages VS0 to VS255. Based on the gradation characteristic adjustment data set in the adjustment register 116 by the logic circuit 40, the gradation voltage selection circuit 114 is selected from among the selection voltages VS0 to VS255, for example, 64 in the case of 64 gradations ( In a broad sense, S voltages (R> S) are selected and output as gradation voltages V0 to V63. In this way, it is possible to generate a gradation voltage having an optimum gradation characteristic (γ correction characteristic) according to the display panel. In the case of polarity inversion driving, a positive ladder resistance circuit and a negative ladder resistance circuit may be provided in the selection voltage generation circuit 112. Further, the resistance value of each resistance element of the ladder resistor circuit may be changed based on the adjustment data set in the adjustment register 116. Further, the selection voltage generation circuit 112 and the gradation voltage selection circuit 114 may be provided with an impedance conversion circuit (an operational amplifier having a voltage follower connection).

  FIG. 10A shows a configuration example of each DAC (Digital Analog Converter) included in the D / A conversion circuit 54 of FIG. Each DAC in FIG. 10A can be provided, for example, for each subpixel (or for each pixel), and is configured by a ROM decoder or the like. Then, based on the 6-bit digital image data D0 to D5 from the memory 20 and the inverted data XD0 to XD5, any one of the gradation voltages V0 to V63 from the gradation voltage generation circuit 110 is selected. Data D0 to D5 are converted into analog voltages. The obtained analog voltage signal DAQ (DAQR, DAQG, DAQB) is output to the output circuit 56.

  In addition, when the data signals for R, G, and B are multiplexed and sent to the display driver by the display driver for the low-temperature polysilicon TFT (in the case of FIG. 10C), for R and G , B image data can also be D / A converted using one common DAC. In this case, each DAC in FIG. 10A is provided for each pixel.

  FIG. 10B shows a configuration example of each output unit SQ included in the output circuit 56 of FIG. Each output unit SQ in FIG. 10B can be provided for each pixel. Each output unit SQ includes impedance conversion circuits OPR, OPG, and OPB (voltage follower-connected operational amplifiers) for R (red), G (green), and B (blue), and signals DAQR and DAQQ from the DAC , DAQB impedance conversion is performed, and data signals DATAR, DATAG, and DATAB are output to the R, G, and B data signal output lines. For example, in the case of a low-temperature polysilicon TFT panel, switch elements (switch transistors) SWR, SWG, and SWB as shown in FIG. 10C are provided, and data signals for R, G, and B are multiplexed. The impedance conversion circuit OP may output the data signal DATA that has been processed. Further, the data signal may be multiplexed over a plurality of pixels. Further, the output unit SQ may be provided with only a switch element or the like without providing the impedance conversion circuit as shown in FIGS.

4). 4.1 Arrangement of Scan Driver Blocks, Power Supply Circuit Blocks, etc. 4.1 Adjacent to Circuit Blocks In this embodiment, as shown in FIG. 11, circuit blocks CB1 to CBN are connected to scan driver blocks SB for driving scan lines, and power supply voltages Includes at least one data driver block DB for driving data lines, and at least one memory block MB for storing image data. The scan driver block SB and the power supply circuit block PB are arranged adjacent to each other along the direction D1, for example. Further, the data driver block DB and the memory block MB are arranged adjacent to each other along the direction D1.

  That is, it is necessary to supply the scan driver block SB with a high voltage (for example, 20 V, −20 V) power generated by the power supply circuit block PB (boost circuit). Then, if the scanning driver block SB and the power supply circuit block PB are arranged along the direction D1, as shown in FIG. 11, this high voltage power supply wiring can be connected by a short path, and is generated from the high voltage power supply wiring. The adverse effects of noise can be minimized.

  Further, although the number of wirings connecting the scan driver block SB and other circuit blocks (for example, the power supply circuit block PB and the logic circuit block LB) is small, it is between the scan driver block SB and the output side I / F area 12. The number of wires is very large. That is, it is necessary to connect a large number of output signal lines from the scan driver block SB to the output transistors formed under the pads in the output side I / F region 12 or under the pads.

  As shown in FIG. 11, if the scanning driver block SB and the power supply circuit block PB are arranged along the direction D1, the empty space (space indicated by C1) existing in the output-side I / F area 12 on the D2 direction side of PB. A scanning signal output pad (scanning driver pad) can be arranged. A large number of output signal lines from the scan driver block SB can be connected to the output transistor formed at or below the pad. Accordingly, the wiring efficiency in the output-side I / F region 12 can be improved, the width W of the integrated circuit device 10 in the D2 direction can be reduced, and a slim and slender integrated circuit device 10 can be realized. It should be noted that a modification in which another circuit block is inserted between the scan driver block SB and the power supply circuit block PB is also possible. In this case, the power supply circuit block PB may be disposed at least between the scan driver block SB, the data driver block DB, and the memory block MB.

  In FIG. 11, the reason why the data driver block DB and the memory block MB are arranged adjacent to each other along the direction D1 is as follows.

  For example, in the comparative example of FIG. 1A, as shown in FIG. 12A, the memory block MB and the data driver block DB are arranged along the D2 direction, which is the short side direction, according to the signal flow. . For this reason, the width of the integrated circuit device in the D2 direction is increased, and it is difficult to realize a slim elongated chip. In addition, if the number of pixels of the display panel, display driver specifications, memory cell configuration, etc. change, and the width in the D2 direction and the length in the D1 direction of the memory block MB and data driver block DB change, the effect will be different. The design block becomes inefficient.

  On the other hand, in FIG. 11, since the data driver block DB and the memory block MB are arranged along the D1 direction, the width W of the integrated circuit device in the D2 direction can be reduced, as shown in FIG. Ultra slim slim chip can be realized. In addition, when the number of pixels of the display panel changes, it is possible to cope with this by dividing the memory block, so that the design can be made more efficient.

  In FIG. 12A, since the word line WL is arranged along the direction D1 which is the long side direction, the signal delay in the word line WL is increased, and the image data reading speed is decreased. In particular, since the word line WL connected to the memory cell is formed of a polysilicon layer, this signal delay problem is serious. In this case, in order to reduce the signal delay, there is a method of providing buffer circuits 520 and 522 as shown in FIG. However, when this method is adopted, the circuit scale increases correspondingly, resulting in an increase in cost.

  In contrast, in the present embodiment, as shown in FIG. 11, in the memory block MB, the word lines WL are wired along the D2 direction which is the short side direction, and the bit lines BL are arranged in the D1 direction which is the long side direction. Arranged along. In this embodiment, the width W of the integrated circuit device in the direction D2 is short. Therefore, the length of the word line WL in the memory block MB can be shortened, and the signal delay in WL can be remarkably reduced as compared with the comparative example of FIG. Further, since it is not necessary to provide the buffer circuits 520 and 522 as shown in FIG. 12B, the circuit area can be reduced. In the comparative example of FIG. 12A, even when a part of the access area of the memory is accessed from the host, the word line WL that is long in the D1 direction and has a large parasitic capacitance is selected. Become. On the other hand, if the technique of dividing the memory in the direction D1 as in the present embodiment is adopted, the memory block (Jth memory block) corresponding to the access area at the time of host access (access from the host side) ) Is selected, so that low power consumption can be realized.

  Note that WL in FIG. 11 is a word line connected to the memory cells of the memory block MB. That is, it is a local word line connected to the gate of the transfer transistor of the memory cell. On the other hand, BL in FIG. 11 is a bit line through which image data (stored data signal) stored in the memory block MB (memory cell array) is output to the data driver block DB. That is, the image data signal stored in the memory block MB is output from the memory block MB to the data driver block DB in the direction along the bit line BL.

  A method of arranging the memory block MB and the data driver block DB along the direction D2 as in the comparative example of FIG. 12A is reasonable in consideration of the direction of signal flow.

  In this regard, in this embodiment, as shown in FIG. 11, the output line DQL of the data signal from the data driver block DB is wired along the direction D2 in the DB. On the other hand, the data signal output line DQL is wired along the direction D1 (D3) in the output-side I / F region 12 (first interface region). Specifically, in the output-side I / F region 12, the data signal output line DQL is arranged along the D1 direction by using a global wiring that is lower than the pad and higher than the local wiring (transistor wiring) in the area. Wiring. In this way, even if the data driver block DB and the memory block MB are arranged in the direction D1, the data signal from the DB can be properly output to the display panel via the pad. If the data signal output line DQL is wired as shown in FIG. 11, the data signal output line DQL can be connected to a pad or the like by using the output side I / F region 12, and D2 of the integrated circuit device. An increase in the width W in the direction can be prevented.

4.2 Arrangement Example of Data Driver Block and Memory Block In FIGS. 13A and 13B, circuit blocks CB1 to CBN are data driver blocks DB1 to DB4 (at least one data driver block in a broad sense) and memory blocks MB1 to MB1. MB4 (at least one memory block in a broad sense) is included.

  In FIG. 13A, the first scan driver block SB1 is arranged as the first circuit block CB1 (circuit block on the side SD1 side) among the circuit blocks CB1 to CBN. A second scan driver block SB2 is arranged as the Nth circuit block CBN (circuit block on the side SD3 side) among the CB1 to CBN. The scan driver block SB1 and the power supply circuit block PB are arranged along the direction D1. Data driver blocks DB1 to DB4 and memory blocks MB1 to MB4 are arranged between the scan driver block SB1 and the power supply circuit block PB and the scan driver block SB2.

  As shown in FIG. 13A, if the scan driver blocks SB1 and SB2 are arranged as the circuit blocks CB1 and CBN located at both ends of the integrated circuit device 10, the first scan signal group from SB1 is displayed on the display panel, for example. It is possible to input from the left side and input the second scanning signal group from SB2 from, for example, the right side of the display panel. By doing so, it is possible to realize efficient mounting, comb drive of the display panel, and the like.

  When the scanning driver blocks SB1 and SB2 are arranged at both ends of the integrated circuit device 10 as shown in FIG. 13A, the scanning signal output pads may be arranged at both ends of the output I / F region 12. It is desirable considering the wiring efficiency. On the other hand, in FIG. 13A, the data driver blocks DB 1 to DB 4 are arranged near the center of the integrated circuit device 10. Therefore, it is desirable to arrange the output pad for the data signal near the center of the output-side I / F region 12 in consideration of the wiring efficiency.

  As shown in FIG. 13A, if the power supply circuit block PB having a relatively large circuit area is arranged between the scan driver block SB1 and the data driver blocks DB1 to DB4 and the memory blocks MB1 to MB4, By utilizing the empty space (space indicated by C2) on the D2 direction side of the circuit block PB, the output pad for the scanning signal and the output transistor formed under the pad can be arranged. As shown in FIG. 13A, if data driver blocks DB1 to DB4 and memory blocks MB1 to MB4 are arranged between the scan driver block SB1 and the power supply circuit PB and the scan driver block SB2, DB1 to DB4. In addition, by using the space (shown by C3 and C4) on the D2 direction side of MB1 to MB4, an output pad for data signals (data driver pad) and an output transistor formed under the pad can be arranged. Become. Accordingly, the wiring efficiency in the output-side I / F region 12 can be improved, the width W of the integrated circuit device 10 in the D2 direction can be reduced, and a slim and slender integrated circuit device 10 can be realized.

  In FIG. 13A, the high voltage power supply (20V, −20V) generated by the power supply circuit block PB is scanned using wiring formed along the D1 direction on the output I / F region 12. You may supply to driver block SB2. By so doing, it is possible to minimize the adverse effects of the wiring of the high voltage power supply on other circuit blocks.

  In FIG. 13B, the scan driver block SB is arranged as the first circuit block CB1 among the circuit blocks CB1 to CBN. Data driver blocks DB1 to DB4 and memory blocks MB1 to MB4 are arranged on the D1 direction side of the scan driver block SB and the power supply circuit block PB. Note that the D1 direction of the present embodiment is not limited to the right direction, and may be the left direction. The first circuit block CB1 (scan driver block SB) is not limited to the leftmost circuit block of the integrated circuit device 10, and may be the rightmost circuit block.

  If a power supply circuit block PB having a relatively large circuit area is arranged as shown in FIG. 13B, an empty space on the D2 direction side of PB (space shown by C5) is used to output a scanning signal output pad and its An output transistor formed under the pad can be arranged. Further, as shown in FIG. 13B, if the data driver blocks DB1 to DB4 and the memory blocks MB1 to MB4 are arranged on the D1 direction side of the scan driver block SB1 and the power supply circuit PB, DB1 to DB4 and MB1 to MB4 Using the space on the D2 direction side (spaces indicated by C6 and C7), an output pad for data signals and an output transistor formed under the pad can be arranged. Accordingly, the wiring efficiency in the output-side I / F region 12 can be improved, the width W of the integrated circuit device 10 in the D2 direction can be reduced, and a slim and slender integrated circuit device 10 can be realized.

5. Details of Memory Block and Data Driver Block 5.1 Block Division As shown in FIG. 14A, the display panel has a number of pixels in the vertical scanning direction (data line direction) of VPN = 320, and the horizontal scanning direction (scanning). Assume that the QVGA panel has HPN = 240 pixels in the line direction. Further, it is assumed that the bit number PDB of image (display) data for one pixel is 6 bits for each of R, G, and B, and PDB = 18 bits. In this case, the number of bits of image data necessary for displaying one frame of the display panel is VPN × HPN × PDB = 320 × 240 × 18 bits. Therefore, the memory of the integrated circuit device stores image data for at least 320 × 240 × 18 bits. Further, the data driver displays HPN = 240 data signals (data signals corresponding to 240 × 18 bits of image data) every horizontal scanning period (every period during which one scanning line is scanned). Output to the panel.

  In FIG. 14B, the data driver is divided into DBN = 4 data driver blocks DB1 to DB4. The memory is also divided into MBN = DBN = 4 memory blocks MB1 to MB4. Accordingly, each data driver block DB1 to DB4 outputs HPN / DBN = 240/4 = 60 data signals to the display panel every horizontal scanning period. Each of the memory blocks MB1 to MB4 stores (VPN × HPN × PDB) / MBN = (320 × 240 × 18) / 4 bits of image data.

  As shown in FIG. 14B, in the present embodiment, the memory block MB1 and MB2 share the column address decoder CD12. The memory blocks MB3 and MB4 share the column address decoder CD34. For example, in the comparative example of FIG. 13A, since the column address decoder is arranged on the D4 direction side of the memory cell array, the column address decoder cannot be shared as shown in FIG. On the other hand, in this embodiment, since the column address decoders CD12 and CD34 can be shared, the circuit area can be reduced and the cost can be reduced. If the data driver blocks DB1 to DB4 and the memory blocks MB1 to MB4 are arranged as shown in FIG. 5B, such column address decoders cannot be shared. Instead, in FIG. 5B, there is an advantage that the pitch of the data signal lines from the data driver block can be made uniform and wiring can be easily routed.

5.2 Reading Multiple Times in One Horizontal Scan Period In FIG. 14B, each data driver block DB1 to DB4 outputs 60 data signals in one horizontal scan period. Therefore, it is necessary to read image data corresponding to 240 data signals for each horizontal scanning period from the memory blocks MB1 to MB4 corresponding to DB1 to DB4.

  However, if the number of bits of image data to be read for each horizontal scanning period increases, it is necessary to increase the number of memory cells (sense amplifiers) arranged in the D2 direction. As a result, the width W in the direction D2 of the integrated circuit device is increased, and the slimming of the chip is prevented. In addition, the word line WL becomes long, which causes a problem of WL signal delay.

  Therefore, in the present embodiment, a method of reading image data stored in each of the memory blocks MB1 to MB4 from the memory blocks MB1 to MB4 a plurality of times (RN times) for each data driver block DB1 to DB4 in one horizontal scanning period. Is adopted.

  For example, in FIG. 15, as indicated by A1 and A2, the memory access signal MACS (word selection signal) becomes active (high level) only RN = 2 times in one horizontal scanning period. Thus, image data is read from each memory block to each data driver block RN = 2 times in one horizontal scanning period. Then, the data latch circuits included in the first and second data drivers DRa and DRb of FIG. 16 provided in the data driver block read out the images based on the latch signals LATa and LATb indicated by A3 and A4. Latch data. A D / A conversion circuit included in the first and second data drivers DRa and DRb performs D / A conversion of the latched image data, and an output circuit included in DRa and DRb is obtained by D / A conversion. The data signals DATAa and DATAb are output to the data signal output lines as indicated by A5 and A6. Thereafter, as shown at A7, the scanning signal SCSEL inputted to the gate of the TFT of each pixel of the display panel becomes active, and the data signal is inputted and held in each pixel of the display panel.

  In FIG. 15, the image data is read twice in the first horizontal scanning period, and the data signals DATAa and DATAb are output to the data signal output line in the same first horizontal scanning period. However, the image data is read and latched twice in the first horizontal scanning period, and the data signals DATAa and DATAb corresponding to the latched image data are supplied to the data signal output lines in the next second horizontal scanning period. It may be output. Further, FIG. 15 shows a case where the number of times of reading RN = 2, but RN ≧ 3 may be possible.

  According to the method of FIG. 15, as shown in FIG. 16, image data corresponding to 30 data signals is read from each memory block, and each data driver DRa, DRb outputs 30 data signals. To do. As a result, 60 data signals are output from each data driver block. As described above, in FIG. 15, it is only necessary to read image data corresponding to 30 data signals from each memory block in one reading. Therefore, the number of memory cells and sense amplifiers in the direction D2 in FIG. 16 can be reduced as compared with the method of reading only once in one horizontal scanning period. As a result, the width of the integrated circuit device in the D2 direction can be reduced, and an ultra slim slim chip as shown in FIG. 2B can be realized. In particular, the length of one horizontal scanning period is about 52 μsec in the case of QVGA. On the other hand, the memory read time is, for example, about 40 nsec, which is sufficiently shorter than 52 μsec. Therefore, even if the number of readings in one horizontal scanning period is increased from one to a plurality of times, the influence on the display characteristics is not so great.

  FIG. 14A shows a QVGA (320 × 240) display panel. If the number of readings in one horizontal scanning period is set to RN = 4, for example, it corresponds to a VGA (640 × 480) display panel. It is also possible to increase the degree of design freedom.

  The plurality of readings in one horizontal scanning period may be realized by a first method in which a row address decoder (word line selection circuit) selects a plurality of different word lines in each memory block in one horizontal scanning period. Alternatively, the same word line in each memory block may be realized by a second method in which a row address decoder (word line selection circuit) selects a plurality of times in one horizontal scanning period. Alternatively, it may be realized by a combination of both the first and second methods.

5.3 Arrangement of Data Driver and Driver Cell FIG. 16 shows an arrangement example of the data driver and the driver cell included in the data driver. As shown in FIG. 16, the data driver block includes a plurality of data drivers DRa and DRb (first to mth data drivers) arranged in a stack along the direction D1. Each data driver DRa, DRb includes a plurality of 30 (Q in a broad sense) driver cells DRC1 to DRC30.

  When the first data driver DRa selects the word line WL1a of the memory block and the first image data is read from the memory block as shown by A1 in FIG. 15, the first data driver DRa reads based on the latch signal LATa shown by A3. The output image data is latched. Then, D / A conversion of the latched image data is performed, and a data signal DATAa corresponding to the first read image data is output to the data signal output line as indicated by A5.

  On the other hand, when the word line WL1b of the memory block is selected and the second image data is read from the memory block as shown in A2 of FIG. 15, the second data driver DRb is based on the latch signal LATb shown in A4. The read image data is latched. Then, the latched image data is D / A converted, and a data signal DATAb corresponding to the second read image data is output to the data signal output line as indicated by A6.

  In this way, each data driver DRa, DRb outputs 30 data signals corresponding to 30 pixels, so that 60 data signals corresponding to 60 pixels in total are output. It becomes like this.

  If a plurality of data drivers DRa and DRb are arranged (stacked) in the D1 direction as shown in FIG. 16, the width of the integrated circuit device in the D2 direction due to the size of the data driver. The situation where W becomes large can be prevented. The data driver has various configurations depending on the type of the display panel. Also in this case, according to the method of arranging a plurality of data drivers along the direction D1, data drivers having various configurations can be efficiently laid out. FIG. 16 shows the case where the number of data drivers arranged in the direction D1 is two, but the number of arranged data drivers may be three or more.

  In FIG. 16, each data driver DRa, DRb includes 30 (Q) driver cells DRC1 to DRC30 arranged side by side along the direction D2. Here, each of driver cells DRC1 to DRC30 receives image data for one pixel. Then, D / A conversion of the image data for one pixel is performed, and a data signal corresponding to the image data for one pixel is output. Each of the driver cells DRC1 to DRC30 can include a data latch circuit, a DAC of FIG. 10A (DAC for one pixel), and an output unit SQ of FIGS. 10B and 10C.

  In FIG. 16, the number of pixels in the horizontal scanning direction of the display panel (in the case where the data lines of the display panel are driven by sharing with a plurality of integrated circuit devices) It is assumed that HPN is used, the number of blocks of the data driver block (number of block divisions) is DBN, and the number of input image data input to the driver cell in one horizontal scanning period is IN. Note that IN is equal to the number of read times RN of the image data in one horizontal scanning period described with reference to FIG. In this case, the number Q of driver cells DRC1 to DRC30 arranged along the direction D2 can be expressed as Q = HPN / (DBN × IN). In the case of FIG. 16, since HPN = 240, DBN = 4, and IN = 2, Q = 240 / (4 × 2) = 30.

  When the width (pitch) in the D2 direction of the driver cells DRC1 to DR30 is WD and the width in the D2 direction of the peripheral circuit portion (buffer circuit, wiring region, etc.) included in the data driver block is WPCB, The width WB (maximum width) in the D2 direction of the N-th circuit blocks CB1 to CBN can be expressed as Q × WD ≦ WB <(Q + 1) × WD + WPCB. Further, when the width in the D2 direction of the peripheral circuit portion (row address decoder RD, wiring area, etc.) included in the memory block is WPC, it can be expressed as Q × WD ≦ WB <(Q + 1) × WD + WPC.

  Further, the number of pixels in the horizontal scanning direction of the display panel is HPN, the number of bits of image data for one pixel is PDB, the number of memory blocks is MBN (= DBN), and data is read from the memory block in one horizontal scanning period. Assume that the number of times of reading image data is RN. In this case, the number P of sense amplifiers (sense amplifiers that output 1-bit image data) arranged in the direction D2 in the sense amplifier block SAB is expressed as P = (HPN × PDB) / (MBN × RN). be able to. In the case of FIG. 16, since HPN = 240, PDB = 18, MBN = 4, and RN = 2, P = (240 × 18) / (4 × 2) = 540. Note that the number P is the number of effective sense amplifiers corresponding to the number of effective memory cells, and does not include the number of ineffective sense amplifiers such as sense amplifiers for dummy memory cells.

  When the width (pitch) in the D2 direction of each sense amplifier included in the sense amplifier block SAB is WS, the width WSAB in the D2 direction of the sense amplifier block SAB (memory block) is WSAB = P × WS. Can be represented. The width WB (maximum width) in the D2 direction of the circuit blocks CB1 to CBN is P × WS ≦ WB <(P + PDB) when the width in the D2 direction of the peripheral circuit portion included in the memory block is WPC. It can also be expressed as × WS + WPC.

5.4 Memory Cell FIG. 17A shows a configuration example of a memory cell (SRAM) included in the memory block. This memory cell includes transfer transistors TRA1 and TRA2, load transistors TRA3 and TRA4, and drive transistors TRA5 and TRA6. When the word line WL becomes active, the transfer transistors TRA1 and TRA2 are turned on, and image data can be written to the nodes NA1 and NA2 and image data can be read from the nodes NA1 and NA2. The written image data is held in the nodes NA1 and NA2 by a flip-flop circuit composed of transistors TRA3 to TRA6. The memory cell of this embodiment is not limited to the configuration shown in FIG. 17A, and modifications such as using a resistance element as the load transistors TRA3 and TRA4 and adding other transistors are possible.

  FIGS. 17B and 17C show layout examples of memory cells. FIG. 17B shows a layout example of a horizontal cell, and FIG. 17C shows a layout example of a vertical cell. Here, as shown in FIG. 17B, the horizontal cell is a cell in which the word line WL is longer than the bit lines BL and XBL in each memory cell. On the other hand, as shown in FIG. 17C, the vertical cell is a cell in which the bit lines BL and XBL are longer than the word line WL in each memory cell. Note that WL in FIG. 17C is a local word line formed of a polysilicon layer and connected to the transfer transistors TRA1 and TRA2, but a metal layer word line for preventing signal delay of WL and stabilizing the potential. May be further provided.

  FIG. 18 shows an arrangement example of memory blocks and driver cells when the horizontal cell shown in FIG. 17B is used as a memory cell. FIG. 18 shows in detail a portion corresponding to one pixel in the driver cell and the memory block.

  As shown in FIG. 18, a driver cell DRC that receives image data for one pixel includes data latch circuits DLATR, DLATG, and DLATB for R (red), G (green), and B (blue). Each data latch circuit DLATR, DLATG, DLATB latches image data when a latch signal LAT (LATa, LATb) becomes active. The driver cell DRC includes the R, G, and B DACR, DACG, and DACB described with reference to FIG. The output unit SQ described with reference to FIGS. 10B and 10C is also included.

  The portion corresponding to one pixel in the sense amplifier block SAB includes R sense amplifiers SAR0 to SAR5, G sense amplifiers SAG0 to SAG5, and B sense amplifiers SAB0 to SAB5. The bit lines BL and XBL of the memory cells MC arranged along the D1 direction on the D1 direction side of the sense amplifier SAR0 are connected to SAR0. In addition, the bit lines BL and XBL of the memory cells MC arranged along the D1 direction on the D1 direction side of the sense amplifier SAR1 are connected to the SAR1. The same applies to the relationship between other sense amplifiers and memory cells.

  When the word line WL1a is selected, image data is read from the memory cell MC to which the gate of the transfer transistor is connected to WL1a to the bit lines BL and XBL, and sense amplifiers SAR0 to SAR5, SAG0 to SAG5, and SAB0. ... SAB5 performs signal amplification operation. DLATR latches 6-bit R image data D0R to D5R from SAR0 to SAR5, DACR performs D / A conversion of the latched image data, and output unit SQ outputs a data signal DATAR. . DLATG latches 6-bit G image data D0G to D5G from SAG0 to SAG5, DACG performs D / A conversion of the latched image data, and output unit SQ outputs a data signal DATAT. . DLATB latches 6-bit B image data D0B to D5B from SAB0 to SAB5, DACB performs D / A conversion of the latched image data, and output unit SQ outputs data signal DATAB. .

  In the case of the configuration shown in FIG. 18, the image data can be read a plurality of times in one horizontal scanning period shown in FIG. 15 as follows. That is, in the first horizontal scanning period (first scanning line selection period), first, the word line WL1a is selected to read the image data for the first time, and the first data is displayed as indicated by A5 in FIG. The signal DATAa is output. Next, in the same first horizontal scanning period, the word line WL1b is selected, the image data is read for the second time, and the second data signal DATAb is output as indicated by A6 in FIG. In the next second horizontal scanning period (second scanning line selection period), the word line WL2a is first selected to read the image data for the first time, and the first data signal DATAa is output. Next, in the same second horizontal scanning period, the word line WL2b is selected, the image data is read for the second time, and the second data signal DATAb is output. When horizontal cells are used in this way, a plurality of different word lines (WL1a, WL1b) in the memory block are selected in one horizontal scanning period, so that multiple readings in one horizontal scanning period can be realized.

  FIG. 19 shows an arrangement example of memory blocks and driver cells when the vertical cell shown in FIG. 17C is used as the memory cell. In the vertical cell, the width in the D2 direction can be made shorter than that in the horizontal cell. Therefore, the number of memory cells in the D2 direction can be doubled as compared with the horizontal cells. In the vertical cell, the column of memory cells connected to each sense amplifier is switched using column selection signals COLa and COLb.

  For example, in FIG. 19, when the column selection signal COLa becomes active, the memory cell MC on the column Ca side among the memory cells MC on the D1 direction side of the sense amplifiers SAR0 to SAR5 is selected and connected to the sense amplifiers SAR0 to SAR5. Is done. The signals of the image data stored in these selected memory cells MC are amplified and output as D0R to D5R. On the other hand, when the column selection signal COLb becomes active, the memory cell MC on the column Cb side among the memory cells MC on the D1 direction side of the sense amplifiers SAR0 to SAR5 is selected and connected to the sense amplifiers SAR0 to SAR5. The signals of the image data stored in these selected memory cells MC are amplified and output as D0R to D5R. The same applies to reading of image data of memory cells connected to other sense amplifiers.

  In the case of the configuration shown in FIG. 19, the image data can be read a plurality of times in one horizontal scanning period shown in FIG. 15 as follows. That is, in the first horizontal scanning period, first, the word line WL1 is selected, the column selection signal COLa is activated, the first reading of the image data is performed, and the first data signal is displayed as indicated by A5 in FIG. DATAa is output. Next, the same word line WL1 is selected in the same first horizontal scanning period, the column selection signal COLb is activated, and the second reading of the image data is performed. As shown in A6 in FIG. 15, the second data is read. The signal DATAb is output. In the next second horizontal scanning period, the word line WL2 is selected, the column selection signal COLa is activated, the image data is read for the first time, and the first data signal DATAa is output. Next, the same word line WL2 is selected in the same second horizontal scanning period, the column selection signal COLb is activated, the image data is read a second time, and the second data signal DATAb is output. As described above, in the case of a vertical cell, the same word line in the memory block is selected a plurality of times in one horizontal scanning period, so that reading can be performed a plurality of times in one horizontal scanning period.

  The configuration and arrangement of the driver cell DRC are not limited to those shown in FIGS. 18 and 19, and various modifications can be made. For example, when a data driver for R, G, and B is multiplexed and sent to a display panel as shown in FIG. 10C by a display driver for a low-temperature polysilicon TFT, one common DAC is used. It is possible to perform D / A conversion of image data for R, G, and B (image data for one pixel). Therefore, in this case, the driver cell DRC may include one shared DAC having the configuration shown in FIG. In FIG. 18 and FIG. 19, R circuits (DLATR, DACR), G circuits (DLATG, DACG), and B circuits (DLATB, DACB) are arranged along the direction D2 (D4). Yes. However, the R, G, and B circuits may be arranged along the direction D1 (D3).

6). Electronic Device FIGS. 20A and 20B show examples of electronic devices (electro-optical devices) including the integrated circuit device 10 of the present embodiment. Note that the electronic apparatus may include components (for example, a camera, an operation unit, a power supply, or the like) other than those illustrated in FIGS. The electronic device according to the present embodiment is not limited to a mobile phone, and may be a digital camera, a PDA, an electronic notebook, an electronic dictionary, a projector, a rear projection television, a portable information terminal, or the like.

  20A and 20B, the host device 410 is, for example, an MPU (Micro Processor Unit), a baseband engine (baseband processor), or the like. The host device 410 controls the integrated circuit device 10 that is a display driver. Alternatively, processing as an application engine or baseband engine, or processing as a graphic engine such as compression, decompression, or sizing can be performed. In addition, an image processing controller (display controller) 420 in FIG. 20B performs processing as a graphic engine such as compression, decompression, and sizing on behalf of the host device 410.

  The display panel 400 includes a plurality of data lines (source lines), a plurality of scanning lines (gate lines), and a plurality of pixels specified by the data lines and the scanning lines. A display operation is realized by changing the optical characteristics of the electro-optical element (in a narrow sense, a liquid crystal element) in each pixel region. The display panel 400 can be constituted by an active matrix panel using switching elements such as TFTs and TFDs. Note that the display panel 400 may be a panel other than the active matrix method, or may be a panel other than the liquid crystal panel.

  In the case of FIG. 20A, the integrated circuit device 10 having a built-in memory can be used. That is, in this case, the integrated circuit device 10 once writes the image data from the host device 410 into the built-in memory, reads the written image data from the built-in memory, and drives the display panel. On the other hand, in the case of FIG. 20B, an integrated circuit device 10 without a memory can be used. That is, in this case, the image data from the host device 410 is written into the built-in memory of the image processing controller 420. The integrated circuit device 10 drives the display panel 400 under the control of the image processing controller 420.

7). Modified Example 7.1 Global Wiring Method In order to reduce the width of the integrated circuit device in the D2 direction, it is necessary to efficiently wire signal lines and power supply lines between circuit blocks arranged along the D1 direction. . Therefore, in the present embodiment, signal lines and power supply lines between circuit blocks are wired by a global wiring method. Specifically, in this global wiring method, a lower layer than the I-th (I is an integer of 3 or more) layer between adjacent circuit blocks among the first to N-th circuit blocks CB1 to CBN in FIG. Local lines formed of wiring layers (for example, first to fourth aluminum wiring layers ALA, ALB, ALC, ALD) are wired as signal lines or power supply lines. On the other hand, between non-adjacent circuit blocks among the first to Nth circuit blocks CB1 to CBN, a global line formed of a wiring layer (for example, the fifth aluminum wiring layer ALE) of the Ith layer or higher is connected to the signal line. As a line or a power supply line, a circuit block interposed between non-adjacent circuit blocks is wired along the direction D1.

  FIG. 21 shows an example of global line wiring. In FIG. 21, driver global lines GLD for supplying driver control signals from the logic circuit block LB to the data driver blocks DB1 to DB3 are wired on the buffer circuits BF1 to BF3 and the row address decoders RD1 to RD3. That is, the driver global line GLD formed by the fifth aluminum wiring layer ALE, which is the top metal, is substantially straight along the D1 direction from the logic circuit block LB to the buffer circuits BF1 to BF3 and the row address decoders RD1 to RD3. Wired to The driver control signals supplied by these driver global lines GLD are buffered by the buffer circuits BF1 to BF3 and input to the data drivers DR1 to DR3 arranged on the D2 direction side of the buffer circuits BF1 to BF3. The

  In FIG. 21, a memory global line GLM for supplying at least a write data signal (or an address signal and a memory control signal) from the logic circuit block LB to the memory blocks MB1 to MB3 is wired along the direction D1. The That is, the memory global line GLM formed of the fifth aluminum wiring layer ALE is wired from the logic circuit block LB along the direction D1.

  More specifically, in FIG. 21, repeater blocks RP1 to RP3 are arranged corresponding to the memory blocks MB1 to MB3. These repeater blocks RP1 to RP3 include a buffer that buffers at least a write data signal (or an address signal or a memory control signal) from the logic circuit block LB and outputs the buffered data to the memory blocks MB1 to MB3. As shown in FIG. 21, the memory blocks MB1 to MB3 and the repeater blocks RP1 to RP3 are adjacently disposed along the direction D1.

  For example, when a write data signal, an address signal, and a memory control signal from the logic circuit block LB are supplied to the memory blocks MB1 to MB3 using the memory global line GLM, if these signals are not buffered, the signal rises. Waveform and falling waveform are dull. As a result, there is a possibility that the data writing time to the memory blocks MB1 to MB3 becomes long or a writing error occurs.

  In this regard, if repeater blocks RP1 to RP3 as shown in FIG. 21 are arranged adjacent to each memory block MB1 to MB3, for example, on the D1 direction side, these write data signals, address signals, and memory control signals are transmitted to the repeater blocks RP1 to RP1. The data is buffered by RP3 and input to each of the memory blocks MB1 to MB3. As a result, it is possible to reduce the dullness of the rising waveform and falling waveform of the signal, and it is possible to realize proper data writing to the memory blocks MB1 to MB3.

  In FIG. 21, the integrated circuit device includes a gradation voltage generation circuit block GB for generating gradation voltages. A gradation global line GLG for supplying the gradation voltage from the gradation voltage generation circuit block GB to the data driver blocks DB1 to DB3 is wired along the direction D1. That is, the gradation global line GLG formed by the fifth aluminum wiring layer ALE is wired from the logic circuit block LB along the direction D1. The gradation voltage supply lines GSL1 to GSL3 for supplying the gradation voltages from the gradation global line GLG to the data drivers DR1 to DR3 are wired along the direction D2 in each of the data drivers DR1 to DR3. Specifically, the gradation voltage supply lines GSL1 to GSL3 are wired along the D2 direction on the D / A converter of each subpixel driver cell across a plurality of subpixel driver cells described later.

  Further, in this embodiment, as shown in FIG. 21, the memory global line GLM is wired along the direction D1 between the gradation global line GLG and the driver global line GLD.

  That is, as shown in FIG. 21, in this embodiment, the buffer circuits BF1 to BF3 and the row address decoders RD1 to RD3 are arranged along the direction D1. By wiring the driver global line GLD along the D1 direction from the logic circuit block LB through the buffer circuits BF1 to BF3 and the row address decoders RD1 to RD3, the wiring efficiency can be greatly improved.

  Further, it is necessary to supply the grayscale voltage from the grayscale voltage generation circuit block GB to the data drivers DR1 to DR3. For this purpose, the grayscale global line GLG is wired along the direction D1.

  On the other hand, address signals, memory control signals, and the like are supplied to the row address decoders RD1 to RD3 through the memory global line GLM. Therefore, the memory global line GLM is preferably wired near the row address decoders RD1 to RD3.

  In this regard, in FIG. 21, the memory global line GLM is wired between the gradation global line GLG and the driver global line GLD. Accordingly, an address signal, a memory control signal, and the like from the memory global line GLM can be supplied to the row address decoders RD1 to RD3 through a short path. Further, the gradation global line GLG can be arranged substantially straight along the direction D1 above the memory global line GLM. Accordingly, it is possible to perform wiring without crossing the global lines GLG, GLM, and GLD by using a single aluminum wiring layer ALE, and wiring efficiency can be improved.

7.2 Repeater Block FIG. 22 shows a configuration example of a repeater block. In FIG. 22, write data signals (WD0, WD1,...) From the logic circuit block LB are buffered by buffers BFA1, BFA2,... Composed of two inverters, and output to the repeater block at the next stage. Is done. Specifically, in FIG. 5B, buffering is performed from the repeater block arranged on the D1 direction side of the memory block MB4 to the next-stage repeater block arranged on the D1 direction side of the memory block MB3. A signal is output. The write data signal from the logic circuit block LB is buffered by the buffers BFB1, BFB2,... And output to the memory block. Specifically, in FIG. 5B, a buffered signal is output to the memory block MB4 from a repeater block arranged on the D1 direction side of the memory block MB4. As described above, in this embodiment, the write data signal is provided not only with the buffers BFA1, BFA2,... For output to the memory block at the next stage, but also with the buffers BFB1, BFB2. ing. By doing so, it is possible to effectively prevent the write data signal waveform from becoming dull due to the parasitic capacitance of the memory cells of the memory block, and to prolong the write time and cause a write error.

  Address signals (CPU column address, CPU row address, LCD row address, etc.) from the logic circuit block LB are buffered by the buffers BFC1... And output to the memory block and the next repeater block. Memory control signals (read / write switching signal, CPU enable signal, bank selection signal, etc.) from the logic circuit block LB are buffered by the buffers BFD1... And output to the memory block and the next-stage repeater block. The

  Further, the repeater block of FIG. 22 is also provided with a buffer for read data signals from the memory block. Specifically, when the bank selection signal BANKM becomes active (H level) and the memory block (the Jth memory block among the first to Ith memory blocks) is selected, the memory block ( Read data signals from the Jth memory block) are buffered by the repeater block buffers BFE1, BFE2,... Corresponding to the memory block and output to the read data lines RD0L, RD1L,. On the other hand, when the bank selection signal BANKM becomes inactive (L level) and the memory block (Jth memory block) is not selected, the repeater block buffers BFE1, BFE2,. • The output state is set to the high impedance state. As a result, the read data signal from another memory block in which the bank selection signal is activated can be appropriately output to the logic circuit block LB. In this embodiment, when accessing from the host side, the memory block corresponding to the access area is selected, and only the word line WL of the memory block is selected. As a result, the read data signal is output from the selected memory block to the read data lines RD0L, RD1L,... Via the repeater block.

7.3 Arrangement of Power Supply Circuit, Logic Circuit, and Scan Driver In FIG. 23, a power supply global line GPD for supplying the power supply voltage generated in the power supply circuit block PB to the data driver blocks DB1 and DB2 and the logic circuit block LB. , GPL is wired along the D1 direction on the circuit block interposed between PB and DB1, DB2 or between PB and LB.

  That is, the display driver circuit includes an LV region (first circuit region in a broad sense) in which a circuit that operates with a power source having a voltage level of LV (Low Voltage) (first voltage level in a broad sense), LV It is formed in an MV region (second circuit region in a broad sense) or the like in which a circuit that operates with a power source having a higher MV (Middle Voltage) voltage level (second voltage level in a broad sense) is disposed. For example, logic circuit blocks and memory block circuits are formed in the LV region. The D / A converter and operational amplifier circuits included in the data driver block are formed in the MV region. For this reason, the power supply circuit block incorporated in the display driver needs to generate these LV and MV power supply voltages and supply them to each circuit block.

  In this case, if only the output I / F area 12 and the input I / F area 14 are used to wire the power supply lines, it becomes difficult to wire other signal lines to these areas 12 and 14. , Wiring efficiency decreases. Further, if the power supply line is detoured, the power supply impedance may increase and the power supply capability may decrease.

  Therefore, in this embodiment, not only signal lines but also power supply lines are wired with global lines. For example, in FIG. 23, the MV and LV power generated in the power circuit block PB is supplied to the data driver blocks DB1 and DB2 using the power global line GPD. Then, D / A converters, operational amplifiers and the like in the data driver blocks DB1 and DB2 are operated by the supplied MV power supply. Further, the latch circuits and the like in the data driver blocks DB1 and DB2 are operated by the supplied LV power supply. In FIG. 23, the LV power generated in the power circuit block PB is supplied to the logic circuit block LB using the power global line GPL. In this way, the logic circuit block LB can operate with the LV power supply from the power supply circuit block PB even if no digital power supply is supplied from the outside.

  In FIG. 23, since the global lines GPD and GPL from the power supply circuit block PB are wired in a substantially straight line to the data driver blocks DB1 and DB2 and the logic circuit block LB, an increase in power supply impedance can be minimized. Stable power supply becomes possible.

  In FIG. 23, the data driver blocks DB1 and DB2 are arranged between the power supply circuit block PB and the logic circuit block LB. In FIG. 23, scan driver blocks SB1 and SB2 are arranged at both ends of the integrated circuit device.

  When the scan driver blocks SB1 and SB2 are arranged at both ends of the integrated circuit device in this way, the scan driver pads for electrically connecting the output lines of the scan driver blocks SB1 and SB2 and the scan lines of the display panel. Also, regarding the wiring efficiency, it is desirable to arrange them at both ends of the integrated circuit device. On the other hand, the data driver blocks DB1 and DB2 are arranged near the center of the integrated circuit device. Therefore, the data driver pads for electrically connecting the output lines of the data driver blocks DB1 and DB2 and the data lines of the display panel should be arranged near the center of the integrated circuit device in consideration of wiring efficiency. desirable.

  Therefore, in FIG. 23, the data driver pads are arranged on the D2 direction side of the data driver blocks DB1 and DB2, and are arranged on the D2 direction side of the memory blocks adjacent to the DB1 and DB2. Further, a scan driver pad is disposed on the D2 direction side of the power supply circuit block PB. That is, scan driver pad placement areas are provided at both ends of the output-side I / F area 12, and data driver pad placement areas are provided between the scan driver pad placement areas. Thus, the output lines of the scan driver blocks SB1 and SB2 and the output lines of the data driver blocks DB1 and DB2 can be efficiently connected to the scan driver pads and the data driver pads.

  In particular, in FIG. 23, the power supply circuit block PB and the logic circuit block LB having a large circuit area are arranged on both sides of the data driver blocks DB1 and DB2. In this manner, the scan driver pad arrangement region is formed by effectively utilizing the empty regions (regions indicated by B1 and B2) on the D2 direction side of the power supply circuit block PB and logic circuit block LB having a large circuit area. it can. Accordingly, the wiring efficiency in the output I / F region 12 can be improved, the width W in the direction D2 of the integrated circuit device can be reduced, and a slim and slender integrated circuit device can be realized.

7.4 Shield Line FIG. 24 shows a detailed layout near the scan driver block SB1 and the logic circuit block LB. In FIG. 24, the scan driver global line GLS1, which is the output line of the scan driver block SB1, is wired on the logic circuit block LB from the scan driver block SB1 to the scan driver pad in the output side I / F area 12. Is done. FIG. 25 shows a detailed layout in the vicinity of the scan driver block SB2 and the power supply circuit block PB. In FIG. 25, the scan driver global line GLS2, which is the output line of the scan driver block SB2, is wired on the power supply circuit block PB from the scan driver block SB2 to the scan driver pad in the output I / F area 12. Is done.

  24 and 25, the number of scan driver pads is large, and the number of output lines of the scan driver blocks SB1 and SB2 is also large. For this reason, the occupied area of the wiring region of the scan driver global lines GLS1 and GLS2 also increases. As a result, in FIG. 24 and FIG. 25, the wiring areas of the scan driver global lines GLS1 and GLS2 are widely formed on the logic circuit block LB and the power supply circuit block PB.

  The output transistors of the scan driver blocks SB1 and SB2 operate at a high power supply voltage (HV) such as 30V. Therefore, when the scan driver global lines GLS1 and GLS2 are wired on the logic circuit block LB and the power supply circuit block PB as shown in FIGS. 24 and 25, the voltage levels of the scan driver global lines GLS1 and GLS2 change. Noise is transmitted to the circuits and signal lines in the logic circuit block LB and the power supply circuit block PB through the parasitic coupling capacitance. As a result, problems such as malfunction of the circuit may occur.

  Therefore, in the present embodiment, shield lines are wired under the scan driver global lines GLS1 and GLS2 in the logic circuit block LB and the power supply circuit block PB. Specifically, when the scan driver global lines GLS1 and GLS2 are formed of the fifth aluminum wiring layer ALE, a shield line formed of the fourth aluminum wiring layer ALD or the like below is wired.

  FIG. 26 shows a layout example of the shield line. 26, the scan driver global line GLS1 from the scan driver block SB1 passes over the logic circuit block LB (power supply circuit block PB) and is wired to the scan driver pads Pn, Pn + 1, Pn + 2,. In the logic circuit block LB (power supply circuit block PB), shield lines SDL1, SDL2, SDL3,... Are wired below these scan driver global lines GLS1. If such a shield line is wired, noise due to a change in the voltage level of the scan driver global line GLS1 is transmitted to the circuits and signal lines in the logic circuit block LB (power supply circuit block PB) by the coupling capacitance. Is prevented. As a result, malfunction of these circuits can be prevented.

7.5 Subpixel Driver Cell Arrangement FIG. 27 shows an arrangement example of subpixel driver cells. In FIG. 27, the data driver block includes a plurality of subpixel driver cells SDC1 to SDC180, each of which outputs a data signal corresponding to image data for one subpixel. That is, a plurality of subpixel driver cells are arranged along the D1 direction (a direction along the long side of the subpixel driver cell), and a plurality of subpixel driver cells are arranged along the D2 direction orthogonal to the D1 direction. . A data driver pad for electrically connecting the output line of the data driver block and the data line of the display panel is disposed on the D2 direction side of the data driver block. Data driver pads are also arranged on the D2 direction side of the memory block.

  For example, the driver cell DRC1 of the data driver DRa in FIG. 16 can be configured by the subpixel driver cells SDC1, SDC2, and SDC3 in FIG. Here, SDC1, SDC2, and SDC3 are subpixel driver cells for R (red), G (green), and B (blue), respectively, and R, G, and B corresponding to the first data signal. Image data (R1, G1, B1) is input from the memory block. The subpixel driver cells SDC1, SDC2, and SDC3 perform D / A conversion of these image data (R1, G1, and B1), and the first R, G, and B data signals (data voltages) are converted to the first data. Are output to the R, G, and B pads corresponding to the data lines.

  Similarly, the driver cell DRC2 includes R, G, and B subpixel driver cells SDC4, SDC5, and SDC6, and R, G, and B image data (R2, G2,. B2) is input from the memory block. Then, the subpixel driver cells SDC4, SDC5, and SDC6 perform D / A conversion of these image data (R2, G2, and B2), and the second R, G, and B data signals (data voltages) are the second. Are output to the R, G, and B pads corresponding to the data lines. The same applies to the other subpixel driver cells.

  Note that the number of subpixels is not limited to three, and may be four or more. The arrangement of the subpixel driver cells is not limited to that shown in FIG. 27, and R, G, and B subpixel driver cells may be stacked in the D2 direction, for example.

7.6 Arrangement of Sense Amplifier and Memory Cell FIG. 28 shows an arrangement example of the sense amplifier and the memory cell. The portion corresponding to one pixel in the sense amplifier block includes R sense amplifiers SAR0 to SAR5, G sense amplifiers SAG0 to SAG5, and B sense amplifiers SAB0 to SAB5. In FIG. 28, two (a plurality in a broad sense) sense amplifiers (and buffers) are stacked in the D1 direction. Of the two memory cell columns (vertical cells) arranged along the D1 direction on the D1 direction side of the stacked first and second sense amplifiers SAR0 and SAR1, the bit of the memory cell column in the upper row For example, the line is connected to the first sense-up SAR0, and the bit line of the memory cell column in the lower row is connected to the second sense amplifier SAR1, for example. Then, the first and second sense-up SAR0 and SAR1 perform signal amplification of the image data read from the memory cell, whereby 2-bit image data is output from SAR0 and SAR1. The same applies to the relationship between other sense amplifiers and memory cells.

  In the case of FIG. 28, readout of image data a plurality of times in one horizontal scanning period can be realized as follows. That is, in the first horizontal scanning period (first scanning line selection period), first, the word line WL1a is selected, the image data is read for the first time, and the first data signal DATAa is output. In this case, R, G, and B image data from the sense amplifiers SAR0 to SAR5, SAG0 to SAG5, and SAB0 to SAB5 are input to the subpixel driver cells SDC1, SDC2, and SDC3, respectively. Next, in the same first horizontal scanning period, the word line WL1b is selected, the image data is read for the second time, and the second data signal DATAb is output. In this case, R, G, and B image data from the sense amplifiers SAR0 to SAR5, SAG0 to SAG5, and SAB0 to SAB5 are input to the subpixel driver cells SDC91, SDC92, and SDC93, respectively.

7.7 Rearrangement Wiring Area In this embodiment, a rearrangement wiring area for rearranging the arrangement order of the output lines for the output signals of the subpixel driver cells can be provided in the subpixel driver arrangement area. In this way, switching of the wiring layer can be minimized, so that the width in the direction D2 of the wiring region between the data driver block and the pad can be reduced, and a slim and slender chip can be realized.

  For example, as shown in E1 and E2 of FIG. 29, the output lines (data signals) of the output signals (data signals) of the subpixel driver cells are wired along the D2 direction (vertical direction), for example. These extraction lines are lines for extracting the output signal of the subpixel driver cell from the data driver block, and are formed by, for example, the fourth aluminum wiring layer ALD. In FIG. 29, pads P1, P2, P3,... For connecting the output lines of the subpixel driver cells and the data lines of the display panel are arranged on the D2 direction side of the data driver block and the memory block. .

  In FIG. 29, rearrangement wiring areas (first and second rearrangement wiring areas) for rearranging the arrangement order of these extraction lines are provided in the subpixel driver arrangement area. Specifically, the rearrangement wiring region is formed in a region above the first and second aluminum wiring layers ALA and ALB which are local lines in the subpixel driver cell. In this rearrangement wiring area, the arrangement order of the extraction lines is rearranged in the order corresponding to the arrangement order of the pads. Here, the order corresponding to the arrangement order of the pads may be the arrangement order of the pads themselves, or may be an order obtained by changing the arrangement order of the pads according to a predetermined rule. The rearrangement wiring area is a wiring area formed by extraction lines indicated by E1 and E2 and extraction position change lines E6 to E9 described later.

  For example, in FIG. 29, the subpixel driver cells SDC1, SDC2, SDC4, SDC5, SDC7, SDC8... Whose cell number is not a multiple of 3 (in the broad sense, a multiple of J. J is an integer of 2 or more) The subpixel driver cells SDC3, SDC6, SDC9,... Belonging to one group and whose cell number is a multiple of 3 belong to the second group.

  The first group extraction line indicated by E1 is an output signal extraction line for the subpixel driver cells SDC1, SDC2, SDC4, SDC5, SDC7, SDC8,... Belonging to the first group. The arrangement order of the extraction lines of the first group indicated by E1 is rearranged in the first rearrangement wiring area. Specifically, in the first rearrangement wiring area, the arrangement order of the extraction lines is rearranged in the order of the pads P1, P2, P4, P5, P7, P8. That is, the arrangement order of the extraction lines is rearranged in the arrangement order of the pads excluding the pad whose pad number is a multiple of 3. In this way, the output lines of the subpixel driver cells are extracted in the order of SDC1, SDC2, SDC4, SDC5, SDC7, SDC8,... At the boundary (extraction port) on the D2 direction side of the data driver block. Are sorted and arranged.

  On the other hand, the extraction line of the second group indicated by E2 is an extraction line of output signals of the subpixel driver cells SDC3, SDC6, SDC9,... Belonging to the second group. The arrangement order of the second group extraction lines indicated by E2 is rearranged in the second rearrangement wiring region. Specifically, in the second rearrangement wiring area, the arrangement order of the extraction lines is rearranged in the order of the pads P3, P6, P9. That is, the arrangement order of the extraction lines is rearranged in the arrangement order of the pads whose pad number is a multiple of 3. In this way, the output lines of the output lines of the subpixel driver cells are rearranged in the order of SDC3, SDC6, SDC9,... At the boundary (extraction port) on the D2 direction side of the data driver block. Will come to be.

  Thus, if the rearrangement wiring area is provided in the subpixel driver and the arrangement order of the extraction lines is rearranged, the switching of the wiring layer in the area indicated by E3 which is the wiring area between the pad and the data driver block is minimized. Can be suppressed. As a result, the width WIT in the direction D2 of the wiring region indicated by E3 can be reduced, and a slim and slender chip can be realized.

  In the wiring area indicated by E3, the connection lines for connecting the first group extraction lines indicated by E1 and the pads P1, P2, P4, P5, P7, P8. Wiring is performed by three layers of aluminum wiring layers ALC (wires of a given layer in a broad sense). On the other hand, the connection line for connecting the second group lead-out line indicated by E2 and the pads P3, P6, P9..., As shown by E5, is the fourth aluminum wiring layer ALD (in a broad sense). Wired on a different layer than the given layer).

  For example, the connection line indicated by E4 is a line connecting the lead-out line from the subpixel driver cell SDC10 and the pad P10. On the other hand, the connection line indicated by E5 is a line connecting the lead-out line from the subpixel driver cell SDC9 and the pad P9. In this case, the connection line E4 is formed by the aluminum wiring layer ALC, and the connection line E5 is formed by the aluminum wiring layer ALD that is different from the ACL. Accordingly, it is not necessary to switch the wiring layer, and the E4 connection line and the E5 connection line can be overlapped in the E3 wiring region. As a result, the width WIT of the wiring region E3 in the direction D2 can be further reduced, and a slim and slender chip can be realized.

7.8 Extraction Position Change Line In this embodiment, extraction position change lines for changing the extraction positions of the extraction lines shown in E1 and E2 in FIG. 29 are wired in the rearrangement wiring area. For example, QCL1 and QCL2 indicated by E6 are extraction position change lines for changing the extraction positions of output signals (output lines) of the subpixel driver cells SDC1 and SDC2. Similarly, QCL4 and QCL5 indicated by E7 are take-out position change lines for SDC4 and SDC5, QCL7 and QCL8 indicated by E8 are take-out position change lines for SDC7 and SDC8, and QCL10 and QCL11 indicated by E9 are SDC10 and SDC11. It is an extraction position change line.

  Here, for example, as indicated by E6, the extraction position change lines QCL1 and QCL2 are wired in the D1 direction (lateral direction) across the plurality of subpixel driver cells SDC1 and SDC2 arranged along the D1 direction. That is, two take-out position change lines QCL1 and QCL2 are routed across the two subpixel driver cells SDC1 and SDC2 arranged along the direction D1. By doing so, it becomes possible to take out the output signals of the subpixel driver cells SDC1 and SDC2 from any position along the direction D1 of the first rearrangement wiring region using the takeout line.

  That is, the extraction position change lines QCL1 and QCL2 are wired by the third layer aluminum wiring layer ALC. Therefore, if vias of ALC and ALD are formed at arbitrary positions of the extraction position change lines QCL1 and QCL2 wired along the direction D1, the extraction line formed by ALD is moved from the via formation position to the direction D2. Can be wired. As a result, the extraction line can be wired in the D2 direction from an arbitrary extraction position in the D1 direction, and the arrangement order of the extraction lines can be easily rearranged.

  FIG. 30A shows an example of how each aluminum wiring layer is used. For example, the first aluminum wiring layer ALA wired in the vertical or horizontal direction is used as a source / drain / gate connection line of a transistor in a circuit block. The second aluminum wiring layer ALB mainly wired in the vertical direction is used as a power supply line, a signal line, a gradation voltage supply line, or the like. The third aluminum wiring layer ALC that is mainly wired in the horizontal direction is used as an extraction position change line for a data driver, an image data supply line for a memory, and the like. The fourth aluminum wiring layer ALD mainly wired in the vertical direction is used as a data driver lead-out line, a gradation voltage supply line, and the like. Further, the fifth aluminum wiring layer ALE, which is a top metal wired mainly in the horizontal direction, is used as a global line or the like for wiring between non-adjacent circuit blocks.

  FIG. 30B shows a layout example of the aluminum wiring layer ALC wired in the subpixel driver cell. In FIG. 30B, the take-out position change line and the DAC drive line are wired along the D1 direction (lateral direction) by the thick aluminum wiring layer ALC. Further, for example, 18 image data supply lines corresponding to one pixel are wired along the direction D1 by the aluminum wiring layer ALC. In this way, in the subpixel driver cell, a large number of image data supply lines and the take-out position change lines indicated by E6 in FIG. 29 are wired by the same aluminum wiring layer ALC.

  In the present embodiment, the gradation voltage supply line for supplying the gradation voltage to the D / A converter DAC of the subpixel driver cell is wired along the D2 direction across the plurality of subpixel driver cells. . Specifically, the gradation voltage supply line is wired by effectively utilizing the empty area where the extraction line is not arranged by the aluminum wiring layer ALD of the same layer as the extraction line.

  Thus, in the present embodiment, the take-out position change line and the image data supply line along the D1 (lateral) direction are wired by the aluminum wiring layer ALC. On the other hand, the lead-out line and the gradation voltage supply line along the D2 (vertical) direction are wired by an aluminum wiring layer ALD which is a layer different from the ALC. In this way, the extraction position change line, the image data supply line, the extraction line, and the gradation voltage supply line can be efficiently wired using the two aluminum wiring layers ALC and ALD. Therefore, it is not necessary to use an aluminum wiring layer of another layer such as ALE, and ALE can be used for a global line or the like, so that the wiring efficiency can be improved and a slim and slender chip can be realized.

  In the present embodiment, a rearrangement wiring region is provided in the region of the output portion SSQ of the subpixel driver cell. For example, as shown in FIG. 29, the first rearrangement wiring region is provided in the region of the output part SSQ of the subpixel driver cells SDC1, SDC2, SDC4, SDC5, SDC7, SDC8,. The second rearrangement wiring region is provided in the region of the output portion SSQ of the second group of subpixel driver cells SDC3, SDC6, SDC9,. In this way, rearrangement of the arrangement order of the extraction lines can be realized by effectively utilizing the area of the output part SSQ of the subpixel driver cell. That is, as shown in E1 and E2 of FIG. 29, if the extraction line is wired in the output portion SSQ area and the SSQ area is set as the rearrangement wiring area, the gradation voltage supply line is connected to the DAC area on both sides of the SSQ. Can be wired. Accordingly, the lead-out line and the gradation voltage supply line can be wired by the same aluminum wiring layer ALD, and the wiring efficiency can be improved.

7.9 Layout of Subpixel Driver Cell FIG. 31 shows a detailed layout example of the subpixel driver cell. As shown in FIG. 31, each of the subpixel driver cells SDC1 to SDC180 includes a latch circuit LAT, a level shifter L / S, a D / A converter DAC, and an output unit SSQ. Note that another logic circuit such as an FRC (Frame Rate Control) circuit for gradation control may be provided between the latch circuit LAT and the level shifter L / S.

  A latch circuit LAT included in each subpixel driver cell latches 6-bit image data corresponding to one subpixel from the memory block MB1. The level shifter L / S converts the voltage level of the 6-bit image data signal from the latch circuit LAT. The D / A converter DAC performs D / A conversion of 6-bit image data using the gradation voltage. The output unit SSQ includes an operational amplifier OP (voltage follower connection) that performs impedance conversion of the output signal of the D / A converter DAC, and drives one data line corresponding to one subpixel. In addition to the operational amplifier OP, the output unit SSQ can include transistors for discharge, 8-color display, and DAC drive (switch elements).

  As shown in FIG. 31, each subpixel driver cell (first and second data drivers DRa and DRb) operates with a power supply having a voltage level of LV (Low Voltage) (first voltage level in a broad sense). A circuit that operates with a power supply of an LV region (first circuit region in a broad sense) in which a circuit is disposed and a voltage level (second voltage level in a broad sense) of MV (Middle Voltage) higher than LV is disposed. MV region (second circuit region in a broad sense). Here, LV is an operating voltage of the logic circuit block LB, the memory block MB, and the like. MV is an operating voltage of a D / A converter, an operational amplifier, a power supply circuit, and the like. Note that an output transistor of the scan driver is supplied with power at an HV (High Voltage) voltage level (third voltage level in a broad sense) to drive the scan line.

  For example, a latch circuit LAT (or other logic circuit) is arranged in the LV region (first circuit region) of the subpixel driver cell. In the MV region (second circuit region), a D / A converter DAC and an output unit SSQ having an operational amplifier OP are arranged. The level shifter L / S converts the LV voltage level signal into an MV voltage level signal.

  In FIG. 31, a buffer circuit BF1 is provided on the D4 direction side of the subpixel driver cells SDC1 to SDC180. The buffer circuit BF1 buffers the driver control signal from the logic circuit block LB and outputs it to the subpixel driver cells SDC1 to SDC180. In other words, it functions as a repeater block for driver control signals.

  Specifically, the buffer circuit BF1 includes an LV buffer arranged in the LV area and an MV buffer arranged in the MV area. The LV buffer receives and buffers a driver control signal (such as a latch signal) having a voltage level of LV from the logic circuit block LB, and buffers the LV buffer in the LV region of the sub-pixel driver cell arranged on the D2 direction side (LAT). ). Also, the MV buffer receives a driver control signal (DAC control signal, output control signal, etc.) of the LV voltage level from the logic circuit block LB, converts it to the MV voltage level by the level shifter, and buffers it. Are output to the circuits (DAC, SSQ) in the MV region of the subpixel driver cells arranged in (1).

  In this embodiment, as shown in FIG. 31, the subpixel driver cells SDC1 to SDC180 are arranged so that the MV regions (or LV regions) of the subpixel driver cells are adjacent to each other along the D1 direction. That is, adjacent subpixel driver cells are mirror-arranged with an adjacent boundary along the direction D2. For example, the subpixel driver cells SDC1 and SDC2 are arranged so that the MV regions are adjacent to each other. The subpixel driver cells SDC3 and SDC91 are also arranged so that the MV regions are adjacent to each other. The subpixel driver cells SDC2 and SDC3 are arranged so that the LV regions are adjacent to each other.

  If the MV regions are arranged adjacent to each other as shown in FIG. 31, it is not necessary to provide a guard ring or the like between the subpixel driver cells. Therefore, the width of the data driver block in the direction D1 can be reduced compared with the method in which the MV region and the LV region are adjacent to each other, and the area of the integrated circuit device can be reduced.

  Further, according to the arrangement method of FIG. 31, the MV region of the adjacent subpixel driver cell can be effectively used as the wiring region of the output line for the output signal of the subpixel driver cell, and the layout efficiency can be improved.

  As shown in FIGS. 27 and 31, in the present embodiment, the first and second data drivers DRa and DRb are arranged so that their MV regions (second circuit regions) are adjacent to each other. The LV region (first circuit region) of the first data driver DRa is adjacent to the first memory block MB1 (Jth memory block), and the LV region (first circuit region) of the second data driver DRb. ) Are arranged adjacent to the second memory block MB2 (J + 1th memory block). For example, in FIGS. 27 and 31, the first memory block MB1 is arranged adjacent to the LV region of the subpixel driver cells SDC1, SDC4, SDC7... SDC88 of the first data driver DRa. The second memory block MB2 is arranged adjacent to the LV region of the subpixel driver cells SDC93, SDC96, SDC99... SDC180 of the second data driver DRb. The memory blocks MB1 and MB2 operate with a power supply having a voltage level of LV. Therefore, if the LV region of the subpixel driver cell is arranged adjacent to the memory block in this way, the width of the driver macrocell constituted by the data driver block and the memory block in the direction D1 can be reduced, and the integrated circuit device can be reduced. The area can be increased.

7.10 D / A Converter FIG. 32 shows a detailed configuration example of the D / A converter (DAC) included in the subpixel driver cell. This D / A converter is a circuit that performs so-called tournament D / A conversion, and includes gradation voltage selectors SLN1 to SLN11, SLP1 to SLP11, and a predecoder 120.

  Here, the gradation voltage selectors SLN1 to SLN11 are selectors formed of N-type (first conductivity type in a broad sense) transistors, and the gradation voltage selectors SLP1 to SLP11 are P-type (second conductivity type in a broad sense). These N-type and P-type transistors are paired to form a transfer gate. For example, an N-type transistor constituting SLN1 and a P-type transistor constituting SLP1 are paired to constitute a transfer gate.

  The input terminals of the gradation voltage selectors SLN1 to SLN8 and SLP1 to SLP8 are V0 to V3, V4 to V7, V8 to V11, V12 to V15, V16 to V19, V20 to V23, V24 to V27, V28 to V31, respectively. Grayscale voltage supply lines are connected. The predecoder 120 receives the image data D0 to D5 and performs a decoding process as shown in the truth table of FIG. The selection signals S1 to S4 and XS1 to XS4 are output to the gradation voltage selectors SLN1 to SLN8 and SLP1 to SLP9, respectively. The selection signals S5 to S8 and XS5 to XS8 are output to SLN9 and SLN10, SLP9 and SLP10, respectively, and S9 to S12 and XS9 to XS12 are output to SLN11 and SLP11, respectively.

  For example, when the image data D0 to D5 is (100000), the selection signals S2, S5, and S9 (XS2, XS5, and XS9) become active as shown in the truth table of FIG. Thus, the gradation voltage selectors SLN1 and SLP1 select the gradation voltage V1, SLN9 and SLP9 select the outputs of SLN1 and SLP1, and SLN11 and SLP11 select the outputs of SLN9 and SLP9. Therefore, the gradation voltage V1 is output to the output unit SSQ. Similarly, when the image data D0 to D5 are (010000), the selection signal S3 (XS3) becomes active, so that the gradation voltage selectors SLN1 and SLP1 select the gradation voltage V2, and the output unit SSQ has a level. A regulated voltage V2 is output. When the image data D0 to D5 are (001000), the selection signals S1, S6, S9 (XS1, XS6, XS9) are activated. Therefore, the gradation voltage selectors SLN2 and SLP2 select the gradation voltage V4, SLN9 and SLP9 select the outputs of SLN2 and SLP2, and SLN11 and SLP11 select the outputs of SLN9 and SLP9. Therefore, the gradation voltage V4 is output to the output unit SSQ.

  In this embodiment, as shown in FIGS. 33B and 33C, the gradation voltage supply line for supplying the gradation voltages V0 to V31 to the D / A converter of FIG. 32 includes a plurality of subpixel drivers. Wiring is performed along the D2 (D4) direction across the cells. For example, in FIG. 33B, the grayscale voltage supply line is wired in the D2 direction across the subpixel driver cells SDC1, SDC4, and SDC7 arranged in the D2 direction. Further, these gradation voltage supply lines are wired on the arrangement area of the D / A converter (gradation voltage selector) as shown in FIGS.

  More specifically, as shown in FIG. 33B, in the D / A converter arrangement region of the subpixel driver cell, an N-type transistor region (P-type well), a P-type transistor region ( N-type well) is arranged. On the other hand, in the arrangement region of circuits (output unit, level shifter, latch circuit) other than the D / A converter of the subpixel driver cell, an N-type transistor region (P-type well), P along the D1 direction orthogonal to the D2 direction. A type transistor region (N type well) is disposed. In other words, the subpixel driver cells adjacent along the D2 direction are mirror-arranged with an adjacent boundary along the D1 direction. For example, the driver cells SDC1 and SDC4 are mirror-arranged with the adjacent boundary therebetween, and SDC4 and SDC7 are mirror-arranged with the adjacent boundary interposed therebetween.

  For example, the N-type transistors constituting the gradation voltage selectors SLN1 to SLN11 of the D / A converter of the subpixel driver cell SDC1 are formed in the N-type transistor region NTR1 of the subpixel driver cell shown in FIG. P-type transistors constituting the voltage regulator selectors SLP1 to SLP11 are formed in the P-type transistor region PTR1. Specifically, as shown in FIG. 33C, the N-type transistors TRF1 and TRF2 constituting the gradation voltage selector SLN11 and the N-type transistors TRF3 and TRF4 constituting the gradation voltage selectors SLN9 and SLN10 are N-type. It is formed in transistor region NTR1. On the other hand, the P-type transistors TRF5 and TRF6 constituting the gradation voltage selector SLP11 and the P-type transistors TRF7 and TRF8 constituting the gradation voltage selectors SLP9 and SLP10 are formed in the P-type transistor region PTR1. The N-type transistor region and the P-type transistor region of other circuits of the subpixel driver cell are arranged along the direction D1, whereas the N-type transistor region NTR1 and the P-type transistor region PTR1 are arranged along the direction D2. Arranged.

  In the D / A converter of FIG. 32, for example, an N-type transistor constituting the gradation voltage selector SLN1 and a P-type transistor constituting the gradation voltage selector SLP1 form a pair to form a transfer gate. Therefore, if the gradation voltage supply line is wired along the D2 direction, the gradation voltage supply line can be commonly connected to these P-type and N-type transistors, and the transfer gate can be easily configured, and the layout can be realized. Efficiency can be improved.

  On the other hand, it is necessary to input image data from a memory block to a circuit other than the D / A converter, for example, a latch circuit. Then, as shown in FIG. 33B, this image data is supplied by an image data supply line wired along the direction D1. As is clear from the layout of FIG. 31, the direction of signal flow in the subpixel driver cell is the D1 direction. Therefore, if the N-type transistor region and the P-type transistor region of the circuit other than the D / A converter are arranged side by side along the D1 direction as shown in FIG. 33B, an efficient layout along the signal flow is possible. become. Therefore, the arrangement of the transistor regions as shown in FIG. 33B is an optimal layout for the subpixel driver cells arranged as shown in FIG.

  Although the present embodiment has been described in detail as described above, it will be easily understood by those skilled in the art that many modifications can be made without departing from the novel matters and effects of the present invention. Accordingly, all such modifications are intended to be included in the scope of the present invention. For example, in the specification or drawings, terms (output-side I / F region, input-side I / F) described at least once together with different terms having a broader meaning or the same meaning (first interface region, second interface region, etc.) (Area, etc.) can be replaced with the different terms anywhere in the specification or drawings. Further, the configuration, arrangement, and operation of the integrated circuit device and the electronic device are not limited to those described in this embodiment, and various modifications can be made.

1A, 1B, and 1C are explanatory diagrams of a comparative example of the present embodiment. FIGS. 2A and 2B are explanatory views for mounting an integrated circuit device. 1 is a configuration example of an integrated circuit device according to an embodiment. Examples of various types of display drivers and the circuit blocks they contain. 5A and 5B are plan layout examples of the integrated circuit device of this embodiment. 6A and 6B are examples of cross-sectional views of the integrated circuit device. 6 is a circuit configuration example of an integrated circuit device. 8A, 8B, and 8C are configuration examples of a data driver and a scan driver. 9A and 9B are configuration examples of a power supply circuit and a gradation voltage generation circuit. 10A, 10B, and 10C are configuration examples of a D / A conversion circuit and an output circuit. Explanatory drawing of the method of arrange | positioning a scanning driver block and a power supply circuit block adjacent, and arrange | positioning a data driver block and a memory block adjacently. 12A and 12B are explanatory diagrams of a comparative example. 13A and 13B show arrangement examples of the data driver block and the memory block. 14A and 14B are explanatory diagrams of the arrangement of memory blocks and data driver blocks. Explanatory drawing of the method of reading image data in multiple times in 1 horizontal scanning period. Data driver and driver cell arrangement example. 17A, 17B, and 17C are configuration examples of memory cells. An arrangement example of memory blocks and driver cells in the case of a horizontal cell. An arrangement example of memory blocks and driver cells in the case of a vertical cell. 20A and 20B are configuration examples of electronic devices. Example of global wiring. The structural example of a repeater block. Explanatory drawing of the wiring method of the global line for power supplies. An example layout of a logic circuit block and a scan driver block. The layout example of a power supply circuit block and a scanning driver block. Explanatory drawing of the global line shielding technique. An arrangement example of subpixel driver cells. An example of arrangement of sense amplifiers and memory cells. Explanatory drawing of a pad wiring method. 30 (A) and 30 (B) are explanatory views of usage modes of the aluminum wiring layer. 2 shows a configuration example of a subpixel driver cell. The structural example of a D / A converter. FIGS. 33A, 33B, and 33C are a truth table of a sub-decoder of a D / A converter and an explanatory diagram of a layout of the D / A converter.

Explanation of symbols

CB1 to CBN 1st to Nth circuit blocks, 10 integrated circuit devices,
12 output side I / F area, 14 input side I / F area, 20 memory,
22 memory cell array, 24 row address decoder,
26 column address decoder, 28 write / read circuit,
40 logic circuit, 42 control circuit, 44 display timing control circuit,
46 host interface circuit, 48 RGB interface circuit,
50 data drivers, 52 data latch circuits, 54 D / A conversion circuits,
56 output circuit, 70 scan driver, 72 shift register,
73 scanning address generation circuit, 74 address decoder, 76 level shifter,
78 output circuit, 90 power supply circuit, 92 booster circuit, 94 regulator circuit, 96 VCOM generation circuit, 98 control circuit, 110 gradation voltage generation circuit,
112 selection voltage generation circuit, 114 gradation voltage selection circuit, 116 adjustment register

Claims (19)

An integrated circuit device for driving a display panel,
A direction toward a third side opposite the first side which is the short side of the integrated circuit device to the first direction, said integrated circuit device a long side which is the fourth to an opposing second side of the When the direction toward the side is the second direction, the first to Nth circuit blocks (N is an integer of 2 or more) arranged along the first direction,
The first to Nth circuit blocks are:
A scan driver block for driving scan lines of the display panel ;
A power supply circuit block for generating a power supply voltage;
At least one data driver block for driving data lines of the display panel ;
At least one memory block for storing image data;
The data driver block that is connected to the memory block and drives the data line by the image data stored in the memory block, and the memory block are arranged adjacent to each other along the first direction,
The power circuit block is
An integrated circuit device arranged between the scan driver block and the data driver block and the memory block. In claim 1,
A first scan driver block is disposed as a first circuit block among the first to Nth circuit blocks, and a second scan is performed as an Nth circuit block among the first to Nth circuit blocks. Driver block is placed
At least one data driver block and at least one memory block are arranged between the first scan driver block, the power supply circuit block, and the second scan driver block. apparatus. In claim 1,
The scan driver block is arranged as a first circuit block among the first to Nth circuit blocks,
An integrated circuit device, wherein at least one of the data driver blocks and at least one of the memory blocks are arranged on the first direction side of the scan driver block and the power supply circuit block. In any one of Claims 1 thru | or 3,
The first to Nth circuit blocks are:
First to I-th memory blocks (I is an integer of 2 or more);
An integrated circuit comprising: a first to a first data driver block arranged adjacent to each of the first to I-th memory blocks along the first direction; Circuit device. In claim 4,
When the direction opposite to the first direction is the third direction, the Jth memory block (1 ≦ J <I) of the first to Ith memory blocks is located on the third direction side. , J-th data driver block among the first to I-th data driver blocks is arranged adjacently,
The J + 1th data driver block among the first to Ith data driver blocks is disposed on the first direction side of the Jth memory block,
An integrated circuit device, wherein a J + 1th memory block of the first to Ith memory blocks is adjacently arranged on the first direction side of the J + 1th data driver block. In any one of Claims 1 thru | or 5 ,
A word line connected to the memory cell of the memory block is wired along the second direction in the memory block,
An integrated circuit device, wherein a bit line through which image data stored in the memory block is output to the data driver block is wired along the first direction in the memory block. In any one of Claims 1 thru | or 6 .
An integrated circuit device, wherein image data stored in the memory block is read from the memory block to the data driver block a plurality of times in one horizontal scanning period. In any one of Claims 1 thru | or 7 ,
The data driver block is:
An integrated circuit device comprising: a plurality of data drivers arranged in a stack along the first direction. In any one of Claims 1 thru | or 8 .
The data driver included in the data driver block is:
An integrated circuit device comprising Q driver cells, each of which outputs a data signal corresponding to image data for one pixel and is arranged along the second direction. In claim 9 ,
When the number of pixels in the horizontal scanning direction of the display panel is HPN, the number of data driver blocks is DBN, and the number of input image data input to the driver cell in one horizontal scanning period is IN,
The number Q of the driver cells arranged along the second direction is Q = HPN / (DBN × IN). In any one of Claims 1 thru | or 10 .
The number of pixels in the horizontal scanning direction of the display panel is HPN, the number of bits of image data for one pixel is PDB, the number of memory blocks is MBN, and image data read from the memory block in one horizontal scanning period is read. When the number of times is RN,
The sense amplifier block of the memory block includes P sense amplifiers arranged along the second direction,
The number P of the sense amplifiers is P = (HPN × PDB) / (MBN × RN). In any one of Claims 1 thru | or 11 ,
In the sense amplifier block of the memory block, a plurality of sense amplifiers are stacked in the first direction. In claim 12 ,
Of the two memory cell columns arranged along the first direction on the first direction side of the first and second sense amplifiers arranged in a stack, the bit lines of the memory cell columns in the upper row are the An integrated circuit device, wherein the bit line of a memory cell column in a lower row is connected to the first sense amplifier, and the bit line of the memory cell column in the lower row is connected to the second sense amplifier. In any one of Claims 1 thru | or 13 .
A data driver pad for electrically connecting the output line of the data driver block and the data line is disposed on the second direction side of the data driver block, and the second of the memory block. Placed on the direction side of
An integrated circuit device, wherein a scan driver pad for electrically connecting the output line of the scan driver block and the scan line is disposed on the second direction side of the power supply circuit block. In claim 14 ,
A power supply global line for supplying a power supply voltage generated by the power supply circuit block to the data driver block is arranged in the first direction on a circuit block interposed between the power supply circuit block and the data driver block. An integrated circuit device characterized by being wired along. In claim 14 or 15 ,
An integrated circuit device, wherein a scan driver global line, which is an output line of the scan driver block, is wired on the power supply circuit block from the scan driver block to the scan driver pad. In claim 16 ,
In the power supply circuit block, a shield line is wired below the scan driver global line. In any one of Claims 1 thru | or 17 ,
A first interface region provided along the fourth side on the second direction side of the first to Nth circuit blocks;
A second interface region provided along the second side on the fourth direction side of the first to Nth circuit blocks when a direction opposite to the second direction is a fourth direction. And an integrated circuit device. An integrated circuit device according to any one of claims 1 to 18 ,
And the display panel driven by the integrated circuit device,
An electronic device comprising:

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