JP4661089B2 - Method of manufacturing high electron mobility transistor - Google Patents

Description

The present invention relates to the production how the HEM T is a high electron mobility transistor.

  Conventionally, as a semiconductor element having excellent high-frequency characteristics, a high electron mobility transistor (hereinafter referred to as “HEMT (High Electron)” having a structure in which a compound semiconductor layer doped with impurities and a compound semiconductor layer not doped with impurities are heterojunctioned. Mobility Transistor) ”)) is widely known (see, for example, Patent Document 1).

  As shown in FIG. 7, the HEMT 100 includes a GaAs doped layer 102, an n + AlGaAs doped layer 103, an AlGaAs (aluminum gallium arsenic) spacer layer 104, and an InGaAs (gallium arsenic) substrate 101 on an upper surface of a GaAs (gallium arsenic) substrate 101. Indium, gallium, arsenic) channel layer 105, AlGaAs spacer layer 106, n + GaAs doped layer 107, n-AlGaAs barrier layer 108, and n + GaAs ohmic cap layer 109 are epitaxially grown in this order. .

  A gate electrode 111 formed in contact with the n-AlGaAs barrier layer 108 and a source electrode 112 and a drain electrode 113 formed in contact with the n + GaAs ohmic cap layer 109 are provided on the upper surface of the epitaxial layer 110. A SiN (silicon nitride) film as an insulating film is formed between the source electrode 112, the gate electrode 111, and the drain electrode 113, and on the upper surface of the epitaxial layer 110 outside the source electrode 112 and the drain electrode 113. 114.

  Since the HEMT100 configured in this manner is a semiconductor element capable of high-speed operation, for example, as a switch IC or power amplifier IC of a mobile communication device such as a mobile phone or PDA (Personal Digital Assistance) that performs high-speed data communication It was used.

  Since this mobile communication device is generally a device that operates with finite power supplied from a battery, it is necessary to reduce the power consumption of the HEMT 100 used as a switch IC or a power amplifier IC.

  Therefore, in recent years, as shown in FIG. 8, a low resistance type HEMT 116 has been developed that achieves low power consumption by providing a low resistance region 115.

  In FIG. 8, the same reference numerals are given to the components corresponding to the components of the HEMT 100 shown in FIG. 7, and the description thereof is omitted.

  This low resistance type HEMT 116 reduces the ohmic contact resistance of the source electrode 112 and the drain electrode 113 by forming the low resistance region 115 in the n-AlGaAs barrier layer 108 below the source electrode 112 and the drain electrode 113. The power consumption was reduced by reducing the on-resistance during operation.

The low resistance region 115 is damaged by ion implantation by ion-implanting n-type impurity Si (silicon) into the n-AlGaAs barrier layer 108 and then performing heat treatment at a high temperature of 800 ° C. or higher. It was formed by thermally diffusing Si inside the n-AlGaAs barrier layer 108 while recovering the crystal structure of the surface of the -AlGaAs barrier layer 108.
JP 2001-7319

  However, the conventional low resistance type HEMT 116 has been subjected to a heat treatment at a high temperature of 800 ° C. or higher in order to thermally diffuse Si ion-implanted into the n-AlGaAs barrier layer 108. There was a possibility that atoms would be activated and interdiffusion of atoms would occur.

  In particular, if this interdiffusion of atoms occurs at the interface of the InGaAs channel layer 105, the mobility of electrons moving inside the InGaAs channel layer 105 is extremely reduced when the low resistance HEMT 116 is operated. As a result, the channel resistance in the InGaAs channel layer 105 is increased.

  As a result, although the ohmic contact resistance at the source electrode 112 and the drain electrode 113 can be reduced by providing the low resistance region 115, the channel resistance in the InGaAs channel layer 105 is increased. The on-resistance cannot be reduced, and the low-resistance HEMT 116 cannot sufficiently reduce power consumption.

Therefore, this onset bright according to claim 1, on a substrate made of GaAs, a first step of forming a buffer layer made of GaAs, the buffer layer, an AlGaAs doped with Si as an n-type impurity A second step of forming a first n + doped layer, a third step of forming a first spacer layer made of undoped AlGaAs on the first n + doped layer, and on the first spacer layer Further, a fourth step of forming a channel layer made of undoped InGaAs, a fifth step of forming a second spacer layer made of undoped AlGaAs on the channel layer, and on the second spacer layer, a sixth step of forming a second n + doped layer made of AlGaAs doped with Si, which is an n-type impurity, at a relatively high concentration; and an n-type impurity on the second n + doped layer A seventh step of forming an n-barrier layer made of AlGaAs doped with n, an eighth step of forming an ohmic cap layer made of GaAs doped with an n-type dopant on the n-barrier layer, and the ohmic cap A ninth step of selectively removing a part of the layer; a tenth step of forming an insulating film made of SiN on the ohmic cap layer and the n-barrier layer; and in a hydrogen atmosphere at about 600 ° C. An eleventh step of performing a heat treatment to form a low resistance region made of AlGaAs in which an n-type impurity is diffused at a relatively high concentration below the ohmic cap layer, and removing the insulating film on the ohmic cap layer by etching A twelfth step of exposing the ohmic cap layer, and a source electrode and a drain electrode on the exposed ohmic cap layer. Includes a thirteenth step of forming, a, wherein the large active diffusion coefficient than Si as a dopant, selenium interdiffusion of atoms in the channel layer is thermally diffused at a temperature which does not generate (Se) or sulfur (S) It was set as the manufacturing method of the used high electron mobility transistor .

  The present invention has the following effects.

In the present invention according to claim 1 , in the method of manufacturing a high electron mobility transistor in which a dopant is injected into a barrier layer between an electrode and a channel layer and a low resistance region is formed by thermal diffusion, Using a material with a larger diffusion coefficient than silicon, the ohmic contact resistance of the source and drain electrodes is reduced, and the increase in channel resistance in the channel layer is suppressed, resulting in low power consumption. Transistors can be manufactured. In addition, as a dopant, a substance that thermally diffuses at a temperature that does not cause mutual diffusion of atoms in the channel layer is used. Therefore, when forming a low resistance region, mutual diffusion of atoms can be suppressed, thereby increasing channel resistance. It is also possible to manufacture a high electron mobility transistor in which the ohmic contact resistance of the source electrode and the drain electrode is reduced while suppressing. Furthermore, since selenium or sulfur is used as the dopant, a high electron mobility transistor having a channel resistance lower than that of the high electron mobility transistor using silicon as the dopant can be manufactured.

  A semiconductor device according to the present invention includes a high electron mobility transistor (hereinafter referred to as “HEMT (High Electron Mobility Transistor)”) formed on a semiconductor substrate.

  In this HEMT, a dopant is injected into a barrier layer below the source electrode and the drain electrode, and the ohmic contact resistance of the source electrode and the drain electrode is reduced by thermal diffusion to form a low resistance region.

  In particular, a material having a diffusion coefficient larger than that of silicon is used as a dopant to be diffused into the barrier layer when forming the low resistance region.

  Further, as this dopant, a substance that can be diffused into the barrier layer by a heat treatment at a temperature that does not cause mutual diffusion of atoms in the channel layer to form a low resistance region is used.

  The low resistance region is formed using selenium or sulfur as a material having a diffusion coefficient larger than that of silicon and thermally diffusing at a temperature at which no mutual diffusion of atoms occurs in the channel layer.

  Below, the manufacturing method of HEMT1 (refer FIG. 6) based on this invention is demonstrated concretely, referring drawings.

  First, a substrate 2 made of semi-insulating GaAs (gallium arsenide) is prepared, and a buffer layer 3 made of GaAs is epitaxially grown on the upper surface of the substrate 2.

  Next, a first n + doped layer 4 made of AlGaAs (aluminum / gallium / arsenic) doped with Si (silicon), which is an n-type impurity, at a relatively high concentration is epitaxially grown on the upper surface of the buffer layer 3.

  Next, a first spacer layer 5 made of undoped AlGaAs is epitaxially grown on the upper surface of the first n + doped layer 4.

  Next, a channel layer 6 made of undoped InGaAs (indium gallium arsenide) is epitaxially grown on the upper surface of the first spacer layer 5.

  Next, a second spacer layer 7 made of undoped AlGaAs is epitaxially grown on the upper surface of the channel layer 6.

  Next, a second n + doped layer 8 made of AlGaAs doped with a relatively high concentration of Si, which is an n-type impurity, is epitaxially grown on the upper surface of the second spacer layer 7.

  Next, an n− barrier layer 9 made of AlGaAs doped with an n-type impurity at a relatively low concentration is epitaxially grown on the upper surface of the second n + doped layer 8.

  Then, an epitaxial layer 11 as shown in FIG. 1 is formed on the upper surface of the n-barrier layer 9 by epitaxially growing an ohmic cap layer 10 made of GaAs doped with an n-type impurity at a relatively high concentration.

  In particular, as a dopant to be doped when forming the ohmic cap layer 11, Se (selenium) or S (sulfur) is used as a substance having a diffusion coefficient larger than that of Si.

  After forming the first n + doped layer 4, the second n + doped layer 8, the n− barrier layer 9, and the ohmic cap layer 10, annealing is performed at a relatively low temperature of about 600 ° C. The crystal structure damaged by doping with n-type impurities is recovered.

  Next, after forming a resist film (not shown) on the upper surface of the ohmic cap layer 10, patterning is performed to form the source electrode 12 and the drain electrode 13 (see FIG. 5) using a photolithography method, and then As shown in FIG. 2, the ohmic cap layer 10 other than the portions where the source electrode 12 and the drain electrode 13 are formed is removed by etching.

  Next, as shown in FIG. 3, SiN (Chemical Vapor Deposition) method is used on the upper surface of the epitaxial layer 11 from which the ohmic cap layer 10 other than the portion where the source electrode 12 and the drain electrode 13 are formed is removed. An insulating film 14 made of silicon nitride is formed.

  Next, the epitaxial layer 11 on which the insulating film 14 is formed is heat-treated in a hydrogen atmosphere to diffuse the n-type impurity doped in the ohmic cap layer 10 into the n-barrier layer 9. As a result, as shown in FIG. 4, a low resistance region 15 made of AlGaAs in which n-type impurities are diffused at a relatively high concentration is formed below the ohmic cap layer 10.

  In particular, since the n-type impurity diffused into the n-barrier layer 9 by the heat treatment performed here is a substance having a diffusion coefficient larger than that of Si as described above, Si is diffused into the n-barrier layer 9. It is not necessary to perform a heat treatment at a high temperature of 800 ° C. or higher as in the case of performing the process, and n-type impurities can be diffused into the n-barrier layer 9 by a heat treatment at a relatively low temperature of about 600 ° C.

  Therefore, the occurrence of interdiffusion of atoms at the interface of the channel layer 6 due to this heat treatment can be suppressed, and an increase in channel resistance can be suppressed.

  Next, after forming a resist film on the upper surface of the insulating film 14, patterning is performed to form the source electrode 12 and the drain electrode 13 using a photolithography method, and then the source electrode 12 and the drain electrode 13 are formed. A portion of the insulating film 14 is removed by etching.

  Subsequently, as shown in FIG. 5, the source electrode 12 and the drain electrode 13 are formed on the upper surface of the ohmic cap layer 10 where the insulating film 14 is removed.

  Finally, after forming a resist film on the upper surface of the epitaxial layer 11 on which the source electrode 12 and the drain electrode 13 are formed, patterning for forming the gate electrode 16 is performed using a photolithography method, and then the gate electrode 16 is formed. The portion of the insulating film 14 to be formed is removed by etching, and the gate electrode 16 is formed in contact with the portion of the n-barrier layer 9 from which the insulating film 14 has been removed, thereby producing a HEMT 1 as shown in FIG. To do.

  Thus, the HEMT 1 manufactured by the manufacturing method according to the present embodiment has a low resistance region 15 in which a material having a diffusion coefficient larger than Si is diffused in the n-barrier layer 9 below the source electrode 12 and the drain electrode 13. As a result, the ohmic contact resistance of the source electrode 12 and the drain electrode 13 can be reduced, and an increase in channel resistance in the channel layer 6 can be suppressed.

  As a result, the on-resistance when the HEMT 1 operates is reduced, so that power consumption can be reduced.

It is sectional drawing which shows the manufacturing process of HEMT which concerns on this invention. It is sectional drawing which shows the manufacturing process of HEMT which concerns on this invention. It is sectional drawing which shows the manufacturing process of HEMT which concerns on this invention. It is sectional drawing which shows the manufacturing process of HEMT which concerns on this invention. It is sectional drawing which shows the manufacturing process of HEMT which concerns on this invention. It is explanatory drawing which shows HEMT which concerns on this invention. It is explanatory drawing which shows the conventional HEMT. It is explanatory drawing which shows the conventional HEMT.

Explanation of symbols

1 HEMT
2 substrate 3 buffer layer 4 first n + doped layer 5 first spacer layer 6 channel layer 7 second spacer layer 8 second n + doped layer 9 n-barrier layer 10 ohmic cap layer 11 epitaxial layer 12 source electrode 13 Drain electrode 14 Insulating film 15 Low resistance region 16 Gate electrode

Claims (1)

A first step of forming a buffer layer made of GaAs on a substrate made of GaAs;
A second step of forming a first n + doped layer made of AlGaAs doped with Si, which is an n-type impurity, on the buffer layer;
Forming a first spacer layer of undoped AlGaAs on the first n + doped layer;
A fourth step of forming a channel layer made of undoped InGaAs on the first spacer layer;
Forming a second spacer layer made of undoped AlGaAs on the channel layer; and
A sixth step of forming a second n + doped layer made of AlGaAs on the second spacer layer, which is doped with Si, which is an n-type impurity, at a relatively high concentration;
A seventh step of forming an n− barrier layer made of AlGaAs doped with an n-type impurity on the second n + doped layer;
An eighth step of forming an ohmic cap layer made of GaAs doped with an n-type dopant on the n-barrier layer;
A ninth step of selectively removing a part of the ohmic cap layer;
A tenth step of forming an insulating film made of SiN on the ohmic cap layer and the n-barrier layer;
An eleventh step of performing a heat treatment at about 600 ° C. in a hydrogen atmosphere to form a low resistance region made of AlGaAs in which an n-type impurity is diffused at a relatively high concentration below the ohmic cap layer;
Removing the insulating film on the ohmic cap layer by etching and exposing the ohmic cap layer;
Forming a source electrode and a drain electrode on the exposed ohmic cap layer, and
Wherein the large active diffusion coefficient than Si as a dopant, the manufacturing method of the high electron mobility transistor using a selenium (Se) or sulfur (S) in which the mutual diffusion of atoms in the channel layer is thermally diffused at a temperature which does not occur.

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