JPH043944A - Field-effect transistor - Google Patents

Abstract

PURPOSE:To obtain a field-effect transistor having low source resistance by forming a potential barrier layer formed onto an operating layer with the exception of a pair of ohmic source-electrode and drain-electrode forming sections formed onto a high impurity-concentration semiconductor layer. CONSTITUTION:A pair of high impurity-concentration semiconductor layers 2 are shaped to an ohmic-electrode forming section on a semi-insulating GaAs substrate 1, and the shapes of end sections are formed in a tapered shape and a pair of a source electrode 5 and a drain electrode 6 are formed onto the high impurity-concentration semiconductor layers 21 but alloyed regions 8 are formed through heat treatment from an electrode metal. An N-type GaAs operating layer 3 is formed onto the high impurity-concentration semiconductor layers 2 in regions, in which the source electrode 5 and the drain electrode 6 are not formed, and onto the semi-insulating substrate 1 of a gate-electrode forming section, an undoped AlGaAs potential barrier layer 4 is formed onto the operating layer 3, and a gate electrode 7 ts further formed onto the potential barrier layer 4. Accordingly, there is no potential barrier layer among the source electrode and the drain electrode and the operating layer, thus acquiring a field- effect transistor capable of reducing source resistance.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a field effect transistor, and particularly to a metal-insulator-semiconductor type field effect transistor having a heterojunction (hereinafter referred to as a hetero MIS type field effect transistor).
Regarding.

[Conventional technology]

As a compound semiconductor device, an MIS field effect transistor is known which has a structure in which a potential barrier layer is provided on an active layer and a gate electrode is formed on the potential barrier layer. Among such MIS type field effect transistors, a hetero MIS type field effect transistor in which the active layer is an n-type GaAs layer and the potential barrier layer is a non-doped AlGaAs layer is described by I.
EE ELEFTRON Device Letters (I
EEE Electron Device Letter
s) Vol. 8, p. 557 (1987), it has excellent characteristics such as current drive ability.

FIG. 4 shows a cross-sectional view of a conventional hetero MIS field effect transistor. An n-type GaAs active layer 3 is formed on a semi-insulating GaAs substrate 1, and a non-doped AlGaAs potential barrier layer 4 is formed on the n-type GaAs active layer 3. The gate electrode 7 is made of Ti/Au, for example, and is formed on the non-doped AlGaAs potential barrier layer 4 by a vacuum evaporation method and a lift-off method. Further, the source electrode 5 and the drain electrode 6 are made of non-doped AlGaAs.
A metal film such as Au/Ge/Ni is formed on the layer 4, and an n-type GaAs operating layer 3 is formed by penetrating the non-doped AlGaAs layer 4.
It is formed by alloying a metal and a semiconductor up to 7 and contacting the active layer 3 through the alloyed region 8. Furthermore, in order to reduce the source resistance, an n-type dopant ion is implanted into the ohmic electrode formation portion to form the ion implantation region 9 before the ohmic electrode is formed.

In addition, a recess gate type structure has also been proposed, as shown in Proceedings of the Spring National Conference of the Electronics, Information and Communication Engineers, Vol. 5, p. 356 (1989). A cross-sectional view of the hetero MIS field effect transistor is shown in FIG.
For example, a high concentration n-type GaAs layer is formed thereon as the high impurity concentration semiconductor layer 2. The gate electrode forming portion is formed by etching the high impurity concentration semiconductor layer 2 and forming a T
The gate electrode 7 is formed of i/Au or the like. Further, the source electrode 5 and the drain electrode 16 are formed by forming a metal film such as Au/Ge/Ni on the high impurity concentration semiconductor layer 2, as in the example shown in FIG. An n-type GaAs operating layer 3 passes through the non-doped AlGaAs layer 4.
The metal and the semiconductor are alloyed and brought into contact with the active layer 3 through the alloyed region 8.

For example, as shown in Proceedings of the 1989 Autumn Academic Conference of the Japan Society of Applied Physics, page 1062, Tsukada et al. proposed a method of selectively regrowing a highly impurity-concentrated semiconductor layer on the ohmic electrode formation area. has been done. A cross-sectional view of the field effect transistor is shown in FIG. An n-type GaAs active layer 3 and non-doped AlG are formed on a semi-insulating GaAs substrate 1.
An aAs potential barrier layer 4 is formed, and the non-doped AlGaAs potential barrier layer 4 and the n-type GaAs operating layer 3 in the ohmic electrode formation area are etched to form an opening, and a high impurity concentration semiconductor layer 2 is selectively formed in the opening. n
type GaAs layer was grown using metal organic chemical vapor deposition method (hereinafter referred to as MOC).
It is formed by regrowth using a VD method (referred to as VD method) or the like. Furthermore, in order to reduce the contact resistance at the interface between the regrown layer and the active layer 3, a method is also used in which an n-type dopant is ion-implanted into the ohmic electrode formation portion to form the ion-implanted region 9 before the regrowth.

[Problem to be solved by the invention]

In the hetero MIS type field effect transistor as described in the conventional example, many problems have arisen in the ohmic electrode portion. First, as shown in FIG. 4, when alloying the electrode metal and the semiconductor layer through the potential barrier layer,
The alloying conditions were difficult, and when the alloying conditions were not appropriate, the source resistance increased and the variation increased.

For example, the potential barrier layer is non-doped A I GaA
In the case of s, alloying through the potential barrier layer requires a higher alloying temperature than without the potential barrier layer. It is also well known that even if the alloying temperature is optimized, the source resistance will be higher than with or without the potential barrier layer.

Further, even if an n-type dopant is ion-implanted to reduce the source resistance, the reduction in the source resistance is not sufficient to solve the problem that the source resistance increases due to the potential barrier layer. Furthermore, ion implantation complicates the manufacturing process, and the ion implantation region spreads laterally due to dopant diffusion, and short channel effects are likely to occur due to current flowing from the ion implantation region under the active layer. Ta.

Further, as shown in FIG. 5, even when a highly impurity-concentrated semiconductor layer is provided, the above-mentioned problem that the source resistance increases due to the potential barrier layer is not solved.

Further, in this structure, it is difficult to control the depth of recess etching of the gate forming portion, and variations in the etching depth cause variations in characteristics such as threshold voltage.

Furthermore, as shown in FIG. 6, when the potential barrier layer in the ohmic electrode formation area is etched and removed and a high impurity concentration semiconductor layer is selectively regrown in the opening, the parasitic resistance in the potential barrier layer increases. It has the advantage of being extremely small. However, it is difficult to increase the contact area between the regrown layer and the active layer, which tends to increase the source resistance.

Although it is possible to reduce the parasitic resistance at the regrowth interface by ion-implanting an n-type dopant into the ohmic electrode formation region, it has been difficult to sufficiently reduce the source resistance. Furthermore, the manufacturing process became complicated and short channel effects were likely to occur.

Further, problems arise when using an ohmic electrode that contacts only the high impurity concentration semiconductor layer, such as in a non-alloy ohmic device using an InGaAs layer or the like as the high impurity concentration semiconductor layer. Here, the high impurity concentration semiconductor layer is InXGa1
-xIf the In composition ratio X of As is gradually increased from O to 1 from the bottom to the surface in an n-type 1nGaAs gradient composition layer, there is theoretically a potential barrier between the electrode metal and the n-type GaAs layer. This can be achieved by forming an ohmic electrode with extremely low source resistance. Furthermore, such non-alloy ohmics have the advantage of being able to use heat-resistant metals such as WSi. However, when such a non-alloy ohmic is applied to the conventional example, for example, in the structure shown in FIG. 5, a current must flow from the electrode metal to the active layer through the potential barrier layer. Here, if the potential barrier is large, the parasitic resistance in the potential barrier layer becomes large, and the source resistance becomes large. For example, if the potential barrier is a non-doped AI (,3Gao, 7As layer with 200 layers), the parasitic resistance in the potential barrier layer is approximately 4X.
10-'Ωcm2, which is more than an order of magnitude larger than the case without the potential barrier layer. Furthermore, when applied to the structure shown in Fig. 6, selective regrowth of the InGaAs graded composition layer is technically difficult, and if the crystal growth conditions are not appropriate, regrowth may not be possible or the regrowth layer may not be able to be regrown. internal resistance tends to increase.

SUMMARY OF THE INVENTION An object of the present invention is to provide a hetero MIS type field effect transistor with a low source resistance and which eliminates the drawbacks of the conventional transistors.

[Means for Solving the Problems] A field effect transistor of the present invention includes a semiconductor substrate, a pair of high impurity concentration semiconductor layers formed opposite to each other on the semiconductor substrate, and a semiconductor layer formed on the pair of high impurity concentration semiconductor layers. a pair of ohmic source and drain electrodes formed;
An active layer formed on a semiconductor substrate between a pair of high impurity concentration semiconductor layers so as to cover at least a portion of the high impurity concentration semiconductor layer, and an active layer formed on the semiconductor substrate except for at least the source electrode and drain electrode forming portions. and a Schottky gate electrode formed on the potential barrier layer between a pair of high impurity concentration semiconductor layers.

[Effect]

In the hetero MIS field effect transistor of the present invention, since there is no potential barrier layer between the source/drain electrode and the active layer, the problem of increased source resistance and variation due to the presence of the potential barrier layer does not occur. do not have. Furthermore, since the source/drain electrodes are formed on the high impurity concentration semiconductor layer, the source resistance is reduced.

Furthermore, since the active layer is formed to cover the high impurity concentration semiconductor layer, it is possible to increase the contact area between the active layer and the high impurity concentration semiconductor layer, which also contributes to reducing the source resistance.

Furthermore, since the source resistance can be reduced without implanting ions into the ohmic electrode formation portion, it is possible to avoid the problem of short channel effects caused by the ion implantation region.

Furthermore, since it is possible to form the active layer and the potential barrier layer after etching the high impurity concentration semiconductor layer, the active layer and the potential barrier layer can be formed by etching the active layer and the potential barrier layer depending on the etching depth, as in the conventional example shown in FIG. - Problems such as variations in the distance to the negative electrode and variations in characteristics such as threshold voltage do not occur.

Further, in the structure of the present invention, an ohmic electrode that contacts only the high impurity concentration semiconductor layer can be used, such as a non-alloy ohmic electrode using 1nGaAs or the like as the high impurity concentration semiconductor layer. This is because there is no potential barrier layer between the active layer and the high impurity concentration semiconductor layer, and it is possible to realize a low resistance ohmic electrode using non-alloy ohmic using an InGaAs graded composition layer. Furthermore, since the InGaAs graded composition layer is grown continuously on the semiconductor substrate, there is no need for selective regrowth, which is technically difficult, as in the structure shown in FIG.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 shows an embodiment of the present invention in which a semi-insulating GaAs substrate is used as the semiconductor substrate, a high concentration n-type GaAs layer is used as the high impurity concentration semiconductor layer, and a non-doped AlGaAs potential barrier layer is formed on the n-type GaAs active layer. 1 is a cross-sectional view of a hetero field effect transistor having a structure in which .

A pair of high impurity concentration semiconductor layers (high concentration n-type GaAs
Form layer) 2. For example, the thickness is 3000, impurities (S
i) The concentration is 2X 1011018a, and the end shape is tapered. A pair of source electrode 5 and drain electrode 6 are formed on this high impurity concentration semiconductor layer 2. The electrode metal is, for example, Au (1000 people)/Ge (500 people)/
N1 (400 people), and is alloyed with the semiconductor layer by heat treatment to form an alloyed region 8. Source electrode5. Semi-insulating substrate 1 on the high impurity concentration semiconductor layer 2 in the region where the drain electrode 6 is not formed and on the gate electrode forming part
For example, 200 n-type GaAs operating layers 3 are formed on top of the n-type GaAs operating layer 3.
For example, 200 non-doped AlGaAs potential barrier layers 4 are formed on the type GaAs active layer 3.
A gate electrode [i7 is formed on the lGaAs potential barrier layer 4. The electrode metal is, for example, Ti (500)/Au.
(3000 people).

In this way, since the potential barrier layer 4 does not exist between the source electrode 5 and drain electrode 6 and the active layer 3, problems such as an increase in source resistance or an increase in variation due to the potential barrier layer do not occur. The source resistance can be reduced by the highly impurity concentration semiconductor layer (high concentration n-type GaAs layer) 2. Furthermore, the end of the high impurity concentration semiconductor layer 2 is tapered and the n-type GaAs active layer 3 can be regrown to cover the high impurity concentration semiconductor layer 2, so that the active layer 3 and the high impurity concentration semiconductor layer 2 can be It is possible to increase the contact area, which contributes to reducing source resistance.

Furthermore, since the source resistance can be reduced without implanting ions into the ohmic electrode formation portion, an ion implantation region is unnecessary, and the problem that short channel effects are likely to occur due to the ion implantation region can be avoided.

Further, after etching the high impurity concentration semiconductor layer 2,
To form the operating layer 3 and the potential barrier layer 4,
Unlike the conventional example shown in FIG. 5, the problem of variations in the distance between the active layer 3 and the gate electrode 7 due to the depth of etching, resulting in variations in characteristics such as threshold voltage, does not occur.

FIGS. 2A to 2D are cross-sectional views in the order of steps for explaining a first manufacturing method of a field effect transistor according to an embodiment of the present invention.

First, as shown in FIG. 2(a), a high impurity concentration semiconductor layer (high concentration n-type GaAs layer) 2 is provided on a semi-insulating GaAs substrate 1, and a gate electrode forming portion of the high impurity concentration semiconductor layer 2 is formed. Etch into a tapered shape. The high impurity concentration semiconductor layer 2 has a thickness of, for example, 3000 and an impurity (Si) concentration of 2X.
It is assumed to be 1018 cm-2. In addition, if the semi-insulating GaAs substrate 1 is a (100) substrate and the gate electrode is in the [011] direction, a highly impurity-concentrated semiconductor layer (highly-concentrated n-type GaAs layer)
Using brominemethanol as the etching solution in step 2 and using silicon dioxide as a mask, etching can be performed so that the (111) plane appears, and tapered etching is possible. , a source electrode 5 and a train electrode 6 are formed on the high impurity concentration semiconductor layer 2 by, for example, a vacuum evaporation method and a lift-off method. The electrode metal is, for example, Au (1000 people)/Ge (500 people)/N1 (
400 people) in a hydrogen gas atmosphere using an electric furnace.
Heat treatment is performed at 00°C for 3 minutes.

By this heat treatment, an alloyed region 8 having a depth of about 1500 mm is formed in the highly impurity concentration semiconductor layer 2, and an ohmic electrode is formed.

Next, as shown in FIG. 2(c), for example, the source electrode 5
Then, using the drain electrode 6 as a mask, the n-type GaAs active layer 3 is selectively regrown by, for example, 200 people, by molecular beam vapor deposition (hereinafter referred to as MBE method) or MOCVD, and on this n-type GaAs active layer 3. Similarly, for example, 200 non-doped AlGaAs potential barrier layers 4 are grown again. High impurity concentration semiconductor layer (high concentration n-type GaA
Since the end of the s layer 2 is etched into a tapered shape, regrowth is possible even on steps. Also, n-type GaA
By regrowing the s-operation layer 3 so as to cover the high impurity concentration semiconductor layer 2, the contact area between the two can be increased, and the parasitic resistance at the regrown interface can be reduced.

Next, as shown in FIG. 2(d), the high impurity concentration semiconductor layer 2 is removed by etching, and then the non-doped A layer is regrown.
On the lGaAs potential barrier layer 4, Ti (500 >/Au
(3000 people) etc. to form the gate electrode 7.

By the process explained above, semi-insulating G as a semiconductor substrate can be used.
A hetero field effect transistor, which is an embodiment of the present invention, has a structure in which an aAs substrate is used, a highly doped n-type GaAs layer is used as a highly impurity-concentrated semiconductor layer, and a non-doped AlGaAs potential barrier layer is formed on an n-type GaAs active layer. can be manufactured.

FIGS. 3(a) to 3(d) are cross-sectional views in order of steps for explaining a second manufacturing method of a field effect transistor according to an embodiment of the present invention.

First, as shown in FIG. 3(a), a high impurity concentration semiconductor layer (high concentration n-type GaAs layer) 2 is provided on a semi-insulating GaAs substrate 1, and a gate electrode forming portion of the high impurity concentration semiconductor layer 2 is formed. Etch into a tapered shape. The high impurity concentration semiconductor layer 2 has a thickness of, for example, 3,000 layers and an impurity (Si) concentration of 2
X 1018c+a-2. Also, semi-insulating GaA
Is the s substrate 1 a (100) substrate and the gate electrode (OL'l
) direction, the highly impurity concentration semiconductor layer (high concentration n-type Ga
Using bromine methanol as the etching solution for As layer) 2,
Using silicon dioxide as a mask, etching can be performed so that the (111) plane appears, and tapered etching is possible.

Next, as shown in FIG. 3(b), the MBE method or M
For example, 200 n-type GaAs active layers 3 are regrown on the entire surface by OCVD method or the like, and a non-doped AlGaAs potential barrier layer 4 is similarly grown on this n-type GaAs active layer 3.
For example, re-grow by 200 people. High impurity concentration semiconductor layer (
Since the end of the high concentration n-type GaAs layer 2 is etched into a tapered shape, regrowth is possible even on a step.

Next, as shown in FIG. 3(c), the non-doped AlGaAs potential barrier layer 4 and the n-type GaAs operating layer 3 in the ohmic electrode formation area are etched with phosphoric acid or the like using the photoresist film as a mask to open them. In this case, the n-type GaAs active layer 3 may remain without being etched. Next, a source electrode 5 and a drain electrode 6 are formed in the opened portion by, for example, a vacuum evaporation method and a lift-off method.

Here, the photoresist film used for etching can be used as is. The ohmic electrode is, for example, AU(1
A metal film is formed using Ge (500 people) / N1 (400 people), etc., and a source electrode 5.000 is formed by heat treatment using an electric furnace. Train electrode6. and forming an alloyed region 8 to obtain ohmic properties.

Next, as shown in FIG. 3(d), the high impurity concentration semiconductor layer 2 is removed by etching, and the non-doped A layer is regrown.
Ti (500)/Au is deposited on the lGaAs potential barrier layer 4 by, for example, a vacuum evaporation method and a lift-off method.
(3000 people) etc. to form the gate electrode 7.

By the process explained above, semi-insulating G as a semiconductor substrate can be used.
A hetero field effect transistor, which is an embodiment of the present invention, has a structure in which an aAs substrate is used, a highly doped n-type GaAs layer is used as a highly impurity-concentrated semiconductor layer, and a non-doped AlGaAs potential barrier layer is formed on an n-type GaAs active layer. can be manufactured.

In this embodiment, a hetero-type field effect transistor was described in which a highly doped n-type GaAs layer was used as the highly impurity-concentrated semiconductor layer and a non-doped AlGaAs potential barrier layer was formed on the n-type GaAs active layer. is a high concentration n-type 1nGaAs layer as a high impurity concentration semiconductor layer.
The present invention can also be applied to other field effect transistors such as a hetero field effect transistor using a monograded composition layer. Also,
It is not necessary to limit the active layer to n-type GaAs and the potential barrier layer to non-doped AlGaAs. Furthermore, the ohmic electrode may be formed of other metals such as Pd/Ge. Similarly, the gate electrode may be other metals such as WSi.

〔Effect of the invention〕

As explained above, in the field effect transistor of the present invention, there is no potential barrier layer between the source electrode and the train electrode and the active layer, so the potential barrier layer increases the source resistance and increases the variation. There are no problems.

Furthermore, the source resistance can be reduced without implanting ions into the ohmic electrode formation area, so there is no possibility of short channel effects caused by the ion implantation region causing variations in characteristics such as threshold voltage. .

In addition, in the structure of the present invention, since there is no potential barrier layer between the active layer and the high impurity S concentration semiconductor layer, a low resistance ohmic electrode using non-alloy ohmic using an InGaAs graded composition layer etc. can be realized. It is possible.

[Brief explanation of drawings]

FIG. 1 is a sectional view for explaining an embodiment of the present invention, and FIGS. 2(a) to (d) are cross-sectional views for explaining a first manufacturing method of a field effect transistor according to an embodiment of the present invention. 3(a) to 3(d) are cross-sectional views in the order of steps for explaining a second manufacturing method of a field effect transistor according to an embodiment of the present invention. FIG. 4 is a sectional view of a first conventional field effect transistor, FIG. 5 is a sectional view of a second conventional field effect transistor, and FIG. 6 is a sectional view of a third conventional field effect transistor. It is. DESCRIPTION OF SYMBOLS 1...Semi-insulating GaAs substrate, 2...High impurity concentration semiconductor layer, 3...N-type GaAs operating layer, 4...Undoped AlGaAs potential barrier layer, 5...Source electrode, 6...Drain Electrode, 7... Gate electrode, 8.
... Alloying region, 9... Ion implantation region.

Claims (1)

[Claims] a semiconductor substrate, a pair of high impurity concentration semiconductor layers formed opposite to each other on the semiconductor substrate, a pair of ohmic source and drain electrodes formed on the pair of high impurity concentration semiconductor layers; an active layer formed on the semiconductor substrate between the pair of high impurity concentration semiconductor layers so as to cover at least a portion of the high impurity concentration semiconductor layer; A field effect transistor comprising: a potential barrier layer formed on the active layer; and a Schottky gate electrode formed on the potential barrier layer between the pair of high impurity concentration semiconductor layers. .