JP4578777B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a capacitor and a manufacturing method thereof.
[0002]
[Prior art]
Flash memories and ferroelectric memories (FeRAM) are known as nonvolatile memories that can store information even when the power is turned off.
[0003]
A flash memory has a floating gate embedded in a gate insulating film of an insulated gate field effect transistor (IGFET), and stores information by accumulating charges as stored information in the floating gate. For writing and erasing information, it is necessary to pass a tunnel current through the gate insulating film, which requires a relatively high voltage.
[0004]
The FeRAM has a ferroelectric capacitor that stores information using the hysteresis characteristics of the ferroelectric. In a ferroelectric capacitor, the ferroelectric film formed between the upper electrode and the lower electrode generates polarization according to the voltage value applied between the upper electrode and the lower electrode, and maintains the polarization even when the applied voltage is removed. Have spontaneous polarization. If the polarity of the applied voltage is reversed, the polarity of the spontaneous polarization is also reversed. Information can be read by detecting the polarity and magnitude of this spontaneous polarization.
[0005]
FeRAM has an advantage that it operates at a lower voltage than a flash memory and can perform high-speed writing with power saving.
[0006]
An FeRAM ferroelectric capacitor has a ferroelectric film such as a PZT-based material or a bismuth layer structure compound. The ferroelectric film is formed into an amorphous phase on the lower electrode film by a sputtering method, an MOCVD method, a sol-gel method or the like, and then crystallized into a perovskite structure by a heat treatment.
[0007]
Since heat is also applied to the lower electrode film during the heat treatment for crystallizing the ferroelectric film, the stress of the lower electrode film changes due to thermal expansion. For example, a platinum film formed at a low temperature as a lower electrode film has a compressive stress, but changes to a tensile stress by a heat treatment for crystallizing the ferroelectric film formed thereon. When the amount of change is large, the lower electrode film is easily peeled off from the base film.
[0008]
On the other hand, Patent Document 1 below describes that the lower electrode film is made to have a tensile stress at the time of film formation. In Patent Document 1, an adhesion layer made of a metal oxide is formed on an insulating film, and a platinum film is sputtered on the adhesion layer as a lower electrode film at a substrate temperature of 200 to 600 ° C. 2 × 10⁹dyne / cm²It is described that the tensile stress is as described above.
[0009]
Also, platinum film is used as the lower electrode film._xJapanese Patent Application Laid-Open No. 2004-260688 describes that the stress on the ferroelectric capacitor stack is reduced on the adhesive layer at 300 to 800 ° C. and the thermal stability thereof is increased.
[0010]
Furthermore, although the stress is not controlled, the orientation of the ferroelectric film formed on the lower electrode film is made random by forming an iridium film as a lower electrode film at a relatively high temperature of 450 to 600 ° C. Patent Document 3 below describes increasing the polarization inversion charge amount of a ferroelectric capacitor.
[0011]
[Patent Document 1]
JP-A-9-246082 (paragraph number 0014)
[Patent Document 2]
JP 2001-313376 A (paragraph number 0005)
[Patent Document 3]
JP 2002-57298 A (paragraph number 0037)
[0012]
[Problems to be solved by the invention]
However, if the growth temperature of the single layer film of platinum or iridium constituting the lower electrode is only controlled, the lower electrode is easily peeled off when the ferroelectric film on the lower electrode is heat-treated for crystallization. For example, the stress of a platinum film formed at low temperature is compressive stress, and the underlying TiO_xSince the layer is almost tensile stress, platinum film and TiO_xThe stress direction is opposite to that of the layer, the adhesion is deteriorated, and the film peeling of the lower electrode is likely to occur. Further, when the platinum film is formed at a high substrate temperature, the leakage current of the capacitor tends to increase. Further, when the platinum film is formed at a high temperature, a defect is likely to occur in the connection between the platinum film and the lead-out wiring.
[0013]
Therefore, in order to form a lower electrode having a multilayer structure, it is not sufficient to control the temperature of the single-layer film of platinum or iridium as the main conductor film, and it is necessary to consider conditions other than the temperature. Therefore, it is necessary to optimize the lower electrode film having a multilayer structure from a new viewpoint.
[0014]
An object of the present invention is to provide a semiconductor device capable of preventing a capacitor formed on an insulating film from peeling off and reducing a leakage current as compared with the conventional semiconductor device and a method for manufacturing the same.
[0015]
[Means for Solving the Problems]
  According to one aspect of the present invention,Forming an insulating film above the semiconductor substrate; (a) forming an iridium film on the insulating film at a substrate temperature of 450 to 550 ° C .; and (b) forming an iridium oxide film on the iridium film. (C) forming a first platinum film on the iridium oxide film; (d) forming a platinum oxide film on the first platinum film; and (e). A step of forming a second platinum film on the platinum oxide film is performed, and the iridium film, the iridium oxide film, the first platinum film, and the platinum oxide are formed by the steps (a) to (e). Forming a first conductive film having a multilayer structure comprising a film and the second platinum film; forming a dielectric film on the first conductive film; and forming a first conductive film on the dielectric film. Forming a second conductive film, and patterning the second conductive film to Forming a dielectric upper electrode; patterning the dielectric film to form a capacitor dielectric film under the capacitor upper electrode; and patterning the first conductive film to pattern the capacitor dielectric film. Forming a capacitor lower electrode underneath, immediately after the step of forming the first conductive film, the first conductive film is -2 × 10 ⁹ ~ 5x10 ⁹ dyne / cm ² Semiconductor device manufacturing method characterized by having a stress ofIs provided.
[0017]
According to the present invention, when a lower electrode having a laminated structure of two or more layers is formed, the lower electrode is made as a whole at −2 × 10.⁹~ 5x10⁹dyne / cm²It is controlled so as to be a stress.
[0018]
According to the lower electrode formed by such stress, it is difficult to cause film peeling of the capacitor composed of the lower electrode, the dielectric film, and the upper electrode, and it is clear from experiments that the leakage current density of the capacitor is reduced. Became.
[0019]
In order to form the first conductive film having such a stress, a platinum film constituting a laminated structure is formed by −3.3 × 10.⁹dyne / cm²2 × 10⁹dyne / cm²It is preferable to form with lower stress. Further, an iridium film constituting the laminated structure is 1.1 × 10⁹~ 12.3x10⁹dyne / cm²It is preferable to form with the stress of.
[0020]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
(First embodiment)
1 to 5 are first cross-sectional views showing the steps of forming a semiconductor memory device according to the first embodiment of the present invention. 6 and 7 are second cross-sectional views illustrating the steps of forming the semiconductor memory device according to the first embodiment of the present invention.
[0021]
First, steps required until a sectional structure shown in FIG.
[0022]
In FIG. 1A, an element isolation insulating film 2 is formed on the surface of a silicon (semiconductor) substrate 1 by a LOCOS (Local Oxidation of Silicon) method. The element isolation insulating film 2 may adopt an STI (Shallow Trentch Isolation) structure. The silicon substrate 1 is a 6-inch wafer in this embodiment and the following embodiments.
[0023]
Subsequently, by introducing p-type impurities into a predetermined active region (transistor forming region) surrounded by the element isolation insulating film 2 in the memory cell region of the silicon substrate 1, a plurality of p wells 3a are formed in the active region. To do.
[0024]
Thereafter, the surface of the silicon substrate 1 is thermally oxidized to form a silicon oxide film used as the gate insulating film 4 on the p well 3a.
[0025]
Next, an amorphous silicon film and a tungsten silicide film are sequentially formed on the element isolation insulating film 2 and the gate insulating film 4. Then, the amorphous silicon film and the tungsten silicide film are patterned into a predetermined shape by photolithography to form gate electrodes 5a and 5b above the p well 3a. A polysilicon film may be formed in place of the amorphous silicon film constituting the gate electrodes 5a and 5b.
[0026]
Above the p-well 3a, two gate electrodes 5a and 5b are formed at a substantially parallel interval, and these gate electrodes 5a and 5b extend on the element isolation insulating film 2 and become word lines WL. .
[0027]
Next, n-type impurities are ion-implanted into both sides of the gate electrodes 5a and 5b in the p-well 3a in the memory cell region, and the n-channel MOS transistor T₁, T₂First to third n-type impurity diffusion regions 7a, 7b, 7c to be source / drains are formed.
[0028]
Thereafter, an insulating film is formed on the silicon substrate 1, the element isolation insulating film 2, and the gate electrodes 5a and 5b. Then, by etching back the insulating film, the sidewall insulating film 6 is left on both sides of the gate electrodes 5a and 5b. As the insulating film, for example, silicon oxide (SiO 2) formed by a CVD method.₂).
[0029]
Further, n-type impurity diffusion regions 7a-7c are LDD-implanted by ion-implanting n-type impurities into n-type impurity diffusion regions 7a-7c using gate electrodes 5a, 5b and sidewall insulating film 6 on p well 3a as a mask. Make the structure.
[0030]
Thus, the first nMOS transistor T having the first and second n-type impurity diffusion regions 7a and 7b and the gate electrode 5a is formed.₁And the second nMOS transistor T having the second and third n-type impurity diffusion regions 7b and 7c and the gate electrode 5b.₂The formation of is finished.
[0031]
After this, the nMOS transistor T₁, T₂An insulating cover film 10 is formed on the silicon substrate 1 by plasma CVD. For example, a silicon oxynitride (SiON) film having a thickness of about 200 nm is formed as the cover film 10.
[0032]
Next, silicon oxide (SiO 2) is formed by plasma CVD using TEOS gas.₂) A film is grown to a thickness of about 1.0 μm, and this silicon oxide film is used as the first interlayer insulating film 11.
[0033]
Subsequently, as a densification process of the first interlayer insulating film 11, the first interlayer insulating film 11 is heat-treated at a temperature of 700 ° C. for 30 minutes in a normal-pressure nitrogen atmosphere. After that, the upper surface of the first interlayer insulating film 11 is polished and planarized by a chemical mechanical polishing (CMP) method. Here, since the cover film 10 functions as a CMP stopper film, a part of the cover film 10 is exposed above, for example, the word line WL on the element isolation insulating film 2.
[0034]
Next, by patterning the first interlayer insulating film 11 by photolithography, the first to third contact holes 11a to 11c are formed on the first to third n-type impurity diffusion regions 7a to 7c, respectively. Form.
[0035]
Thereafter, a titanium (Ti) film having a thickness of 20 nm and a TiN (titanium nitride) film having a thickness of 50 nm are sputtered as a glue film on the upper surface of the first interlayer insulating film 11 and the inner surfaces of the first to third contact holes 11a to 11c. It forms in order by the method. Further, a tungsten (W) film having a thickness for completely filling the first to third contact holes 11a to 11c is grown on the glue film by the CVD method.
[0036]
Subsequently, the tungsten film and the glue film are polished by the CMP method and removed from the upper surface of the first interlayer insulating film 11. Thereby, the tungsten film and the glue film left in the first to third holes 11a to 11c are referred to as first to third conductive plugs 12a to 12c, respectively.
[0037]
Above the p-well 3a, the second conductive plug 12b on the second n-type impurity diffusion region 7b sandwiched between the two gate electrodes 5a and 5b is electrically connected to a bit line to be described later. The first and third conductive plugs 12a and 12c on both sides are electrically connected to the upper electrode of the capacitor described later.
[0038]
Next, a SiON film having a thickness of about 100 nm and a SiON film having a thickness of about 130 nm are formed as a base insulating film 13 on the first interlayer insulating film 11 and the conductive plugs 12a to 12c.₂Films are sequentially formed by a CVD method. The SiON film is formed to prevent oxidation of the conductive plugs 12a to 12c.₂The film is formed in order to suppress deterioration of crystallinity of the lower electrode of the capacitor, which will be described later. Note that SiO constituting the base insulating film 13₂The film is formed using TEOS as a source gas.
[0039]
Subsequently, the base insulating film 13 and the first interlayer insulating film 11 are degassed in a nitrogen atmosphere at 650 ° C. for 30 minutes.
[0040]
Next, as shown in FIG. 1B, a titanium (Ti) film 14 x and a platinum (Pt) film 14 y are sequentially formed as the first conductive film 14 on the first interlayer insulating film 11. The Ti film 14x and the Pt film 14y are formed by DC sputtering in succession in two chambers without being exposed to the atmosphere. The Ti film 14x is formed, for example, at a film forming temperature of 20 ° C. and a thickness of about 20 nm. The Pt film 14y is formed, for example, at a film forming temperature of 150 to 250 ° C. and a thickness of 175 nm. According to such film formation conditions, the single stress of the Pt film 14y is −3.24 × 10 6.⁹~ 1.55 × 10⁹dyne / cm²The overall stress of the first conductive film 14 is −3.19 × 10.⁹~ 1.26 × 10⁹dyne / cm²It becomes.
[0041]
In addition, the minus (−) of the stress value is a compressive stress, and the plus of the stress value is a tensile stress.
[0042]
Thereafter, as shown in FIG. 2 (a), the ferroelectric film 15 has a thickness of 100 to 300 nm of PLZT ((Pb, La) (Zr, Ti) O)._Three) A film is formed on the first conductive film 14 by RF sputtering. In this case, the PLZT film has a compressive stress.
[0043]
The formation method of the ferroelectric layer 15 includes a MOD method, an MOCVD method, a sol-gel method, and the like in addition to the sputtering method. The material of the ferroelectric layer 15 is not limited to PLZT but PZT (Pb (Zr, Ti) O_Three), Or other PZT materials such as PZT doped with Ca, etc., or SrBi₂Ta₂O₉(SBT, Y1), SrBi₂(Ta, Nb)₂O₉Bi layered structure compounds such as (SBTN, YZ), (Sr, Ti) O_Three, (Ba, Sr) TiO_ThreeOther metal oxide ferroelectrics may be employed.
[0044]
Subsequently, as a crystallization process for the PLZT film constituting the ferroelectric film 15, argon (Ar) and oxygen (O₂) Is performed at a temperature of 600 ° C. or higher, for example, at 650 to 850 ° C. for 30 to 120 seconds, and rapid thermal annealing (RTA) is performed. During the crystallization, the Pt film 14b constituting the first conductive film 14 is densified, and platinum atoms and oxygen at the boundary surface between the first conductive film 14 and the PLZT ferroelectric film 14 and in the vicinity thereof. Interdiffusion of atoms is suppressed. Further, it is desirable that the first conductive film 14 and the ferroelectric 15 are all changed to tensile stress by the RTA treatment, and the change in the warpage amount of the silicon substrate 1 which is a wafer is small.
[0045]
Further, as shown in FIG. 2B, iridium oxide (IrO) is formed on the ferroelectric film 15 as a second conductive film 16.₂) A film is formed by sputtering to a thickness of 100 to 300 nm, for example 200 nm. Note that platinum, ruthenium strontium oxide, or the like may be used for the second conductive film 16.
[0046]
6A is a cross-sectional view of the capacitor formation region and its periphery in this state as seen from the line II in FIG. 2B. 6 and 7 show cross-sectional views of the same part.
[0047]
Next, steps required until a structure shown in FIG.
[0048]
First, by patterning the second conductive film 16, a plurality of capacitor upper electrodes 16a are formed at intervals above the element isolation insulating film 2 in the memory cell region. The upper electrode 16a is a MOS transistor T₁T₂Are formed at intervals in the extending direction of the word lines WL. Thereafter, in order to recover the film quality of the ferroelectric film 15 damaged by etching, annealing is performed in an oxygen atmosphere at a duty number temperature of 650 ° C. for 60 minutes.
[0049]
Subsequently, the ferroelectric film 15 is patterned to form a stripe-shaped capacitor dielectric film 15a along the word line WL extending direction under the plurality of upper electrodes 16a.
[0050]
After that, the first capacitor protective insulating film 17 on the upper electrode 16a, the dielectric film 15a and the first conductive film 14 is made of alumina (Al₂O_Three) A film is formed by sputtering to a thickness of about 50 nm. PZT or the like may be used instead of alumina.
[0051]
Subsequently, in order to recover the film quality of the dielectric film 15a from damage caused by sputtering, the dielectric film 15a is annealed, for example, in an oxygen atmosphere at a substrate temperature of 700 ° C. for 1 minute.
[0052]
Next, as shown in FIGS. 3A and 6B, the first conductive film 14 is etched using a resist pattern (not shown) to form stripes under the dielectric film 15a. An extended capacitor lower electrode 14a is formed. Thereby, in the memory cell region, the capacitor Q having the lower electrode 14a, the dielectric film 15a, and the upper electrode 16a is formed. A plurality of capacitors Q are formed with the upper electrode 16a as a unit.
[0053]
The capacitor protection insulating film 17 is patterned in the same planar shape as the lower electrode 14a.
[0054]
Thereafter, as shown in FIGS. 3B and 6C, a silicon oxide film is formed on the capacitor Q, the capacitor protection insulating film 17 and the base insulating film 13 by a CVD method using a source gas containing TEOS. The film is formed to a thickness of about 1 μm, and this film is used as the second interlayer insulating film 18. The second interlayer insulating film 18 has a compressive stress.
[0055]
Subsequently, the upper surface of the second interlayer insulating film 18 is planarized by CMP, and the remaining film thickness of the second interlayer insulating film 18 after CMP is set to about 300 nm on the capacitor Q.
[0056]
Thereafter, as shown in FIG. 4 (a), the second interlayer insulating film 18 and the base insulating film 13 are etched using a resist pattern (not shown) to form first to third conductive plugs 12a to 12c. The fourth to sixth contact holes 18a to 18c are formed on the top of the substrate, respectively.
[0057]
Next, as shown in FIG. 4B, a TiN film of about 50 nm is formed in the fourth to sixth contact holes 18a to 18c and on the second interlayer insulating film 18, and the fourth to sixth After a W film having a thickness that completely fills the contact holes 18a to 18c is formed on the TiN film, the W film and the TiN film are removed from the second interlayer insulating film 18 by CMP. Thus, the W film and the TiN film remaining in the fourth to sixth contact holes 18a to 18c are used as the fourth to sixth conductive plugs 19a to 19c.
[0058]
Thereafter, as shown in FIGS. 5A and 7A, a SiON film is formed as an antioxidant film 20 on the fourth to sixth conductive plugs 19a to 19c and the second interlayer insulating film 18. Is formed by a CVD method, and then a portion of each of the capacitors Q is etched by etching a part of the antioxidant film 20, the second interlayer insulating film 18 and the capacitor protection insulating film 17 using a resist pattern (not shown). Upper electrode contact holes 18d and 18e are formed on the upper electrode 16a. At the same time, as shown in FIG. 7A, a lower electrode contact hole 18f is formed on the contact region at the end of the lower electrode 14a where the capacitor Q is not formed.
[0059]
Subsequently, the capacitor Q is annealed in an oxygen atmosphere through the upper electrode contact holes 18d and 18e, thereby recovering the capacitor characteristics from the damage caused by the etching. As annealing conditions, for example, the substrate temperature is 550 ° C. and the time is 60 minutes. After such annealing, the antioxidant film 20 is removed by etching back.
[0060]
Next, steps required until the structure shown in FIGS. 5B and 7B is formed will be described.
[0061]
First, a TiN film having a thickness of 20 to 50 nm and an Al-Cu film having a thickness of about 400 nm are formed on the fourth to sixth conductive plugs 19a to 19c, the second interlayer insulating film 18 and the contact holes 18d to 18f. Are formed in order.
[0062]
Then, by patterning the TiN film and the Al—Cu film, the first region extending from the fourth conductive plug 19a into the contact hole 18d on one capacitor Q above the p-well region 3a in the memory cell region. A wiring 21a, a second wiring 21c extending from the sixth conductive plug 19c into the contact hole 18e on the other capacitor Q, and an island-shaped conductive pad 21b on the fifth conductive plug 19b Form. Further, a third wiring 21d that is drawn out from the contact hole 18f on the contact region of the lower electrode 14a is formed.
[0063]
Thereafter, although not shown, a third interlayer insulating film is formed on the first to third wirings 21a, 21c, 21d, the conductive pad 21b, and the second interlayer insulating film 18, and further connected to the conductive pad 21b. A process such as forming a conductive plug to be formed in the third interlayer insulating film and forming a bit line electrically connected to the conductive pad 21b on the third interlayer insulating film is performed. Omitted.
[0064]
In the above-described embodiment, when the leakage current, the orientation, the switching charge amount, and the like of the Ti film 14x and the Pt film 14y constituting the first conductive film 14 serving as the lower electrode 14a were tested, the following results were obtained. It was.
[0065]
First, as described above, a Pt film 14y with a thickness of 175 nm is formed on a Ti film 14x with a thickness of 20 nm formed at a substrate temperature of 20 ° C. at 20 ° C., 50 ° C., 100 ° C., 150 ° C., 200 ° C., 250 A plurality of samples grown at different temperatures and growth temperatures were prepared, and the dependency relationship between the (222) plane orientation integrated strength and the film formation temperature was examined for each of the Pt films 14y of these samples, as shown in FIG. Results were obtained. In the figure, BEL is an abbreviation for bottom electrode, and the same applies to the following embodiments. Further, the integrated integral intensity is measured by X-ray diffraction analysis in this embodiment and the following embodiments.
[0066]
According to FIG. 8, it can be seen that the (222) orientation integral intensity of the Pt film 14y on the Ti film 14x monotonously increases as the film formation temperature increases.
[0067]
Further, as shown in the table of FIG. 9, both the Pt film 14y and the Ti film 14x formed at room temperature (for example, 20 ° C.) or more and 200 ° C. or less are compressive stress, but Pt formed at 250 ° C. or more. The film 14y becomes a tensile stress, and the stress of the entire first conductive film 14 formed of the laminated structure of the Ti film 14x and the Pt film 14y becomes a tensile stress. The strength of the tensile stress of the entire film 14 is also increased.
[0068]
Further, when the relationship between the switching charge amount Qsw of the capacitor Q formed on the wafer (silicon substrate 1) and the film formation temperature of the Pt film 14y was examined, the result shown in FIG. 10 was obtained. In FIG. 10, a voltage of 3V is applied between the lower electrode 14a and the upper electrode 16a of each capacitor Q, and Qsw for the capacitor Q at 71 points for each of the plurality of silicon substrates 1 having different Pt deposition temperatures. And the average value, maximum value, and minimum value of them were examined.
[0069]
According to FIGS. 10 and 8, the (222) orientation integral strength of the Pt film 14y in the first conductive film 14 constituting the lower electrode 14a depends on the deposition temperature of the Pt film 14y. Qsw is less dependent on the growth temperature of the Pt film 14y, and the in-plane Qsw is 28.9-31.6 μC / cm.²It is.
[0070]
Further, for each of these 71-point capacitors Q, the relationship between the leakage current density and the growth temperature of the Pt film 14y was examined, and the results shown in FIGS. 11 (a) and 11 (b) were obtained. FIG. 11A shows the case where the voltage applied to the capacitor Q is 6V, and FIG. 11B shows the case where the applied voltage is inverted to −6V.
[0071]
According to FIG. 11, when the deposition temperature of the Pt film 14y is low, the leakage current density is high. This is presumably because the Pt film 14y formed at a low temperature has low density and Pb, Pt, and Ti are interdiffused with the film above and below the Pt film 14y. When the growth temperature of the Pt film 14y is set to 150 ° C. or higher, the denseness increases and the leakage current density can be suppressed.
[0072]
According to the above experimental results, the first conductive film is formed by setting the substrate temperature during the growth of the Pt film 14y in the multi-layered first conductive film 14 constituting the lower electrode 14a to 150 to 250 ° C. The stress of the entire film 14 was minimized, the (222) orientation strength of the Pt film 14y was increased, and the leakage current density of the capacitor Q was further reduced. Further, according to such a film formation temperature, as shown in the table of FIG. 9, the single stress of the Pt film 14y is −3.24 × 10.⁹~ 1.55 × 10⁹dyne / cm²The overall stress of the first conductive film 14 is −3.19 × 10.⁹~ 1.26 × 10⁹dyne / cm²It becomes.
[0073]
By the way, when the Pt film 14y is formed at a temperature of 350 ° C. or higher, the aluminum film and the lower electrode 14a constituting the wiring 21d are formed at the connection portion between the lower electrode 14a and the wiring 21d shown in FIG. As shown in FIG. 12A, the Pt film 14y to be subjected to the eutectic reaction tends to cause the eutectic 29. The eutectic 29 resulting from such a eutectic reaction causes poor connection between the wiring 21d and the lower electrode 14a. On the other hand, when the Pt film 14y is formed at a temperature lower than 350 ° C., as shown in FIG. 12B, the connection between the lower electrode 14a and the wiring 21d is improved, so that the Pt film 14y is at least 350 ° C. In this case, the stress of the laminated structure of the Ti film 14x and the Pt film 14y is 5 × 10⁹dyne / cm²It is as follows.
[0074]
Note that an alloy containing at least Ti, for example, PtTi, IrTi, or RuTi may be formed instead of the Ti film 14x formed on the first interlayer insulating film 11 in the first conductive film 14 described above. Alternatively, Ir may be used, or an alloy containing at least Ir, such as PtIr, IrTi, or RuIr, may be used. These films function as an adhesion layer between the first conductive film 14 and the first interlayer insulating film 11 and a barrier layer of the first conductive film 14.
[0075]
Furthermore, instead of the Pt film 14y of the first conductive film 14, other noble metal or noble metal oxide, two or more alloys of noble metals or two or more alloys of noble metal oxides may be used. Examples of noble metals include Ir, Ru, and Pd in addition to Pt, and noble metal oxides include PtO._x, IrO_x, RuO_x, PdO_xThere is. The film constituting the first conductive film 14 may have a laminated structure including two or more of such noble metals, noble metal oxides, noble metal alloys, and noble metal oxide alloys.
(Second Embodiment)
In the first embodiment, the Pt film 14y is continuously formed on the Ti film 14x after the Ti film 14x constituting the lower electrode 14a is formed. However, in the present embodiment, after the Ti film 14x is oxidized. A structure for forming the Pt film 14y will be described.
[0076]
13-15 is sectional drawing which shows the manufacturing process of the semiconductor device based on 2nd Embodiment of this invention. 13 to 15, the same reference numerals as those in FIGS. 1 to 5 indicate the same elements.
[0077]
First, steps required until a structure shown in FIG.
[0078]
In FIG. 13A, the MOS transistor T is formed on the silicon substrate 1 by the same process as shown in the first embodiment.₁, T₂Forming a MOS transistor T₁, T₂A cover film 10 and a first interlayer insulating film 11 are formed in order, and the first interlayer insulating film 11 is planarized by CMP. Further, a base insulating film 13 is formed on the first interlayer insulating film 11 as in the first embodiment. A Ti film 14x is formed on the first interlayer insulating film 11 by DC sputtering to a thickness of 20 nm at room temperature (about 20 ° C.).
[0079]
Thereafter, as shown in FIG. 13 (b), the Ti film 14x is oxidized by RTA at a substrate temperature of 700 ° C. in an atmosphere containing oxygen and argon, thereby obtaining TiO 2._xA film 14z is formed.
[0080]
Subsequently, as shown in FIG._xA Pt film 14y having a thickness of 150 nm is formed on the film 14z at a film forming temperature of 200 to 300 ° C. by DC sputtering.
[0081]
Next, steps required until a structure shown in FIG.
[0082]
First, a ferroelectric film 15, for example, a PLZT film, is formed on the Pt film 14y under the same conditions as shown in the first embodiment, and the ferroelectric film 15 is made of Ar and O.₂A heat treatment at 600 ° C. is performed by an RTA method in an atmosphere having By crystallizing the ferroelectric film 15, the Pt film 14 y is densified, and interdiffusion of Pt and O 2 in the vicinity of the interface between the Pt film 14 y and the PLZT ferroelectric film 15 is suppressed. . By the heat treatment, TiO_xThe film 14z, the Pt film 14y, and the ferroelectric film 15 are all preferably changed into tensile stress, and it is desirable that the change in the amount of warpage of the wafer at this time is small.
[0083]
Subsequently, after forming a second conductive film 16 (for example, an iridium oxide film) on the ferroelectric film 15, annealing is performed in an oxygen-containing atmosphere under the same conditions as in the first embodiment.
[0084]
Next, as shown in FIG. 15A, by patterning the second conductive film 16 to form the upper electrode 16a and patterning the ferroelectric film 15 by the process shown in the first embodiment. After forming the film 15a, the capacitor protection insulating film 17 is formed, and further, the capacitor protection film 17, the Pt film 14y, and TiO_xThe film 14z is patterned to form the lower electrode 14b. The lower electrode 14b is made of a Pt film 14y and TiO._xIt is comprised from the film | membrane 14z.
[0085]
Thereby, a capacitor Q composed of the upper electrode 16a, the dielectric film 15a, and the lower electrode 14b is formed.
[0086]
Thereafter, as shown in FIG. 15B, the second interlayer insulating film 18 is formed by the same process as in the first embodiment, the conductive plugs 19a to 19c are formed, and the wirings 21a, 21c, 21d and Conductive pad 21b is formed. After that, as in the first embodiment, a third interlayer insulating film and the like are formed, but details are omitted.
[0087]
In the above process, an experiment was conducted on how the amount of warpage and stress of the wafer change depending on the difference in the deposition temperature of the Pt film 14y constituting the lower electrode 14b.
[0088]
FIG. 16 shows a change in the amount of warpage of the wafer due to the difference in the deposition temperature of the Pt film 14y constituting the lower electrode 14b, and FIG. 17 shows the film due to the difference in the deposition temperature of the Pt film 14y constituting the lower electrode 14b. Shows the difference in stress.
[0089]
In FIG. 16, “SiO₂As shown in FIG. 2, the second interlayer insulating film 11 is SiO₂After measuring the warping amount of the silicon substrate 1 based on the film, “TiO_xAs shown in FIG._xThe film 14z is formed and the amount of warpage is measured, and the Pt film 14y is made of TiO as shown in “BEL-PT”._xFormed on the film 14z and measured the amount of warpage, and as shown in "FER-PZT", a PLZT film as a ferroelectric film 15 was formed on the Pt film 14y and measured the amount of warpage. As shown in “FER-ANI”, the ferroelectric film 15 was crystallized and annealed, and the amount of warpage was measured. It should be noted that the temperature at which the Pt film 14y is formed is measured for a plurality of samples in which the temperature is changed to 100 ° C, 150 ° C, 200 ° C, 250 ° C, 300 ° C, and 350 ° C. The magnitude of stress in FIG. 17 is measured together with the amount of warpage.
[0090]
According to FIGS. 16 and 17, the warpage amount and stress of the wafer before the Pt film 14y is formed are almost the same value. Also, TiO formed by oxidizing Ti film 14x with compressive stress_xThe stress of the film 14z changes in the direction of tensile stress, and its strength is large. Further, when the growth temperature of the Pt film 14y is 100 ° C. and 150 ° C., the stress of the Pt film 14y is in the direction of compressive stress, and when the growth temperature is 200 ° C. or higher, the stress is in the direction of tensile stress. In addition, when the PLZT film, which is the ferroelectric film 15, is formed on the Pt film 14y, the whole changes in the direction of compressive stress, and then the PLZT film is replaced with Ar and O.₂When heated at 600 ° C. in this atmosphere, it changes in the direction of tensile stress.
[0091]
By the way, if the stress (stress) changes drastically every time the film is formed, the film is easily peeled off. Accordingly, in FIGS. 16 and 17, it is desirable that the amount of warpage of the wafer and the amount of change in film stress be small, so that the film forming temperature of the Pt film 14y is preferably 200 to 300 ° C.
[0092]
When the Pt film 14y is formed by sputtering, the stress can be made closer to 0 by increasing the flow rate of Ar introduced into the chamber. For example, it is preferable that the Ar flow rate in sputtering is 116 sccm and the pressure is 3 mTorr.
[0093]
Next, when the relationship between the switching charge amount Qsw of the capacitor Q and the film formation temperature of the Pt film 14y was examined, the result shown in FIG. 18 was obtained.
[0094]
According to FIG. 18, the dependence of the Pt film forming temperature on Qsw is not so much, but when the Pt film 14y is formed at 200 to 300 ° C., the in-plane distribution of Qsw is slightly improved. The range of Qsw is 29.2 to 32.0 μC / cm²It is. In order to obtain the data shown in FIG. 18, Qsw is examined for each of a plurality of capacitors Q on a plurality of wafers having different Pt film forming temperatures. A square in FIG. 18 indicates a region having the highest Qsw, and a horizontal line in the square indicates a peak.
[0095]
Further, as to the fatigue characteristics (fatigue) of the PLZT ferroelectric film 15 constituting the plurality of capacitors Q formed on the wafer, it was examined what kind of difference appears due to the difference in the deposition temperature of the Pt film 14y. The result as shown in FIG. 19 was obtained.
[0096]
FIG. 19 shows that the ferroelectric film 15 is inverted in polarization at 7 V, and 2.88 × 10.⁷The fat loss after cycling is shown. Writing and reading after polarization inversion were performed at 3V.
[0097]
According to FIG. 19, there was no fatigue loss of the capacitor when the deposition temperature of the Pt film 14y was set in the range of 200 to 300 ° C.
[0098]
Next, an experimental result about how the film formation temperature of the Pt film 14y affects the capacitor leakage current density will be described.
[0099]
First, a plurality of capacitors Q were formed on a plurality of silicon wafers in accordance with the above-described steps while varying the deposition temperature of the Pt film 14y. Then, the leakage current density of 71 points of capacitors Q on each wafer was examined. Then, when the cumulative probability of the leakage current density of the capacitor Q was examined for each difference in the deposition temperature of the Pt film 14y, the results shown in FIGS. 20 (a) and 20 (b) were obtained. 20A and 20B show the difference between the case where 6V is applied to the capacitor Q and the case where -6V is applied.
[0100]
According to FIGS. 20A and 20B, the leakage current density of the capacitor Q is hardly changed at the film forming temperature of 100 to 300 ° C. of the Pt film 14y. Internal distribution occurs and is slightly worse.
[0101]
Next, the capacitor Q on the sample whose leakage current density was investigated was tested to determine whether film peeling occurred using an adhesive tape. As shown in the table of FIG. 21, the Pt film 14y was 100 ° C. Pt film 14y and TiO_xSome films peeled off at the interface of the film 14z. Therefore, in order to prevent the capacitor Q from peeling off, the film forming temperature of the Pt film 14y may be set to 150 ° C. or higher.
[0102]
FIG. 21 shows the amount of warpage of the wafer, the amount of warpage change, the leakage current density, the film stress, the film peeling condition, and the capacitor leakage current in each process due to the difference in the deposition temperature of the Pt film 14y, in addition to the film peeling. . The warpage change amount indicates a difference in warpage amount before and after film formation.
[0103]
16 to 21, it can be seen that by setting the deposition temperature of the Pt film 14y to 150 ° C. to 300 ° C., the amount of stress change in the capacitor Q is reduced and the adhesion of the entire film is improved. It was. In this case, TiO_xThe stress of the entire lower electrode 14b composed of the laminated structure of the film 14x and the Pt film 14y is −7.2 × 10⁹~ 4.6 × 10⁹dyne / cm²It became. Further, in order to reduce the leakage current density and prevent film peeling, the stress of the Pt film 14y constituting the lower electrode 14b is −3.3 × 10.⁹2 × 10⁹dyne / cm²It is preferable to make it lower. This range of Pt stress produces the effect of reducing the leakage current even in the lower electrode 14a of the first embodiment.
[0104]
Note that 5.0 × 10 5 when the deposition temperature of the Pt film 14 y is 150 ° C. or higher and lower than 350 ° C.⁹dyne / cm²No film peeling occurred on the lower electrode 14b.
[0105]
In addition, TiO formed on the first interlayer insulating film 11 in the first conductive film 14 described above._xInstead of the film 14z, a nitride of Ti, an oxide or nitride of an alloy containing at least Ti, or an oxide of Ir may be used. As an oxide or nitride of an alloy containing Ti, for example, there is an oxide film or nitride of PtTi, IrTi, or RuTi.
[0106]
TiO_xInstead of the film 14z, an oxide of Ir, or an oxide of an alloy containing at least Ir, or Ir may be used, or an oxide of an alloy containing at least Ir, for example, An oxide of PtIr, IrTi, or RuIr may be used. These films function as an adhesion layer between the first conductive film 14 and the first interlayer insulating film 11 and a barrier layer of the first conductive film 14.
[0107]
Furthermore, instead of the Pt film 14y of the first conductive film 14, other noble metal or noble metal oxide, two or more alloys of noble metals or two or more alloys of noble metal oxides may be used. Examples of noble metals include Ir, Ru, and Pd in addition to Pt, and noble metal oxides include PtO._x, IrO_x, RuO_x, PdO_xThere is. The film constituting the first conductive film 14 may have a laminated structure including two or more of such noble metals, noble metal oxides, noble metal alloys, and noble metal oxide alloys.
(Third embodiment)
In the first and second embodiments described above, the planar capacitor having a structure in which it is electrically drawn from the upper surface of the lower electrode has been described. In the present embodiment, a stack type capacitor having a structure of being electrically drawn out from the lower surface of the lower electrode through a conductive plug will be described.
[0108]
22 to 26 are cross-sectional views illustrating the steps of forming the semiconductor device according to the embodiment of the present invention.
[0109]
First, steps required until a structure shown in FIG.
[0110]
As shown in FIG. 22A, after element isolation grooves are formed around the transistor formation region of the silicon (semiconductor) substrate 40 by photolithography, silicon oxide (SiO 2) is formed in the element isolation grooves.₂) Are embedded to form the element isolation film 41. The element isolation film 41 having such a structure is called STI. Note that an insulating film formed by the LOCOS method as in the first embodiment may be employed as the element isolation film.
[0111]
Subsequently, a p-type impurity is introduced into the transistor formation region of the silicon substrate 40 to form a p-well 42. Further, the surface of the transistor formation region of the silicon substrate 40 is thermally oxidized to form a silicon oxide film that becomes the gate insulating film 43.
[0112]
Next, an amorphous or polycrystal silicon film and a silicon nitride film are sequentially formed on the entire upper surface of the silicon substrate 40, and these silicon film and silicon nitride film are patterned by a photolithography method to obtain a silicon nitride film 44. Are formed to form gate electrodes 45a and 45b.
[0113]
Two gate electrodes 45a and 45b are formed in parallel on one p-well 42, and these gate electrodes 45a and 45b constitute part of the word line.
[0114]
Next, n-type impurities are ion-implanted on both sides of the gate electrodes 45a and 45b in the p-well 42 to form first to third n-type impurity diffusion regions 46a to 46c which become source / drains.
[0115]
Further, an insulating film such as silicon oxide (SiO 2) is formed by CVD.₂After the film is formed on the entire surface of the silicon substrate 40, the insulating film is etched back to leave insulating side wall spacers 48 on both sides of the gate electrodes 45a and 45b.
[0116]
Subsequently, by using the gate electrodes 45a and 45b and the sidewall spacers 48 as masks, n-type impurities are ion-implanted again into the first to third n-type impurity diffusion regions 46a to 46c, so that a high concentration impurity region is obtained. 47a to 47c are formed to make the first to third n-type impurity diffusion regions 46a to 46c have an LDD structure.
[0117]
Note that the first n-type impurity diffusion region 46a between the two gate electrodes 45a and 45b in one transistor formation region is electrically connected to the bit line, and the second and third regions at both ends of the transistor formation region. N-type impurity diffusion regions 46b and 46c are electrically connected to a lower electrode of a capacitive element to be described later.
[0118]
Through the above steps, the two MOS transistors T having the gate electrodes 45a and 45b and the n-type impurity diffusion layers 46a to 46c having the LDD structure are formed in the p well 42.₁, T₂Is formed.
[0119]
Next, MOS transistor T₁, T₂A silicon oxynitride (SiON) film having a thickness of about 200 nm is formed on the entire surface of the silicon substrate 40 by a plasma CVD method as a cover insulating film 49 covering the substrate. Thereafter, a silicon oxide (SiO 2 film having a thickness of about 1.0 μm is formed as the first interlayer insulating film 50 by plasma CVD using TEOS gas.₂) A film is formed on the cover film 49.
[0120]
Subsequently, as a densification process of the first interlayer insulating film 50, the interlayer insulating film 50 is heat-treated at a temperature of 700 ° C. for 30 minutes, for example, in a normal-pressure nitrogen atmosphere. Thereafter, the upper surface of the first interlayer insulating film 50 is planarized by a chemical mechanical polishing (CMP) method.
[0121]
Next, steps required until a structure shown in FIG.
[0122]
First, the first interlayer insulating film 50 is patterned by a photolithography method to form a first contact hole 50a having a depth reaching the first impurity diffusion region 46a. Thereafter, a Ti film having a thickness of 30 nm and a titanium nitride (TiN) film having a thickness of 50 nm are sequentially formed as a glue film on the upper surface of the first interlayer insulating film 50 and the inner surface of the first contact hole 50a by a sputtering method. In addition, WF₆A tungsten (W) film is grown on the TiN film by a CVD method using, thereby completely filling the first contact hole 50a.
[0123]
Subsequently, the W film and the TiN film are polished by the CMP method and removed from the upper surface of the first interlayer insulating film 50. The tungsten film and TiN film left in the first contact hole 50a are used as the first conductive plug 51a.
[0124]
Thereafter, on the first interlayer insulating film 50 and the first conductive plug 51a, silicon nitride (Si_ThreeN_Four) Anti-oxidation insulating film 52a and SiO film having a thickness of 100 nm₂A base insulating film 52b is formed in order by plasma CVD. Its SiO₂The film is grown by plasma CVD using TEOS. The anti-oxidation insulating film 52a is formed to prevent the first conductive plug 51a from being abnormally oxidized during the subsequent heat treatment such as annealing and causing a contact failure, and the film thickness thereof is set to, for example, 70 nm or more. It is desirable.
[0125]
Next, steps required until a state as shown in FIG.
[0126]
First, by using a resist pattern (not shown), the anti-oxidation insulating film 52a, the base insulating film 52b, and the first interlayer insulating film 50 are etched to form the second and third contact holes 50b and 50c in the second and third contact holes 50b and 50c. Over the third impurity diffusion regions 46b and 46c.
[0127]
Further, a Ti film having a thickness of 30 nm and a TiN film having a thickness of 50 nm are formed as a glue film on the upper surface of the base insulating film 52b and the inner surfaces of the second and third contact holes 50b and 50c by sputtering. Further, a W film is grown on the TiN film by CVD to completely fill the second and third contact holes 50b and 50c.
[0128]
Subsequently, the W film, the TiN film, and the Ti film are polished by a CMP method and removed from the upper surface of the base insulating film 52b. As a result, the tungsten film, the TiN film, and the Ti film remaining in the second and third contact holes 50b and 50c are used as the second and third conductive plugs 51b and 51c, respectively.
[0129]
Next, steps required until a structure shown in FIG.
[0130]
First, an iridium (Ir) film 53 is formed on the second and third conductive plugs 51b and 51c and the base insulating film 52b.
[0131]
For the Ir film 53, for example, the substrate temperature is set to 450 to 550 ° C., the power is set to 1 kW, argon (Ar) gas is introduced into the growth atmosphere at a flow rate of 100 sccm, the growth time is set to 140 seconds, and the film formation pressure is set. The film is formed to a thickness of 200 nm by sputtering under the condition of 0.35 Pa.
[0132]
Next, as shown in FIG. 24A, on the Ir film 53, iridium oxide (IrO_x) Film 54, first platinum (Pt) film 55, platinum oxide (PtO)_x) A film 56 and a second platinum (Pt) film 57 are formed in this order.
[0133]
IrO_xThe film 54 has, for example, a substrate temperature set to 50 ° C. and a power set to 1 kW, and Ar gas is grown to 60 sccm and oxygen (O₂) Gas is introduced at a flow rate of 60 sccm, the growth time is 11 seconds, and the film forming pressure is 0.37 Pa. The film is formed to a thickness of 30 nm by sputtering.
[0134]
For example, the first Pt film 55 has a substrate temperature set at 350 ° C. and a power set at 1 kW, Ar gas is introduced into the growth atmosphere at a flow rate of 100 sccm, the growth time is 8 seconds, and the film formation pressure is 0.38 Pa. And a thickness of 15 nm is formed by sputtering.
[0135]
After this, the silicon substrate 40 is once taken out of the sputter layer chamber (for example, in the atmosphere) on which the first Pt film 55 is formed, the chamber is sufficiently cleaned using a dummy wafer, and the silicon is again put in the chamber. Put the substrate 40 and PtO_xA film 56 is formed on the first Pt film 55.
[0136]
PtO_xThe film 56 is formed, for example, by setting the substrate temperature to 350 ° C., the power to 1 kW, and Ar gas to 36 sccm, oxygen (O₂) Gas is introduced at a flow rate of 144 sccm, the growth time is 22 seconds, and the film forming pressure is 6.2 Pa. The film is formed to a thickness of 25 nm by sputtering.
[0137]
Next, PtO_xAfter the silicon substrate 40 is taken out from the chamber of the sputtering apparatus in which the film 56 is formed and the inside of the chamber is sufficiently cleaned using a dummy wafer, the silicon substrate 40 is put into the chamber and the second Pt film 57 is formed on the PtO film._xIt is formed on the film 56.
[0138]
The second Pt film 57 is formed, for example, by setting the substrate temperature to 100 ° C. and the power to 1 kW, and introducing Ar gas into the growth atmosphere at a flow rate of 100 sccm, the growth time is 32 seconds, and the deposition pressure is 0.4 Pa. And a thickness of 50 nm is formed by sputtering.
[0139]
Thereafter, the second Pt film 24 is crystallized by rapid heat treatment at 750 ° C. for 60 seconds in an argon atmosphere.
[0140]
The above Ir film 53, IrO_xFilm 54, first Pt film 55, PtO_xPt / PtO composed of the film 56 and the second Pt film 57_x/ Pt / IrO_xThe / Ir structure is a first conductive film 58.
[0141]
As the lower electrode 58, a laminated structure including other noble metals and noble metal oxides, or the structures shown in the first embodiment and the second embodiment may be used.
[0142]
Next, as shown in FIG. 24B, a PLZT film of, eg, a 100 nm-thickness is formed as a ferroelectric film 59 on the first conductive film 58 by sputtering. As a material of the ferroelectric film 59, in addition to PLZT, the PZT-based material, Bi layer structure compound material, other metal oxide ferroelectric materials shown in the first embodiment may be used. As a method for forming the film 59, the method shown in the first embodiment may be adopted.
[0143]
Subsequently, the ferroelectric film 26 is crystallized by annealing in an oxygen atmosphere. As the annealing, for example, the first step is a substrate temperature of 600 ° C. for 90 seconds in a mixed gas atmosphere of argon and oxygen, and the second step is a substrate temperature of 750 ° C. for 60 seconds in an oxygen atmosphere. RTA processing is adopted.
[0144]
Further, on the ferroelectric film 59, as the second conductive film 60, for example, iridium oxide (IrO) with a film thickness of 50 nm is formed.₂) Is formed by sputtering. The second conductive film 60 is IrO_xA Pt film may be formed instead of the film.
[0145]
Thereafter, the ferroelectric film 59 is rapidly heated through the second conductive film 60 in an argon introduced atmosphere.
[0146]
Thereafter, a TiN film and SiO as a hard mask (not shown) are formed on the second conductive film 60.₂A film is formed in order. The hard mask is patterned so as to have a capacitor planar shape above the second and third conductive plugs 51b and 51c by photolithography.
[0147]
Next, as shown in FIG. 25, the second conductive film 60, the ferroelectric film 59, and the first conductive film 58 in a region not covered with a hard mask (not shown) are sequentially etched.
[0148]
As a result, the lower electrode 58a made of the first conductive film 58, the dielectric film 59a made of the ferroelectric film 59, and the upper electrode 60a made of the second conductive film 60 are formed on the base insulating film 52b. It is formed. Then, the capacitor Q is formed by the upper electrode 60a, the dielectric film 59a, and the lower electrode 58a.₁Is formed.
[0149]
In the transistor formation region, one capacitor Q₁The lower electrode 58a is electrically connected to the second impurity diffusion region 46b through the second conductive plug 51b, and is connected to another capacitor Q.₁The lower electrode 58a is electrically connected to the third impurity diffusion region 46c through the third conductive plug 51c.
[0150]
Thereafter, the hard mask (not shown) is removed.
[0151]
Subsequently, recovery annealing is performed to recover damage to the ferroelectric film 26 due to etching. In this case, the recovery annealing is performed, for example, in an oxygen atmosphere at a substrate temperature of 650 ° C. for 60 minutes.
[0152]
Next, as shown in FIG.₁After forming an alumina protective film 61 having a film thickness of 50 nm above the substrate by sputtering as an insulating protective film 61 covering the capacitor, the capacitor Q is subjected to a condition of 650 ° C. for 60 minutes in an oxygen atmosphere.₁Anneal. The protective film 61 prevents the capacitor Q from being damaged by process.₁And may be made of PZT.
[0153]
Thereafter, silicon oxide (SiO 2 having a film thickness of about 1.0 μm is formed as the second interlayer insulating film 62 by plasma CVD using TEOS gas.₂) Is formed on the protective film 61. Further, the upper surface of the second interlayer insulating film 62 is planarized by the CMP method.
[0154]
Next, steps required until a structure shown in FIG.
[0155]
First, the second interlayer insulating film 62, the protective film 61, the base insulating film 52b, and the antioxidant insulating film 52a are selectively etched using a resist mask (not shown) to form holes on the first conductive plug 51a. 62a is formed. After the etching, capacitor Q₁In order to recover the ferroelectric film 59 constituting the dielectric film 59a from damage, for example, annealing is performed for 60 minutes at a substrate temperature of 550 ° C. in an oxygen atmosphere.
[0156]
Further, a TiN film having a thickness of 50 nm is sequentially formed as a glue film in the hole 62a and on the second interlayer insulating film 62 by a sputtering method. Further, a W film is grown on the glue layer by the CVD method and the hole 62a is completely filled.
[0157]
Subsequently, the W film and the TiN film are polished by the CMP method and removed from the upper surface of the second interlayer insulating film 62. Then, the tungsten film and the glue layer left in the hole 62 a are used as the fourth conductive plug 63. The fourth conductive plug 63 is electrically connected to the first impurity diffusion region 46a through the first conductive plug 51a.
[0158]
Next, steps required until a structure shown in FIG.
[0159]
First, a SiON film is formed as a second antioxidant film 64 on the fourth conductive plug 63 and the second interlayer insulating film 62 by the CVD method. Further, the second antioxidant film 64 and the second interlayer insulating film 62 are patterned by photolithography to form the capacitor Q.₁A contact hole 65 is formed on the upper electrode 34a.
[0160]
Capacitor Q damaged by forming contact hole 65₁Is recovered by annealing. The annealing is performed, for example, in an oxygen atmosphere at a substrate temperature of 550 ° C. for 60 minutes.
[0161]
Thereafter, the second antioxidant film 64 formed on the second interlayer insulating film 62 is removed by etching back and the upper surface of the fourth conductive plug 63 is exposed.
[0162]
Next, steps required until a structure shown in FIG.
[0163]
First, capacitor Q₁A multilayer metal film is formed in the contact hole 65 on the upper electrode 60 a and on the second interlayer insulating film 62. Thereafter, by patterning the multilayer metal film, a conductive layer composed of a multilayer metal film connected to the fourth conductive plug 63 and a wiring layer 66a composed of the multilayer metal film connected to the upper electrode 60a through the contact hole 65. A pad 66b is formed. As the multilayer metal film, for example, Ti with a thickness of 60 nm, TiN with a thickness of 30 nm, Al—Cu with a thickness of 400 nm, Ti with a thickness of 5 nm, and TiN with a thickness of 70 nm are formed in this order.
[0164]
Further, a third interlayer insulating film 67 is formed on the second interlayer insulating film 62, the wiring layer 66a, and the conductive pad 66b. Subsequently, the third interlayer insulating film 67 is patterned to form a hole 67a on the conductive pad 66b, and a fifth conductive plug 68 made of a TiN film and a W film is formed in the hole 67a in this order from the bottom. .
[0165]
Thereafter, although not particularly shown, a second layer wiring including a bit line is formed on the third interlayer insulating film 97. The bit line is electrically connected to the first impurity diffusion region 46a through the fifth conductive plug 68, the conductive pad 66b, the fourth conductive plug 63, and the first conductive plug 51a. Subsequently, an insulating film or the like covering the second wiring layer is formed, but details thereof are omitted.
[0166]
In the above-described process, how the stress of the Ir film 53, the stress of the entire first conductive film 58, the amount of warpage of the entire wafer, and the like are affected by the deposition temperature of the Ir film 53 constituting the first conductive film 58. The results shown in the table of FIG. 30 were obtained.
[0167]
As shown in “BEL-IR” in FIG. 30, these measurements are performed by measuring the stress of the entire silicon substrate (wafer) 1 on which the base insulating film 52 b is formed, and then insulating the bases of a plurality of silicon substrates 1. An Ir film 53 is formed on each of the films 52b at different film formation temperatures of 400 ° C., 450 ° C., 500 ° C., and 550 ° C., and the stress of the Ir film 53 is examined and the amount of warpage of the wafer is measured. did. Furthermore, as shown in “BEL-PT”, IrO on the Ir film 53 under the above-described conditions._xFilm 54, first Pt film 55, PtO_xThe film 56 and the second Pt film 57 were formed, and the stress of the entire first conductive film 58, the integrated intensity of the (111) orientation of the second Pt film 57, and the amount of warpage of the entire wafer were measured. Further, as shown in “BEL-AN”, the Ir film 53, IrO_xFilm 54, first Pt film 55, PtO_xAfter the first conductive film 58 composed of the film 56 and the second Pt film 57 was annealed by RTA under the above conditions, the stress of the first conductive film 58 and the amount of warpage of the entire wafer were measured. Next, as shown in “Co-ANL”, a ferroelectric film 59 made of PLZT is formed on each of the first conductive films 58, and the ferroelectric film 59 is heat-treated under the above-described conditions, and further the second After the conductive film 60 was formed and heat-treated under the above-described conditions, the film stress, the amount of warpage of the entire wafer, and the film peeling state were measured. In this case, in FIG.₁The change in the amount of warpage after the formation of the plurality of films constituting the film is shown as the maximum amount of change in the capacitor.
[0168]
According to the table of FIG. 30, when the Ir film formation temperature is low, the crystal grains become small, so the Ir film 53, IrO_xFilm 54, first Pt film 55, PtO_xEach surface of the film 56 becomes slightly flat, and the integrated intensity of the (111) orientation of the uppermost Pt film 57 of the first conductive film 58 that becomes the lower electrode 58a is increased. In general, when the orientation of the first conductive film 58 is improved, the orientation of the ferroelectric film 59 formed thereon also increases (111) strength, and the capacitor Q₁The amount of switching charge becomes better.
[0169]
However, according to an experiment, when the Ir film 53 was formed at 400 ° C., the film constituting the capacitor was peeled after the second conductive film 60 was heated by RTA. This is because the stress direction of the Ir film 53 formed at 400 ° C. is a strong compressive stress, whereby the stress of the first conductive film 58 also becomes a strong compressive stress, and the stress is reversed by subsequent annealing, which is dramatic. It is thought that film peeling occurred due to the stress change.
[0170]
Therefore, according to the table of FIG. 30, the optimum film formation temperature of the Ir film 53 is 450 ° C. or more and 550 ° C. or less, and as shown in “BEL-PT”, the stress of the entire first conductive film 58 having a laminated structure is shown. -2 × 10⁹~ 5x10⁹dyne / cm²It is important to keep it at a minimum. The stress is substantially the same as the preferable range of stress of the entire laminated structure constituting the lower electrode shown in the first embodiment.
[0171]
Further, the film peeling after annealing after the formation of the second conductive film 60 is caused by a change in the total amount of warpage of the first conductive film 58, the ferroelectric film 59, and the second conductive film 60 constituting the capacitor. Depending on the amount, according to FIG. 30, the change in the amount of warp is preferably 100 μm or less. In addition, the Ir film 53 is 1.1 × 10⁹~ 12.3x10⁹dyne / cm²It is preferable to form with the stress of.
[0172]
According to the first to third embodiments described above, in order to prevent peeling of the lower electrode having a laminated structure including the platinum film and the film constituting the capacitor and to reduce the leakage current, the stress is −2. × 10⁹~ 5x10⁹dyne / cm²It is necessary to form a laminated structure film that constitutes the lower electrode under the condition of the above range.
[0173]
Also, in order to prevent film peeling of the lower electrode of the laminated structure, the change in the amount of warpage of the wafer that occurs from the first layer film to the final layer film constituting the lower electrode is reduced, and a capacitor is formed. It is necessary to reduce the change in the stress of the capacitor constituent film up to. To that end, from FIG. 16, FIG. 17 and FIG. 30, the amount of change in the amount of warpage of the wafer that occurs from the first layer film to the last layer film constituting the lower electrode is set in the range of −13 to 13 μm. Is preferred.
(Supplementary note 1) a first insulating film formed on a semiconductor substrate;
It has a laminated structure of different materials formed on the first insulating film and is −2 × 10⁹~ 5x10⁹dyne / cm²A capacitor lower electrode having a stress of:
A dielectric film formed on the capacitor lower electrode;
A capacitor upper electrode formed on the dielectric film;
A second insulating film covering the capacitor including the capacitor lower electrode, the dielectric film, and the capacitor upper electrode;
A semiconductor device comprising:
(Supplementary note 2) The semiconductor device according to supplementary note 1, wherein the stress of the capacitor lower electrode is a value including a metal oxide film or a metal nitride film formed on the first insulating film. .
(Supplementary Note 3) The semiconductor device according to Supplementary Note 1 or 2, wherein the capacitor lower electrode includes at least one of a noble metal film and a noble metal oxide film.
(Appendix 4) Forming an insulating film on a semiconductor substrate;
-2 × 10 having a laminated structure of different materials⁹~ 5x10⁹dyne / cm²Forming a first conductive film having the above stress on the insulating film;
Forming a dielectric film on the first conductive film;
Forming a second conductive film on the dielectric film;
Patterning the second conductive film to form a capacitor upper electrode; patterning the dielectric film to form a capacitor dielectric film under the capacitor upper electrode;
Forming a capacitor lower electrode under the lower electrode by patterning the first conductive film;
A method for manufacturing a semiconductor device, comprising:
(Supplementary Note 5) The first conductive film has a platinum film, and the platinum film is -3.3 × 10⁹2 × 10⁹dyne / cm²The method for manufacturing a semiconductor device according to appendix 4, wherein the method includes a step of forming with lower stress.
(Appendix 6) The laminated structure of the first conductive film has an iridium film, and the iridium film is 1.1 × 10⁹~ 12.3x10⁹dyne / cm²The method of manufacturing a semiconductor device according to appendix 4 or appendix 5, characterized by comprising a step of forming with a stress of.
(Appendix 7) The semiconductor substrate is wafer-shaped, and the amount of warpage of the semiconductor substrate from the formation of the first layer of the first conductive film having the stacked structure to the end of the formation of the final layer is determined. 7. The method of manufacturing a semiconductor device according to any one of appendix 4 to appendix 6, wherein the change is set to −13 μm to 13 μm.
(Additional remark 8) The said semiconductor substrate is a wafer form, and the variation | change_quantity of the curvature amount of the said semiconductor substrate until formation of the said 1st electrically conductive film, the said dielectric material film, and the said 2nd electrically conductive film shall be 100 micrometers or less. 8. A method for manufacturing a semiconductor device according to any one of appendix 4 to appendix 7, wherein:
(Additional remark 9) After forming the said 2nd electrically conductive film, it has the process of forming a mask in a capacitor formation field on the 2nd electrically conductive film,
The capacitor upper electrode, the capacitor dielectric film, and the capacitor lower electrode continuously etch a region of the second conductive film, the dielectric film, and the first conductive film that is not covered with the mask. 9. The method for manufacturing a semiconductor device according to any one of appendix 4 to appendix 8, wherein the method is formed.
[0174]
【The invention's effect】
As described above, according to the present invention, when a lower electrode having a laminated structure of two or more layers is formed, the lower electrode is set to −2 × 10.⁹~ 5x10⁹dyne / cm²Therefore, it is possible to make it difficult for the capacitor composed of the lower electrode, the dielectric film and the upper electrode to peel off, and to reduce the leakage current density of the capacitor.
[Brief description of the drawings]
FIGS. 1A and 1B are first cross-sectional views (part 1) illustrating a process for forming a semiconductor device according to a first embodiment of the present invention;
FIGS. 2A to 2C are first cross-sectional views (No. 2) showing a step of forming a semiconductor device according to the first embodiment of the present invention. FIGS.
FIGS. 3A and 3B are first cross-sectional views (part 3) illustrating the process of forming the semiconductor device according to the first embodiment of the invention. FIGS.
FIGS. 4A and 4B are first cross-sectional views (part 4) illustrating the process of forming the semiconductor device according to the first embodiment of the invention. FIGS.
FIGS. 5A and 5B are first cross-sectional views (part 5) illustrating the process of forming the semiconductor device according to the first embodiment of the invention. FIGS.
FIGS. 6A to 6C are second cross-sectional views (part 1) showing the process of forming the semiconductor device according to the first embodiment of the invention. FIGS.
FIGS. 7A and 7B are second cross-sectional views (part 2) showing the process of forming the semiconductor device according to the first embodiment of the invention. FIGS.
FIG. 8 is a view showing the dependency relationship between the Pt (222) orientation integrated strength of the lower electrode of the capacitor constituting the semiconductor device according to the first embodiment of the present invention and the Pt film forming temperature.
FIG. 9 is a diagram showing the stress of the lower electrode Pt / Ti and the leakage current of the capacitor according to the deposition temperature of Pt of the lower electrode of the capacitor constituting the semiconductor device according to the first embodiment of the present invention. .
FIG. 10 is a diagram showing a dependency relationship between in-plane Qsw on the wafer and Pt film forming temperature of the capacitor constituting the semiconductor device according to the first embodiment of the present invention;
FIG. 11 is a diagram showing the dependency relationship between the leakage current density of the capacitor and the film formation temperature of the lower electrode Pt constituting the semiconductor device according to the first embodiment of the present invention.
12A and 12B are cross-sectional views showing a connection portion between a conventional capacitor lower electrode and a wiring connection portion and a capacitor lower electrode of the semiconductor device according to the first embodiment of the present invention. It is.
FIGS. 13A and 13B are cross-sectional views (part 1) showing a process for forming a semiconductor device according to a second embodiment of the invention. FIGS.
FIGS. 14A and 14B are cross-sectional views (part 2) showing the process of forming the semiconductor device according to the second embodiment of the invention. FIGS.
FIGS. 15A and 15B are cross-sectional views (No. 3) showing a step of forming a semiconductor device according to the second embodiment of the invention. FIGS.
FIG. 16 is a diagram showing a dependency relationship between a warpage amount in each step of capacitor formation and a deposition temperature of a lower electrode Pt in a semiconductor device according to a second embodiment of the present invention.
FIG. 17 is a diagram showing a dependency relationship between stress in each step of capacitor formation of the semiconductor device according to the second embodiment of the present invention and a deposition temperature of the lower electrode Pt.
FIG. 18 is a diagram showing a dependency relationship between stress in each step of capacitor formation and a deposition temperature of a lower electrode Pt in a semiconductor device according to the second embodiment of the present invention.
FIG. 19 is a view showing the dependency relationship between the fatigue loss of the capacitor and the film formation temperature of the lower electrode Pt of the semiconductor device according to the second embodiment of the present invention.
FIGS. 20 (a) and 20 (b) are diagrams showing the dependency relationship between the leakage current density of the capacitor and the lower electrode Pt deposition temperature of the semiconductor device according to the second embodiment of the present invention.
FIG. 21 is a diagram showing the amount of wafer warpage, film peeling, and leakage current in each step depending on the Pt film formation temperature in the capacitor formation step of the semiconductor device according to the second embodiment of the present invention; .
FIGS. 22A and 22B are cross-sectional views (part 1) showing a process for forming a semiconductor device according to the third embodiment of the invention. FIGS.
FIGS. 23A and 23B are cross-sectional views (No. 2) showing a step of forming a semiconductor device according to the third embodiment of the invention. FIGS.
FIGS. 24A and 24B are cross-sectional views (part 3) showing a process for forming a semiconductor device according to the third embodiment of the present invention. FIGS.
FIG. 25 is a sectional view (No. 4) showing the step of forming the semiconductor device according to the third embodiment of the invention.
FIG. 26 is a sectional view (No. 5) showing the step of forming the semiconductor device according to the third embodiment of the invention.
FIG. 27 is a sectional view (No. 6) showing a step of forming a semiconductor device according to the third embodiment of the invention;
FIG. 28 is a sectional view (No. 7) showing a step of forming a semiconductor device according to the third embodiment of the invention;
FIG. 29 is a sectional view (No. 8) showing a step of forming a semiconductor device according to the third embodiment of the invention;
FIG. 30 is a diagram showing the amount of wafer warpage, stress, and film peeling in each step depending on the Ir film formation temperature in a semiconductor device formation step according to the third embodiment of the present invention;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Silicon (semiconductor) substrate, 2 ... Element isolation insulating film, 3a ... Well, 4 ... Gate insulating film, 5a, 5b ... Gate electrode, 6 ... Side wall insulating film, 7a-7c ... N-type impurity diffusion region, 10 ... Cover film, 11 ... first interlayer insulating film, 12a to 12c ... conductive plug, 13 ... underlying insulating film, 14x ... Ti film, 14y ... Pt film, 14z ... TiO_xFilm, 14 ... first conductive film. 14a, 14b ... lower electrode, 15 ... ferroelectric film, 15a ... dielectric film, 16 ... second conductive film, 16a ... upper electrode, 17 ... capacitor protective insulating film, 18 ... second interlayer insulating film, 19a- 19c ... conductive plug, 21a, 21c, 21d ... wiring, 21b ... conductive pad, 40 ... silicon (semiconductor) substrate, 41 ... element isolation film, 42 ... well, 43 ... gate insulating film, 44 ... silicon nitride film, 45a, 45b ... gate electrodes, 46a-46c ... n-type impurity diffusion regions, 48 ... sidewall spacers, 49 ... cover films, 50 ... first interlayer insulating films, 51a-51c ... conductive plugs, 52a ... antioxidant films, 52b: base insulating film, 53: Ir film, 54: IrO_xMembrane, 55 ... Pt membrane, 56 ... PtO_xFilm 57 ... Pt film 58 ... first conductive film 58a ... lower electrode 59 ... ferroelectric film 59a ... dielectric film 60 ... second conductive film 60a ... upper electrode 61 ... protective film 62 ... second interlayer insulating film, 63 ... conductive plug, 66a ... wiring, 66b ... conductive pad, T₁, T₂... MOS transistors, Q, Q₁... capacitor.

Claims (2)

Forming an insulating film above the semiconductor substrate;
  (A) forming an iridium film on the insulating film at a substrate temperature of 450 to 550 ° C .;
  (B) forming an iridium oxide film on the iridium film;
  (C) forming a first platinum film on the iridium oxide film;
  (D) forming a platinum oxide film on the first platinum film;
  (E) performing a step of forming a second platinum film on the platinum oxide film, and by the steps (a) to (e),
  Forming a first conductive film having a laminated structure including the iridium film, the iridium oxide film, the first platinum film, the platinum oxide film, and the second platinum film;
  Forming a dielectric film on the first conductive film;
  Forming a second conductive film on the dielectric film;
  Patterning the second conductive film to form a capacitor upper electrode;
  Patterning the dielectric film to form a capacitor dielectric film under the capacitor upper electrode;
  Forming a capacitor lower electrode under the capacitor dielectric film by patterning the first conductive film,
  Immediately after the step of forming the first conductive film, the first conductive film is -2 × 10. ⁹ ~ 5x10 ⁹ dyne / cm ² A method for manufacturing a semiconductor device, characterized by comprising: Forming an insulating film above the semiconductor substrate;
  (A) forming an iridium film on the insulating film at a substrate temperature of 450 to 550 ° C .;
  (B) forming an iridium oxide film on the iridium film;
  (C) forming a first platinum film on the iridium oxide film;
  (D) forming a platinum oxide film on the first platinum film;
  (E) performing a step of forming a second platinum film on the platinum oxide film, and by the steps (a) to (e),
  Forming a first conductive film having a laminated structure including the iridium film, the iridium oxide film, the first platinum film, the platinum oxide film, and the second platinum film;
  Forming a dielectric film on the first conductive film;
  Forming a second conductive film on the dielectric film;
  Patterning the second conductive film to form a capacitor upper electrode;
  Patterning the dielectric film to form a capacitor dielectric film under the capacitor upper electrode;
  Forming a capacitor lower electrode under the capacitor dielectric film by patterning the first conductive film,
  Immediately after the step of forming the first conductive film, the first conductive film is -2 × 10. ⁹ ~ 5x10 ⁹ dyne / cm ² The semiconductor device manufactured by the manufacturing method of the semiconductor device characterized by having the above-mentioned stress.

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