JP2002057298A - Ferroelectric element and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a ferroelectric element as well as manufacturing method there of where the orientation of a ferroelectric thin film is controlled for good reproducibility, for controlling a polarization reversal charge amount. SOLUTION: A lower-part electrode thin film 9 is formed on a first inter-layer insulating film 8 on a silicon substrate 4, over which a ferroelectric thin film 10 is formed. Here, the lower-part electrode thin film 9 is formed at such a relatively high temperature as 450-600 deg.C. Thus, the orientation of the ferroelectric thin film 10 becomes irregular, and the polarization reversal charge amount of a ferroelectric capacitor 3 is such a large value as 24 μC/cm2. So, a sufficient margin is provided as element operation when the information stored in the ferroelectric capacitor 3 as the polarization reversal charge amount is read by taking it out and converting a voltage between extraction electrodes 16 and 18.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a ferroelectric element used for a semiconductor memory device and the like, and a ferroelectric element manufactured by the method.

[0002]

2. Description of the Related Art Ferroelectrics have been applied to various devices because they have characteristics such as spontaneous polarization, high dielectric constant, pyroelectricity and piezoelectricity. In particular, in recent years, non-volatile memories using ferroelectric thin films for semiconductor memory devices have been actively studied.

At present, ferroelectric materials expected to be applied to memory devices are roughly classified into the following two types. One is Pb (Zr _x Ti _1-x ) O which is a typical ferroelectric material.
₃ (PZT) is a lead-based ferroelectric. This lead-based ferroelectric material is characterized in that a large remanent polarization can be obtained relatively stably at room temperature and the Curie temperature is high. The other is a bismuth layered structure ferroelectric such as SrBi ₂ Ta ₂ O ₉ (SBT). This bismuth layered structure ferroelectric has a characteristic that although it has a small amount of remanent polarization as compared with the above-mentioned lead-based ferroelectric, it has excellent resistance to fatigue deterioration due to repeated polarization inversion.

On the other hand, as a method of applying the ferroelectric material to a memory device, there are roughly two types of application methods. One is a DRAM (Dynamic Random Access Memory) capacitor replacement type memory element using a ferroelectric material as an insulating film of a storage capacitor. Another is an MFS (Metal Ferroelectric Film Semiconductor Type) FET type memory element using a ferroelectric material as a gate insulating film of a MISFET (Metal Insulating Film Semiconductor Field Effect Transistor). Since the 1T (transistor) / 1C (capacitor) type element structure is an element of a method of converting a polarization charge amount into a voltage and reading it out, it is desired to have a large polarization inversion charge amount of about 20 μC / cm ² . Also, MFSF
The ET type element structure is a type of element that detects a change in the resistivity of the semiconductor due to spontaneous polarization of the ferroelectric substance, so that there is sufficient polarization inversion charge to form an inversion layer in the channel part of the semiconductor. On the contrary, if the amount of the domain-inverted charges is too large, the stability of the device operation is adversely affected. That is, D
RAM capacitor replacement type memory device and MFSFE
For a T-type memory element, it is important to control the amount of domain-inverted charges of the ferroelectric without damaging the crystallinity and film quality of the ferroelectric.

[0005] It is known that a ferroelectric thin film has different electrical characteristics and the like depending on its crystal orientation. Therefore,
In order to apply a ferroelectric to a semiconductor memory, it is necessary to control the crystal orientation of the ferroelectric thin film. As a method for forming a ferroelectric thin film on a substrate, there is a spin coating method in which a ferroelectric precursor solution is applied on a substrate, dried, and then baked to form a ferroelectric thin film. In the spin coating method, when controlling the crystal orientation of the ferroelectric, conventionally,
A method of controlling the orientation by changing the temperature conditions of drying and baking as disclosed in Japanese Patent Application Laid-Open No. 6-116095, and a method of controlling a ferroelectric thin film as disclosed in Japanese Patent Application Laid-Open No. 10-199999. A method of forming an orientation control insulating film between the lower electrode thin film and the lower electrode thin film is used.

[0006]

However, the method for controlling the crystal orientation of the ferroelectric in the above-mentioned conventional spin coating method has the following problems. That is, as disclosed in the above-mentioned JP-A-6-116095,
In the case where the orientation is controlled by the drying and baking temperatures at the time of producing the ferroelectric thin film, there is a problem that a desired orientation cannot be obtained due to a slight temperature shift or the like at the time of producing the ferroelectric thin film. Further, when the temperature varies within the wafer surface, the orientation of the ferroelectric thin film also becomes non-uniform within the wafer surface.

For example, when the PZT film forming temperature is changed, a correlation as shown in FIG. 11 is obtained between the PZT film forming temperature and the amount of domain-inverted charges. Therefore, when the deposition temperature of PZT is high, the amount of domain-inverted charges increases. However, phenomena such as Pb loss during PZT occur, and it is difficult to obtain PZT having a stable composition. On the other hand, when the PZT film forming temperature is low, the crystallinity of PZT and the leak current density are deteriorated. As described above, it is difficult to obtain a desired amount of domain-inverted charge by controlling the film formation temperature of PZT.

Further, as disclosed in the above-mentioned Japanese Patent Application Laid-Open No. Hei 10-199999, when an insulating film for controlling orientation is formed between a ferroelectric thin film and a lower electrode thin film, the process becomes complicated. There is a disadvantage that.

It is an object of the present invention to provide a method of manufacturing a ferroelectric element capable of controlling the orientation of a ferroelectric thin film with good reproducibility and, at the same time, controlling the amount of domain-inverted charges, and a method of manufacturing the same. To provide a ferroelectric device.

[0010]

According to a first aspect of the present invention, there is provided a lower electrode thin film formed of a material containing a Group 8A element on an insulating substrate, and a lower electrode thin film formed on the lower electrode thin film. A method of manufacturing a ferroelectric element having a ferroelectric thin film, wherein the orientation of the ferroelectric thin film is controlled by controlling the temperature at which the lower electrode thin film is formed.

As shown in FIG. 7, in a laminated structure in which a silicon substrate 21, a silicon oxide film 22, an Ir lower electrode thin film 23, a PZT ferroelectric thin film 24 and an upper electrode 25 are sequentially stacked, the Ir lower electrode thin film 23 is formed. The relationship between the temperature and the a-axis orientation strength of the PZT ferroelectric thin film 24 is as shown in FIGS. That is, when the formation temperature (substrate temperature) of the Ir film is 430 ° C. or less, a compressive stress is generated in the Ir film, and when it is 430 ° C. or more, a tensile stress is generated. Further, as the compressive stress in the Ir film increases, PZT
A-axis orientation becomes strong. Also, as the tensile stress in the Ir film increases, the a-axis orientation of PZT becomes weaker and approaches the random orientation.

Therefore, when manufacturing a ferroelectric element having a laminated body of the lower electrode thin film and the ferroelectric thin film as in the above configuration, the lower electrode thin film is made of a material containing a Group 8A element and has a substrate temperature. Is controlled so that the orientation of the ferroelectric thin film is controlled.

In this case, the relationship between the a-axis orientation strength and the amount of domain-inverted charges for the PZT ferroelectric thin film 24 is as shown in FIG. That is, as the a-axis orientation of the PZT ferroelectric thin film 24 becomes stronger, the polarization inversion charge amount ΔQ becomes smaller, and as the PZT ferroelectric thin film 24 approaches random orientation, the polarization inversion charge amount ΔQ becomes larger.

Therefore, when forming a ferroelectric element requiring a large amount of polarization inversion charge of ²⁰ μC / cm ² or more, it is necessary to generate a large tensile stress in the ferroelectric thin film, Must be formed at a temperature higher than 450 ° C. On the other hand, when forming a ferroelectric element requiring a polarization inversion charge amount of about 10 μC / cm ² , it is necessary to generate a large compressive stress in the ferroelectric thin film. It must be formed at a temperature lower than 200 ° C.

In the method of manufacturing a ferroelectric element according to the first aspect of the present invention, it is preferable that the temperature for forming the lower electrode thin film is higher than 450 ° C. and lower than 600 ° C.

If the substrate temperature at the time of forming the lower electrode thin film is 600 ° C. or higher, it is not preferable because the productivity is lowered and the characteristics of the device are changed.
According to the above configuration, the formation temperature of the lower electrode thin film is 45
Since the temperature is 0 ° C to 600 ° C, the a-axis orientation strength of PZT is
4 and 5 in terms of the (100) / (211) peak intensity ratio.
6 and FIG. 6, the a-axis orientation intensity of PZT is about “3”, and the polarization inversion charge amount of PZT at that time is about 24 μC / c.
the m ^2. Therefore, a ferroelectric thin film having a large amount of domain-inverted charge of ²⁰ μC / cm ² or more can be obtained easily and with good reproducibility.

Further, in the method of manufacturing a ferroelectric element according to the first aspect of the present invention, the film stress of the lower electrode thin film is reduced to 0.008 Pa.
It is desirable to be larger and smaller than 0.02 Pa.

When the film stress of the lower electrode thin film is 0.02 Pa or more, it is not preferable because there is a possibility that peeling or cracks may occur in the film. According to the above configuration, the film stress of the lower electrode thin film is 0.008 Pa to 0.02 Pa. Therefore, a ferroelectric thin film having a large amount of domain-inverted charges of ²⁰ μC / cm ² or more can be obtained without causing peeling, cracking, and the like in the lower electrode thin film.

In the method of manufacturing a ferroelectric element according to the first aspect of the present invention, it is preferable that the temperature for forming the lower electrode thin film is higher than 20 ° C. and lower than 200 ° C.

When the lower electrode thin film is formed at a substrate temperature of 20 ° C. or less, it is difficult to control a film forming apparatus. According to the configuration, the formation temperature of the lower electrode thin film is 20 ° C.
4 to 5 and FIG. 6, P
The a-axis orientation intensity of ZT is about “12 to 25”, and the polarization inversion charge of PZT at that time is about 12 μC / cm ^{2 to} 25 μC.
/ cm ² . Therefore, a ferroelectric thin film having a polarization inversion charge of about 10 μC / cm ² can be obtained with good controllability and good reproducibility.

Further, in the method of manufacturing a ferroelectric element according to the first aspect of the present invention, the film stress of the lower electrode thin film is reduced to -0.06 Pa.
It is desirable to be larger and smaller than -0.04 Pa.

The film stress of the lower electrode thin film is -0.06 Pa.
The following cases are not preferable because there is a possibility that peeling or cracking may occur in the film. According to the above configuration, the film stress of the lower electrode thin film is -0.06 Pa to -0.04 Pa.
Therefore, a ferroelectric thin film having a polarization inversion charge amount of about 10 μC / cm ² can be obtained without peeling or cracking of the lower electrode thin film.

In the method of manufacturing a ferroelectric element according to the first aspect of the present invention, the material of the lower electrode thin film may be made of Ir or
Alloys containing at least Ir Pt-Ir, Ru-Ir, Rh-I
It is desirable to use an oxide of r or Ir, or an oxide of an alloy containing at least Ir, Pt-Ir, Ru-Ir or Rh-Ir.

According to the above configuration, a ferroelectric element requiring a large amount of domain-inverted charge of ²⁰ μC / cm ² or more, or a 10 μC / c
A ferroelectric element requiring an amount of domain-inverted charges of about m ² can be obtained simply and with good reproducibility by controlling the formation temperature of the lower electrode thin film.

According to a second aspect of the present invention, there is provided a metal oxide semiconductor (MOS) transistor formed on a semiconductor substrate, and a lower electrode thin film, a ferroelectric thin film, and an upper electrode formed on the semiconductor substrate via an interlayer insulating film. A ferroelectric capacitor that is sequentially stacked, and a source region or a drain region of the MOS transistor and a lower electrode thin film of the ferroelectric capacitor are electrically connected through a contact plug formed in the interlayer insulating film. In the connected ferroelectric element, the lower electrode thin film and the ferroelectric thin film of the ferroelectric capacitor are formed by applying the ferroelectric element manufacturing method of the first invention. I have.

The information stored as the polarization inversion charge amount in the ferroelectric capacitor formed by laminating the lower electrode thin film, the ferroelectric thin film and the upper electrode is converted into a voltage between the source region of the MOS transistor and the upper electrode. A ferroelectric memory element having a structure for reading by conversion requires a large amount of domain-inverted charge of ²⁰ μC / cm ² or more. According to the above configuration, the lower electrode thin film and the ferroelectric thin film of the ferroelectric capacitor in the ferroelectric memory element having the above structure are:
The ferroelectric element is formed by applying the method for manufacturing a ferroelectric element of the first invention. Therefore, by setting the formation temperature of the lower electrode thin film to 450 ° C. to 600 ° C., the amount of domain-inverted charges of the ferroelectric capacitor exhibits a large value of ²⁰ μC / cm ² or more, and a sufficient operation margin as a memory element is obtained. can get.

According to a third aspect of the present invention, a MOS transistor formed on a semiconductor substrate and a ferroelectric thin film and a ferroelectric thin film and an upper electrode laminated in this order on the semiconductor substrate via an interlayer insulating film. A ferroelectric element having a dielectric capacitor, wherein a source region or a drain region of the MOS transistor and an upper electrode of the ferroelectric capacitor are electrically connected by a wiring layer; The thin film and the ferroelectric thin film are characterized by being formed by applying the method for manufacturing a ferroelectric element of the first invention.

The information stored as the polarization inversion charge amount in the ferroelectric capacitor formed by laminating the lower electrode thin film, the ferroelectric thin film and the upper electrode is converted into a voltage between the source region of the MOS transistor and the lower electrode. A ferroelectric memory element having a structure for reading by conversion requires a large amount of domain-inverted charge of ²⁰ μC / cm ² or more. According to the configuration, since the ferroelectric capacitor is formed by applying the method of manufacturing a ferroelectric element of the first invention, the formation temperature of the lower electrode thin film is set to 450 ° C. to 600 ° C. In this case, a large amount of domain-inverted charges of ²⁰ μC / cm ² or more can be obtained, and a sufficient operation margin as a memory element can be obtained.

According to a fourth aspect of the present invention, there is provided a semiconductor substrate, a source region and a drain region formed in the semiconductor substrate, and a gate insulating film and a gate insulating film formed on the semiconductor substrate between the source region and the drain region. In a ferroelectric element having a gate laminated in the order of one electrode, a ferroelectric thin film, and a gate second electrode, the gate first electrode and the ferroelectric thin film of the gate are the ferroelectric material according to the first invention. It is characterized by being formed by applying an element manufacturing method.

A ferroelectric memory having a structure in which information stored as a spontaneous polarization amount of a ferroelectric thin film forming a gate is converted into a change in resistivity of a channel region between a source region and a drain region in a semiconductor substrate and read out. The device has a 10 μC sufficient to form an inversion layer in the channel region.
It suffices if there is a polarization inversion charge amount of about / cm ² . According to the above configuration, the gate first electrode and the ferroelectric thin film constituting the gate are formed by applying the method for manufacturing a ferroelectric element of the first invention. Therefore, the ferroelectric thin film exhibits a value of about 10 μC / cm ² by setting the formation temperature of the gate first electrode at 20 ° C. to 200 ° C., and the ferroelectric memory element having the above structure And a sufficient amount of domain-inverted charge required for the operation described above.

[0031]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments. <First Embodiment> FIG. 1 is a sectional view of a ferroelectric memory device according to the present embodiment. The ferroelectric memory element has a stack type structure, and has a structure in which a selection transistor 2 and a ferroelectric capacitor 3 are electrically connected by a conductive plug 1 made of polysilicon or the like.

The selection transistor 2 has a gate electrode 5 formed on a silicon substrate 4 and source and drain regions 6 and 7 formed on the silicon substrate 4 on both sides of the gate electrode 5.
It is composed of A conductive plug 1 is formed on a silicon substrate 4 so as to cover a select transistor 2.
It is formed buried in a hole penetrating through the interlayer insulating film 8 and is connected to the drain region 7 of the select transistor 2. The ferroelectric capacitor 3 has a three-layer structure of a lower electrode thin film 9, a ferroelectric thin film 10, and an upper electrode 11, and the lower electrode thin film 9 includes a diffusion barrier film 12 and a Ti film 1.
3 is connected to the conductive plug 1.

Further, a second interlayer insulating film 14 is formed on the ferroelectric capacitor 3 and the first interlayer insulating film 8, and a first contact hole 15 formed in the second interlayer insulating film 14 is formed. The upper electrode 11 is connected to the extraction electrode 16
It is connected to the. Similarly, second contact holes 1 formed in first interlayer insulating film 8 and second interlayer insulating film 14 are formed.
The source region 6 of the selection transistor 2 is connected to the extraction electrode 18 via 7. Reference numeral 19 denotes a locos film.

FIG. 2 is a sectional view showing a manufacturing procedure of the ferroelectric memory device having the stack type structure shown in FIG.
Hereinafter, the method of manufacturing the ferroelectric memory device according to the present embodiment will be described in detail with reference to FIG. In this embodiment, the silicide layer is formed by heat-treating the metal film (Ti film) 13 formed on the conductive plug 1 made of polysilicon.

First, as shown in FIG. 2A, a LOCOS film 19 having a thickness of about 500 nm is formed on the surface of the silicon substrate 4 to form an element isolation region. Next, the gate electrode 5, the source region 6, and the drain region 7 are formed using a conventional method.
Is formed. After that, CV
First method as interlayer insulating film by D (chemical vapor deposition) method
An interlayer insulating film 8 is formed to a thickness of about 500 nm, and then a contact hole 20 of about 0.6 μm is formed on the drain region 7.

Next, as shown in FIG.
Therefore, a contact hole 20 is formed by forming a polysilicon film.
After embedding, the surface is removed by CMP (chemical mechanical polishing).
The polysilicon plug as the conductive plug 1 is planarized.
Form a lug. Next, the surface of the polysilicon plug 1 is
Wet treatment with hydrofluoric acid. After that, DC magnetron
The polysilicon plug 1 and the first layer are formed by sputtering.
On the inter-insulating film 8, a Ti film 13 is formed with a thickness of 1 nm to 30 nm.
To achieve. Subsequently, DC reactive magnetron sputtering
The diffusion barrier film 12 is formed on the Ti film 13 by the
Ta_xSi_{l - x}N_yForm a film with a thickness of 50nm to 150nm
I do. Note that Ta in the present embodiment is_xSi _{l - x}N_yFilm formation
The film conditions were as follows: using a target of Ta / Si = 10/3,
Temperature 500 ° C, sputtering power 2 kV, sputtering gas
Pressure is 0.7 Pa, Ar / N_TwoIs 3/2.

After the formation of the diffusion barrier film 12, a heat treatment at 500 ° C. to 800 ° C. is performed in a pure nitrogen atmosphere to form the silicide layer. Subsequently, an Ir thin film as the lower electrode thin film 9 is formed with a thickness of about 200 nm on the diffusion barrier film 12 by DC magnetron sputtering.
The Ir thin film forming conditions in the present embodiment are DC
The power is 0.5 kW, the substrate temperature is 450 ° C. to 600 ° C., and the gas pressure is 0.6 Pa.

Thereafter, P as the ferroelectric thin film 10
b (Zr _0.52 Ti _0.48 ) O ₃ (PZT) is formed to a thickness of 250 nm by spin coating. The method of forming the PZT film is as follows. First, the precursor solution is applied to the substrate using a spinner at a rotation speed of 2000 rpm. continue,
After being thermally decomposed at a substrate temperature of 250 ° C. on a hot plate, the seed layer is baked for 5 minutes in an oxygen atmosphere of 575 ° C. using an RTA (rapid thermal annealing) furnace.
(One layer) is formed. For the second and subsequent layers, the precursor solution is
After the application at 0 rpm, the same thermal decomposition process as described above is repeated three times, and thereafter, calcination is performed in an oxygen atmosphere at 650 ° C. for 1 minute in an RTA furnace to form a growth layer. Thus, a PZT film is obtained. Subsequently, an Ir thin film as the upper electrode 11 is formed to a thickness of 100 nm by a sputtering method.

After that, by lithography and dry etching, as shown in FIG.
3, diffusion barrier film 12, lower electrode thin film 9, ferroelectric thin film 1
A laminated structure composed of 0 and the upper electrode 11 is formed. After forming up to the ferroelectric capacitor 3 in this manner, R
Post-annealing is performed for 5 minutes in an oxygen atmosphere at 650 ° C. in a TA furnace.

Thereafter, as shown in FIG. 2D, a second interlayer insulating film 14 is formed by a CVD method. And Ir
A first contact hole 15 is formed in the second interlayer insulating film 14 on the upper electrode 11, and an aluminum extraction electrode 16 connected to the Ir upper electrode 11 is formed around the first contact hole 15 by DC magnetron sputtering. . Next, the first interlayer insulating film 8 on the source region 6 and the second
A second contact hole 17 is formed in the interlayer insulating film 14, and an aluminum lead electrode 18 connected to the source region 6 is formed around the second contact hole 17.
Thus, a ferroelectric memory element having a stacked structure as shown in FIG. 1 is obtained.

The ferroelectric characteristics of the ferroelectric capacitor 3 manufactured by the above-described method are as shown in FIG.
When a voltage of 3 V is applied, the amount of polarization inversion charge ΔQ = 24 μC / c
m ² , and the leak current density was 6.5 × 10 ⁻⁷ A / cm ² .

As described above, in the present embodiment, the first interlayer insulating film 8 formed on the silicon substrate 4
A lower electrode thin film 9 is formed thereon by an Ir thin film, and a PZT ferroelectric thin film 10 is formed thereon. In that case,
In this embodiment, the orientation of the PZT ferroelectric thin film 10 is controlled by controlling the formation temperature of the lower electrode thin film 9. 4 to 6 show the lower electrode thin film 9.
The relationship between the substrate temperature when an Ir film is formed as a reference and the amount of domain-inverted charges of the PZT ferroelectric thin film formed on the Ir film is shown. Specifically, FIG. 4 shows the substrate temperature and the Ir
3 shows the relationship with the film stress. FIG. 5 shows the Ir film stress and the a-axis orientation strength of the PZT ferroelectric thin film ((100) / (211)).
(Peak intensity ratio). FIG. 6 shows the PZT
4 shows the relationship between the a-axis orientation strength and the amount of polarization-reversed charge for a ferroelectric thin film.

FIG. 7 shows that a silicon oxide film 22 is formed on a silicon substrate 21,
This is a laminated structure in which a lower electrode thin film 23, a PZT ferroelectric thin film 24, and an upper electrode 25 are sequentially laminated. When a laminated structure as shown in FIG.
The relationship between the stress included in No. 3 and the a-axis orientation strength of the PZT ferroelectric thin film 24 is as shown in FIG. And PZT
The a-axis orientation strength of the ferroelectric thin film 24 affects the electrical characteristics of the PZT ferroelectric thin film 24. That is defined as ΔQ = P ^* -P ^∧ polarization inversion charge amount Delta] Q of the ferroelectric.
Here, P ^* is the amount of polarization charge when the applied electric field is removed from the state where the ferroelectric capacitor is polarized to the minus side and then polarized to the plus side. P ^∧ is the difference between the positive polarization value and the remanent polarization value. FIG. 6 shows the relationship between the polarization inversion charge amount ΔQ value and the a-axis orientation strength in the PZT ferroelectric thin film 24. According to FIG.
It can be seen that the weaker the a-axis orientation strength of the ZT ferroelectric thin film 24, in other words, the more random the orientation of the PZT ferroelectric thin film 24, the larger the polarization inversion charge ΔQ value of the ferroelectric.

From the above results, the following conclusions are drawn. That is, when the formation temperature (substrate temperature) of the Ir film as the lower electrode thin films 9 and 23 is 430 ° C. or lower, a compressive stress is generated in the Ir film, and when the temperature is 430 ° C. or higher, a tensile stress is generated. Can be. Furthermore, as the compressive stress in the Ir film increases, the a-axis orientation of the PZT ferroelectric thin films 10, 24 formed thereon increases. Also,
As the tensile stress in the Ir film increases, the a-axis orientation of the PZT ferroelectric thin films 10 and 24 decreases, approaching a random orientation. As the a-axis orientation of the PZT ferroelectric thin films 10 and 24 becomes stronger, the polarization inversion charge amount ΔQ becomes smaller,
As the T ferroelectric thin films 10 and 24 approach random orientation, the amount of domain-inverted charges ΔQ increases.

From the above relationship, the stress contained in the lower electrode thin film 9 can be changed by the substrate temperature at the time of forming the lower electrode thin film 9 in FIG. And
The crystal orientation of the PZT ferroelectric thin film 10 formed thereon can be changed by the stress contained in the lower electrode thin film 9, and the domain-inverted charge of the obtained PZT ferroelectric thin film 10 can be changed by the crystal orientation. It can be seen that the amount changes. Therefore, in the case of a ferroelectric element requiring a large amount of domain-inverted charges of ²⁰ μC / cm ² or more, it is necessary to form the lower electrode thin film 9 at a relatively high temperature of 450 ° C. to 600 ° C. The substrate temperature at the time of forming the Ir lower electrode thin film 9 is 60
A temperature of 0 ° C. or higher is not preferable because it causes a decrease in productivity and a change in characteristics when a device is manufactured.

Here, when the stress contained in the Ir lower electrode thin film 9 is -0.06 Pa or less or 0.02 Pa or more, it is not preferable because the film may be peeled or cracked. Further, from FIGS. 5 and 6, Ir
It can be seen that when the stress of the lower electrode thin film 9 has a negative value, the amount of domain-inverted charges decreases. Therefore, it is desirable that the film stress of the Ir lower electrode thin film 9 is larger than 0.008 Pa and smaller than 0.02 Pa. Therefore, from FIG.
The substrate temperature at the time of forming the lower electrode thin film 9 is 450 ° C.
More preferably, the temperature is 500 ° C.

The ferroelectric memory device according to the present embodiment is a MOSFE formed on the silicon substrate 4.
The drain region 7 of the select transistor 2 made of T and the lower electrode thin film 9 of the ferroelectric capacitor 3 are electrically connected via the contact plug 1. Then, the information stored as the polarization inversion charge amount is extracted to the extraction electrodes 16 and 18.
It has a structure in which the voltage is converted and read out. In this case, since the ferroelectric capacitor 3 formed by the manufacturing method in the present embodiment has a large amount of domain-inverted charges of 24 μC / cm ² , a sufficient margin for element operation can be obtained.

<Second Embodiment> FIG. 8 is a sectional view of a ferroelectric memory device according to the present embodiment. In FIG. 8, a ferroelectric capacitor 33 is provided on a silicon substrate 31.
A selection transistor 32 composed of a MOSFET or the like is formed as an access switch element for access. Further, a ferroelectric capacitor 33 having a three-layer structure of a lower electrode thin film 35, a ferroelectric thin film 36, and an upper electrode 37 is formed on the first interlayer insulating film 34 on the silicon substrate 31. The upper and side surfaces of the ferroelectric capacitor 33 are covered with a capacitor protection film 38 made of a Ti oxide film. Further, a second interlayer insulating film 39 is formed on the capacitor protection film 38.

The selection transistor 32 includes a gate electrode 40 formed on a silicon substrate 31 and a source region 41 and a drain region 42 formed on the silicon substrate 31 on both sides of the gate electrode 40. Then, the drain region 4 of the select transistor 32 is formed in the first interlayer insulating film 34.
A first contact hole 43 exposing the second contact hole 2 is formed. Further, a second contact hole 44 exposing the upper electrode 37 of the ferroelectric capacitor 33 is formed in the second interlayer insulating film 39 and the capacitor protection film 38.
Tungsten metal is buried in the first contact hole 43, and a wiring for electrically connecting the drain region 42 and the upper electrode 37 via the tungsten metal in the first contact hole 43 and the second contact hole 44. A layer 45 is formed.

On the first interlayer insulating film 34, the second interlayer insulating film 39 and the wiring layer 45, a surface protective film 46 is formed over the entire surface. Reference numeral 47 denotes a TiN film for improving electrical contact between the upper electrode 37 and the wiring layer 45. Reference numeral 48 denotes a locos film.

FIG. 9 is a sectional view showing a procedure for manufacturing the ferroelectric memory element shown in FIG. Hereinafter, a method of manufacturing the ferroelectric memory element according to the present embodiment will be described in detail with reference to FIG.

First, as shown in FIG. 9A, a LOCOS film 48 is formed in a predetermined region on the upper surface of the silicon substrate 31 to form an element isolation region. Next, after the selection transistor 32 including the gate electrode 40, the source region 41, and the drain region 42 is formed, the first interlayer insulating film 34 is deposited over the entire surface of the silicon substrate 31. Thereafter, a lower electrode thin film 35 made of an Ir thin film is formed in a predetermined region on the first interlayer insulating film 34 by a sputtering method.
In the present embodiment, the conditions for forming the Ir lower electrode thin film 35 are as follows: DC power is 0.5 kW, substrate temperature is 450 ° C.
The temperature is 600 ° C. and the gas pressure is 0.6 Pa.

Subsequently, on the Ir lower electrode thin film 35,
A ferroelectric thin film 36 made of PZT is formed in the same manner as in the first embodiment. Thereafter, an upper electrode 37 made of Ir is formed on the PZT ferroelectric thin film 36. Thus, the ferroelectric capacitor 33 is formed.

Next, as shown in FIG. 9B, a Ti metal thin film is formed on the entire surface of the first interlayer insulating film 34 and the ferroelectric capacitor 33 by a sputtering method. Thereafter, the Ti metal thin film is oxidized to form a Ti oxide film 38 '. Next, the ferroelectric capacitor 33 is masked with a resist pattern by photolithography,
Dry etching is performed on the i-oxide film 38 ', and FIG.
As shown in FIG. 3C, the capacitor protection film 38 is formed by leaving the Ti oxide film 38 'on the top and side surfaces of the ferroelectric capacitor 33. Then, after depositing a second interlayer insulating film 39 on the ferroelectric capacitor 33, the first interlayer insulating film 34 is etched to form a first contact hole 43 exposing the upper surface of the drain region 42.

Next, a Ti film and a Ti nitride film are deposited on the upper surfaces of the first interlayer insulating film 34 and the second interlayer insulating film 39 and on the bottom and wall surfaces of the first contact hole 43 by a sputtering method. Furthermore, a tungsten metal is deposited thereon by a CVD method to a thickness of 500 nm,
The deposited film is left only in the first contact hole 43 by the etch back method.

Next, as shown in FIG. 9D, the second interlayer insulating film 39 and the capacitor protection film 38 are continuously etched to form the upper surface of the upper electrode 37 of the ferroelectric capacitor 33. Is formed to expose a part of the second contact hole. Then, the second contact hole 44
Then, a Ti nitride film is formed with a thickness of 100 nm on the lower part and the wall surface, and etching is performed so that only the region of the upper electrode 37 remains to obtain a TiN film 47.

Next, as shown in FIG. 9E, the first contact hole 43 is applied to the TiN film 47 so as to have a thickness of 5 nm.
Deposit a thin metal film consisting of 00 nm aluminum. Thereafter, the metal thin film is etched to leave only a predetermined region, thereby forming the wiring layer 45. Finally, a surface protective film 46 is formed over the entire surface of the first interlayer insulating film 34, the second interlayer insulating film 39, and the wiring layer 45, and a ferroelectric memory device as shown in FIG. 8 is obtained.

The ferroelectric characteristics of the ferroelectric capacitor 33 manufactured by the above-described method are similar to those of the first embodiment when the voltage of +3 V is applied and the domain-inverted charge amount ΔQ = 24 μC / cm. ^2. Leak current density = 6.5 × 10 ^-7
A / cm ² .

Also in this embodiment, the silicon substrate 3
A lower electrode thin film 35 is formed by an Ir thin film on a first interlayer insulating film 34 formed on the first interlayer insulating film 1, and a PZT ferroelectric thin film 36 is formed thereon. Then, information stored as the amount of polarization inversion charge is read out as a voltage between the source region 41 and the lower electrode thin film 35 via a contact hole (not shown). In that case, the substrate temperature at the time of forming the lower electrode thin film 35 is 450 ° C.
The temperature is set to 600 ° C. Therefore, the ferroelectric capacitor 33 has a large amount of domain-inverted charges of 24 μC / cm ^{2, and} a sufficient margin for device operation can be obtained.

<Third Embodiment> FIG. 10 is a diagram showing a sectional structure of a ferroelectric memory device according to the present embodiment. 10, a source region 52 and a drain region 53 are formed on a surface of a silicon substrate 51 at predetermined intervals. Then, a region between the source region 52 and the drain region 53 becomes a channel region. On the silicon substrate 51 in the channel region, a gate insulating film 54,
The lower electrode thin film 55 as the gate first electrode, the ferroelectric thin film 56, and the upper electrode 57 as the gate second electrode are sequentially formed.

In the ferroelectric memory device having the above structure, an MIS capacitor is constituted by the silicon substrate 51, the source region 52, the drain region 53, the channel region, the gate insulating film 54 and the lower electrode thin film 55, and the lower electrode thin film 5
5. A ferroelectric capacitor 58 is constituted by the ferroelectric thin film 56 and the upper electrode 57.

The ferroelectric memory device having the above configuration is
Since the memory element is of a type that detects a change in the resistivity of the semiconductor due to the spontaneous polarization of the ferroelectric, the ferroelectric capacitor 58 has sufficient polarization inversion charge for forming an inversion layer in the channel region of the silicon substrate 51. On the other hand, if the amount of the domain-inverted charges is too large, the stable operation of the memory element will be adversely affected.

In the ferroelectric memory device according to the present embodiment, the lower electrode thin film 55 is formed by applying a DC power of 0.5 kW, a substrate temperature of 20 ° C. to 200 ° C., and a gas pressure of 0.5 kW.
It is formed under the condition of 6 Pa. As described above, in the case of the first and second embodiments, 450 ° C. to 60 ° C.
Since the lower electrode thin film 55 is formed at a formation temperature of 20 ° C. to 200 ° C. lower than 0 ° C., as can be seen from FIGS. 4 and 5, a compressive stress acts on the lower electrode thin film 55, and the strong The dielectric thin film 56 is oriented in the a-axis. If the substrate temperature at the time of forming the lower electrode thin film 55 is 20 ° C. or lower, it is not preferable because control of the film forming apparatus is not easy. As a result, a voltage was applied between the upper electrode 57 and the lower electrode thin film 55 of the obtained ferroelectric capacitor 58 and the ferroelectric characteristics were measured.
μC / cm ² and 2 in the case of the first and second embodiments.
The value is smaller than 4 μC / cm ² . This value is neither high nor low for operating the ferroelectric memory element of the present embodiment, and is a necessary and sufficient ferroelectric characteristic.

In each of the above embodiments, a semiconductor memory device has been described as an example of a ferroelectric device using a ferroelectric thin film. However, the ferroelectric device of the present invention is limited to a semiconductor memory device. However, the present invention can be applied to other devices using a high dielectric thin film.

Further, PZT is used as a ferroelectric material,
Although Ir was used as the lower electrode thin film material, the present invention
It is not limited to this. P as ferroelectric material
LZT ((Pb_1-yLa_y) (Zr_xTi_1-x) O_Three) Or the above SBT
May be used. Further, as the lower electrode thin film material,
Pt which is an alloy of Ir_xIr_1-x, Ru_xIr_1-x, Rh_xIr
_1-x(0 ≦ x <1) or IrO which is an oxide of Ir_TwoAnd Ir
Pt is an alloy oxide of_xIr _1-xO_y, Ru_xIr_1-xO_y, Rh_x
Ir_1-xO_yThe same effect can be expected when using
You.

[0066]

As is apparent from the above description, the method of manufacturing a ferroelectric element according to the first aspect of the present invention comprises a lower electrode thin film formed of a material containing a Group 8A element and a ferroelectric element formed on the lower electrode thin film. When manufacturing a ferroelectric element having a dielectric thin film,
Since the orientation of the ferroelectric thin film is controlled by controlling the formation temperature of the lower electrode thin film, a compression stress is generated in the lower electrode thin film by setting the formation temperature to 430 ° C. or less, and this compression stress is increased. By doing so, the a-axis orientation of the ferroelectric thin film can be enhanced. In addition, 430
C. or higher to cause tensile stress in the lower electrode thin film. By increasing the tensile stress, the a-axis orientation of the ferroelectric thin film can be weakened and a random orientation can be obtained.

In this case, the polarization-reversed charge amount ΔQ decreases as the a-axis orientation of the ferroelectric thin film increases, and the polarization-reversal charge amount ΔQ increases as the orientation approaches random orientation. Therefore, by forming the lower electrode thin film at a temperature higher than 450 ° C. and generating a large tensile stress in the ferroelectric thin film, a large amount of domain-inverted charge of ²⁰ μC / cm ² or more can be obtained. Further, by forming the lower electrode thin film at a temperature lower than 200 ° C. to generate a large compressive stress in the ferroelectric thin film,
A polarization inversion charge of about 0 μC / cm ² can be obtained.

Further, in the method of manufacturing a ferroelectric element according to the first aspect of the present invention, the temperature for forming the lower electrode thin film may be set at 450 ° C. to 6 ° C.
If the temperature is set to 00 ° C., the temperature for forming the lower electrode thin film is 600 ° C.
Since the temperature is lower than ° C, it is possible to prevent a decrease in productivity and a change in characteristics when a device is manufactured. Therefore, a ferroelectric thin film having a large amount of domain-inverted charge of ²⁰ μC / cm ² or more can be obtained easily and with good reproducibility.

Further, in the method of manufacturing a ferroelectric element according to the first aspect of the present invention, the film stress of the lower electrode thin film is set to 0.008 Pa or less.
If it is 0.02 Pa, the film stress of the lower electrode thin film is 0.02 Pa.
Since it is smaller than 02 Pa, it is possible to prevent the film from being peeled or cracked. Therefore, a ferroelectric thin film having a large amount of domain-inverted charge of ²⁰ μC / cm ² or more can be obtained without causing peeling, cracking, and the like in the lower electrode thin film.

Further, in the method for manufacturing a ferroelectric element according to the first aspect of the present invention, the temperature for forming the lower electrode thin film may be in the range of 20 ° C. to 20 ° C.
If the temperature is set to 0 ° C., the lower electrode thin film is higher than 20 ° C., so that control of the film forming apparatus is easy. Therefore, 10μ
A ferroelectric thin film having a polarization inversion charge amount of about C / cm ²
It can be obtained with good controllability and good reproducibility.

Further, in the method of manufacturing a ferroelectric element according to the first aspect of the present invention, the film stress of the lower electrode thin film is set to -0.06 Pa or less.
-0.04Pa, the film stress of the lower electrode thin film is-
Since it is larger than 0.06 Pa, it is possible to prevent the film from being peeled or cracked. Therefore, a ferroelectric thin film having a polarization inversion charge amount of about 10 μC / cm ² can be obtained without causing peeling, cracking or the like in the lower electrode thin film.

Further, in the method of manufacturing a ferroelectric element according to the first aspect of the present invention, the material of the lower electrode thin film may be made of Ir or
Alloys containing at least Ir Pt-Ir, Ru-Ir, Rh-I
r or an oxide of Ir, or an oxide of an alloy containing at least Ir, Pt-Ir, Ru-Ir, Rh-Ir,
Large domain-inverted charge of ²⁰ μC / cm ² or more or 10
A ferroelectric element requiring a domain-inverted charge amount of about μC / cm ² can be obtained simply and with good reproducibility by controlling the formation temperature of the lower electrode thin film.

The ferroelectric element according to the second aspect of the present invention uses a MOS transistor which stores information stored as a polarization inversion charge amount in a ferroelectric capacitor in which a lower electrode thin film, a ferroelectric thin film and an upper electrode are laminated. A ferroelectric memory device having a structure in which the voltage is converted into a voltage between the source region and the upper electrode and read out, wherein the lower electrode thin film and the ferroelectric thin film are formed by using the ferroelectric device of the first invention. Since the manufacturing method was applied, the formation temperature of the lower electrode thin film was set to 45
By setting the temperature to 0 ° C. to 600 ° C., it is possible to obtain a ferroelectric capacitor having a large polarization inversion charge of ²⁰ μC / cm ² or more. Therefore, a sufficient operation margin as a memory element can be obtained.

The ferroelectric element according to the third invention is characterized in that information stored as a polarization inversion charge amount in a ferroelectric capacitor formed by laminating a lower electrode thin film, a ferroelectric thin film and an upper electrode is transferred to a MOS transistor. A ferroelectric memory element having a structure in which a voltage is converted between a source region and the lower electrode and read out, wherein the lower electrode thin film and the ferroelectric thin film are formed by using the ferroelectric element of the first invention. Since the manufacturing method was applied, the formation temperature of the lower electrode thin film was set to 45
By setting the temperature to 0 ° C. to 600 ° C., it is possible to obtain a ferroelectric capacitor having a large polarization inversion charge of ²⁰ μC / cm ² or more. Therefore, a sufficient operation margin as a memory element can be obtained.

The ferroelectric element according to the fourth aspect of the present invention uses the information stored as the amount of spontaneous polarization of the ferroelectric thin film forming the gate as the resistivity of the channel region between the source region and the drain region in the semiconductor substrate. In the ferroelectric memory device having a structure of converting and reading out changes, the method of manufacturing the ferroelectric device of the first invention is applied to the formation of the gate first electrode of the gate and the ferroelectric thin film. By setting the formation temperature of the gate first electrode to 20 ° C. to 200 ° C., it is possible to obtain a ferroelectric thin film having a polarization inversion charge amount of about 10 μC / cm ² . Therefore, it is possible to obtain a sufficient amount of domain-inverted charges required for the operation of the ferroelectric memory element having the above-described structure.

[Brief description of the drawings]

FIG. 1 is a sectional view of a ferroelectric memory device as a ferroelectric device of the present invention.

FIG. 2 is a cross-sectional view showing a procedure for manufacturing the ferroelectric memory element shown in FIG.

FIG. 3 is a diagram showing ferroelectric characteristics of the ferroelectric capacitor obtained in FIG.

4 is a diagram showing a relationship between a substrate temperature and a film stress of Ir at the time of forming an Ir film in FIG. 2;

5 is a diagram showing the relationship between the film stress of Ir and the a-axis orientation strength of PZT in FIG.

FIG. 6 is a diagram showing the relationship between the a-axis orientation intensity and the amount of domain-inverted charge for PZT.

FIG. 7 is a cross-sectional view of a stacked structure in which a silicon oxide film and a ferroelectric capacitor are stacked on a silicon substrate.

FIG. 8 is a sectional view of a ferroelectric memory element different from FIG.

9 is a cross-sectional view showing a procedure for manufacturing the ferroelectric memory element shown in FIG.

FIG. 10 is a sectional view of a ferroelectric memory element different from FIGS. 1 and 8;

FIG. 11 is a diagram illustrating a relationship between a PZT film forming temperature and a polarization inversion charge amount.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Polysilicon plug, 2, 32 ... Selection transistor, 3, 33, 58 ... Ferroelectric capacitor, 4, 21, 31, 51 ... Silicon substrate, 5, 40 ... Gate electrode, 6, 41, 52 ... Source region 7, 42, 53 ... drain region, 8, 34 ... first interlayer insulating film, 9, 23, 35, 55 ... lower electrode thin film, 10, 24, 36, 56 ... ferroelectric thin film, 11, 25, 37 57, upper electrode, 12: diffusion barrier film, 13: Ti film, 14, 39: second interlayer insulating film, 15, 43: first contact hole, 16, 18, extraction electrode, 17, 44: second contact Holes 19, 48 Locos film 22 Silicon oxide film 38 Capacitor protective film 45 Wiring layer 46 Surface protective film 47 TiN film 54 Gate insulating film

Continuation of front page (72) Inventor Masaya Nagata 22-22 Nagaike-cho, Abeno-ku, Osaka-shi, Japan F-term (reference) in Sharp Corporation 5F083 AD21 FR02 GA30 JA15 JA17 JA36 JA38 JA39 JA40 JA43 MA06 MA17 PR22 PR34 PR39

Claims (9)

[Claims] 1. A method of manufacturing a ferroelectric element comprising: a lower electrode thin film formed of a material containing a Group 8A element on an insulating substrate; and a ferroelectric thin film formed on the lower electrode thin film. By controlling the formation temperature of the lower electrode thin film,
A method for manufacturing a ferroelectric element, comprising controlling the orientation of the ferroelectric thin film. 2. The method for manufacturing a ferroelectric device according to claim 1, wherein a temperature for forming the lower electrode thin film is higher than 450 ° C. and lower than 600 ° C. . 3. The method for manufacturing a ferroelectric element according to claim 1, wherein the film stress of the lower electrode thin film is larger than 0.008 Pa and smaller than 0.02 Pa. A method for manufacturing a dielectric element. 4. The method of manufacturing a ferroelectric element according to claim 1, wherein the temperature for forming the lower electrode thin film is higher than 20 ° C.
A method for manufacturing a ferroelectric element, wherein the temperature is lower than 00 ° C. 5. The method for manufacturing a ferroelectric device according to claim 1, wherein a film stress of the lower electrode thin film is larger than -0.06 Pa and smaller than -0.04 Pa. Of manufacturing a ferroelectric element. 6. The method of manufacturing a ferroelectric element according to claim 1, wherein the material of the lower electrode thin film is Ir or an alloy Pt-Ir containing at least Ir. Ru-Ir, Rh-Ir, or
Oxide of Ir or alloy Pt- containing at least Ir
A method for manufacturing a ferroelectric device, comprising an oxide of Ir, Ru-Ir, and Rh-Ir. 7. A ferroelectric capacitor comprising: a metal oxide semiconductor transistor formed on a semiconductor substrate; and a lower electrode thin film, a ferroelectric thin film, and an upper electrode laminated in this order on the semiconductor substrate via an interlayer insulating film. And a source or drain region of the metal oxide semiconductor transistor and a lower electrode thin film of the ferroelectric capacitor are electrically connected via a contact plug formed in the interlayer insulating film. In the device, the lower electrode thin film and the ferroelectric thin film of the ferroelectric capacitor are formed by applying the method of manufacturing a ferroelectric device according to any one of claims 1 to 3 and 6. A ferroelectric element characterized in that: 8. A ferroelectric capacitor comprising: a metal oxide semiconductor transistor formed on a semiconductor substrate; and a lower electrode thin film, a ferroelectric thin film, and an upper electrode laminated in this order on the semiconductor substrate via an interlayer insulating film. And a source or drain region of the metal oxide semiconductor transistor and an upper electrode of the ferroelectric capacitor are electrically connected by a wiring layer, wherein the lower electrode of the ferroelectric capacitor The thin film and the ferroelectric thin film are formed by applying the method for manufacturing a ferroelectric element according to any one of claims 1 to 3 and 6. element. 9. A semiconductor substrate, a source region and a drain region formed on the semiconductor substrate, and a gate insulating film, a gate first electrode, and a ferroelectric material on the semiconductor substrate between the source region and the drain region. 7. A ferroelectric element having a gate formed by laminating a thin film and a gate second electrode in this order, wherein the gate first electrode and the ferroelectric thin film of the gate are any one of claims 1 and 4 to 6. A ferroelectric element formed by applying the method for manufacturing a ferroelectric element described in (1).