JP4358116B2 - Semiconductor memory device and method for controlling semiconductor memory device - Google Patents

Description

【Technical field】
[0001]
The present invention relates to a semiconductor memory device and a control method therefor, and more particularly to a semiconductor memory device and a control method therefor that improve bit line equalization operations.
[Background]
[0002]
Some semiconductor memory devices such as a dynamic random access memory (hereinafter abbreviated as DRAM) use a shared sense amplifier system in which two memory blocks share one sense amplifier group. In this case, a bit line isolation gate (BT) is provided in order to separate the bit line in the unselected memory block from the sense amplifier.
[0003]
FIG. 10 is a diagram showing a part of the shared sense amplifier system. A sense amplifier S / A is connected between the bit line BLZ and the complementary bit line BLX and is shared by the adjacent memory blocks BLK1 and BLK2. Isolation gates BTL and BTR are connected between corresponding memory blocks BLK1 and BLK2 and sense amplifier S / A, respectively, and conduct / non-conduct in response to corresponding isolation gate control signals sbltlx and sbltrx. Note that the equalization of the bit lines is performed by an equalize circuit 150 provided on the sense amplifier side.
[0004]
Here, the alternative sense amplifier S / As shown in FIG. 10 may be used in place of the sense amplifier S / A. In the sense amplifier S / A described above, the internal step-down voltage Vcc is supplied to the sense amplifier active line PSA and the ground voltage Vss is supplied to the sense amplifier active line NSA, so that the sense amplifier S / A is activated. It is a structure. On the other hand, in the alternative sense amplifier S / As, when the low level alternative sense amplifier activation signal LEX is input to the transistor Tr9 and the high level alternative sense amplifier activation signal LEZ is input to the transistor Tr10, Vcc and Vss are supplied to the alternative sense amplifier S / As. Is supplied and activated.
[0005]
FIG. 11 is a timing chart showing the self-refresh operation. A self-refresh operation is performed in response to the “high” level (active) of the self-refresh enable signal SREFE. During the period of self-refreshing the block BLK1, the control signal sbltlx is maintained at the “high” level, the isolation gate BTL is turned on, and the bit lines BLLZ and BLLX in the block BLK1 are connected to the sense amplifier S / A. The bit lines BLZ and BLX are kept connected. During that period, the word lines swl0, swl1,... Are sequentially activated in response to the transition of the internal RAS signal / RAS to the low level, the bit lines BLLZ and BLLX are restored, and the high level of / RAS is restored. In response to the transition, the word lines swl0, swl1,... Are deactivated to equalize the bit lines BLLZ and BLLX.
[0006]
Further, the separation gate BTR on the non-selected block BLK2 side is separated by setting the control signal sbltrx to the “high” level every period when / RAS is “high” level, that is, every period when the bit line of BLK1 is equalized. Gate BTR is turned on. As a result, the bit lines BLRZ and BLRX of the non-selected block BLK2 are connected to the bit lines BLZ and BLX and equalized. Conversely, when self-refreshing the block BLK2, the same equalization control is performed on the block BLK1. Thereafter, the same operation is performed on each block, whereby the self-refresh is completed for all the memory cells.
[0007]
On the other hand, as disclosed in Patent Documents 1 and 2, in the control shown in FIG. 12, the control signal for the separation gate on the non-selected block side is always set to the “low” level during the refresh period of the memory cell on the selected block side. keep. For this reason, the sense amplifier S / A and the bit line on the non-selected block side are not connected during the equalization period of the selected block. Unlike the case of FIG. 11 in which the non-selected block is connected for each equalization of the selected block, the switching operation of the separation gate connected to the non-selected block is not performed, and the charge / discharge current is reduced. .
[0008]
In the semiconductor memory devices disclosed in Patent Documents 3 and 4, a bit line equalize circuit is provided for each memory block separated from the sense amplifier by a bit line isolation gate. Therefore, even during the period when the bit line between the non-selected memory block and the sense amplifier is in a non-conductive state, the equalize operation is performed using the bit line equalize circuit provided in the non-selected memory block. It is possible to prevent a potential shift caused by the floating state of the line potential.
[0009]
In FIG. 10, both the bit line equalization control signal BRS and the equalization control signal BRSS of the sense amplifier activation line PSA / NSA are controlled between the boosted voltage Vpp and the ground voltage Vss. By driving with the boosted voltage Vpp boosted from the external power supply voltage Vdd, the drive capability of the equalizing transistor is enhanced, and the equalizing time is shortened.
[0010]
In recent semiconductor memory devices, the bit line length may be shortened in order to increase the speed of the restore operation by the sense amplifier or improve the sensitivity to the accumulated charge. As a result, the wiring capacity of the bit line is reduced, and the current consumption at the time of restoration is reduced and the equalization time is shortened.
[0011]
Prior art documents are shown below.
[Patent Document 1]
JP-A-9-161477
[Patent Document 2]
Japanese Patent Laid-Open No. 10-222977
[Patent Document 3]
JP-A-8-153391
[Patent Document 4]
Japanese Patent Laid-Open No. 9-45879
DISCLOSURE OF THE INVENTION
[Problems to be solved by the invention]
[0012]
The first problem is a problem related to the control of the bit line isolation gate of the non-selected block, and the second problem is related to the equalization control.
[0013]
Problems related to the control of the bit line isolation gate will be described. 10 and 11, when the memory block BLK1 is a selected block for the self-refresh operation, the control of the separation gate BTR on the non-selected block BLK2 side is performed every period of the equalizing operation when / RAS is at a high level. The signal sbltrx becomes high level. Therefore, since the switching operation of the separation gate BTR is repeatedly performed every equalization period, the charge / discharge current increases, which is a problem.
[0014]
In a semiconductor memory device having a bit line equalize circuit for each memory block separated from the sense amplifier by the bit line isolation gate, the isolation gate of the non-selected block is kept nonconductive as shown in FIG. Even then, the bit line potential of the non-selected block is in a floating state and the potential does not shift. However, as compared with the circuit configuration in which the sense amplifier is provided with the equalize circuit as in the equalize circuit 150 in FIG. 10, the number of components increases in the circuit configuration in which the bit line equalize circuit is provided for each memory block. In a semiconductor memory device having a large number of bit lines, an increase in chip occupation area due to an increase in the number of constituent elements of the bit line equalize circuit is a problem.
[0015]
Next, problems related to equalization control will be described. In the circuit of FIG. 10, the current consumption is reduced by the drive amplitude of the bit line equalize control signal BRS and the equalize control signal BRSS of the sense amplifier activation line PSA / NSA, and the booster circuit (not shown) for generating the boosted voltage Vpp. In order to reduce current consumption, it is conceivable to change the drive amplitude from between the boosted voltage Vpp and the ground voltage Vss to between the internal step-down voltage Vcc and the ground voltage Vss. However, in this case, as shown in FIG. 13, the drive capability of the equalize transistor is insufficient, and the equalization end time between the sense amplifier active lines PSA and NSA and between the bit lines BLZ and BLX extends from T1 to T2. There is a risk that. As a result, the equalizing operation is not completed within the cycle time, and there is a possibility that data destruction may occur. Further, in order not to cause data destruction, it is necessary to relax the specification of the cycle time in accordance with the decrease in the equalization speed, but this is a problem because the access operation speed decreases.
[0016]
Therefore, a case is considered in which the wiring capacity is reduced by shortening the bit line length to increase the equalization speed. In this case, since the wiring capacities of the sense amplifier active lines PSA and NSA are not changed, as shown in FIG. 14, there is a time difference in the equalizing operation between the sense amplifier active lines PSA and NSA and between the bit lines BLZ and BLX. Therefore, a short abnormal current may flow through the transistor of the sense amplifier. There is a period in which the voltage levels of the bit lines BLZ and BLX, which are gate terminal voltages, are more than the threshold voltage compared to the voltage levels of the sense amplifier active lines PSA and NSA which are source terminal voltages of the sense amplifier transistors. Because. As a result, current consumption cannot be reduced, which is a problem.
[0017]
Further, in FIG. 10, problems in the case where an alternative sense amplifier S / As is used instead of the sense amplifier S / A will be described. When the memory block BLK1 is a selected block, there is a time difference between the equalization end time of the bit lines BLLZ and BLLX in the memory block BLK1 and the equalization end time of the bit lines BLZ and BLX to which the sense amplifier is connected. There is a case.
[0018]
The bit lines BLLZ and BLLX are equalized via the separation gate BTL. In addition, the transistor size of the isolation gate BTL may be limited due to requirements for device integration, and it may take time to equalize via the isolation gate due to the influence of the on-resistance. Since the specification of the cycle time is determined in accordance with the latest equalization time, if there is a difference in equalization time, it is difficult to demonstrate the original performance of the semiconductor memory device.
[0019]
The present invention has been made to solve at least one of the problems of the prior art, and a semiconductor memory capable of equalizing bit lines with low current consumption while maintaining a normal access operation speed and chip area. An object of the present invention is to provide an apparatus and a control method thereof.
[Means for Solving the Problems]
[0020]
In the semiconductor memory device according to the first aspect of the invention made to achieve the above object, the memory information is read out to the first bit line according to the selected word line, and the selected word line In a semiconductor memory device including a second memory block from which stored information is read in response to the second bit line and a sense amplifier shared by the first bit line and the second bit line, the first bit line and the sense A first isolation gate that controls connection / separation with the amplifier, a second isolation gate that controls connection / separation between the second bit line and the sense amplifier, and the first bit line and the second bit line are equalized. A signal for activating the equalizing unit and the first isolation gate is identified for k word lines that are successively selected in the second memory block. refresh A control circuit is provided that generates based on a predetermined logical combination of addresses and a reset signal indicating an equalization period.
[0021]
In the semiconductor memory device according to the first invention, the signal for activating the first isolation gate identifies k word lines that are successively selected in the second memory block. refresh The address is generated in the control circuit based on a predetermined logical combination of addresses and a reset signal indicating an equalization period.
[0022]
In the method for controlling a semiconductor memory device according to the first aspect of the invention, when an access operation is performed on the second memory block, a restore operation following the word line selection is performed for the second bit line. And so Selection block where subsequent equalization is repeated continuously refresh Steps and k word lines selected in succession in the second memory block are identified. refresh And a non-selected block equalizing step for connecting the first bit line and the sense amplifier based on a reset signal indicating that the address has a predetermined logical combination and an equalizing period.
[0023]
Thereby, the charge / discharge current by the switching operation can be reduced by reducing the number of times of switching of the first isolation gate of the non-selected block.
【The invention's effect】
[0030]
According to the present invention, by appropriately combining the control method of the bit line isolation gate, the control method of the equalize circuit, the arrangement and circuit configuration of the equalize circuit, while maintaining the operation speed and the chip area during the normal access operation, It is possible to provide a semiconductor memory device capable of operating with low current consumption and a method for controlling the semiconductor memory device.
BEST MODE FOR CARRYING OUT THE INVENTION
[0031]
DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a semiconductor memory device and a control method therefor according to the present invention will be described below in detail with reference to FIGS. 1 to 9 and with reference to the drawings.
[0032]
FIG. 1 is a diagram showing a part of a shared sense amplifier system in the semiconductor memory device of the first embodiment. This is an embodiment relating to control of an isolation gate of an unselected memory block and equalization control of a bit line.
[0033]
First, a method for controlling the bit line isolation gate will be described. In the shared sense amplifier system, a bit line isolation gate is provided in order to separate a bit line in an unselected memory block from a bit line connected to the sense amplifier. The isolation gate BTL connects the bit lines BLLZ and BLLX of the memory block BLK1 and the bit lines BLZ and BLX connected to the sense amplifier S / A. Similarly, the isolation gate BTR connects the bit lines BLRZ and BLRX to the bit lines BLZ and BLX. Here, the bit lines BLZ and BLX sandwiched between the bit line isolation gates BTL and BTR may be referred to as an inner bit line portion, and the bit lines BLLZ, BLLX and BLRZ and BLRX may be referred to as an outer bit line portion.
[0034]
The BLT generation circuit 103 receives an address Add for identifying a memory block, a signal BT for controlling the bit line isolation gate, and an n / k activation control signal φ, and outputs bit line isolation gate control signals sbltlx and sbltrx as outputs. . The isolation gates BTL and BTR are composed of NMOS transistors, and are turned on when high level bit line isolation gate control signals sbltlx and sbltrx are input to the isolation gate, and low level bit line isolation gate control signals are When input, it is turned off.
[0035]
Before the access to the memory cell, it is necessary to short-circuit between the bit lines BLX and BLZ, between BLLZ and BLLX, and between BLRZ and BLRX and initialize them to the equalize voltage Vpr. That's it. Similarly, it is necessary to initialize between the sense amplifier active lines PSA and NSA to the equalize voltage Vpr, which is called an equalize operation of the sense amplifier active lines PSA and NSA.
[0036]
Bit lines BLX and BLZ are separated from memory blocks BLK1 and BLK2 by a bit line isolation gate. The bit line equalize circuit 107 is provided in the bit lines BLZ and BLX, and is constituted by NMOS transistors Tr6 to Tr8. The bit lines BLZ and BLX are connected via a transistor Tr6, and the equalize voltage Vpr is connected to bit lines BLZ and BLX via transistors Tr7 and Tr8. A bit line equalize control signal BRS is connected to the gates of the transistors Tr6 to Tr8.
[0037]
Here, the equalize circuit provided in the inner bit line portion may be referred to as an inner equalize portion, and the equalize circuit provided in the outer bit line portion may be referred to as an outer equalize portion.
[0038]
The PSA / NSA equalize circuit 111 includes NMOS transistors Tr3 to Tr5, and the circuit configuration is the same as that of the bit line equalize circuit 107. A PSA / NSA line equalize control signal BRSS is connected to the gates of the transistors Tr3 to Tr5.
[0039]
The equalization control signal EQ, which is the output of the EQ generation circuit 108, is input to the PSA / NSA equalization circuit 111 and the bit line equalization circuit 107 via inverter gates 109 and 110. From the LE generation circuit 115, the sense amplifier activation signal LE is input to the NMOS transistor Tr2, and / LE inverted by the inverter gate is input to the PMOS transistor Tr1.
[0040]
When the low level equalization control signal EQ is input from the EQ generation circuit 108 to the inverter gates 109 and 110, the inverter gate 109 receives the high level PSA / NSA line equalization control signal BRSS of the boosted voltage Vpp. Outputs a high level bit line equalize control signal BRS of boosted voltage Vpp or internal step-down voltage Vcc. When the high level bit line equalize control signal BRS is input to the bit line equalize circuit 107, the NMOS transistor Tr6 is turned on and the bit lines BLX and BLZ are short-circuited, and at the same time, the NMOS transistors Tr7 and Tr8 are turned on and the bit line BLX is turned on. And BLZ are charged to the equalize voltage Vpr to initialize the bit line. Similarly, when the high level PSA / NSA line equalization control signal BRSS is input to the PSA / NSA equalization circuit 111, the sense amplifier activation lines PSA, NSA are initialized to the equalize voltage Vpr.
[0041]
When the memory block BLK1 is selected, the charge (information) of the memory cell connected to any one of the word lines swl0... Is transmitted to the bit line BLLZ or BLLX. At this time, since the voltage difference between the bit lines BLLZ and BLLX is minute, it is necessary to perform differential amplification by the sense amplifier S / A. Sense amplifier active lines PSA and NSA are connected to the sense amplifier, and are connected to the internal step-down voltage Vcc and the ground voltage Vss through transistors Tr1 and Tr2, respectively.
[0042]
In order to read out the charge of the memory cell selected by one selected word line of the word lines swl0... By differential amplification by the sense amplifier S / A, first, the isolation gate BTL is in a conductive state. Isolation gate BTR is turned off. Next, a high level sense amplifier activation signal LE is output from the LE generation circuit 115, and the transistors Tr1 and Tr2 are turned on. As a result, the internal step-down voltage Vcc is supplied to the sense amplifier active line PSA and the ground voltage Vss is supplied to the sense amplifier active line NSA, so that the sense amplifier S / A is activated.
[0043]
After restoration of the bit lines BLLZ and BLLX, a low level sense amplifier activation signal LE is output from the LE generation circuit 115, and the transistors Tr1 and Tr2 are turned off. Further, after the selected word line is deactivated, equalization between the bit lines BLZ and BLX and between the sense amplifier activation lines PSA and NSA is performed by the low level of the equalization control signal EQ, and the next memory cell charge Preparation for reading is completed. At this time, it is necessary that the bit line BLRZ-BLRX in the non-selected memory block BLK2 is also maintained at the equalize voltage Vpr.
[0044]
FIG. 2 shows a control circuit for the separation gate of the non-selected memory block. FIG. 3 is a timing chart when the control circuit for the separation gate of FIG. 2 is applied to FIG.
[0045]
In FIG. 1, when the block BLK1 is selected and the self-refresh operation is performed, the word lines swl0... Are sequentially activated with the equalization operation of the bit lines BLLZ and BLLX between them. The n / k activation control signal φ activates the bit line isolation gate BTR on the non-selected block BLK2 side for n times (n ≦ k−1) of the k bit line equalization operations, and the bit line BLRZ, This is a control signal for equalizing BLRX. The word line swl0 of the block BLK1 is “m-th word line activation → equalization of bit lines BLLZ and BLLX → m + 1th activation of word line → equalization of bit lines BLLZ and BLLX”. The word lines are sequentially activated while being repeatedly activated and equalized. Among them, every time k / n word lines are activated, the isolation gate BTR is turned on in the equalizing period of the bit line immediately after that. When the block BLK2 is selected and the refresh operation is performed, the operation opposite to the above is performed. That is, every time k / n word lines in the block BLK2 are activated, the isolation gate BTL is turned on in the equalizing period of the bit line immediately after that.
[0046]
FIG. 2 shows a generation control circuit for the n / k activation control signal φ. The configuration example of FIG. 2 includes an isolation gate 121, a BT control circuit 123, and a logic unit 124. FIG. 2 shows a case where n = k / 23, which is a configuration example in which the isolation gate 121 becomes conductive every time the eight word lines are activated. When a low level n / k activation control signal φ is input from the BT control circuit 123 to the bit line isolation gate 121, the isolation gate 121 is turned off and the high level n / k activation control signal φ is set to the bit line. When input to the isolation gate 121, the isolation gate 121 is turned on.
[0047]
The BT control circuit 123 includes a latch circuit 125. An NMOS transistor is connected between the nodes N1 and N2 between the ground voltage Vss. The set signal set is input to the NMOS on the node N1 side, and the reset signal rst and the control signal norstx are input to the NMOS connected in series on the node N2 side. The signal φ becomes low level when the set signal set becomes high level and the node N1 is set to the ground voltage Vss, and during the access operation in the selected memory block. The isolation gate to the non-selected block becomes non-conductive. On the other hand, the φ signal becomes high level when both the reset signal rst and the control signal norstx become high level and the node N2 is set to the ground voltage Vss. This time is a bit line equalization operation in the selected memory block and a timing that matches a control condition in a logic unit 124 described later. At that time, the isolation gate 121 to the non-selected block becomes conductive.
[0048]
The NAND gate 126 of the logic unit 124 inverts and outputs the logical product of the lower three bits of the refresh addresses rfaz1 to rfaz3. Further, the NOR gate 127 inverts the logical sum of the refresh operation control signal REN and the output signal of the NAND gate 126 and outputs the control signal norstx.
[0049]
The refresh operation control signal REN is at a low level during the refresh operation. In this operation state, the NOR gate 127 outputs the high level control signal norstx only when the refresh addresses rfaz1 to rfaz3 are all at the high level. That is, the output of the logic unit 124 is set to the high level only once out of 8 times when the refresh address transitions.
[0050]
The control signal norstx of the logic unit 124 is input to the BT control circuit 123. The reset signal rst is set to the high level for each equalization period in the selected memory block, but the control signal norstx is set to the high level only once in the eight equalization periods as described above. Only high times. Therefore, isolation gate 121 is rendered conductive only once for eight equalizing operations.
[0051]
Further, the logic unit 128 may be used instead of the logic unit 124. The logic unit 128 includes an edge detection circuit 129, and receives a refresh operation control signal REN and a refresh address rfaz4. The refresh operation control signal REN is at a low level during the refresh operation, and at this time, the edge detection circuit 129 is in an operating state.
[0052]
The refresh address rfaz4 is an address one bit higher than the refresh addresses rfaz1 to rfaz3, and the state transitions from the high level to the low level or from the low level to the high level for every logical combination of the rfaz1 to rfaz3. In response to this state transition, a high-level pulse wave is output from the edge detection circuit 129 and input to the BT control circuit 123 as the control signal norstx. When both the reset signal rst and the control signal norstx are at the high level and the node N2 is at the ground voltage Vss, the n / k activation control signal φ is at the high level, and the isolation gate 121 is turned on. Therefore, even when the logic unit 128 is used, the isolation gate 121 is turned on only once per eight equalizing operations.
[0053]
In this way, by using the refresh address for controlling the separation gate, it is not necessary to newly input or generate a dedicated timing signal.
[0054]
FIG. 3 shows a timing chart. A self-refresh operation is performed in response to the “high” level (active) of the self-refresh enable signal SREFE. During the period in which the block BLK1 is self-refreshed, the control signal sbltlx is maintained at the “high” level, the isolation gate BTL is turned on, and the bit lines BLLZ and BLLX of the block BLK1 are connected to the bit lines BLZ and BLX. to continue. During that period, in response to the / RAS "low" level transition, the word lines swl0... Are sequentially activated to access the memory cells, restore BLLZ and BLLX, and respond to the / RAS "high" level transition. The word lines swl0... Are sequentially deactivated and the bit lines BLLZ and BLLX are equalized.
[0055]
Each time activation for eight consecutive word lines is completed, in the subsequent equalization period, the bit line isolation gate control signal sbltrx is set to “high” level once, and the isolation gate BTR is made conductive. Bit lines BLRZ and BLRX are connected to bit lines BLZ and BLX. Then, the bit lines BLLZ and BLLX of the selected block BLK1 are equalized, and the bit lines BLRZ and BLRX of the non-selected block BLK2 are also equalized.
[0056]
In the first embodiment shown in FIG. 3, the control signal sbltrx of the separation gate on the non-selected block BLK2 side is set to the “high” level for each equalizing period of the selected block BLK1 in the first embodiment shown in FIG. It can be seen that the charge / discharge current can be reduced by the switching operation by reducing the number of switching of the separation gate of the non-selected block to 1/8.
[0057]
If the control method of the separation gate of the first embodiment shown in FIG. 3 is used, the sense amplifier S / S as shown in FIG. 1 can be provided without providing the bit lines equalizing circuit in both of the memory blocks BLK1 and BLK2. Even a circuit configuration having a bit line equalize circuit on the A side can solve the problem caused by floating of the bit line potential. Therefore, the problem of floating of the bit line potential can be solved by the low current consumption operation while suppressing the increase of the chip area.
[0058]
Of course, the activation frequency of the activation control signal φ of the isolation gate is not limited to the value of ８ used in the first embodiment, and it is needless to say that it can be appropriately optimized according to each semiconductor memory device. Yes.
[0059]
The addresses input to the NAND gate 126 of the logic unit 124 and the edge detection circuit 129 of the logic unit 128 shown in FIG. 2 are not limited to the refresh address, and for example, addresses for continuous access such as a burst operation can be used. At this time, a signal input to the NOR gate 127 and the edge detection circuit 129 becomes a continuous access control signal or the like instead of the refresh operation control signal REN.
[0060]
Next, a control method for the equalize circuit in the first embodiment will be described.
[0061]
If the voltage of the control signal BRS for controlling the bit line equalizing circuit 107 and the voltage of the control signal BRSS for controlling the PSA / NSA equalizing circuit 111 are set according to the wiring capacitance to be equalized, the bit line BLZ− Occurrence of equalization time difference between BLX and sense amplifier active line PSA-NSA can be suppressed.
[0062]
In FIG. 1, an inverter gate 109 that outputs an equalize control signal BRSS for the sense amplifier activation lines PSA / NSA has a voltage level conversion function, and an internal step-down voltage Vcc is converted into a step-up voltage Vpp and supplied. Yes. On the other hand, in the inverter gate 110 that outputs the bit line equalize control signal BRS, the internal step-down voltage Vcc is supplied without voltage level conversion.
[0063]
While shortening the bit line length, the line lengths of the sense amplifier active lines PSA and NSA are not changed, so that the wiring capacity of the bit line is lowered and the wiring capacity of the sense amplifier active line is not changed. Therefore, when the equalizing time of the bit line and the sense amplifier active line is not changed before and after the change of the bit line length, the PSA / NSA equalizing circuit 111 is compared with the driving capability of the transistor used in the bit line equalizing circuit 107. The driving capability of the transistors used in the above must be increased.
[0064]
In the first embodiment, the boosted voltage Vpp is used for the PSA / NSA line equalize control signal BRSS, and the internal step-down voltage Vcc is used for the bit line equalize control signal BRS. As a result, as shown by the solid line portion in FIG. 4, as a first effect, the time difference between the equalization time between the bit lines BLZ and BLX and the equalization time between the sense amplifier active lines PSA and NSA can be reduced. . By equalizing BLZ-BLX and PSA-NSA at the same timing, it is possible to prevent a short-circuit abnormal current in the sense amplifier S / A due to equalization and reduce current consumption. As a second effect, by using the internal step-down voltage Vcc instead of the step-up voltage Vpp as the control signal BRS, the equalization circuit transistor using the step-up voltage Vpp is not increased without increasing the equalization time between BLZ and BLX and between PSA and NSA. Drive current consumption can be reduced. In addition, the current consumption of the booster circuit (not shown) can be reduced.
[0065]
Of course, when the relationship of the equalization time difference between BLZ-BLX and PSA-NSA is reversed due to the fact that the wiring capacity of the bit line is larger than the wiring capacity of the sense amplifier active line, the control signal BRS By changing the voltage to be used from the internal step-down voltage Vcc to the boosted voltage Vpp and the voltage to be used for the control signal BRSS from the boosted voltage Vpp to the internal step-down voltage Vcc, the same effect can be obtained in reducing the equalization time difference and reducing current consumption. .
[0066]
The value of the power supply voltage for driving the equalize circuits 107 and 111 is not limited to the boosted voltage Vpp and the internal step-down voltage Vcc used in this specific example. For example, it is possible to drive equalize circuits 107 and 111 using any appropriate combination of external voltage Vdd, boosted voltage Vpp, and internal step-down voltage Vcc in accordance with each semiconductor memory device.
[0067]
Furthermore, if the control method of the isolation gate used in the first embodiment and the control method of the equalize circuit are combined, it is possible to further reduce the current consumption while suppressing an increase in memory cell area and a decrease in access operation speed. Can do.
[0068]
In the second embodiment shown in FIG. 5, two bit line equalize circuits 132 and 133 are provided in place of the bit line equalize circuit 107 of the first embodiment shown in FIG. 1, and the bit lines BLLZ and BLLX are respectively connected. Are connected between the bit lines BLRZ and BLRX. The equalization control signal EQ is input to the BRS generation circuit 131, and the voltage-converted bit line equalization control signals BRSL and BRSR are output and input to the bit line equalization circuits 132 and 133, respectively. The configuration and operation of bit line equalize circuits 132 and 133 are the same as those of equalize circuit 107 (FIG. 1). Even when the bit line isolation gate of the non-selected memory block is maintained in a non-conductive state, the circuit configuration can solve problems such as the possibility of data destruction due to floating of the bit line potential.
[0069]
Also in the circuit configuration of FIG. 5, the same effect as that of the first embodiment can be obtained by using the control method of the equalizing circuit of the first embodiment. That is, when the bit line lengths of the bit lines BLLZ, BLLX, BLRZ, and BLRX are configured shorter than before, the boost voltage Vpp is used for the PSA / NSA line equalize control signal BRSS, and the internal voltage is decreased for the bit line equalize control signals BRSL and BRSR. The voltage Vcc may be used.
[0070]
As a result, the time difference between the equalization times of both is reduced, so that an abnormal current short-circuited in the sense amplifier S / A due to equalization can be prevented, and current consumption can be reduced. In addition, by using internal step-down voltage Vcc for equalize control signals BRSL and BRSR, the drive current consumption of the transistors of the equalize circuit by boosted voltage Vpp can be reduced without increasing the equalization time of the bit line and the sense amplifier active line. In addition, the current consumption of the booster circuit (not shown) can be reduced. When the bit line wiring capacity is larger than the sense amplifier active line wiring capacity, the voltage used for control signals BRSL and BRSR is changed from internal step-down voltage Vcc to step-up voltage Vpp, and to PSA / NSA line equalization control signal BRSS. If the voltage to be used is changed from the boosted voltage Vpp to the internal step-down voltage Vcc, the same effect can be obtained.
[0071]
In the third embodiment of FIG. 6, three bit line equalize circuits 134, 135, 136 are used in place of the bit line equalize circuits 132, 133 of the second embodiment shown in FIG. And BLLX, between bit lines BLZ and BLX, and between bit lines BLRZ and BLRX. In addition, bit line equalization control signals BRSL, BRS, BRSR are input, respectively. The configuration and operation of bit line equalize circuits 134, 135, and 136 are the same as those of equalize circuit 107 (FIG. 1). Even when the bit line isolation gate of the non-selected memory block is maintained in a non-conductive state, the circuit configuration can solve problems such as the possibility of data destruction due to floating of the bit line potential.
[0072]
Also in the circuit configuration of FIG. 6, it is possible to obtain the same effect as that of the first embodiment by using the equalizing circuit control method of the first embodiment. That is, when the bit lines BLLZ, BLLX, and BLRZ, BLRX are configured to have a bit line length shorter than the conventional one, the boost voltage Vpp is used for the control signal BRSS, and the internal internal step-down voltage Vcc is used for the control signals BRS, BRSL, and BRSR. That's fine.
[0073]
As a result, the time difference between the equalization times of the two is reduced, so that an abnormal current short-circuited in the sense amplifier S / A due to equalization can be prevented, and current consumption can be reduced. In addition, the driving current consumption of the transistors of the equalizing circuit and the current consumption of the boosting circuit by the boosted voltage Vpp can be reduced without increasing the equalizing time of the bit line and the sense amplifier active line. If the bit line wiring capacity is larger than the sense amplifier active line wiring capacity, the same effect can be obtained by using the boosted voltage Vpp for the bit line equalization control signals BRS, BRSL and BRSR and the internal step-down voltage Vcc for the control signal BRSS. An effect is obtained.
[0074]
In the fourth embodiment of FIG. 7, three bit line equalize circuits 137, 138 and 139 are used in place of the bit line equalize circuit of the third embodiment of FIG. 6, and the bit lines BLLZ and BLLX are respectively connected. Are connected between the bit lines BLZ and BLX and between the bit lines BLRZ and BLRX. Also, bit line equalize control signals BRSL, BRS, BRSR are connected to each other. Bit line equalize circuits 137 and 139 are composed of two NMOS transistors and have a function of supplying equalize voltage Vpr to the bit lines. The equalizing circuit 138 is composed of one element NMOS transistor and has a function of shorting the bit lines BLZ and BLX.
[0075]
In this circuit configuration, even when the bit line isolation gate of the non-selected memory block is maintained in a non-conductive state, there is no possibility of data destruction due to floating of the bit line potential. In addition, the number of transistor elements used for bit line equalization can be reduced as compared with the second and third embodiments (FIGS. 5 and 6), and the chip area can be reduced. That is, in the second embodiment (FIG. 5), six elements are required in the bit line equalize circuits 132 and 133, and in the third embodiment (FIG. 6), nine elements are required in the bit line equalize circuits 134, 135, and 136. On the other hand, in FIG. 7, a circuit configuration is possible with a total of five elements in the bit line equalize circuits 137, 138, and 139. Also in the circuit of FIG. 7, it is possible to obtain the same effect as in the first embodiment by using the equalizing circuit control method of the first embodiment.
[0076]
In the fifth embodiment of FIG. 8, three equalize circuits 140, 141, 142 are provided in place of the bit line equalize circuits 137, 138, 139 of the fourth embodiment of FIG. 7, and the bit lines BLLZ and BLLX are respectively provided. Between the bit lines BLZ and BLX and between the bit lines BLRZ and BLRX. In addition, bit line equalization control signals BRSL, BRS, BRSR are input, respectively. Equalize circuit 141 and equalize circuits 137 and 139 in FIG. 7 have the same circuit configuration, and equalize circuits 140 and 142 and equalize circuit 138 in FIG. 7 have the same circuit configuration.
[0077]
With this circuit configuration, the equalizing circuits 140 to 142 can be configured with a total of four transistor elements. On the other hand, the equalize circuits 137 to 139 in the fourth embodiment shown in FIG. 7 require a total of five elements. Therefore, compared with the equalize circuit of the fourth embodiment, the circuit area of the fifth embodiment can further reduce the chip area.
[0078]
Also in the circuit of the fifth embodiment, as described in the fourth example (FIG. 7), the same effect as that of the first embodiment can be obtained by using the control method of the equalizing circuit of the first embodiment. Is possible. Further, as in the first embodiment (FIG. 1), it is preferable to further use a method for controlling the isolation gate in order to prevent the bit line on the non-selected block side from floating.
[0079]
In the sixth embodiment, a case where an alternative sense amplifier S / As is used in place of the sense amplifier S / A in the third to fifth embodiments (FIGS. 6 to 8) will be described. The alternative sense amplifier S / As is supplied with the internal step-down voltage Vcc and the ground voltage Vss when the low level and high level signals are input to the sense amplifier control signals LEX and LEZ, respectively. This is a configuration that is in an active state. Further, due to the difference in wiring capacity, the time when the outer bit line pair BLLZ-BLLX, BLRZ-BLRX in the selected memory block ends equalization, and the time when the inner bit line pair BLZ-BLX connected to the alternative sense amplifier ends equalize There may be a time difference. Then, the equalization time is limited to the longer one, and the original operation performance of the semiconductor memory device cannot be realized.
[0080]
In FIG. 6 of the third embodiment, by configuring the line lengths of the bit lines BLLZ and BLLX in the memory block BLK1 and the bit lines BLRZ and BLRX in the memory block BLK2 to be shorter than those in the related art, the alternative sense amplifier S / Consider a case where the wiring capacity of the bit lines in the memory block is smaller than the wiring capacity of the bit lines BLZ and BLX to which As is connected. At this time, assuming that the internal step-down voltage Vcc is used for both the control signal line BRSL of the bit line equalize circuit 134 and the control signal line BRS of the equalize circuit 135, as shown in FIG. 9, the bit lines BLLZ-BLLX The equalizing time between BLLZ and BLLX is faster than the equalizing time between the bit lines BLZ and BLX.
[0081]
Therefore, if the control signal BRSL of the equalize circuit 134 is controlled by different voltages such that the internal step-down voltage Vcc is used for the control signal BRSL and the boost signal Vpp is used for the control signal BRS of the equalize circuit 135, Equalization time difference is reduced. That is, in FIG. 9, the equalization time between BLZ and BLX is shortened (from the wavy line portion to the solid line portion in FIG. 9), so that the time difference between equalization of both bit lines is reduced. Of course, when the memory block BLK2 is selected, the same effect can be obtained if the internal step-down voltage Vcc is used for the control signal BRSR and the step-up voltage Vpp is used for the control signal BRS.
[0082]
Of course, because the wiring capacity of the bit lines BLLZ and BLLX in the memory block increases compared to the wiring capacity of the bit lines BLZ and BLX to which the alternative sense amplifier S / As is connected, When the relationship of the equalization time difference between BLLZ and BLLX is reversed, the voltage used for control signal BRS is changed from boosted voltage Vpp to internal reduced voltage Vcc, and the voltage used for control signal BRSL is changed from internal reduced voltage Vcc to boosted voltage Vpp. The same effect can be obtained by changing and reducing the equalization time difference. The value of the power supply voltage for driving the equalizing circuit is not limited to the boosted voltage Vpp and the internal stepped-down voltage Vcc used in the sixth embodiment. For example, the equalize circuit can be driven using any appropriate combination of external voltage Vdd, boosted voltage Vpp, and internal step-down voltage Vcc in accordance with each semiconductor memory device.
[0083]
Also in the fourth embodiment (FIG. 7) and the fifth embodiment (FIG. 8), it is possible to use an equalize circuit using an alternative sense amplifier S / As by the control method shown in the sixth embodiment. it can.
[0084]
The present invention is not limited to the above-described embodiment, and it goes without saying that various improvements and modifications can be made without departing from the spirit of the present invention. Needless to say, the control method of the bit line isolation gate, the control method of the bit line and sense amplifier active line equalizing circuit, the arrangement and circuit configuration of the equalizing circuit can be combined as appropriate.
[Brief description of the drawings]
[0085]
FIG. 1 is a diagram showing a part of a shared sense amplifier system in a semiconductor memory device according to a first embodiment.
FIG. 2 is a control circuit diagram of an isolation gate of an unselected memory block in the first embodiment.
FIG. 3 is a timing chart showing the operation of the semiconductor memory device of the first embodiment.
FIG. 4 is a diagram showing a relationship between equalization time between bit lines and equalization time between sense amplifier active lines in the first embodiment;
FIG. 5 is a diagram showing a part of a shared sense amplifier system in the semiconductor memory device of the second embodiment.
FIG. 6 is a diagram showing a part of a shared sense amplifier system in a semiconductor memory device according to a third embodiment.
FIG. 7 is a diagram showing a part of a shared sense amplifier system in the semiconductor memory device of the fourth embodiment.
FIG. 8 is a diagram showing a part of a shared sense amplifier system in a semiconductor memory device according to a fifth embodiment.
FIG. 9 is a diagram illustrating a relationship between an equalizing time between inner bit lines and an equalizing time between outer bit lines according to the sixth embodiment;
FIG. 10 is a diagram showing a part of a conventional shared sense amplifier system;
FIG. 11 is a timing chart showing the operation of a conventional semiconductor memory device.
FIG. 12 is a second timing chart showing the operation of the conventional semiconductor memory device.
FIG. 13 is a diagram showing a relationship between equalization time between bit lines and equalization time between sense amplifier active lines in the prior art.
FIG. 14 is a second diagram showing a relationship between equalization time between bit lines and equalization time between sense amplifier active lines in the prior art.

Claims (3)

A first memory block from which stored information is read out to a first bit line pair in accordance with a selected word line;
A second memory block from which stored information is read out to a second bit line pair in accordance with a selected word line;
In a semiconductor memory device comprising: a sense amplifier shared for each of the first bit line pair and the second bit line pair;
A first isolation gate for controlling connection / separation between the first bit line pair and the sense amplifier;
A second isolation gate for controlling connection / separation between the second bit line pair and the sense amplifier;
An equalizing unit for equalizing the first bit line pair and the second bit line pair;
The signal for activating the first isolation gate is a predetermined logical combination of a refresh address for identifying k word lines successively selected in the second memory block and an equalizing period. A semiconductor memory device comprising: a reset signal indicating that the control circuit is generated based on the reset signal. A first memory block from which stored information is read out to a first bit line pair in accordance with a selected word line;
A second memory block from which stored information is read out to a second bit line pair in accordance with a selected word line;
A sense amplifier shared for each of the first bit line pair and the second bit line pair ;
A first isolation gate for controlling connection / separation between the first bit line pair and the sense amplifier;
A second isolation gate for controlling connection / separation between the second bit line pair and the sense amplifier;
An equalizing unit for performing an equalizing operation for equalizing the first bit line pair and the second bit line pair;
In a method for controlling a semiconductor memory device comprising:
For the second bit line pairs, and restore operations following the word line selection, and the selected block the refresh step of equalizing operation is repeatedly performed successively after their,
In the second memory block, the first bit line is set based on a refresh signal that identifies a predetermined logical combination of k address lines selected in succession and a reset signal indicating an equalization period. A control method for a semiconductor memory device, comprising: a non-selected block equalizing step for connecting a pair and the sense amplifier. A first memory block from which stored information is read out to a first bit line pair in accordance with a selected word line;
A second memory block from which stored information is read out to a second bit line pair in accordance with a selected word line;
In a semiconductor memory device comprising: a sense amplifier shared for each of the first bit line pair and the second bit line pair;
A first isolation gate for controlling connection / separation between the first bit line pair and the sense amplifier;
A second isolation gate for controlling connection / separation between the second bit line pair and the sense amplifier;
An equalizing unit for equalizing the first bit line pair and the second bit line pair;
A refresh address one bit higher than a refresh address for identifying k word lines selected in succession in the second memory block is set to a logic state in order to activate a signal for activating the first isolation gate. A semiconductor memory device comprising: a control circuit that is generated based on a transition and a reset signal indicating an equalization period.

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