JP4024005B2 - DMA controller device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a DMA controller device that accesses a common memory device from a DMA through a bus.
[0002]
[Prior art]
Many DMAs are built in the controller device, and a circuit is formed so as to access a common memory device from these DMAs through a bus. Therefore, contention occurs on the bus at the time of access, and a memory arbiter is provided to mediate this. The memory arbiter arbitrates memory access and sequentially accesses the memory.
In recent years, the operating speed of memory devices has influenced system performance, and development of high-speed memory devices has progressed. As the memory device access speed increases, the system performance depends on the speed of the interface (I / F) circuit connected to the DMA. Therefore, as the memory device speed increases, the interface (I / F) circuit performance increases. The speed is also following up.
[0003]
[Problems to be solved by the invention]
However, in a system in which a plurality of interface (I / F) circuits are connected, each DMA is prioritized by a memory arbiter and is accessed for memory. Therefore, an interface (I / F) connected to a DMA with a lower priority is used. The circuit has a problem that when the memory access requests of a plurality of DMAs compete, even if the interface (I / F) circuit speeds up, the circuit performance is hardly useful.
[0004]
The present invention has been made in view of such problems, and a low-priority DMA connected to a high-speed interface (I / F) circuit is connected to another interface (I / F) circuit. in case of conflict with DMA and is also, it is desirable to make the deterioration of the performance of the system does not occur.
[0005]
[Means for Solving the Problems]
The invention according to claim 1, a memory arbiter for arbitrating access to a shared memory, a plurality of DMA priority of the memory access is predetermined, the contention of the DMA memory access requests according to the priority, the A DMA controller having an interface circuit connected to each of the DMAs, wherein when the plurality of DMA memory access requests conflict, the DMA controller device accesses the memory in the order of the priorities. Means for measuring the number of requested conflicts, and an interface circuit in which the number of conflicts is equal to or greater than a predetermined number and the interface circuit connected to the DMA having the lowest priority is connected to another DMA when it is higher speed, the lowest priority DMA memory access Day The burst length, the longer the range of the data of continuous memory address, by having means for reducing the number of memory commands the DMA, by speeding up of the interface circuit in which the priority is connected to the lowest DMA A DMA controller device characterized in that performance is improved .
[0009]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described.
FIG. 1 is a block diagram of a main part of a DMA controller apparatus to which the present invention is applied. In response to a data transfer request from each device (not shown), the I / F1 circuits 31 to I / F3 circuit 33 are respectively DMA1 circuits 41 to DMA3. A request is issued to the circuit 43. Each of the DMA circuits 41 to 43 requests the memory arbiter circuit 1 to arbitrate bus contention.
The memory arbiter circuit 1 accepts a request with a predetermined priority of DMA1>DMA2> DMA3, and further issues an access request to the external memory 3 to the memory interface (I / F) circuit 2. The memory interface (I / F) circuit 2 issues a command to the external memory 3 to access the memory 3 in accordance with the determined priority.
[0010]
2 to 4 are timing charts showing the relationship between access data and access time. In the figure, CLK represents a memory access clock, and ICLK represents an I / F clock.
Each of DMA1, DMA2, and DMA3 is a memory command, so that the data accessed by the DMA1 circuit 41 is Dat1-1, Dat1-2, and the data accessed by the DMA2 circuit 42 is Dat2-1, Dat2. -2 and the data accessed by the DMA3 circuit 43 are Dat3-1 and Dat3-2.
Further, CMD1, CMD2, and CMD3 are memory commands for the interface (I / F) circuit 31, the interface (I / F) circuit 32, and the interface (I / F) circuit 33, respectively. / F) Data to access the circuit 31 is Data1-1 and Data1-2, and data to access the interface (I / F) circuit 32 is to Data2-1, Data2-2 and the interface (I / F) circuit 33. Data to be accessed is Data3-1 and Data3-2.
The memory arbiter is prioritized in the order of DMA1>DMA2> DMA3. 2 to 4, the burst length of the memory access data at this time is 4 CLK for each DMA.
[0011]
FIG. 3 is a timing chart showing the relationship between access data and access time when the access speed of the interface (I / F) circuit 33 is increased from the state of FIG.
In FIG. 2, the data access period is 4 ICLK for accessing Data 3-1, but in the case of FIG. 3, the same data access may be 2 ICLK for speeding up.
However, since the data access of the interface (I / F) circuit 33 is completed when the access of Data3-2 is completed, it ends with ICLK14, which is only 2ICLK earlier than in FIG.
[0012]
Therefore, the burst length of only the memory access data by the DMA3 circuit 43 having a low priority is superior to that of the interface (I / F) circuit 43 without changing the priority of the memory access by the DMA3 circuit 43 of the interface (I / F) circuit 33. (In this case, two DMAs, DMA1 and DMA2). Then, it is accessed with one memory command.
[0013]
FIG. 3 is a timing chart showing the relationship between the access data and the access time when Dat3-1 and Dat3-2 are accessed in 8 CKL with one memory command.
By increasing the burst length of the memory access data and accessing it with one memory command in this way, the WAIT state by the burst arbiter is relaxed, and the I / F3 data access end period becomes ICLK9, and the I / F3 speed increases. Can be made effective.
[0014]
In order to perform this specifically, the memory arbiter circuit 1 (FIG. 1) confirms the number of conflicts (request number) with other DMA circuits with respect to the request of the DMA3 circuit 43, and exceeds the predetermined number of requests. In this case, the bsize signal for determining the burst length of the external memory access 3 is switched to the longer burst length.
The DMA1 circuit 41 and the DMA2 circuit 42 have a fixed burst length. The memory interface (I / F) circuit 2 determines the burst length by the bsize signal, issues a command to the external memory 3 and accesses it.
[0015]
Further, when the memory arbiter circuit 1 receives a request from the DMA3 circuit 43, it confirms the number of conflicts (the number of requests from other DMA circuits) and switches to add a predetermined burst length. Furthermore, the burst size to be switched can be set.
[0016]
According to this embodiment, it is possible to easily change the burst length according to the situation, and to avoid excessively affecting other interface (I / F) circuits, thereby avoiding deterioration of system performance.
[0017]
【The invention's effect】
According to the present invention, when a DMA having the lowest priority connected to an accelerated interface (I / F) circuit competes with another DMA, only the DMA having the lowest priority has a burst length of memory access data. By reducing the number of memory commands of the DMA by increasing the length in the range of data at consecutive memory addresses, it is possible to avoid the performance degradation of the system .
[Brief description of the drawings]
FIG. 1 is a block diagram of a main part of a DMA controller device to which the present invention is applied.
FIG. 2 is a timing chart showing a relationship between access data and access time according to the embodiment of the present invention.
FIG. 3 is a timing chart showing the relationship between access data and access time according to the embodiment of the present invention.
FIG. 4 is a timing chart showing the relationship between access data and access time according to the embodiment of the present invention.
[Explanation of symbols]
1. Memory arbiter circuit 2. Memory I / F circuit 3. External memory

Claims (1)

Each of the DMAs is connected to a plurality of DMAs that access a common memory and have a memory access priority determined in advance, a memory arbiter that arbitrates contention for memory access requests of the DMA according to the priority, and the DMA. And a DMA controller device that accesses the memory in the order of priority when a plurality of memory access requests of the DMA compete with each other, and measures the number of conflicts of the memory access request of the DMA with the lowest priority. And when the interface circuit connected to the DMA having the lowest priority is faster than the interface circuits connected to other DMAs, and the contention number is equal to or greater than a predetermined number. is the burst length of the memory access data of the lowest priority DMA, The longer the range of the data of memory address continue, by having means for reducing the number of memory commands the DMA, to perform the performance improvement by faster interface circuit in which the priority is connected to the lowest DMA A DMA controller device characterized by the above.

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