JP4335327B2 - Arbitration apparatus and method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an arbitration device and method, and more specifically, can store digitally compressed or decompressed data such as video and audio, and a CPU (computer processing unit) program in a mixed manner. The present invention relates to an arbitration apparatus and method in a system having a shared memory.
[0002]
[Prior art]
In recent years, as represented by digital broadcast receivers and the like, digital still images and natural images of moving images and geometric graphics display by CPU etc. can be displayed simultaneously. Do Video systems have become commonplace. In this video system, the CPU, each processing device that performs digital image display and graphics display has a memory of a necessary capacity for each processing device, and data can be transferred to the memory when necessary. It was possible.
[0003]
FIG. 13A is a block diagram showing an example of the configuration of a conventional video system.
13A, the conventional video system includes a tuner / demodulator 501, an MPEG (Moving Picture Experts Group) TS decoder 502, an MPEG AV decoder 504, a graphics control 506, and a CPU 508. . Each of these processing devices has its own local memory 503, 505, graphic memory 507, and program memory 509, and individually transfers data as necessary. Go ing.
However, with an increase in memory capacity and memory transfer speed that can be built in one chip due to recent technological innovations, there has been a tendency for memories distributed to each processing device to be shared.
[0004]
FIG. 13B is a block diagram showing an example of the configuration of a conventional video system in which the memory is shared.
The conventional video system shown in FIG. 13B has the functions of the TS decoder 502, the AV decoder 504, the graphics control 506, and the CPU 508 that are individually configured in the conventional video system shown in FIG. The function blocks 520 are collectively configured. Further, the local memories 503 and 505, the graphic memory 507, and the program memory 509 are shared and configured as one memory block 530.
[0005]
Thus, when data transfer is performed from a plurality of processing devices to one memory block 530, an arbitration device that arbitrates data transfer between the function block 520 and the memory block 530 is necessary. The arbitrating device determines a data transfer order by a predetermined method in response to a data transfer request competing from each processing device.
[0006]
FIG. 14 is a diagram illustrating an example of main components of a video system using a conventional arbitration device 540.
Referring to FIG. 14, arbitration device 540 receives a function BR 520, that is, a signal BR (Bus Request) indicating a data transfer request from each processing device, determines a transfer order using a certain method, and arbitrarily A signal BG (Bus Grant) indicating data transfer permission is output to one processing apparatus. The processing apparatus that has received this transfer permission BG starts data transfer thereafter.
[0007]
Conventionally, a fixed priority method, a round robin method, or the like is used as a method for determining the data transfer order in the arbitration device 540.
Hereinafter, with reference to FIGS. 15 to 17, among the round robin schemes, the bus use right residence round robin scheme will be described as an example.
[0008]
FIG. 15 is a block diagram showing an example of a configuration of a conventional bus use right residence round robin arbitration device. FIG. 16 is a diagram showing state transition of the conventional bus use right residence round robin arbitration method of FIG. FIG. 17 is a diagram showing an example of data transfer timing in the conventional arbitration system of FIG. The signal in FIG. 17 is low active.
In the following, in FIG. 15 to FIG. 17, a data transfer request is made for ease of explanation. Do A case where there are two processing devices, the first processing device and the second processing device, will be described.
[0009]
In FIG. 15, when a transfer request BRi is received from an i-th (i is 1 or 2, the same applies hereinafter) processing device, the transfer request reception unit 541 is in use (busy) by any of the processing devices. A signal BB (Bus Busy) indicating that the bus is in use is determined. The bus busy BB is a signal that becomes active when any of the processing apparatuses uses the bus. If the bus is not in use at the time of this determination, the transfer request reception unit 541 issues a transfer permission request signal to the transfer permission output unit 542. Upon receiving the transfer permission request signal, the transfer permission output unit 542 determines where the right to use the bus (referred to as a preferential right that the bus can be used immediately) resides at that time. Here, if the transfer request BRi is a request from a processing device in which the right to use the bus is present, the transfer permission BGi has already been issued, so the transfer permission BGi is continuously issued to the processing device. to continue. On the other hand, if the transfer request BRi is a request from a processing device that does not have the right to use the bus, transfer permission BGi is output to the processing device.
[0010]
In this way, the processing device in which the right to use the bus resides can start data transfer simultaneously with outputting the transfer request signal BRi to the arbitrating device 540. On the other hand, the processing device that does not have the right to use the bus can start data transfer only after outputting the transfer request signal BRi to the arbitrating device 540 and receiving the transfer permission signal BGi.
[0011]
Next, referring to FIG. 16, a state transition of a conventional bus use right residence round robin arbitration device will be described. In FIG. 16, a circle figure represents a state, and an arrow represents a state transition. The state “resident i” indicates that the right to use the bus exists for the i-th processing device, and the state “permission i” indicates that the data transfer permission is granted to the i-th processing device. Indicates that
Also, '! BB & BR1 ′ and the like indicate conditions for transitioning the state. In this case, no bus busy BB is generated and a transfer request BR1 is generated.
[0012]
It is assumed that the initial state is the state “resident 1” (state 601). This state “resident 1” is maintained as long as the second processing device does not issue the transfer request BR2. When only the first processing device issues the transfer request BR1 in the state “resident 1”, the transfer permission BG1 has already been output, and thus the state “resident 1” is maintained (transition 621). Data transfer is started without. However, when the second processing device outputs the transfer request BR2 in the state “resident 1”, the state transitions to the state “permission 2” and the transfer permission BG2 for the second processing device is output (transition 611). , State 602).
[0013]
In the state “permission 2”, the second processing apparatus given the transfer permission BG2 waits for the data transfer of the first processing apparatus to be completed while watching the bus busy BB (transition 622). To start. Then, when the data transfer of the second processing device is completed, the state transitions to the “resident 2” state and waits until there is a next transfer request BRi (transition 612, state 603). However, if the transfer request BR1 of the first processing device is generated during the data transfer of the second processing device in this state “permission 2”, the direct state “permission 1” is completed after the data transfer of the second processing device is completed. And transfer permission BG1 is issued to the first processing device (transition 616, state 604). Of course, when the transfer request BR2 of the second processing device continues to be issued in the state “permission 2”, the state remains in the state “permission 2” and the processing for the transfer request BR2 from the second processing device is performed. Continue (state 602).
[0014]
The above processing is performed in the same manner in the state “resident 2” and the state “permitted 1” (states 603 and 604).
[0015]
[Problems to be solved by the invention]
However, the arbitration device 540 of the conventional bus use right resident round robin method, in response to a data transfer request from one processing device, when the bus use right is resident with respect to another processing device, There is a problem that a delay of 2 cycles necessarily occurs before starting the data transfer of the processing device (in FIG. 17, after the transfer request BR1 is output at the twelfth clock, the first cycle is output at the fourteenth clock. 2 cycle delay before the data transfer of the processing unit is started).
The arbitration device 540 that has received the data transfer request gives priority to transfer to the same page of the memory 530 and read transfer. Do It is also a problem that it is not considered that this leads to an increase in total transfer efficiency.
Furthermore, even in the case of data transfer that does not require urgency, the data transfer is performed according to the round-robin system where the right to use the bus is located. Done Therefore, there is a problem that the performance of the entire system is reduced.
[0016]
SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide an arbitration device and method that can improve data transfer efficiency as a total and can effectively use the data transfer performance of a memory.
[0017]
[Means for Solving the Problems and Effects of the Invention]
According to a first aspect of the present invention, a conflicting data transfer between a storage device shared by a plurality of processing devices and the plurality of processing devices is transferred to any one of the processing devices having a data transfer request. An arbitration device that gives a right and indicates a transfer order,
Storage means for storing related information such as a transfer address, transfer size, and read / write related to the previous data transfer;
Corresponding to each of the plurality of processing devices, a plurality of comparison means for comparing the related information regarding the data transfer request received this time and the previous related information stored in the storage means,
Transfer order determining means for determining the data transfer order of the plurality of processing devices based on respective comparison results output by the plurality of comparing means and predetermined rules;
Data transfer processing means for granting data transfer rights to a plurality of processing devices in accordance with the transfer order determining means.
[0018]
As described above, according to the first invention, the sameness of related information (for example, page address, bank address, transfer data size, read / write, etc. of transfer data) regarding the currently accepted data transfer request is considered. To determine the order of data transfer. This makes it possible to minimize overhead such as re-input of row (row) address due to change of page address and resetting of command due to change of transfer data size, and data transfer to the storage device. Efficiency can be improved.
[0019]
According to a second aspect of the present invention, data transfer between a storage device shared by first to Nth processing devices (N is an integer of 2 or more) and the first to Nth processing devices is performed as data transfer. An arbitration device that gives a data transfer right to any one of the requested processing devices and instructs the transfer order,
It corresponds to each of the first to N-th processing devices, and counts the time during which data transfer of the corresponding i-th (i = 1, 2,..., N) processing device is not performed. First to Nth non-transfer time counters that clear the count value at the time transfer starts,
Corresponding to each of the first to N-th processing devices, first to N-th registers for storing predetermined values;
When the value of the i-th non-transfer time counter is compared with the value of the i-th register, and the value of the i-th non-transfer time counter reaches the value of the i-th register, a predetermined comparison result First to Nth comparing means for outputting
Transfer order determining means for determining the data transfer order of the first to Nth processing devices based on the respective comparison results output by the first to Nth comparison means;
Data transfer processing means for granting data transfer rights to the first to Nth processing devices according to the transfer order determining means,
Until the value of the i-th non-transfer time counter reaches the value of the i-th register, data transfer other than the i-th processing device is preferentially performed, and the value of the i-th non-transfer time counter corresponds to the i-th register. When the value of this register is reached, data transfer of the i-th processing device is performed.
[0020]
As described above, according to the second invention, the time during which no data is transferred is counted for each processing device, and the data transfer processing of the processing device is limited until a predetermined time is reached. As a result, data transfer of the fixed number of times within a certain time Can do Efficient arbitration of data transfer between a good processing device and an urgent processing device Do be able to. Therefore, it is possible to improve the execution performance of a processing apparatus that needs to perform data transfer with priority.
[0021]
The third invention corresponds to each of the first to N-th processing devices in the second invention, and counts the time during which data transfer of the corresponding i-th processing device is not performed. First to Nth non-transfer limit time counters that clear the count value when the data transfer is completed to the end;
1st to Nth limit time registers that respectively correspond to the first to Nth processing devices and store predetermined values;
When the value of the i-th non-transfer limit time counter is compared with the value of the i-th limit time register, and the value of the i-th non-transfer limit time counter reaches the value of the i-th limit time register , Further comprising first to Nth limit comparing means for outputting a predetermined limit comparison result,
When any one of the first to Nth limit comparison units outputs a limit comparison result, the transfer order determination unit gives priority to the limit comparison result and transfers the data in the first to Nth processing devices. Decide
When the value of the i-th non-transfer limit time counter reaches the value of the i-th limit time register, the data transfer of the i-th processing device is performed with the highest priority until the end.
[0022]
As described above, according to the third invention, in the second invention, the time during which no data is transferred is further counted for each processing device, and the data of each processing device is counted until a predetermined time is reached. In addition to limiting the transfer process, if the limit time is set in the register in advance and the limit time is reached, the data transfer process is performed with the highest priority. This gives priority to data transfer processing of processing devices that require urgency. Do At the same time, it is possible to guarantee the completion of the data transfer within the limit time even for a processing apparatus that does not need urgent but requires a certain amount of data transfer within the limit time.
[0023]
According to a fourth aspect of the present invention, data transfer between a storage device shared by the first to Nth processing devices (N is an integer of 2 or more) and the first to Nth processing devices is performed as data transfer. An arbitration device that gives a data transfer right to any one of the requested processing devices and instructs the transfer order,
It corresponds to each of the first to N-th processing devices, and counts the time during which data transfer of the corresponding i-th (i = 1, 2,..., N) processing device is not performed. First to Nth non-transfer limit time counters that clear the count value when the transfer is completed to the end;
1st to Nth limit time registers that respectively correspond to the first to Nth processing devices and store predetermined values;
When the value of the i-th non-transfer limit time counter is compared with the value of the i-th limit time register, and the value of the i-th non-transfer limit time counter reaches the value of the i-th limit time register First to Nth limit comparison means for outputting predetermined limit comparison results;
Transfer order determining means for determining the data transfer order of the first to Nth processing devices based on the respective limit comparison results output by the first to Nth limit comparing means;
Data transfer processing means for granting data transfer rights to the first to Nth processing devices according to the transfer order determining means,
When the value of the i-th non-transfer limit time counter reaches the value of the i-th limit time register, the data transfer of the i-th processing device is performed with the highest priority until the end.
[0024]
As described above, according to the fourth aspect of the invention, the time during which no data is transferred is counted for each processing device, and when the limit time is set in advance in the register and the limit time is reached, the highest priority is given. The data transfer process is performed with. As a result, the data transfer within the limit time can be completed for a processing device that does not require urgent but requires a certain amount of data transfer within the limit time.
[0025]
According to a fifth aspect of the present invention, a conflicting data transfer between a storage device shared by a plurality of processing devices and the plurality of processing devices is transferred by giving a data transfer right to the processing device that requested the data transfer. An arbitration system controlled by an arbitration device that indicates an order,
The plurality of processing devices respectively include request output means for outputting a pre-data transfer request indicating in advance that data transfer is to be performed in the future and a data transfer main request indicating that data transfer is currently required.
The arbitrating device includes pre-transfer request processing means for granting a data transfer right to the processing device that has output the pre-data transfer request based on the pre-data transfer request received from any of the plurality of processing devices.
[0026]
As described above, according to the fifth aspect, a pre-data transfer request is output in advance before the actual data transfer request is output from the processing device that may cause data transfer in the future to the arbitration device. By doing so, the request processing means before transfer Before Accordingly, the right to use the bus can be granted to the processing apparatus that has output the pre-data transfer request. Thus, the processing apparatus can immediately start data transfer at the time of the data transfer main request, thereby improving the data transfer efficiency.
[0027]
According to a sixth aspect of the present invention, a conflicting data transfer between a storage device shared by a plurality of processing devices and the plurality of processing devices is transferred by giving a data transfer right to the processing device that requested the data transfer. An arbitration system controlled by an arbitration device that indicates an order,
The plurality of processing devices output a signal indicating the priority of the data transfer request accompanying the data transfer request,
The arbitrating device includes a data transfer processing unit that determines the priority output by the plurality of processing devices and gives a data transfer right in preference to the processing device that has output a high priority.
[0028]
As described above, according to the sixth aspect, together with the data transfer request from each processing device, a signal indicating the priority of the data transfer request is output together. Thereby, the arbitrating device can optimize the prioritization of the data transfer processing of each processing device, and can improve the data transfer efficiency.
[0029]
According to a seventh aspect of the present invention, a conflicting data transfer between a storage device shared by a plurality of processing devices and the plurality of processing devices is transferred by giving a data transfer right to the processing device that requested the data transfer. An arbitration method controlled by an arbitration device that indicates an order,
A first step of outputting a pre-data transfer request indicating that a plurality of processing devices perform future data transfer before performing actual data transfer;
The arbitrating device includes a second step of granting a data transfer right to the processing device that has output the pre-data transfer request based on the pre-data transfer request received from any of the plurality of processing devices;
An arbitration method characterized in that, when a processing apparatus that has output a pre-data transfer request performs actual data transfer, data transfer can be started immediately according to a data transfer right given in advance.
[0030]
As described above, according to the seventh aspect, the pre-data transfer request is output in advance before the actual data transfer request is output from the processing device that may cause data transfer in the future to the arbitration device. And a step of granting the right to use the bus to the processing device side from which the arbitrating device has output the pre-data transfer request in advance. Thus, the processing apparatus can immediately start data transfer at the time of the data transfer main request, thereby improving the data transfer efficiency.
[0031]
According to an eighth aspect of the present invention, a competing data transfer between a storage device shared by a plurality of processing devices and the plurality of processing devices is transferred by giving a data transfer right to the processing device that has requested data transfer. An arbitration method controlled by an arbitration device that indicates the order,
A first step in which a plurality of processing devices output a signal indicating a priority of the data transfer request accompanying the data transfer request;
A second step in which the arbitrating device determines the priority output by the plurality of processing devices;
As a result of the determination in the second step, the arbitration device includes a third step of giving priority to the data transfer right in preference to the processing device that has output a high priority,
An arbitration method, wherein data transfer is performed in an order based on a priority desired by each of a plurality of processing devices.
[0032]
As described above, according to the eighth invention, the step of outputting together with the data transfer request from each processing device the signal indicating the priority of the data transfer request, and the step of the arbitrating device determining the priority, Is provided. Thereby, the arbitrating device can optimize the prioritization of the data transfer processing of each processing device, and can improve the data transfer efficiency.
[0033]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a diagram illustrating a configuration of a system using an arbitration device and method according to each embodiment of the present invention. In FIG. 1, this system includes a functional block 11 and an arbitration device 2N (in the following description, an arbitration device 21 in the first embodiment, an arbitration device 22 in the second embodiment, and a third embodiment). An arbitration device 23; an arbitration device 24 in the fourth embodiment; an arbitration device 25 in the fifth embodiment); and a memory block 31.
[0034]
The functional block 11 includes a plurality of processing devices such as an MPEG TS decoder, an MPEG AV decoder, graphics control, and a CPU, as in the conventional functional block described above. The memory block 31 shares and uses the memory necessary for the plurality of processing devices.
In order to facilitate the following description, it is assumed that there are two processing devices, the first processing device and the second processing device, that are included in the functional block 11 and are subject to arbitration.
[0035]
(First embodiment)
FIG. 2 is a block diagram showing the configuration of the main part of the system using the arbitration method according to the first embodiment of the present invention. In FIG. 2, the arbitrating device 21 includes a transfer request receiving unit 211 and a transfer permission output unit 212. The functional block 11 includes a first processing device 110 and a second processing device 120. Further, the first and second processing devices include pre-request output units 111 and 121 and main request output units 112 and 122, respectively.
[0036]
The transfer request reception unit 211 receives a transfer request BRi from each processing device (i is 1 or 2, which is the same in the following embodiments), and transfers the data to be transferred based on the bus use right resident round robin method The request BRi is determined, and a request to that effect is output to the transfer permission output unit 212. The transfer permission output unit 212 outputs the transfer permission BGi to the corresponding i-th processing device in accordance with the request from the transfer request reception unit 211. The pre-request output units 111 and 121 included in each processing device output a pre-transfer request BRi ′ for notifying the arbitration device 21 that there is a plan to perform data transfer in the future, although it is not necessary now. To do. The request output units 112 and 122 output a transfer request BRi when data transfer is really necessary, as before.
[0037]
Next, an arbitration method performed by the system using the arbitration method of the first embodiment will be described with reference to FIG.
Now, consider a case where the second processing device 120 is in the “resident 2” state where the right to use the bus exists (state 504) and the first processing device 110 outputs the transfer request BR1. When it is found that the first processing device 110 will output a data transfer request in the future (for example, when the first processing device 110 is a CPU, a cache miss occurs and the memory block When it is necessary to read data from 31), the first processing device 110 first outputs the previous transfer request BR1 'to the arbitrating device 21 for only one clock. Upon receiving this pre-transfer request BR1 ′, the arbitrating device 21 changes the state to “permitted 1” (transition 510, state 501).
Here, the pre-transfer request BR1 ′ output from the first processing device 110 indicates the possibility of future data transfer. In fact, the first processing device 110 starts data transfer now. do not do. For this reason, the bus busy BB is not output from the functional block 11 to the arbitrating device 21 (not active). Accordingly, the arbitrating device 21 immediately changes the state to “resident 1” (transition 506, state 502) because neither the bus busy BB nor the transfer request BR2 from the second processing device 120 exists.
[0038]
The above contents will be described in terms of data transfer timing by comparing FIG. 3 and FIG. FIG. 3 is a diagram illustrating data transfer timings in the arbitration system according to the first embodiment.
In the case of transfer using the conventional arbitration method shown in FIG. 17, the transfer request BR1 is output from the first processing device at the 12th clock. For this reason, the actual data transfer is started at the 14th clock after the transition from “resident 2” → “permission 1” → “resident 1”. On the other hand, in the arbitration method according to the first embodiment shown in FIG. 3, the above-described pre-transfer request BR1 ′ is output at the eighth clock, and the “resident 1 ”. Therefore, even when the real transfer request BR1 is output at the twelfth clock, the data transfer can be started immediately without waiting time.
[0039]
As described above, the arbitration method according to the first embodiment is performed before the actual transfer request BR is output from the processing device that may generate data transfer to the arbitration device 21 in the future. A transfer request BR ′ is output. As a result, the arbitrating device 21 can shift the residence state to the processing device side that has output the previous transfer request BR ′, regardless of which processing device has the right to use the bus. Therefore, the processing apparatus can immediately start data transfer at the time of the data transfer request BR, and can improve the data transfer efficiency.
[0040]
Even if the processing apparatus that has issued the previous transfer request BR ′ does not actually perform data transfer thereafter, the subsequent data transfer is normally performed without any problem. In addition, even if a pre-transfer request is output from a plurality of processing devices before this transfer request, there is no inconvenience in data transfer because only the presence status of the bus use right changes.
[0041]
(Second Embodiment)
The arbitration device according to the second exemplary embodiment of the present invention determines an appropriate data transfer processing order based on a predetermined priority when transfer requests BR from a plurality of processing devices compete, and performs data transfer. The purpose is to improve efficiency.
[0042]
FIG. 4 is a block diagram showing the configuration of the arbitrating device 22 according to the second embodiment of the present invention. In FIG. 4, the arbitrating device 22 includes a transfer request receiving unit 211, a transfer permission output unit 212, a result comparison unit 221, first and second result determination units 222 and 223, a page address storage unit 224, A bank address storage unit 225, a size storage unit 226, a page address comparison unit 227, a bank address comparison unit 228, and a size comparison unit 229 are provided.
[0043]
The page address storage unit 224 is a memory block For each bank in 31, the page address location of the data transfer performed last time is stored. The bank address storage unit 225 is a memory for data transfer performed last time. block The bank address location in 31 is stored. The size storage unit 226 stores size information of the data transfer performed last time.
The contents stored in the page address storage unit 224, the bank address storage unit 225, and the size storage unit 226 are stored in the memory via the memory interface as necessary. Reblock (Not shown).
[0044]
The page address comparison unit 227 compares the page address for data transfer requested by the first and second processing devices with the previous page address stored in the page address storage unit 224 for each bank, and The comparison output is output to the first and second result determination units 222 and 223, respectively. The bank address comparison unit 228 compares the bank address for data transfer requested by each of the first and second processing devices with the previous bank address stored in the bank address storage unit 225, and compares the comparison output with the first output. It outputs to the 1st and 2nd result judgment parts 222 and 223, respectively. The size comparison unit 229 compares the data transfer size information requested by the first and second processing devices with the previous size information stored in the size storage unit 226, and compares the comparison output with the first and second size information. It outputs to the 2nd result judgment part 222 and 223, respectively.
[0045]
The first result determination unit 222 receives the comparison result regarding the first processing device and a signal indicating that the data transfer processing indicates read / write, and determines the priority order for the request of the first processing device based on the comparison result. The data is output to the comparison unit 221. The second result determination unit 223 inputs the comparison result regarding the second processing device and a signal indicating whether the data transfer processing is read / write, and determines the priority order for the request of the second processing device based on the comparison result. The data is output to the comparison unit 221. The result comparison unit 221 receives the output of the first result determination unit 222 and the output of the second result determination unit 223, and determines which of the transfer requests of the first processing device and the second processing device has priority. Determine and notify the transfer request accepting unit 211.
[0046]
The transfer request reception unit 211 outputs a request to the transfer permission output unit 212 based on the priority order output from the result comparison unit 221. The transfer permission output unit 212 outputs the transfer permission BGi to the corresponding i-th processing device in accordance with the request from the transfer request reception unit 211.
[0047]
Next, the determination operation in the arbitration device 22 will be described.
In the following, it is assumed that the arbitration device 22 competes with the transfer request BR1 from the first processing device and the transfer request BR2 from the second processing device.
[0048]
First, determination processing for the transfer request BR1 from the first processing device is as follows. The page address comparison unit 227 inputs the page address data in the transfer request BR1. Here, the page address storage unit 224 stores which page address is performed in the previous data transfer. Then, the page address comparison unit 227 determines whether or not the page address of the current transfer request BR1 is the same as the previous page address. The coincidence of the page addresses is determined because the data transfer efficiency is improved when the data transfer request for the same page address is continued. The bank address comparison unit 228 inputs bank address data in the transfer request BR1. Here, the bank address storage unit 225 stores which bank address is used in the previous data transfer. Then, the bank address comparison unit 228 determines whether or not the bank address of the current transfer request BR1 is different from the previous bank address. This difference in bank address is determined because, with respect to banks, data transfer efficiency is improved by changing the target bank for each process, rather than continuing the process for the same bank. Further, the size comparison unit 229 inputs size information data in the transfer request BR1. Here, the size storage unit 226 stores the transfer size in the previous data transfer. Then, the size comparison unit 229 determines whether or not the transfer size of the current transfer request BR1 is the same as the previous transfer size. The reason why the transfer sizes coincide with each other is that, for example, in a memory such as a DRAM, the data transfer efficiency for the data transfer request related to the same transfer size is improved by continuously processing.
[0049]
The determination results from the page address comparison unit 227, the bank address comparison unit 228, and the size comparison unit 229 regarding the transfer request BR1 are input to the first result determination unit 222. The first result determination unit 222 inputs the above three determination results and data indicating whether the transfer request BR1 is a request for reading or a request for writing. Then, the first result determination unit 222 determines the priority of the transfer request BR1 based on the following contents. In the contents shown below, priority 1 is the highest priority data transfer process, and priority 4 is the lowest priority data transfer process.
Priority 1: CPU read request
Priority 2: When the transfer request is for a bank different from the previous one and the same page address as the previous one
Priority 3: When the transfer size is the same as the previous one
Priority 4: If none of the above applies
[0050]
On the other hand, the determination processing for the transfer request BR2 from the second processing device is similar to the determination processing for the transfer request BR1 from the first processing device, the page address comparison unit 227 and the bank address comparison unit 228 regarding the transfer request BR2. The second result determination unit 223 determines the priority of the transfer request BR2 based on the three determination results of the size comparison unit 229 and data indicating whether the transfer request BR2 is a read request or a write request.
[0051]
The result comparison unit 221 inputs the priority of the transfer request BR1 output from the first result determination unit 222 and the priority of the transfer request BR2 output from the second result determination unit 223. Compare degrees. Then, the result comparison unit 221 instructs the transfer request reception unit 211 to perform the data transfer process for the transfer request BRi having the higher priority. In response to the instruction from the result comparison unit 221, the transfer request reception unit 211 outputs a corresponding request to the transfer permission output unit 212. The transfer permission output unit 212 outputs the transfer permission BGi to the i-th processing device based on an instruction from the transfer request reception unit 211.
If the priority of the transfer request BR1 and the priority of the transfer request BR2 are the same, the result comparison unit 221 notifies the transfer request reception unit 211 to that effect. In this case, the transfer request reception unit 211 determines the order of data transfer by the bus use right residence round robin method as usual.
[0052]
As described above, the arbitrating device 22 according to the second embodiment considers the identity of the transfer data page address, bank address, transfer data size, read / write, and the like regarding the received data transfer request. The priority of data transfer, that is, the transfer order is obtained. As a result, it is possible to minimize overhead such as re-input of row (row) address due to change of page address and resetting of command due to change of transfer data size, and data transfer efficiency to memory Can be improved.
[0053]
(Third embodiment)
In the arbitration device according to the third embodiment of the present invention, the transfer request BR for the urgent data transfer process conflicts with the transfer request BR for the data transfer process that does not need to be performed in an arbitrary time. In this case, it is an object to preferentially perform urgent data transfer processing and improve data transfer efficiency.
[0054]
FIG. 5 is a block diagram showing a configuration of the arbitrating device 23 according to the third embodiment of the present invention. In FIG. 5, the arbitrating device 23 includes a transfer request receiving unit 211, a transfer permission output unit 212, first and second non-transfer time counters 231 and 232, and first and second threshold setting registers 233. And 234, and first and second comparators 235 and 236.
[0055]
The first non-transfer time counter 231 inputs the bus busy BB1 related to the first processing device, and counts the time during which data transfer is not performed. The second non-transfer time counter 232 inputs the bus busy BB2 related to the second processing device, and counts the time during which data transfer is not performed. The first and second threshold value setting registers 233 and 234 store predetermined threshold values, respectively. The first comparator 235 compares the time counted by the first non-transfer time counter 231 with the value stored in the first threshold value setting register 233, and the comparison result is transferred to the transfer request receiving unit 211. Output to. The second comparator 236 compares the time counted by the second non-transfer time counter 232 with the value stored in the second threshold value setting register 234, and the comparison result is transferred to the transfer request receiving unit 211. Output to. The transfer request reception unit 211 outputs a request regarding the i-th processing device that is active out of the first comparator 235 and the second comparator 236 to the transfer permission output unit 212. The transfer permission output unit 212 receives a request from the transfer request reception unit 211 and outputs a transfer permission BGi to the corresponding i-th processing device.
[0056]
Next, the determination operation in the arbitrating device 23 will be described.
Hereinafter, in the arbitrating device 23, the transfer request BR1 from the first processing device (herein referred to as CPU) and the transfer request BR2 from the second processing device (herein referred to as TS decoder) compete. Suppose that the transfer request BR1 is urgent. In this case, the data output from the second processing unit, that is, the TS decoder is within a certain time t. In It is only necessary to transfer the data a predetermined number of times. On the other hand, it is assumed that the first processing device, that is, the CPU, has rushed the data transfer due to a cache miss or the like.
[0057]
First, as a premise, when a transfer request BR1 that requires urgent input from the first processing device is input to the transfer request receiving unit 211, the transfer request receiving unit 211 receives a first non-transfer time counter 231 relating to the first processing device. Is set to non-operation, and only the second non-transfer time counter 232 relating to the second processing device is enabled. In addition, the second non-transfer time counter 232 is cleared.
Here, since the transfer request BR1 and the transfer request BR2 are in conflict with the transfer request reception unit 211, data transfer processing is normally performed from a processing device in which the bus use right resides in the bus use right resident round robin method. (See FIG. 6. FIG. 6 is in the state “Resident 2”, where the first processor requests eight data transfers and the second processor requests four data transfers. Show the case). However, since only the second non-transfer time counter 232 is enabled as described above, and the second non-transfer time counter 232 has not yet reached the value of the second threshold setting register 234, The transfer request receiving unit 211 first performs the data transfer process of the first processing device with priority given to the transfer request BR1. While the data transfer process of the first processing device is being performed, the bus busy BB2 becomes active, and the second non-transfer time counter 232 counts the time. The first processing device performs data transfer processing continuously until the count of the second non-transfer time counter 232 reaches the value of the second threshold value setting register 234.
[0058]
Then, when the accumulated time count of the second non-transfer time counter 232 reaches the value of the second threshold value setting register 234, the transfer request receiving unit 211 next moves to the data transfer process of the second processing device. . As a result, the bus busy BB2 becomes inactive, and the second non-transfer time counter 232 is cleared. When the data transfer process of the second processing device is finished, the data of the first processing device is kept until the accumulated time count of the second non-transfer time counter 232 reaches the value of the second threshold value setting register 234 again. Transfer processing is performed.
[0059]
As described above, the data transfer processing of the first processing device is performed a plurality of times until the accumulated time count of the second non-transfer time counter 232 reaches the value of the second threshold value setting register 234, The data transfer process of the processing device is performed once every time the accumulated time count of the second non-transfer time counter 232 reaches the value of the second threshold value setting register 234. By repeating this process, the data transfer process of the first processing device requiring urgent processing is preferentially performed, and the data transfer process of the second processing device not requiring urgent processing is performed within a predetermined time t. Can do.
FIG. 7 is a diagram showing the timing of the above processing.
[0060]
As described above, the arbitrating device 23 according to the third embodiment counts the time during which data is not transferred for each processing device, and the data transfer processing of each processing device until a predetermined time is reached. Limit. As a result, data transfer of the fixed number of times within a certain time Can do Efficient arbitration of data transfer between a processing device (for example, a TS decoder) and an urgent processing device (for example, a CPU) Do be able to. Therefore, it is possible to improve the execution performance of a processing device (for example, CPU) that needs to perform data transfer with priority.
[0061]
(Fourth embodiment)
In the arbitrating device according to the fourth embodiment of the present invention, the arbitrating device 23 according to the third embodiment preferentially performs the data transfer processing of the first processing device that requires urgent. The Therefore, the case where the data transfer process of the second processing apparatus cannot be completed within a certain time t is taken into consideration (see FIG. 9).
[0062]
FIG. 8 is a block diagram showing the configuration of the arbitrating device 24 according to the fourth embodiment of the present invention. In FIG. 8, the arbitrating device 24 includes a transfer request receiving unit 211, a transfer permission output unit 212, first to fourth non-transfer time counters 231, 232, 241, and 242, and first to fourth thresholds. Value setting registers 233, 234, 243 and 244, and first to fourth comparators 235, 236, 245 and 246 are provided.
[0063]
As can be seen by comparing FIG. 5 and FIG. 8, the configuration of the arbitration device 24 of the fourth embodiment is the same as that of the arbitration device 23 of the third embodiment described above. Time counters 241 and 242, third and fourth threshold setting registers 243 and 244, and third and fourth comparators 245 and 246 are further added. The other configuration of the arbitration device 24 according to the fourth embodiment is the same as the configuration of the arbitration device 23 according to the third embodiment, and the same reference numerals are used for the configuration and the description thereof is omitted. Omitted.
[0064]
The third non-transfer time counter 241 receives the transfer request BR1 related to the first processing device, the time during which data transfer other than the first processing device is being performed, and no data transfer is being performed. Accumulate time. The fourth non-transfer time counter 242 receives the transfer request BR2 related to the second processing device, the time during which data transfer other than the second processing device is being performed, and no data transfer is being performed. Accumulate time. The third and fourth threshold value setting registers 243 and 244 store predetermined threshold values, respectively. The third comparator 245 compares the time counted by the third non-transfer time counter 241 with the value stored in the third threshold value setting register 243, and the comparison result is transferred to the transfer request receiving unit 211. Output to. The fourth comparator 246 includes a second non-transfer time counter 2 3 2 compares the time counted by 2 with the value stored in the fourth threshold value setting register 244, and outputs the comparison result to the transfer request reception unit 211. As described above, the transfer request reception unit 211 initially outputs a request regarding the i-th processing device, which is the active one of the first comparator 235 and the second comparator 236, as a transfer permission output. To the unit 212. However, the transfer request reception unit 211 activates the output of the third comparator 245 or the fourth comparator 246 and outputs a request regarding the i-th processing device that is active to the transfer permission output. The output is fixed to the unit 212.
[0065]
Next, the determination operation in the arbitrating device 24 will be described.
In the following description, it is assumed that the arbitration device 24 is also the case described in the arbitration device 23 of the third embodiment.
[0066]
First, as a premise, the transfer request receiving unit 211 receives the urgent transfer request BR1 from the first processing device, and inputs the third non-transfer time counter 241 related to the first processing device to the transfer request receiving unit 211. Is also set to non-operation, and the fourth non-transfer time counter 242 related to the second processing device is also enabled. The fourth non-transfer time counter 242 is cleared. The fourth threshold value setting register 244 is a time (including a time during which nothing is performed) that can be allocated to data transfer of other processing devices other than the second processing device, that is, the second processing. A time is set by excluding the time required for the data transfer of the second processing device from the fixed time t at which the device must transfer the data.
[0067]
As described above, the arbitrating device 24 first performs the data transfer processing of the first processing device with priority on the transfer request BR1. While the data transfer process of the first processing device is being performed, the second non-transfer time counter 232 counts time by the bus busy BB2, and the transfer request BR2 is active, so the fourth non-transfer The time counter 242 also counts time. Until the count of the fourth non-transfer time counter 242 reaches the value of the fourth threshold value setting register 244, as described above, the data transfer process of the first processing unit and the data of the second processing unit The transfer process is repeated.
[0068]
Here, if the data transfer of both the first and second processing devices is completed before the count of the fourth non-transfer time counter 242 reaches the value of the fourth threshold value setting register 244, there is no problem. Absent. On the other hand, when the count of the fourth non-transfer time counter 242 reaches the value of the fourth threshold value setting register 244 even when the data transfer process of the first processing device still remains The transfer request accepting unit 211 determines that there is a limit for processing by lowering the priority regarding the data transfer processing of the second processing device (that is, if the data transfer processing is further delayed, it remains within a certain time t). It is impossible to transfer all the data). The transfer request reception unit 211 issues a request regarding the second processing device until all the data transfer processing of the second processing device is completed regardless of the outputs of the first and second comparators 235 and 236. to continue.
[0069]
In this way, the processing of the third embodiment described above is performed until the limit for processing with a lower priority for an arbitrary processing device is reached, and when the limit is reached, processing is performed with the highest priority to the end. . Therefore, even if the processing apparatus originally has a low priority, the data transfer process can be completed within a predetermined time t by setting a threshold value for the limit.
FIG. 10 is a diagram showing the timing of the above processing.
[0070]
As described above, the arbitrating device 24 according to the fourth embodiment counts the time during which data is not transferred for each processing device, and the data transfer processing of each processing device until a predetermined time is reached. In addition, a limit time is set in advance so that all data transfer is completed within a certain time, and when the limit time is reached, data transfer processing is performed with the highest priority. This gives priority to data transfer processing of processing devices that require urgency. Do In addition, even for a processing apparatus that does not require urgent but requires a certain amount of data transfer within a certain time, it is possible to guarantee completion of data transfer within a certain time.
[0071]
The third and fourth non-transfer time counters 241 and 242, the third and fourth threshold setting registers 243 and 244, the third and fourth in the arbitrating device 24 according to the fourth embodiment. The comparators 245 and 246 are not necessarily configured to accompany the configuration of the arbitration device 23 according to the third embodiment, and the transfer request receiving unit 211 and the transfer permission output unit 212 are not necessarily included. Even with this configuration alone, it is possible to complete a certain amount of data transfer within a certain time with respect to an arbitrary processing device while following the bus use right residence round robin method.
[0072]
(Fifth embodiment)
When the arbitration method according to the fifth embodiment of the present invention outputs the transfer request BR in the processing device, the arbitration method outputs a signal indicating whether the priority of the transfer request BR is high or low together. The purpose is to determine an appropriate order of data transfer processing based on the priority, regardless of the robin method, and to improve data transfer efficiency.
[0073]
FIG. 11 is a block diagram showing a configuration of a main part of a system using the arbitration method according to the fifth embodiment of the present invention. In FIG. 11, the arbitrating device 25 includes a transfer request receiving unit 211 and a transfer permission output unit 212. The functional block 11 includes a first processing device 110 and a second processing device 120. The first and second processing devices include request output units 113 and 123 and priority output units 114 and 124, respectively.
[0074]
The transfer request reception unit 211 inputs the transfer request BRi and priority from each processing device, determines the transfer request BRi to be subjected to data transfer processing based on the priority, and sends a request to that effect to the transfer permission output unit It outputs to 212. The transfer permission output unit 212 outputs the transfer permission BGi to the corresponding i-th processing device in accordance with the request from the transfer request reception unit 211. The request output units 113 and 123 included in each processing device output a transfer request BRi to obtain transfer permission when performing data transfer. The priority output units 114 and 124 output signals indicating whether the priority of the transfer request BRi output from the request output units 113 and 123 is high or low.
[0075]
Next, an arbitration method performed by a system using the arbitration method of the fifth embodiment will be described with reference to FIG. FIG. 12 is a diagram illustrating state transition of the arbitration method performed by the system using the arbitration method of the fifth embodiment.
[0076]
When the arbitration method according to the fifth embodiment does not output a signal indicating that the priority is high for the transfer request BRi output by each processing device, the transition is completely different from the conventional bus use right residence round robin method described above. Absent. However, when the transfer request BR1 of the first processing device and the transfer request BR2 of the second processing device compete with each other in the state “resident 1”, when the priority of the transfer request BR1 is low, the conventional bus use right As in the resident round robin method, the state transitions to “permission 2” to perform data transfer processing to the second processing device (transition 311 and state 302), but when the priority of the transfer request BR1 is high, Even if the priority of the transfer request BR2 is high, the state transitions to the “permitted” state (transition 317, state 304) in order to continue the data transfer process for the first processing device.
Of course, in the state “resident 1”, when only the transfer request BR2 of the second processing device is present, the state transitions to the state “permission 2” (transition 311 and state 302), and no transfer request BRi is received from each processing device. If there is not, the system waits for the next transfer request BRi in the state “resident 1” (state 301).
[0077]
In the state “permitted 2”, when the transfer request BR1 of the first processing device and the transfer request BR2 of the second processing device compete with each other, only when the priority of the transfer request BR2 is low, Transition to state “permitted 1” to perform data transfer processing to the first processing device after the processing is completed (transition 316, state 302), but as long as the priority of the transfer request BR2 is high, it continues. The state remains “permitted 1” to perform the data transfer process for the second processing device (state 302).
Of course, in the state “permission 2”, when only the transfer request BR1 of the first processing device is present, the state transitions to the state “permission 1” (transition 316, state 304), and nothing is transferred from each processing device to the transfer request BRi. If there is not, the state transits to the “resident 2” state and waits until there is a next transfer request BRi (transition 312, state 303).
[0078]
The above process is performed in the same manner also in the state “resident 2” and the state “permitted 1” (states 303 and 304).
[0079]
Such processing is effective in the following cases.
For example, in the case of a transfer request from the CPU, the requested data is urgently required if it is a fill (read) cycle due to the occurrence of a cache miss. In such a case, CPU performance can be fully exploited by executing the data transfer processing of the CPU with priority over the data transfer processing of other processing devices. Conversely, in the CPU write cycle, after the data is written to the write buffer, the CPU performs the next processing. Do Therefore, the priority for actually writing data into the memory may be low.
[0080]
As described above, the arbitration method according to the fifth embodiment outputs a signal indicating the priority of the transfer request BRi together with the transfer request BRi from each processing device. Thereby, the arbitrating device 25 can optimize the prioritization of the data transfer processing of each processing device, and can improve the data transfer efficiency.
[0081]
In the description of the first to fifth embodiments, the arbitration devices 21 to 25 have been described as being provided separately from the functional block 11, but may be configured in the functional block.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a system using an arbitration device and method according to each embodiment of the present invention.
FIG. 2 is a block diagram showing a configuration of a main part of a system using the arbitration method according to the first embodiment of the present invention.
FIG. 3 is a diagram illustrating data transfer timing of the system using the arbitration method according to the first embodiment.
FIG. 4 is a block diagram showing a configuration of an arbitration device 22 according to a second embodiment of the present invention.
FIG. 5 is a block diagram showing a configuration of an arbitration device 23 according to a third embodiment of the present invention.
FIG. 6 is a diagram illustrating an example of data transfer timing in a conventional arbitration system.
FIG. 7 is a diagram showing data transfer timing of a system using an arbitration device 23 according to a third embodiment.
FIG. 8 is a block diagram showing a configuration of an arbitrating device 24 according to a fourth embodiment of the present invention.
FIG. 9 is a diagram illustrating an example of data transfer timing in a conventional arbitration system.
FIG. 10 is a diagram showing data transfer timing of a system using the arbitrating device 24 according to the fourth embodiment.
FIG. 11 is a block diagram showing a configuration of an arbitration device 25 according to a fifth embodiment of the present invention.
FIG. 12 is a diagram showing a state transition of data transfer in a system using the arbitration method according to the fifth embodiment.
FIG. 13 is a block diagram illustrating an example of a configuration of a conventional video system.
FIG. 14 is a diagram illustrating an example of main components of a system using a conventional arbitration device.
FIG. 15 is a block diagram illustrating an example of a configuration of a conventional bus use right residence round robin arbitration device.
FIG. 16 is a diagram showing state transition of a conventional bus use right residence round robin arbitration method;
FIG. 17 is a diagram illustrating an example of data transfer timing in a conventional arbitration system.
[Explanation of symbols]
11, 520 ... functional block
21-25, 540 ... Arbitration device
31, 530 ... Memory block
110, 120 ... Processing device
111, 121 ... Pre-request output unit
112, 122 ... This request output unit
113, 123 ... request output unit
114, 124 ... priority output unit
211, 541: Transfer request receiving unit
212, 542: Transfer permission output unit
221 ... Result comparison section
222, 223 ... Result judging section
224: Page address storage unit
225 ... Bank address storage unit
226 Size storage unit
227: Page address comparison unit
228 ... Bank address comparison unit
229 ... Size comparison section
231, 232, 241, 242 ... non-transfer time counter
233, 234, 243, 244... Threshold setting register
235, 236, 245, 246 ... comparators
501: Tuner / demodulator
502 ... MPEG TS decoder
503, 505 ... Local memory
504 ... MPEG AV decoder
506: Graphic control
507: Graphic memory
508 ... CPU
509 ... Program memory

Claims (1)

A processing device having a data transfer request for competing data transfer between the storage device shared by the first to Nth (N is an integer of 2 or more) processing devices and the first to Nth processing devices. An arbitration device that gives a data transfer right to any one of them and instructs the transfer order,
It corresponds to each of the first to N-th processing devices, and counts the time during which data transfer of the corresponding i-th (i = 1, 2,..., N) processing device is not performed. First to Nth non-transfer time counters that clear the count value when data transfer starts;
Corresponding to each of the first to N-th processing devices, and first to N-th registers for storing predetermined values;
The value of the i-th non-transfer time counter is compared with the value of the i-th register, and when the value of the i-th non-transfer time counter reaches the value of the i-th register, a predetermined value is set. First to Nth comparing means for outputting a comparison result;
Transfer order determining means for determining the data transfer order of the first to N-th processing devices based on the respective comparison results output by the first to N-th comparing means;
Data transfer processing means for granting a data transfer right to the first to N-th processing devices according to the transfer order determining means ,
The first to Nth non-transfer time counters can be set to non-operation,
The transfer order determining means includes
Until the valid non-transfer time counter value reaches the value of the corresponding register, the data transfer of the processing device corresponding to the non-transfer time counter set to non-operation is prioritized and the transfer order is determined,
An arbitration device characterized in that when the value of a valid non-transfer time counter reaches the value of a corresponding register, the transfer order of data transfer of the processing device corresponding to the non-transfer time counter is determined .

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