JP3850933B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to an improvement in a method for manufacturing a trench type power MOSFET.
[0002]
[Prior art]
Hereinafter, a conventional semiconductor device will be described with reference to FIG. FIG. 9 is a cross-sectional view showing the structure of a power MOSFET having a so-called trench structure.
In this power MOSFET, as shown in FIG. 9, an N − type common drain layer 1 is formed on the surface layer of an N + type semiconductor substrate 8 by an epitaxial growth method, and a P + type semiconductor layer is formed on the surface layer of the common drain layer 1. The channel layer 2 is formed by diffusing impurities. A source region 5 is formed in part of the surface layer of the channel layer 2 by diffusing N + -type impurities, and a groove (trench) is provided so as to penetrate these. A gate insulating film 3 is formed on the surface layer of the trench, and a polysilicon gate 4 is formed on the gate insulating film 3 so as to fill the trench.
[0003]
An interlayer insulating film 6 is formed on the polysilicon gate 4 so as to cover it. A contact hole is formed in the interlayer insulating film 6 in the formation region of the source region 5, and a wiring layer 7 that contacts the source region 5 is formed.
[0004]
[Problems to be solved by the invention]
In order to form a power MOSFET having such a structure, in the conventional manufacturing method, (1) a guard ring forming step, (2) an element isolating step, (3) a channel layer forming step in the element region, (4 ) Body region forming step, (5) impurity diffusion step during source region formation, (6) trench forming step, (7) gate electrode forming step, and (8) contact hole with the source region in the interlayer insulating film. In the step of forming and (9) the patterning step of the wiring layer, the photomasks essential for the photolithographic step for patterning are necessary, and a total of nine photomasks are necessary.
[0005]
For this reason, the mask process and the process accompanying this became very many, the manufacturing process became complicated, and the problem that manufacturing cost became high had arisen.
[0006]
[Means for Solving the Problems]
The present invention has been made in view of the above-mentioned conventional disadvantages. As shown in FIG. 1, after forming a one-conductivity-type common drain layer on the surface layer of one-conductivity-type semiconductor substrate, A step of diffusing a reverse conductivity type impurity over the entire surface layer to form a channel layer; a step of sequentially forming a first conductor layer and a first insulating film on the channel layer; and the first insulating film. Forming a photoresist thereon, selectively exposing the photoresist using a photomask and then patterning the photoresist, and selectively forming the photoresist in a region where a gate electrode is to be formed later; and Using the resist as a mask, patterning the first insulating film and the first conductor layer by etching to form a source electrode made of the first conductor layer; and Forming a source region by diffusing impurities of one conductivity type on the surface of the channel layer using a source electrode as a mask; and forming a second insulating film covering a side wall and an upper surface of the source electrode; Etching the channel layer and the common drain layer using the second insulating film as a mask to form a groove in a region other than the source electrode forming region; and a third insulating film on the surface of the groove Forming a gate electrode by filling the groove and covering the second insulating film over the entire surface to form a gate electrode, over the second conductor layer In addition, the above-described problem is solved by a method for manufacturing a semiconductor device, comprising the step of forming a wiring layer.
[0007]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a power MOSFET having a trench structure according to an embodiment of the present invention will be described with reference to the drawings.
First, the structure of this power MOSFET will be described. FIG. 1 is a cross-sectional view showing the structure of a power MOSFET according to this embodiment.
[0008]
In this power MOSFET, as shown in FIG. 1, an N− type common drain layer 11 formed by epitaxial growth is formed on a semiconductor substrate 10 made of N + type silicon. A channel layer 12 made of a P + type impurity diffusion layer is formed on the surface layer of the common drain layer 11. A plurality of trenches that penetrate the channel layer 12 and reach the inside are formed in the semiconductor substrate 11, and a gate insulating film 18 made of a silicon oxide film having a thickness of about 500 mm is formed on the surface of the trench.
[0009]
A source region 15 made of an N + -type impurity diffusion layer is formed in a part of the surface layer of the channel layer 12 separated into a plurality by the trench, and the channel layer 12 has a thickness so as to be in contact with the source region 15. A source electrode 13 made of a polysilicon layer of about 5000 mm is formed.
An insulating film 16 made of a silicon oxide film having a thickness of about 5000 mm is formed so as to cover the source electrode 13, and a gate electrode made of polysilicon is formed on the entire surface so as to fill the trench and cover the insulating film 16. 19 is formed. Further, a wiring layer 20 made of aluminum having a thickness of about 1 μm is formed on the gate electrode 19.
[0010]
The manufacturing method will be described below with reference to the drawings. Note that the semiconductor substrate 10 is not shown in FIGS.
First, after an N− type common drain layer 11 is formed on the surface layer of the N + type semiconductor substrate 10 by an epitaxial growth method, a P + type impurity B is formed on the entire surface of the common drain layer 11 as shown in FIG. For example, the channel layer 12 is formed by injecting and diffusing + under conditions of a dose amount of about 5 × 10 13 cm −2, and a polysilicon layer 13A is formed on the upper surface of the channel layer 12 by a CVD method to a thickness of about 5000 mm. Thereafter, the polysilicon layer 13A is oxidized to form an oxide film 14 having a thickness of about 5000 mm on the upper surface thereof. Thereafter, a photoresist PR is applied on the upper surface to a thickness of about 1 μm, and the photoresist PR in a region other than a region where a source electrode is to be formed later is selectively exposed using a photomask PM.
[0011]
Next, after developing the photoresist PR and removing the exposed region, the oxide film 14 and the polysilicon layer 13A are sequentially etched and removed using the photoresist PR ′ remaining in the region where the source electrode is to be formed later as a mask. Thus, the source electrode 13 is formed (FIG. 3).
Next, as shown in FIG. 4, the patterned oxide film 14 and the source electrode 13 are used as a mask and AS, which is an N + type impurity, is implanted into the surface layer of the channel layer 12 under the condition of a dose amount of 1 × 10 16 cm −2. The source region 15 is formed by diffusion.
[0012]
Next, after oxidizing the entire surface to form a silicon oxide film having a thickness of about 8000 mm, the entire surface is dry etched to etch and remove the silicon oxide film in the formation region of the source region 15 to expose the source region 15; An insulating film 16 is formed to be integrated with the oxide film 14 on the upper surface of the source electrode 13 together with the side wall spacer of the source electrode 13 (FIG. 5).
[0013]
Next, as shown in FIG. 6, the channel layer 12 and the common drain layer 11 are dry-etched using the insulating film 16 as a mask to form a trench 17 having a depth of about 3 μm that penetrates the channel layer 12 and the common drain layer 11. Thereafter, the surface of the trench 17 is thermally oxidized to form a gate insulating film 18 having a thickness of about 500 mm. The value of 500Å is a value for a 30V power MOSFET, and the film thickness depends on the breakdown voltage of the power MOSFET.
[0014]
Next, as shown in FIG. 7, a polysilicon layer is laminated on the entire surface by CVD or the like, and a gate electrode 19 that fills the trench and covers the entire surface of the insulating film 16 is formed.
Next, as shown in FIG. 8, a wiring layer 20 made of aluminum having a film thickness of about 1 μm is laminated by sputtering or the like.
[0015]
Thereafter, a photoresist (not shown) is applied on the wiring layer 20 and patterned by photolithography using a second photomask. The wiring layer 20 is patterned using the patterned resist as a mask. Then, the power MOSFET as shown in FIG. 1 is completed by patterning by etching and removing the gate electrode 19.
[0016]
As described above, according to the power MOSFET according to the present embodiment, the photoresist PR having the structure shown in FIG. 1 and patterned using one photomask PM as shown in FIG. After forming the source electrode 13 by patterning the oxide film 14 and the polysilicon layer 13A using a mask, the source region 15 shown in FIG. 4 and the trench 17 shown in FIG. This process can be carried out by self-alignment.
[0017]
Therefore, even if the photomask used for the patterning process of the wiring layer 20 is included, only two photomasks are required. Therefore, compared with the conventional manufacturing method in which nine photomasks are used for manufacturing, the mask process. In addition, it is possible to drastically reduce the processes associated therewith, thereby making it possible to save the manufacturing process and greatly reduce the manufacturing cost.
In this embodiment, the process related to element isolation is not explained at all. However, after manufacturing in the above process, each element is cut out and separated by dicing, so that no photomask is required for element isolation. is there.
[0018]
In the above-described embodiment, the Nch MOSFET has been described. However, it is needless to say that the present invention is not limited to the Nch MOSFET and can also be applied to the Pch MOSFET.
In the present embodiment, the source electrode 13 and the gate electrode 19 are formed of polysilicon, but the present invention is not limited to this, and for example, polycide or metal may be used.
[0019]
Furthermore, it goes without saying that various film thicknesses and other conditions are not limited to the above values.
[0020]
【The invention's effect】
As described above, according to the method for manufacturing a semiconductor device of the present invention, the first insulating film and the first conductor layer are patterned using the photoresist patterned using one photomask as a mask. After that, a source region and a groove can be formed using this as a mask, and in the subsequent steps, a photomask is not required until the wiring layer patterning step, and most of the steps can be carried out by self-alignment. .
[0021]
As a result, only two photomasks are required even including the patterning process of the wiring layer. Therefore, compared with the conventional manufacturing method in which as many as nine photomasks are used for manufacturing, the mask process and the accompanying process are accompanied. The process can be greatly reduced, and the manufacturing process can be labor-saving and the manufacturing cost can be greatly reduced.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view illustrating the structure of a trench type power MOSFET according to an embodiment of the present invention.
FIG. 2 is a first cross-sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the invention.
FIG. 3 is a second cross-sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the invention.
FIG. 4 is a third cross-sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the invention.
FIG. 5 is a fourth cross-sectional view illustrating the manufacturing method of the semiconductor device according to the embodiment of the invention.
FIG. 6 is a fifth cross-sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the invention.
FIG. 7 is a sixth cross-sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the invention.
FIG. 8 is a seventh cross-sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the invention.
FIG. 9 is a cross-sectional view illustrating the structure of a conventional trench type power MOSFET.

Claims (4)

A common drain layer of one conductivity type is formed by epitaxial growth on the surface layer of a high concentration semiconductor substrate of one conductivity type, and then a channel layer is formed by diffusing reverse conductivity type impurities over the entire surface layer of the common drain layer. Process,
Sequentially forming a first conductor layer and a first insulating film on the channel layer;
Forming a photoresist on the first insulating film, selectively exposing the photoresist using a photomask, and then patterning to selectively form a region where a gate electrode is to be formed later; ,
Patterning the first insulating film and the first conductor layer by etching using the patterned photoresist as a mask to form a source electrode made of the first conductor layer;
Forming a source region by diffusing impurities of one conductivity type on the surface of the channel layer using the first insulating film and the source electrode as a mask;
Forming a second insulating film covering a side wall and an upper surface of the source electrode;
Etching the channel layer and the common drain layer using the second insulating film as a mask to form a groove in a region other than the source electrode formation region;
Forming a third insulating film on the surface of the groove;
Forming a second conductor layer that fills the trench and covers the second insulating film over the entire surface to form a gate electrode;
And a step of forming a wiring layer on the second conductor layer.   In the step of forming the first conductor layer, a polysilicon or polycide layer is formed, and in the step of forming the first insulating film, a silicon oxide film is formed by oxidizing the first conductor layer. The method of manufacturing a semiconductor device according to claim 1.   In the step of forming the second insulating film covering the sidewall and upper surface of the source electrode, the entire surface is oxidized to form a silicon oxide film, and then the entire surface is etched to form the silicon oxide formed in the source region. 3. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of removing the film and exposing at least a part of the source region.   The step of forming the third insulating film oxidizes the surface of the groove to form a third insulating film made of a silicon oxide film. The manufacturing method of the semiconductor device of description.

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