JP3279007B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device having a bipolar transistor and a MOS transistor formed on an epitaxial layer (hereinafter also referred to as a BiCMOS device ) , and more particularly, to a collector current in a bipolar transistor. Semiconductor that simultaneously satisfies the increase in the MOS and the breakdown voltage of the MOS transistor
The present invention relates to a device manufacturing method .

[0002]

2. Description of the Related Art It has been reported that the characteristics of a BiCMOS device strongly depend on the thickness of an epitaxial layer. For example, the SDM 90-49, I
The "Current state and prospects of BiCMOS device / process technology" of CD90-64 states that the cut-off frequency fT of a bipolar transistor and the withstand voltage BVCBO between a collector and a base depend on the thickness of the epitaxial layer. The more it becomes, the higher the cut-off frequency fT and the lower the collector-base breakdown voltage BVCBO.

From the viewpoint of increasing the cutoff frequency fT,
The thinner the thickness of the epitaxial layer, the better. However, the thinner the epitaxial layer, the more
Since the collector-base breakdown voltage BVCBO decreases,
It cannot be too thin.

[0004]

The reduction in breakdown voltage due to such a reduction in the thickness of the epitaxial layer is caused by the fact that, in a P-channel MOS transistor formed in a BiCMOS device, between a source / drain region and a P-type semiconductor substrate.
This is particularly noticeable.

[0005] For example, as shown in FIG.
An epitaxial layer 6 is formed on the type semiconductor substrate 2,
P channel M formed on epitaxial layer 6
In the OS transistor 14, N
The buried layer 4 may be formed, but the P-type source / drain region 14 and the P-type
Pressure with the semiconductor substrate 2 is weak (arrow X in the figure).
part). This decrease in breakdown voltage is more remarkable as the thickness of the epitaxial layer 6 is smaller.

Therefore, it is conceivable to form the buried layer 4 wider than the N-well 15 and over the entire lower surface of the well.
In that case, it is necessary to ensure a sufficiently large distance between the wells, which hinders high integration. Such a decrease in breakdown voltage due to the thinning of the epitaxial layer 6 is shown in FIG.
As shown in FIG. 2 (B), the effect is further remarkable in the P-channel MOS transistor 16 in which the N-type buried layer is not formed between the P-type semiconductor substrate 2 and the epitaxial layer 6. With the thinning of the epitaxial layer 6, a P-type source
The distance between the drain region 14 and the P-type semiconductor substrate 2 decreases, and the breakdown voltage at the portion indicated by the arrow Y decreases.

In FIG. 12, reference numeral 8 denotes an element isolation region (LOCOS) formed by selective oxidation, reference numeral 10 denotes a gate insulating film, and reference numeral 12 denotes a gate electrode. The present invention has been made in view of such circumstances, and has as its object to provide a method of manufacturing a semiconductor device that can simultaneously increase the collector current of a bipolar transistor and improve the breakdown voltage of a MOS transistor.

[0008]

[0009]

[0010]

According to the present invention, there is provided a method of manufacturing a semiconductor device in which a bipolar transistor and a MOS transistor are formed on an epitaxial layer.
Forming an insulating layer, removing the insulating layer from the surface of the epitaxial layer in a region where the bipolar transistor is formed, and forming a conductive layer on the surface of the epitaxial layer on which the insulating layer is formed. And, when patterning the conductive layer by etching, a step of forming a groove on the surface of the epitaxial layer in a region where the bipolar transistor is formed, and a step of forming a bipolar transistor in the groove, Forming a MOS transistor on the surface of the epitaxial layer where the groove is not formed.

In the region where the bipolar transistor is formed, the step of removing the insulating layer from the surface of the epitaxial layer is performed in the region where the MOS transistor is formed.
The connection between the surface of the epitaxial layer and the conductive layer is preferably performed simultaneously with the step of forming a contact hole in the insulating layer.

[0012] The insulating layer is, and Turkey, such as a gate insulating layer for the MOS transistors is preferred. The conductive layer,
It can be composed of any of the multilayer wiring layers laminated on the epitaxial layer.

[0013]

According to the semiconductor device manufacturing method of the present invention, the semiconductor device is manufactured.
In a semiconductor device to be formed, in a region where a bipolar transistor is formed, an epitaxial layer has a thickness of, for example, 0.3.
Since it is relatively thin, such as about 0.5 μm, it is possible to maximize the collector current in the high injection region of the transistor,
High-speed operation becomes possible. In the region where the MOS transistor is formed, the thickness of the epitaxial layer is, for example, 0.1.
Since it is relatively thick at 5 μm or more, it is possible to effectively prevent a decrease in breakdown voltage between the source / drain region of the MOS transistor and the substrate.

An SRAM is formed in a MOS transistor formation region.
In the case of forming such a memory cell, since the epitaxial layer is relatively thick in the MOS transistor formation region, the soft error resistance is improved. Further, in the present invention in which the intrinsic base region and the emitter region of the bipolar transistor are formed in the trench, the breakdown voltage between the collector and the base is determined only by the distance between the intrinsic base region and the collector buried layer, and the diffusion depth of the external base region is increased. X
_Since it has no relation to _j , the characteristics of the bipolar transistor can be improved without lowering the breakdown voltage between the collector and the base.

In the method for manufacturing a semiconductor device according to the present invention,
BiCMOS having such excellent characteristics can be easily manufactured without increasing the number of steps as compared with a conventional manufacturing method.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for manufacturing a semiconductor device (BiCMOS) according to the present invention in which a bipolar transistor and a MOS transistor are formed on an epitaxial layer will be described below in detail with reference to the drawings.

FIG. 1 shows a BiCMO according to an embodiment of the present invention.
FIG. 2 is a graph showing the relationship between the thickness of the epitaxial layer and the transistor characteristics in BiCMOS, and FIGS. 3A to 3D show Bi according to one embodiment of the present invention.
FIG. 4E is a cross-sectional view of a principal part showing a manufacturing step of the CMOS.
FIG. 5G is a cross-sectional view of a main part showing a continuation of the step shown in FIG. 3, FIGS. 5H to 5K are cross-sectional views of a main part showing a step continuation of the step shown in FIG. ) To (N) are cross-sectional views of essential parts showing a subsequent step shown in FIG. 5, and FIGS. 7 (O) to (Q) are FIGS.
FIG. 4 is an essential part cross sectional view showing a step that follows the step shown in FIG.

First Embodiment As shown in FIG. 1, a BiCM according to a first embodiment of the present invention is shown.
In the OS, a region 21 where an NPN bipolar transistor is formed and a region 23 where a MOS transistor is formed
Is the N-type epitaxial layer 3 on the P-type semiconductor substrate 20
It is formed on 0. The BiCMOS shown in FIG. 1 is used, for example, as a high-speed SRAM.

The details will be described below. As the semiconductor substrate 20, a P-type silicon wafer is used. An N-type epitaxial layer 30 is stacked on the semiconductor substrate 20. In the formation region 21 of the bipolar transistor, an N-type collector buried layer 28a is formed below the epitaxial layer 30.

On the epitaxial layer 30, a region 21 where a bipolar transistor is formed and a region 23 where a MOS transistor is formed are formed. These transistors are isolated by an element isolation region (LOCOS) 32 formed by selective oxidation formed on the surface of the epitaxial layer 30 and an element isolation region 36 formed by an impurity diffusion layer.

In the formation region 23 of the MOS transistor,
A P-type well region 38 is formed in the epitaxial layer 30, and a gate electrode 50 having a polycide structure is formed thereon.
a, 50b are formed via the gate insulating layer 34. One of the gate electrodes 50 b is connected (contacted) to the surface of the epitaxial layer 30. On the surface of the epitaxial layer 30 located on both sides of the gate electrodes 50a and 50b, N-type source / drain regions 62 having an LDD structure and having a low concentration diffusion layer 52 are formed. Although the MOS transistor shown in FIG. 1 is an N-channel MOS transistor, an N-well region may be formed in the MOS transistor formation region 23 to form a P-channel MOS transistor.

In the region 21 where the bipolar transistor is to be formed, a groove 48 is formed in the surface of the epitaxial layer 30.
b is thinner than the thickness tm of the epitaxial layer 30 in the MOS transistor formation region 23. The thickness tb of the epitaxial layer 30 in the bipolar transistor formation region 21 is preferably about 0.3 to 0.5 μm, and the thickness tm of the epitaxial layer 30 in the MOS transistor formation region 23 is preferably 0.5 μm or more. The reason why these film thicknesses are preferable will be described later.

A P-type intrinsic base region 58 and an external base region 56 are formed on the surface of the epitaxial layer 30 in which the groove 48 is formed, and an N-type emitter is formed on the surface of the intrinsic base region 58. An area 82 is formed. Emitter region 82 is formed by thermal diffusion of N-type impurities from emitter electrode 68.

On the surface of the epitaxial layer 30 on which the transistor is formed, a first interlayer insulating layer 64 and a second interlayer insulating layer 70 are formed by lamination. Contact holes are formed in these interlayer insulating layers. A metal wiring layer is formed in a predetermined pattern so as to enter these contact holes, and each of the electrodes 84, 86, 88, 90,.
92. Each of the electrodes 84, 86, 88, 90,
Reference numeral 92 denotes a base extraction electrode, an emitter extraction electrode, a collector extraction electrode, a substrate extraction electrode, and a source / drain region extraction electrode.

In the BiCMOS according to this embodiment, since the thickness tb of the epitaxial layer 30 is relatively thin, for example, 0.3 to 0.5 μm in the formation region 21 of the bipolar transistor, the collector in the high implantation region of the transistor is formed. The current can be extracted to the maximum and high-speed operation can be performed. It is clear from the experimental results shown in FIG. 2 that increasing the collector current in the high injection region of the transistor by making the thickness tb of the epitaxial layer 30 relatively thin, for example, 0.3 to 0.5 μm. is there.

The experimental results shown in FIG. 2 show the results obtained by plotting the collector current Ic of the bipolar transistor when the DC current gain hFE is 50 by changing the thickness of the epitaxial layer. Curve a connecting white square points in the figure
As shown in the figure, the collector current Ic increases as the thickness of the epitaxial layer decreases. However, if the thickness of the epitaxial layer is about 0.25 μm or less, the withstand voltage of the bipolar transistor becomes insufficient and the transistor does not operate.
It is preferably at least 0.5 μm.

The MOS transistor formation region 23
In this case, since the thickness tm of the epitaxial layer 30 is relatively thick, for example, 0.5 μm or more, it is possible to effectively prevent a decrease in withstand voltage between the source / drain region of the MOS transistor and the substrate. FIG. 2 also shows the relationship between the thickness of the epitaxial layer and the breakdown voltage BV between the source / drain region and the semiconductor substrate in the MOS transistor. As shown by the curve b in which the black diamond points shown in FIG. 2 are plotted, when the thickness of the epitaxial layer becomes 0.5 μm or less, the breakdown voltage of the MOS transistor sharply decreases. The thickness of the epitaxial layer is preferably 0.5 μm or more.

In the MOS transistor formation region 23, S
When a memory cell such as a RAM is formed, the epitaxial layer 30 is formed in the MOS transistor formation region 23.
Since the film thickness is relatively large, latch-up hardly occurs, and the soft error resistance is improved.

Next, a method of manufacturing the BiCMOS shown in FIG. 1 will be described. First, as shown in FIG.
A semiconductor substrate 20 composed of a mold silicon wafer is prepared. In this embodiment, a P-type semiconductor substrate 20 is used to form an NPN bipolar transistor and a MOS transistor on the same semiconductor substrate. When the PNP bipolar transistor and the MOS transistor are formed on the same semiconductor substrate, the conductivity types of the constituent materials used in this embodiment may be all reversed. In the following description, N
A case where a PN bipolar transistor and a MOS transistor are formed on the same semiconductor substrate 20 will be described as an example.

On the surface of the semiconductor substrate 20, for example, 400
A silicon oxide layer 22 having a thickness of about nm is formed by thermal oxidation. In the silicon oxide layer 22, an opening 24 is formed by etching in a pattern for forming a collector buried layer. Next, as shown in FIG. 3B, an antimony glass layer 26 is formed on the silicon oxide film 22 in which the openings 24 are formed. Then, using the silicon oxide layer 22 as a mask, antimony, which is an N-type impurity contained in the antimony glass layer 26, is selectively doped from the opening 24 into the collector diffusion layer expected region 28 on the surface of the semiconductor substrate 20. The doping of the impurity may be carried out by vapor phase diffusion or ion implantation in addition to solid phase diffusion.

Next, as shown in FIG.
The silicon oxide layer 22 and the antimony
The glass layer 22 with, for example, buffered hydrofluoric acid.
Remove by etching. Next, as shown in FIG.
An N-type epitaxial layer 30 is formed on the surface of the semiconductor substrate 20.
Grow. As a growth gas, for example, dichloryl
Run (SiH _Two Cl_Two ) And the dopant is
Use phosphorus (P). Due to the deposition of the epitaxial layer 30
The antimony doped in the step shown in FIG.
The diffusion and the collector buried layer planned area 28
A buried layer 28a is formed. Epitaxial layer 30
Is not particularly limited, but is preferably 0.5 μm or more.
Or 0.6 μm or more.

Next, as shown in FIG. 4E, for example, steam oxidation at about 950 ° C. is performed to form an element isolation region (LOCOS) 32 by selective oxidation. At the time of selective oxidation, a silicon nitride layer is used as an oxidation prevention mask. Also, the epitaxial layer 3 between the LOCOS 32
An insulating layer 34 serving as a gate insulating layer of a MOS transistor is formed on the surface of the MOS transistor 0 by a thermal oxidation method or the like.

Thereafter, as shown in FIG. 4F, boron is used as a P-type impurity,
Ion is selectively implanted into the surface of the MOS transistor, a P-type well region 38 is formed in the MOS transistor formation region,
An element isolation region for isolating the bipolar transistors from each other is formed in the bipolar transistor formation region. P-type well region 38 and element isolation region 3
The ion implantation for forming 6 is performed simultaneously or separately.

Next, as shown in FIG. 4 (G), in order to connect the surface of the epitaxial layer 30 to the gate electrode in the MOS transistor formation region, the insulating layer 34 is etched and the contact hole 42 is formed. Form. This contact hole 42 is formed for a so-called buried contact employed in, for example, an SRAM memory cell structure. At that time, in the present embodiment, at the same time, the insulating layer 34 is removed by etching on the surface of the epitaxial layer located in the bipolar transistor formation region, and the opening 40 is formed.

Next, as shown in FIG. 5H, a first conductive layer 44 and a second conductive layer 46 serving as a gate electrode of a MOS transistor are formed on the surface of the epitaxial layer 30 by CV.
It is deposited by D and sputtering. First conductive layer 4
4 is formed of, for example, a polysilicon layer of about 70 to 150 nm, and second conductive layer 46 is formed of, for example, 70 to 150 nm.
It is composed of a silicide layer such as tungsten silicide of about nm. That is, in this embodiment, the gate electrode is formed of a polycide layer.

Next, as shown in FIG. 5I, the first conductive layer 44 and the second conductive layer 46 are etched using photolithography technology and RIE technology, and are formed in the MOS transistor formation region. Gate electrode 50 of predetermined pattern
a, 50b are formed. Part of the gate electrode 50b is formed by the contact hole 42 so that the epitaxial layer 30
(Contact) to the surface of At the time of etching for forming these gate electrodes, FIG.
The surface of the epitaxial layer 30 is also etched at the contact hole 42 and the opening 40 of the insulating layer 34 formed in the step shown in FIG.

As a result, the first groove 4
7 and the second groove 48 are formed. The first groove 47 is
This is a groove formed also in the conventional buried contact structure, and has a depth of about 0.1 μm. Second groove 4
Reference numeral 8 denotes a groove formed for the first time by the method of the present embodiment, and its depth is set so that the remaining film thickness of the epitaxial layer 30 in which the groove 48 is formed becomes 0.3 to 0.5 μm. It is preferably determined, and in this embodiment, 0.1
μm.

Thereafter, low concentration phosphorus, which is an N-type impurity, is ion-implanted only into the MOS transistor formation region, and the gate electrodes 50a, 50
A low concentration diffusion region 52 for an N-type LDD is formed in a self-aligned manner with respect to b. Next, as shown in FIG.
For example, after an insulating layer such as a silicon oxide layer is formed to a thickness of about 300 nm by a CVD method, this is subjected to anisotropic etching such as RIE to form sidewalls 54 on both sides of the gate electrodes 50a and 50b. . The sidewall 54 is also formed in the first groove 47 and the second groove 48. Since the groove width of the first groove portion 47 is narrow, the first groove portion 47 is embedded with the sidewall.

Thereafter, as shown in FIG. 5K, a P-type impurity such as BF ₂ is ion-implanted sequentially into the bipolar transistor formation region in which the second groove 48 is formed, and the intrinsic base region 58 and the external base are formed. The regions 56 are sequentially formed. Further, ion implantation for forming the source / drain regions 62 is performed in the MOS transistor formation region. The source / drain region 62 forms an LDD structure in combination with the low concentration diffusion region 52. Further, an N-type collector electrode extraction diffusion layer 60 is also formed by ion implantation.

Next, as shown in FIG. 6L, a first interlayer insulating layer 64 is deposited. The first interlayer insulating layer 64 is made of, for example, silicon oxide deposited by a CVD method. The thickness of the first interlayer insulating layer is not particularly limited.
It is about 0 nm. Next, as shown in FIG. 6 (M), a contact hole 66 for forming an emitter is formed in the first interlayer insulating layer 64 in the bipolar transistor formation region. A polysilicon layer of, for example, about 200 nm is deposited so as to enter contact hole 66, an N-type impurity such as arsenic is ion-implanted over the entire surface of the polysilicon layer, and the polysilicon layer is etched to form an emitter electrode. A layer 68 is formed.

Thereafter, as shown in FIG. 6N, a second interlayer insulating layer 70 is deposited, and a thin film transistor (TFT), a resistor, a wiring, etc., not shown, are formed thereon. The second interlayer insulating layer 70 is formed of, for example, a boron-phosphorus-doped glass layer (BPSG layer). The thickness of the second interlayer insulating layer 70 is, for example, about 200 nm.

Next, as shown in FIG. 7 (O), contact holes 72, 74, 76, 78, 80 for metal wiring layers are formed in the second interlayer insulating layer 70 and the first interlayer insulating layer 64.
To form Contact holes 72, 74, 76, 7
Reference numerals 8 and 80 are contact holes for a base extraction electrode, an emitter extraction electrode, a collector extraction electrode, a substrate extraction electrode, and a source / drain region extraction electrode, respectively.

Next, as shown in FIG.
By heat-treating the second interlayer insulating layer 70 composed of a reflow layer such as a layer, each of the contact holes 72, 7 is formed.
The opening edges of 4, 76, 78 and 80 are formed in a smooth tapered shape. Due to the heat treatment, the N-type impurity contained in the emitter electrode 68 is thermally diffused to the surface of the intrinsic base 58, and an emitter region 82 is formed.

Next, as shown in FIG. 7 (Q), an aluminum wiring containing titanium Ti, titanium nitride TiN, copper and silicon is inserted into each of contact holes 72, 74, 76, 78, 80. Al-Si-Cu is sequentially deposited by sputtering to form a wiring layer using a TiN layer as a barrier metal. Thereafter, the wiring layer is patterned to form the base extraction electrode 8.
4. An emitter extraction electrode 86, a collector extraction electrode 88, a substrate extraction electrode 90, and a source / drain region extraction electrode 92 are formed.

In the manufacturing method of this embodiment, in the step shown in FIG. 4G, when the contact hole 42 for the conventional buried contact is formed in the insulating layer 34, the bipolar transistor is simultaneously formed. An opening 40 is formed in the formation region. As a result, as shown in FIG. 5I, a second trench 48 is formed in the bipolar transistor formation region. By forming a bipolar transistor in the trench 48, the thickness of the epitaxial layer 30 in the bipolar transistor formation region can be easily reduced as compared with the MOS transistor formation region.

Second Embodiment Next, a method of manufacturing a BiCMOS according to a second embodiment of the present invention will be described. In the second embodiment of the present invention, only the portion where the intrinsic base region and the emitter region are formed among the regions where the bipolar transistor is formed,
A groove is formed.

Hereinafter, the BiCMOS according to the second embodiment will be described.
Will be described in detail based on the manufacturing method. In the present embodiment, FIG. 8 is used in the same manner as the manufacturing process of the first embodiment.
As shown in (E), after the collector buried diffusion layer 28a and the epitaxial layer 30 are formed on the surface of the semiconductor substrate 20, the surface is subjected to, for example, steam oxidation at about 950 ° C. to form an element isolation region (selective oxidation). LOC
OS) 32 is formed. On the surface of the epitaxial layer 30 between the LOCOSs 32, an insulating layer 34 serving as a gate insulating layer of the MOS transistor is formed by a thermal oxidation method or the like.

Then, as shown in FIG. 8F, boron is used as a P-type impurity,
Ion is selectively implanted into the surface of the MOS transistor, a P-type well region 38 is formed in the MOS transistor formation region,
An element isolation region for isolating the bipolar transistors from each other is formed in the bipolar transistor formation region. P-type well region 38 and element isolation region 3
The ion implantation for forming 6 is performed simultaneously or separately. Further, BF ₂ ions are selectively implanted into the bipolar transistor formation region using a resist mask,
An external base region 56a is formed.

Next, as shown in FIG. 8G, in the MOS transistor formation region, in order to connect the surface of the epitaxial layer 30 to the gate electrode, the insulating layer 34 is etched and the contact hole 42 is formed. Form. This contact hole 42 is formed for a so-called buried contact employed in, for example, an SRAM memory cell structure. At this time, in the present embodiment, at the same time, on the surface of the epitaxial layer located in the bipolar transistor formation region, a portion of the insulating layer 34 corresponding to the intrinsic base region is removed by etching to form an opening 40a.

Next, as shown in FIG. 9H, a first conductive layer 44 and a second conductive layer 46 serving as a gate electrode of a MOS transistor are formed on the surface of the epitaxial layer 30 by CV.
It is deposited by D and sputtering. First conductive layer 4
4 is formed of, for example, a polysilicon layer of about 70 to 150 nm, and second conductive layer 46 is formed of, for example, 70 to 150 nm.
It is composed of a silicide layer such as tungsten silicide of about nm. That is, in this embodiment, the gate electrode is formed of a polycide layer.

Next, as shown in FIG. 9I, the first conductive layer 44 and the second conductive layer 46 are etched by using the photolithography technique and the RIE technique, and are formed in the MOS transistor formation region. Gate electrode 50 of predetermined pattern
a, 50b are formed. Part of the gate electrode 50b is formed by the contact hole 42 so that the epitaxial layer 30
(Contact) to the surface of At the time of etching for forming these gate electrodes, FIG.
The surface of the epitaxial layer 30 is also etched at the contact hole 42a and the opening 40a of the insulating layer 34 formed in the step shown in FIG.

As a result, the first groove 4
7 and a second groove 48a are formed. First groove 47
Is a groove formed also in the conventional buried contact structure, and has a depth of about 0.1 μm. The second groove portion 48a is a groove portion formed for the first time by the method of the present embodiment, and the depth thereof is such that the remaining film thickness of the epitaxial layer 30 in which the groove 48a is formed is 0.3 to 0.5 μm.
m, and is preferably 0.1 μm in this embodiment.

Thereafter, only the MOS transistor formation region is ion-implanted with low-concentration phosphorus as an N-type impurity, and the gate electrodes 50a and 50a are formed on the surface of the epitaxial layer 30.
A low concentration diffusion region 52 for an N-type LDD is formed in a self-aligned manner with respect to b. Next, as shown in FIG.
Using the resist film 51 opening 53 in the bipolar transistor formation region is formed selectively (angle of 7-10 degrees) the BF ₂ oblique ion implantation. As a result, the second
Intrinsic base region 58a is formed at the bottom of groove 48a. The oblique ion implantation is used because the side walls of the second trenches 48a are also doped with impurity ions, and the intrinsic base region 5 is formed.
8a and the external base region 56a are satisfactorily connected to each other to lower the internal resistance (r _{bb '} ) of the base.

As a means for doping impurity ions also on the side wall of the second groove 48a, an insulating sidewall 49 containing an impurity such as boron is formed on the side of the second groove 48a, such as BSG. , Its sidewall 49
Alternatively, solid phase diffusion from solid phase can be used. In the case of this embodiment, the BSG sidewall remains in the BiCMOS as the final product.

Next, as shown in FIG. 9 (K), an insulating layer such as a silicon oxide layer is formed for about 300
After forming a film with a thickness of nm, this is subjected to anisotropic etching such as RIE, and on both sides of the gate electrodes 50a and 50b,
The side wall 54 is formed. This sidewall 5
4 is also formed in the first groove 47 and the second groove 48. Since the groove width of the first groove portion 47 is narrow, the first groove portion 47 is embedded with the sidewall.

Thereafter, ion implantation for forming source / drain regions 62 is performed in the MOS transistor formation region. The source / drain region 62 forms an LDD structure in combination with the low concentration diffusion region 52. Further, a diffusion layer 6 for extracting an N-type collector electrode is provided.
0 is also formed by ion implantation.

Next, as shown in FIG. 10L, a first interlayer insulating layer 64 is deposited. The first interlayer insulating layer 64 is made of, for example, silicon oxide deposited by a CVD method. First
The thickness of the interlayer insulating layer is not particularly limited.
It is about 00 nm. Next, as shown in FIG. 10 (M), a contact hole 66 for forming an emitter is formed in the first interlayer insulating layer 64 in the bipolar transistor formation region.
Open a. Next, as shown in FIG.
A polysilicon layer of about 0 nm is deposited, an N-type impurity such as arsenic is ion-implanted over the entire surface of the polysilicon layer, and the polysilicon layer is etched to form an emitter electrode layer 68a.

Thereafter, a second interlayer insulating layer 70 is deposited, and a thin film transistor (TF) (not shown) is formed thereon.
T), resistors, wirings, etc. are formed. Second interlayer insulating layer 70
Is, for example, a boron-phosphorus-doped glass layer (BPSG)
Layers). The thickness of the second interlayer insulating layer 70 is
For example, it is about 200 nm.

Next, as shown in FIG. 11 (O), contact holes 72, 74, 76, 78, 8 for metal wiring layers are formed in the second interlayer insulating layer 70 and the first interlayer insulating layer 64.
0 is formed. Contact holes 72, 74, 76, 7
Reference numerals 8 and 80 are contact holes for a base extraction electrode, an emitter extraction electrode, a collector extraction electrode, a substrate extraction electrode, and a source / drain region extraction electrode, respectively.

Next, as shown in FIG.
Second interlayer insulating layer 70 composed of a reflow layer such as a G layer
Is heat-treated to form contact holes 72, 7
The opening edges of 4, 76, 78 and 80 are formed in a smooth tapered shape. Due to the heat treatment, the N-type impurity contained in the emitter electrode 68 thermally diffuses to the surface of the intrinsic base 58 to form the emitter region 82a. In this case, the intrinsic base region 58a is directly under the emitter region 82a, proliferation diffused, diffusion depth x _j is deepened.

Next, as shown in FIG. 11 (Q), an aluminum wiring containing titanium Ti, titanium nitride TiN, copper and silicon is inserted into each of contact holes 72, 74, 76, 78, 80. Al-Si-Cu
Are sequentially deposited by sputtering to form a wiring layer using a TiN layer as a barrier metal. Thereafter, the wiring layer is patterned to form the base extraction electrode 8.
4. An emitter extraction electrode 86, a collector extraction electrode 88, a substrate extraction electrode 90, and a source / drain region extraction electrode 92 are formed.

In the manufacturing method of this embodiment, in the step shown in FIG. 8G, when the contact hole 42 for the conventional buried contact is formed in the insulating layer 34, the bipolar transistor is simultaneously formed. An opening 40a is formed in the formation region. As a result, as shown in FIG. 9I, the second trench 48a is formed in the bipolar transistor formation region.
Is formed. By forming the intrinsic base region and the emitter region of the bipolar transistor in the trench 48a, the thickness of the epitaxial layer 30 in the intrinsic base region and the emitter region can be easily reduced as compared with the MOS transistor formation region. .

In the BiCMOS according to the present embodiment,
In addition to having the same function as the BiCMOS of the first embodiment, it also has the following function. That is, Bi of the present embodiment
In CMOS, the collector - the breakdown voltage between the base, is determined only by the distance between the intrinsic base region 58a and the collector buried layer 28a, since irrelevant to the diffusion depth x _j of the external base region, lower the breakdown voltage between the collector-base Without this, the characteristics of the bipolar transistor can be improved.

The present invention is not limited to the above-described embodiments, but can be variously modified within the scope of the present invention. For example, in the above embodiment, by forming a groove in the bipolar transistor formation region 21,
Although the thickness of the epitaxial layer 30 was changed,
The thickness of the epitaxial layer 30 may be varied by selectively depositing the epitaxial layer 30 in the transistor formation region 23.

[0065]

As described above, according to the present invention, in the region where the bipolar transistor is formed, the epitaxial layer has a relatively small thickness of, for example, 0.3 to 0.5 μm. The collector current in the region can be maximized, and high-speed operation can be performed. In the region where the MOS transistor is formed, the thickness of the epitaxial layer is relatively thick, for example, 0.5 μm or more, so that a reduction in the breakdown voltage between the source / drain region of the MOS transistor and the substrate can be effectively prevented. .

Further, since the thickness of the epitaxial layer in the MOS transistor formation region is sufficiently large, occurrence of latch-up can be prevented. When a memory cell such as an SRAM is formed in the MOS transistor formation region, the soft error resistance is improved because the thickness of the epitaxial layer is relatively large in the MOS transistor formation region.

According to the present invention in which the intrinsic base region and the emitter region of the bipolar transistor are formed in the trench, the breakdown voltage between the collector and the base is determined only by the distance between the intrinsic base region and the collector buried layer, and the external base region is formed. since irrelevant to the diffusion depth x _j, without lowering the breakdown voltage between the collector-base, it is possible to improve characteristics of a bipolar transistor.

In the method of manufacturing a semiconductor device according to the present invention,
BiCMOS having such excellent characteristics can be easily manufactured without increasing the number of steps as compared with a conventional manufacturing method.

[Brief description of the drawings]

FIG. 1 is a sectional view of a main part of a BiCMOS according to one embodiment of the present invention.

FIG. 2 is a graph showing the relationship between the thickness of an epitaxial layer and transistor characteristics in BiCMOS.

FIGS. 3A to 3D are main-portion cross-sectional views showing a manufacturing process of a BiCMOS according to one embodiment of the present invention.

4 (E) to 4 (G) are cross-sectional views of main parts showing a step that follows the step shown in FIG. 3. FIG.

5 (H) to 5 (K) are cross-sectional views of relevant parts showing a step that follows the step shown in FIG. 4. FIG.

FIGS. 6 (L) to 6 (N) are cross-sectional views of essential parts showing a subsequent step shown in FIG. 5.

7 (O) to 7 (Q) are cross-sectional views of main parts showing a step that follows the step of FIG. 6. FIG.

8 (E) to 8 (G) are cross-sectional views of essential parts showing a manufacturing process of a BiCMOS according to another embodiment of the present invention.

9 (H) to 9 (K) are cross-sectional views of main parts showing a step that follows the step shown in FIG. 8. FIG.

10 (L) to 10 (N) are cross-sectional views of main parts showing a subsequent step shown in FIG.

11 (O) to 11 (Q) are cross-sectional views of main parts showing a step that follows the step shown in FIG.

FIGS. 12A and 12B are schematic cross-sectional views showing a decrease in withstand voltage between a source / drain region and a semiconductor substrate in a MOS transistor.

[Explanation of symbols]

 Reference Signs List 20 semiconductor substrate 21 bipolar transistor formation region 23 MOS transistor formation region 28a collector buried layer 30 epitaxial layer 32 LOCOS 34 insulating layer 38 P well 40 opening 42 contact hole 47 first Groove 48 Second groove 50a, 50b Gate electrode 56, 56a External base region 58, 58a Intrinsic base region 62 Source / drain region 68, 68a Emitter electrode 82, 82a Emitter region

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-5-152520 (JP, A) JP-A-1-122151 (JP, A) JP-A-2-40947 (JP, A) JP-A-1- 199463 (JP, A) JP-A-61-236153 (JP, A) JP-A-2-139962 (JP, A) JP-A-2-144912 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/8249 H01L 27/06

Claims (6)

(57) [Claims] In a method of manufacturing a semiconductor device having a bipolar transistor and a MOS transistor formed on an epitaxial layer, a step of forming an insulating layer on a surface of the epitaxial layer; A step of removing the insulating layer from the surface of the epitaxial layer, a step of forming a conductive layer on the surface of the epitaxial layer on which the insulating layer is formed, and a step of patterning the conductive layer by etching.
Forming a groove on the surface of the epitaxial layer in the region where the bipolar transistor is formed; forming a bipolar transistor in the groove; forming a MOS transistor on the surface of the epitaxial layer where the groove is not formed; Forming a semiconductor device. A step of removing the insulating layer from the surface of the epitaxial layer in the region where the bipolar transistor is formed,
The method for manufacturing a semiconductor device according to claim 1, wherein the step of forming a contact hole in the insulating layer is performed simultaneously with the step of connecting the surface of the epitaxial layer to the conductive layer. 3. The semiconductor device according to claim 1, wherein the insulating layer serves as a gate insulating layer for a MOS transistor, and the conductive layer serves as a gate electrode for a MOS transistor. Production method. 4. The method of manufacturing a semiconductor device according to claim 1, wherein said conductive layer is formed of one of a multilayer wiring layer laminated on an epitaxial layer. 5. When removing the insulating layer from the surface of the epitaxial layer in a region where the bipolar transistor is formed, removing the insulating layer in a portion where an intrinsic base region of the bipolar transistor is formed; The method for manufacturing a semiconductor device according to claim 1, wherein an intrinsic base region and an emitter region are formed at a bottom of the semiconductor device. 6. A method of manufacturing a semiconductor device having a bipolar transistor and a MOS transistor formed on an epitaxial layer, comprising: forming an element isolation region on a surface of the epitaxial layer by selective oxidation; After the formation, a step of forming an insulating layer on the surface of the epitaxial layer; a step of removing the insulating layer from the surface of the epitaxial layer in a region where the bipolar transistor is formed; a surface of the epitaxial layer on which the insulating layer is formed In the step of forming a conductive layer, When patterning the conductive layer by etching,
Forming a groove on the surface of the epitaxial layer in a region surrounded by the element isolation region and in which the bipolar transistor is formed; forming a bipolar transistor in the groove; Forming a MOS transistor on the surface of an epitaxial layer that has not been formed.