JP3240823B2 - Method for manufacturing BiCMOS type semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a BiCMOS type semiconductor device in which a bipolar transistor and a MOS transistor are formed on a semiconductor substrate, and a method of manufacturing the same.

[0002]

2. Description of the Related Art Signaling techniques SDM93-151, ICD9
3-145 (1993-3), "1 Mbit BiCMOS-TTL SRA with Extended Low Voltage Operation Margin"
M ", the first polysilicon layer is used as the gate electrode of the MOS transistor, the second polysilicon layer is the base electrode of the bipolar transistor, and the third polysilicon layer is the emitter of the bipolar transistor. The prior art describes that a TFT (thin film transistor) is formed by the fourth and fifth polysilicon layers used as electrodes and ground wiring in a memory cell, and the emitter / base of the bipolar transistor is formed in a self-aligned manner. Have been.

In general, an interlayer insulating film located below a TFT is subjected to a flattening process by a reflow process or an etch-back process. This is to secure a margin of exposure conditions in the TFT forming process and prevent disconnection of the wiring layer.

[0004]

However, for the planarization process, an interlayer insulating film having a certain thickness is required. In a BiCMOS type semiconductor device, the emitter / base of the bipolar transistor is formed in a self-aligned manner. When considering the film thickness of the offset insulating film formed on the base electrode to a step of the interlayer insulating film surface is substantial.

[0005] The above-mentioned prior art document does not describe the planarization of the interlayer insulating film. However, if the planarization is performed by an ordinary method, the planarized interlayer insulating film located below the TFT is not provided. The film thickness including the film and the offset insulating film for separating the emitter / base is considerably large. Therefore, in reality, the step of the surface of the interlayer insulating film is quite large, and a problem such as disconnection of wiring. Furthermore, as the thickness of the insulating film increases, even if a tungsten plug electrode is buried in the contact hole formed therein,
There are problems in terms of stable coverage of the barrier metal layer formed by the sputtering method and process stability including contact resistance.

The present invention has been made in view of such a situation, and in a BiCMOS type semiconductor device, a step on the surface of an insulating film is small, and a TFT or a wiring layer can be formed in a good pattern thereon. It is another object of the present invention to provide a BiCMOS type semiconductor device capable of forming a bipolar transistor and a MOS transistor having low contact resistance and stable characteristics on the same semiconductor substrate, and a method of manufacturing the same.

[0007]

In order to achieve the above object, a BiCMOS type semiconductor device according to a first aspect of the present invention is provided.
The method of manufacturing the device includes forming a gate insulating layer on the surface of the semiconductor substrate.
Forming a first conductive layer through the first conductive layer,
Etching is performed, and M
Forming a gate electrode of the OS transistor;
Forming an interlayer insulating film on the gate electrode;
Forming a second conductive layer on the interlayer insulating film;
Etch the second conductive layer to form a bipolar transistor
A base extraction electrode is formed in the
In the transistor formation region, a MOS transistor saw
Forming a wiring layer connected to the drain region
And a second electrode forming the base extraction electrode and the wiring layer.
On the two conductive layers, the emitter and the bipolar transistor
Off to form a self-aligned base and base
A process to form a flattening and offset insulating film as a set
And flatten the surface of the flattening / offset insulating film.
And removing impurities contained in the base extraction electrode.
Solid phase diffusion on the surface of the semiconductor substrate to self-align the base region
And a bipolar transistor type.
Planarizing / offset insulating film located in the formation region and the above
Etching the base extraction electrode
Forming base / emitter openings to expose the surface
Insulating the inner wall of the base / emitter opening
Forming an insulating side wall and the insulating side
Inside the base / emitter opening where the wall is formed
To form an emitter extraction electrode
And impurity diffusion from the emitter extraction electrode.
The emitter region on the surface of the semiconductor substrate in a self-aligned manner.
Forming.

A BiCMOS type according to a second aspect of the present invention
A method of manufacturing a semiconductor device includes a method of forming a gate on a surface of a semiconductor substrate.
Forming a first conductive layer via an insulating layer;
Etching the conductive layer to form the MOS transistor
Forming a gate electrode of a MOS transistor in a region
Forming an interlayer insulating film on the gate electrode
Forming a second conductive layer on the interlayer insulating film
And etching the second conductive layer to form a bipolar
Base extraction electrode formed in transistor formation area
A MOS transistor is formed in the MOS transistor formation region.
Form wiring layers connected to the source and drain regions of the star
And forming the base extraction electrode and the wiring layer.
The bipolar transistor is formed on the second conductive layer to be formed.
Separator and base are formed in a self-aligned manner.
A flattened and offset insulating film that serves as an offset for
And the surface of the flattening and offset insulating film
Flattening step, included in the base extraction electrode
Impurities are solid-phase diffused on the surface of the semiconductor substrate, and the base region
Self-aligning process, and the flattening and offset
Of forming an etching stop detection layer on the insulating film
And located in the bipolar transistor formation region.
Etching stop detection layer, flattening and offset insulating film
And etching the base extraction electrode
Open the base / emitter opening to expose the surface of the conductor board.
Forming process and filling the base / emitter opening.
To form a sidewall-forming insulating film
Step and the side wall forming insulating film
Detects that the surface of the sensing layer is exposed
Etch-back processing until the base and emitter
An insulating sidewall on the inner wall of the opening
Process and the base on which the insulating sidewall is formed.
Insert the emitter extraction electrode into the emitter opening
And the edge of this emitter extraction electrode.
At the time of machining, parts other than the lower part of the emitter extraction electrode
Removing the etching stop detection layer for minutes.
Due to the impurity diffusion from the emitter extraction electrode,
An emitter region is formed in a self-aligned manner on the surface of a conductive substrate.
And

The flattening / offset insulating film is made of an impurity
And a heat treatment of the reflow film.
In this way, a flattening process is performed and
Sometimes, the impurities contained in the base extraction electrode
Diffused on the surface of the body substrate to form the base region in a self-aligned
Preferably.

At least on the lower layer side of the reflow film,
It is preferable to form a non-doped insulating film containing no impurities.
Good.

[0011] The upper SL undoped insulating film is preferably formed by a CVD method using TEOS.

It is preferable that at least one of the first conductive layer and the second conductive layer is formed of a polycide film having a stacked structure of a polysilicon film and a silicide film.

[0013]

According to the first and second aspects of the present invention, B
In the BiCMOS type semiconductor device of the present invention manufactured by the method for manufacturing an iCMOS type semiconductor device, the offset insulating film is mainly used as the offset insulating film of the bipolar transistor for flattening the MOS transistor formation region. This eliminates the need for forming a planarizing insulating film separately. As a result, the total thickness of the insulating film is reduced, and an increase in the level difference on the surface of the insulating film can be prevented.

Therefore, a TFT is formed on the surface of the insulating film.
Alternatively, the wiring layer can be satisfactorily formed with a high-precision pattern without causing a disconnection phenomenon of the wiring. Further, since the thickness of the insulating film becomes thinner in total, the contact resistance of the contact portion formed in the insulating film is reduced, the manufacturing process is stabilized, and the characteristics of the obtained transistor are also stabilized.

Further, when a reflow film such as BPSG is used as the planarizing and offset insulating film, the reflow film is sandwiched between non-doped insulating films such as a TEOS-CVD film to reduce impurities contained in the reflow film. ,
Diffusion to the base extraction electrode on the lower layer side and the emitter extraction electrode on the upper layer side can be effectively prevented. Impurities
When diffused into these, there is a possibility that the characteristics of the transistor may fluctuate, but in the present invention, there is no such fear.

Further, by using a polycide film as a base extraction electrode, the polycide film can be
Can also be used as a wiring layer in the transistor formation area,
This simplifies the manufacturing process and reduces steps, and further improves the bipolar transistor characteristics in the high-injection region by reducing the base resistance (the collector current can be increased).

Furthermore, in the manufacturing method of the present invention, the second
When etching the second conductive layer of the layer (for example, a polycide film and serving as a base extraction electrode), overetching is unnecessary, so that the etching depth of the surface of the semiconductor substrate on which the base and the emitter are formed is minimized. Can be suppressed. No need for over-etching
This is for patterning the conductive layer separately from the MOS transistor formation region.

In particular, in the manufacturing method according to the second aspect of the present invention, since the etching stop detection layer is formed on the flattening and offset insulating film, the insulating sidewall (emitter / emitter) is formed in the base / emitter opening. At the time of etching (for example, RI
At E), the end point of the etching process of the insulating film for forming the sidewall can be detected. That is, as the insulating film for forming the sidewall is etched, the etching stop detecting layer is exposed at the timing of the end point, and when the portion is etched, it can be detected by the etching device (RIE device). . As a result, the thickness of the insulating sidewall formed on the side of the base / emitter opening can be controlled well. Therefore, it is possible to manufacture a bipolar transistor with stable emitter / base insulation and stable characteristics.

Further, in this case, since the etching stop detection layer remains on the flattening / offset insulating film and below the emitter extraction electrode, the emitter is removed from the flattening / offset insulating film through the emitter extraction electrode. It is possible to prevent impurities such as phosphorus from diffusing into the region. When the impurity diffusion occurs, it becomes difficult to control the depth of the emitter, but such a situation can be avoided in the present invention.

Furthermore, the presence of the etching stop detection layer (for example, a polysilicon layer) allows the thickness of the emitter extraction electrode to be increased at the time of etching when connecting the emitter electrode on the emitter extraction electrode. Over-digging can be compensated.

Furthermore, most of the etching stop detecting layer is shaved at the same time as the etching of the emitter extraction electrode, so that the etching stop detecting layer itself does not become a factor for increasing the level difference.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A BiCMOS type semiconductor device according to the present invention and a method of manufacturing the same will now be described with reference to the drawings.
This will be described in detail. First Embodiment As shown in FIG. 1, a BiCMOS type semiconductor device 20 according to the present embodiment has a BiCMO having a bipolar transistor formation region 12 and a MOS transistor formation region 14.
S, which is used, for example, as a high-speed BiCMOS type SRAM device.

In the MOS transistor formation region 14, the epitaxial layer 24 formed on the surface of the semiconductor substrate 22
A p-type well region 32 is formed on the surface, and a gate insulating film and a gate electrode 36 having a polycide structure are formed on the surface. On the surface of the epitaxial layer 24 located on both sides of the gate electrode 36, source / drain regions 40 having an LDD structure are formed. A wiring layer 54 is connected to one source / drain region 40, and a MOS electrode 94 is connected to the wiring layer 54 through a contact hole 82.

The bipolar transistor formation region 12 has a collector buried layer 26 formed near the interface between the semiconductor substrate 22 and the epitaxial layer 24. The conductivity type of the collector buried layer 26 is n-type when an npn bipolar transistor is formed, and is doped with an n-type impurity. When a pnp bipolar transistor is formed, a p-type impurity having the opposite conductivity type is doped. In the following description of the embodiment, a case where an npn bipolar transistor is formed will be described as an example. However, the present invention is similarly applicable to a case where a pnp bipolar transistor is formed by reversing the conductivity types. Can be applied.

The conductivity type of the epitaxial layer 24 is n-type, and the epitaxial layer 24 becomes a collector region. An element isolation insulating film (LOCOS film) 28 is formed on the surface of the epitaxial layer 24 by a selective oxidation method (LOCOS method) or the like in a predetermined pattern for separating each element. Epitaxial layer 24 surrounded by LOCOS film 28
A graft base region 62 is formed in a self-aligned manner with respect to the base extraction electrode 52 on the surface. At the center of the graft base region 62, an intrinsic base region 68 is formed, and on its surface, an emitter region 75 is formed in a self-aligned manner with respect to the emitter extraction electrode 72.

An insulating sidewall 70 is formed on the side wall of the base / emitter opening 64, and the insulating sidewall 70 and the reflow film 58
The emitter extraction electrode 72 and the base extraction electrode 52 are insulated. In this embodiment, the reflow film 58
Constitute a flattening and offset insulating film. In addition,
The reflow film 58 is preferably sandwiched between TEOS-CVD films.

The base extraction electrode 52 is connected to a base electrode 88 through a contact hole 76. The emitter extraction electrode 72 is connected to the emitter electrode 90 through the contact hole 78. The collector buried region 26 is connected to a collector take-out region 33, and a collector electrode 92 is connected to the collector take-out region 33 through a contact hole 80.

On these electrodes 88, 90, 92, 94, an interlayer insulating film 96 and an overcoat film 98 are formed. Next, a method of manufacturing the BiCMOS semiconductor device according to the first embodiment of the present invention shown in FIG. 1 will be described. In this embodiment, first, as shown in FIG. 2, a semiconductor substrate 22 made of, for example, silicon single crystal is prepared. The conductivity type of the semiconductor substrate 22 is p-type in this embodiment. A mask layer is formed on the surface of the semiconductor substrate 22. The mask layer is not particularly limited. For example, the mask layer is formed to a thickness of 300 to 500 nm, preferably 4 nm by a thermal oxidation method or the like.
It is composed of a 00 nm silicon oxide layer. In this mask layer, an opening is formed by etching or the like in a pattern in which a collector buried region is formed.

Next, a doped film doped with an impurity for forming a collector buried region is formed from above the mask layer. The doped film is not particularly limited, but is formed of an impurity-doped glass film formed by a CVD method or the like. n
When forming the type collector buried region, it is composed of an Sb glass film doped with antimony Sb, which is an n-type impurity.

The doped layer doped with Sb is used as a semiconductor base.
Along with the plate 22, for example, heat at about 1000 to 1300 ° C.
If processed, the antimony contained in the glass film becomes a mask layer
Is spread over the surface of the semiconductor substrate 22 in a region corresponding to the opening of the semiconductor substrate 22.
The collector buried region 26 shown in FIG.
You. Note that, for forming the collector buried region 26,
The method of introducing impurities is not limited to the above-described embodiment,
It can also be performed by ion implantation. By ion implantation
The dose of the impurity in the case of performing is 2-6 × 10 ^Fifteencm^-2
It is preferred that

Next, the doped layer and the mask layer are removed by etching or the like. As an etching solution, for example, buffered hydrofluoric acid or the like can be used. afterwards,
As shown in FIG. 2, an epitaxial layer 24 is grown on the surface of the semiconductor substrate 22. This epitaxial layer 24
Is not particularly limited, but is, for example, about 1 to 3 μm. This epitaxial layer 24 has the n-type conductivity type because it serves as the collector region of the npn bipolar transistor. As a growth gas for growing the epitaxial layer 24, for example, dichlorosilane (SiH
₂ Cl ₂ ) and phosphorus (P) as a dopant. As the epitaxial layer 24 grows, a collector buried region 26 is formed in a region where antimony is diffused.

Next, as shown in FIG. 3, an element isolation insulating film (LOCOS) 28 is formed on the surface of the epitaxial layer 24 in an element isolation pattern by using, for example, a LOCOS method using a silicon nitride film as a mask. . LOCO
Although the film thickness of S28 is not particularly limited, for example, 300
nm.

Next, as shown in FIG. 4, the element isolation impurity diffusion region 3 is formed in the bipolar transistor formation region in order to separate the bipolar transistors from each other.
0 is formed. This element isolation impurity diffusion region 30
For example, it is formed by selective ion implantation performed twice. The impurity to be ion-implanted has a conductivity type opposite to that of the collector region.
Type impurities are used. Also, simultaneously or in a separate process,
The p-type well region 3 is formed in the MOS transistor formation region.
Form 2

Next, the n-type collector buried layer 2 is formed in the epitaxial layer 24 in the bipolar transistor formation region.
An n-type collector extraction region 33 connecting the substrate 6 and the substrate surface is formed by ion-implanting phosphorus (Phos ⁺ ). The ion implantation conditions are not particularly limited, and are, for example, a condition of a dose of 1 × 10 ¹⁵ cm ⁻² and 500 KeV. After the ion implantation, a heat treatment for diffusing the impurities is performed. The heat treatment is performed, for example, by BiCMO
In the case of the S process, for example, it is performed simultaneously with the heat treatment for forming the source / drain regions. Specifically, the heat treatment temperature is, for example, 800 to 1000 ° C.

Next, on the surface of the semiconductor substrate 24 located between the LOCOSs 28, an insulating film (not shown) serving as a gate insulating film in the MOS transistor formation region is formed. The insulating film is made of, for example, a silicon oxide film, and its thickness is determined according to the designed thickness of the gate insulating film.

Next, a polysilicon layer of about 70 to 150 nm and a silicide layer (for example, tungsten silicide layer) of about 70 to 150 nm are sequentially formed by a CVD method or a sputtering method to form a gate electrode 36 having a polycide film structure. I do. This polycide film becomes the first conductive layer of the first layer formed on the surface of the semiconductor substrate 22.

Next, low-concentration arsenic is ion-implanted into the MOS transistor formation region to form self-aligned low-concentration source / drain regions for NMOS with the gate electrode 36. Next, an insulating sidewall 38 is formed on the side of the gate electrode 36. The insulating sidewall 38 is formed by depositing an insulating film such as a silicon oxide film and then performing anisotropic etching of the insulating film by RIE or the like. Thereafter, source / drain regions 40 having an LDD structure are formed by ion-implanting arsenic at a high concentration. Note that it is preferable to form the capping insulating film 42 before ion implantation for forming source / drain regions. The capping insulating film 42 is made of, for example, C
It is composed of a silicon oxide film formed by the VD method, and its thickness is, for example, 10 nm.

Next, an interlayer insulating film 44 is formed on the capping insulating film 42. The interlayer insulating film 44 is not particularly limited, but is composed of, for example, a silicon oxide film formed by a normal CVD method, a silicon oxide film formed by a TEOS-CVD method, and the like.
0 nm.

Next, a base opening 46 is formed in the interlayer insulating film 44 and the capping insulating film 42 in a pattern in which a base region of the bipolar transistor is formed by etching using a resist film. At the same time, an opening 48 for contact with the source / drain region 40 is formed in the MOS transistor formation region.

Next, as shown in FIG.
m polysilicon layer, 40-100 nm silicide layer
(For example, a tungsten silicide layer)
Alternatively, a film is formed by a sputtering method. This polysilicon
The laminated film of the layer and the silicide layer is a polycide film 50.
Corresponds to the second conductive layer of the second layer. This polycide
By patterning the film 50, the bipolar transistor
A base extraction electrode 52 is formed in the star formation region,
A wiring layer 54 is formed in the MOS transistor formation region.
You. The polycide film serving as the base extraction electrode 52
50 has boron B ⁺Is ion-implanted to form a wiring layer 54.
The polycide film 50 has phosphorus Phos⁺The ion implantation
I do. During these ion implantations, the type of impurities
Therefore, when implanting one ion, the other
Mask with a resist film.

Next, as shown in FIG. 6, TEOS (Tetraethyloxysilane or Tetraethy) is formed on the surface of the semiconductor substrate on which the base extraction electrode 52 and the wiring layer 54 are formed.
CV using lorthosilicate, Si (OC ₂ H ₅ ) ₄ )
A D film 56 is formed to have a thickness of 50 to 100 nm, and a reflow film 58 having a thickness of about 200 to 500 nm is formed thereon.
The film is formed by the VD method. The reflow film 58 becomes a flattening / offset film. As the reflow film 58, BPSG
It is composed of a film (boron and phosphorus-doped glass film), AsSG (arsenic-doped glass film) or PSG film (phosphorus-doped glass film), preferably a BPSG film. The reflow film 58 is reflowed by the heat treatment, and its surface is planarized. At the time of the heat treatment, impurities (boron) contained in the base extraction electrode 52 diffuse into the surface of the semiconductor substrate, and the graft base region 62 is formed.

After the reflow heat treatment, the reflow film 5
8 is, for example, TEO of about 50 to 100 nm.
The S-CVD film 60 is formed. In addition, this TEOS-C
Instead of the VD film 60, a silicon oxide film formed by a normal pressure CVD method may be used. Thus, the reflow film 58 is
The reason why it is sandwiched between non-doped insulating films such as the TEOS-CVD films 56 and 60 is to prevent impurities contained in the reflow film from diffusing into the base extraction electrode 52 or an emitter extraction electrode described later.

The flattening / offset insulating film is not limited to the reflow film 58, but may be an SOG film or the like which performs a flattening process by performing an etch-back process. However, also in this case, the TEOS-C
It is preferable to use in combination with a VD film or the like. This is for improving flattening.

Next, as shown in FIG. 7, the base-emitter opening 64 is etched by a resist film so as to expose the surface of the semiconductor substrate in a pattern corresponding to the intrinsic base of the bipolar transistor. To form Thereafter, an n-type impurity (for example, P, As) is ion-implanted through the opening 64, and an SIC (Selectively Implanted) is formed above the collector buried region 26.
Collector) region 66 is formed. By forming the SIC region 66, it is possible to suppress an increase in the effective base width in the high-injection region, further reduce the collector resistance, suppress an increase in the base-collector capacitance to a minimum portion, and improve the characteristics of the transistor. it can.

Thereafter, boron is ion-implanted into a relatively shallow region of the semiconductor substrate exposed by the opening 64, thereby forming an intrinsic base region 68. Next, as shown in FIG.
An insulating film of about 500 nm is formed over the entire surface. As the insulating film, a silicon oxide film formed by a TEOS-CVD method or a normal pressure CVD method can be used. Thereafter, the insulating film is entirely etched back to form an insulating sidewall 70 in the opening 64. As a result of the insulating sidewall 70 being formed in the opening,
The width of the opening 64 ranges from 0.7 to 0.8 μm to 0.3 to 0.8 μm.
It becomes about 0.4 μm.

Next, a polysilicon layer as a conductive layer serving as an emitter extraction electrode 72 is formed so as to enter the opening 64 in which the insulating sidewall 70 is formed.
A film having a thickness of about 100 to 200 nm is formed, and an n-type impurity is ion-implanted over the entire surface, and then patterned by etching to obtain an emitter extraction electrode 72.

Next, as shown in FIG. 10, an interlayer insulating film 74 is formed on the surface of the semiconductor substrate on which the emitter extraction electrode 72 has been formed. As the interlayer insulating film 74, B
It is preferable to be composed of a PSG film or a reflow film such as a PSG film. This is for planarizing the surface. Further, when a reflow film is used, impurities contained in the reflow film may diffuse into the emitter extraction electrode and change the characteristics of the bipolar transistor.
It is desirable to form a non-doped SiO ₂ film such as a TEOS-CVD film between them. The BiCMOS of the present embodiment
When the semiconductor device is used as a TFT load type SRAM device, a TEOS-type semiconductor device is formed before the interlayer insulating film 74 is formed.
A CVD film is formed, and a gate electrode layer of the TFT is formed thereon.
Gate insulating film, TFT channel layer and TEOS-C
After forming the VD film, an interlayer insulating film 74 is formed.

Next, in this embodiment, the interlayer insulating film 74 composed of a reflow film is heat-treated and flattened. At this time, impurities (for example, arsenic) contained in the emitter extraction electrode 72 diffuse into the surface of the intrinsic base region 68, and an emitter region 75 is formed. After that, the interlayer insulating film 74
Then, contact holes 76, 78, 80, 82 are formed. The contact hole 76 is provided in the base extraction electrode 52.
Is a contact hole for exposing a part of the surface of the substrate and making contact connection thereto. The contact hole 78 is a contact hole for exposing a part of the surface of the emitter extraction electrode 72 and making a contact connection therewith. The contact hole 80 is a contact hole for exposing a part of the surface of the collector extraction region 33 and making a contact connection thereto. The contact hole 82 is a contact hole for exposing a part of the surface of the wiring layer 54 in the MOS transistor formation region and making a contact connection thereto.

Next, as shown in FIG. 11, a barrier metal layer 83 is formed in each of the contact holes 76, 78, 80 and 82.
Is formed, a Ti plug 84 and an aluminum wiring layer 86 containing copper Cu are formed by a sputtering method or the like. The barrier metal layer 83 can be used by stacking Ti and TiN in order.

Thereafter, by patterning the wiring layer 86 and the Ti layer 84, a base electrode 88, an emitter electrode 90, a collector electrode 92 and a MOS electrode 94 are formed. Next, as shown in FIG. 1, after forming an interlayer insulating film 96, a second aluminum wiring layer (not shown) is formed, and an overcoat film 98 is formed thereon. I do. The overcoat film 98 is, for example, a plasma CV
It is composed of a silicon nitride film formed by the method D.

In the BiCMOS type semiconductor device and the method of manufacturing the same according to the present embodiment, the planarization is achieved by the reflow film 58 constituting the planarization / offset insulating film.
In addition, since the reflow film 58, which is a planarizing film, also serves as an offset insulating film, the thickness of the insulating film does not increase, and the step on the surface can be reduced. Therefore, a wide exposure margin for forming the TFT can be secured on the reflow film 58 and the CVD film 60, and the TFT can be formed with a highly accurate pattern. Also,
There is no disconnection of the wiring layer or the like.

Further, since the total thickness of the insulating film is reduced, the contact resistance of the contact portion formed on the insulating film is reduced, and the manufacturing process is stabilized.
The characteristics of the obtained transistor are also stabilized. Further, a reflow film 58 such as BPSG is used as the planarization and offset insulating film.
By sandwiching between the non-doped insulating films such as the VD films 56 and 60, it is possible to effectively prevent the impurities contained in the reflow film 58 from diffusing into the lower base extraction electrode 52 and the upper emitter extraction electrode 72. When impurities are diffused into these, there is a possibility that the characteristics of the transistor may fluctuate. In this embodiment, however, there is no such fear.

Further, as the base extraction electrode 52,
By using a polycide film, the polycide film is
It can also be used as the wiring layer 54 in the OS transistor formation region, which simplifies the manufacturing process and reduces steps.
Furthermore, the bipolar transistor due to the reduced base resistance
Speed of static, it is possible to achieve a high f _T of.

Further, in the manufacturing method of this embodiment, when the second conductive layer (polycide film, which becomes the base extraction electrode 52) of the second layer is etched, excessive over-etching is not required. The amount of etching digging on the surface of the semiconductor substrate on which the base and the emitter are formed can be minimized. Over-etching is unnecessary because the second conductive layer is patterned separately from the MOS transistor formation region. Second Embodiment Next, a second embodiment of the present invention will be described.

Since the manufacturing method of the present embodiment is almost the same as the manufacturing method of the BiCMOS type semiconductor device according to the first embodiment, the process drawings of the completely common parts are omitted, and the common members are omitted. The same reference numerals are given, and the description is partially omitted. In the manufacturing method of the present embodiment, the reflow film 58 is formed on the surface of the semiconductor substrate 22 through the steps of FIGS.
A D film 60 is formed, and on the surface thereof, as shown in FIG.
The etching stop detection layer 100 is formed. When the etching stop detection layer 100 is subjected to an etching process to form an insulating sidewall 70 described later,
This is a layer for detecting the end point of the etching, and is formed of, for example, a polysilicon layer having a thickness of about 30 to 100 nm.

Next, as shown in FIG. 13, the base-emitter opening 64 is etched by a resist film so as to expose the surface of the semiconductor substrate in a pattern corresponding to the intrinsic base of the bipolar transistor. To form Thereafter, an n-type impurity (eg, P, As) is ion-implanted through the opening 64, and an SIC (Selectively Implant) is formed above the collector buried region 26.
(ed Collector) region 66 is formed. SIC area 66
By forming, it is possible to suppress the increase in the effective base width in the high implantation region, further reduce the collector resistance, suppress the increase in the base-collector capacitance to a minimum portion, and improve the characteristics of the transistor.

Thereafter, boron is ion-implanted into a relatively shallow region of the semiconductor substrate exposed by the opening 64, thereby forming an intrinsic base region 68. Next, FIG.
As shown in FIG.
An insulating film of about 500 nm is formed on the entire surface. As the insulating film, a silicon oxide film formed by a TEOS-CVD method or a normal pressure CVD method can be used. Then, this insulating film is etched back on the entire surface,
An insulating sidewall 70 is formed in the opening 64.

Next, a polysilicon layer as a conductive layer serving as an emitter extraction electrode 72 is formed so as to enter the opening 64 in which the insulating sidewall 70 is formed.
A film having a thickness of about 100 to 200 nm is formed, and an n-type impurity is ion-implanted over the entire surface, and then patterned by etching to obtain an emitter extraction electrode 72. At that time, most of the etching stop detection layer 100 is also removed, and C
It remains only in the portion located above the VD film 60 and below the emitter extraction electrode 72.

Next, as shown in FIG. 16, an interlayer insulating film 74 is formed on the surface of the semiconductor substrate on which the emitter extraction electrode 72 has been formed. As the interlayer insulating film 74, B
It is preferable to be composed of a PSG film or a reflow film such as a PSG film. This is for planarizing the surface. When a reflow film is used, it is desirable to form a TEOS-CVD film between the emitter extraction electrode and the reflow film. When the BiCMOS type semiconductor device of this embodiment is used as a TFT load type SRAM device, a TEOS-CVD film is formed before the interlayer insulating film 74 is formed, and a gate electrode of the TFT is formed thereon. After forming a layer, a gate insulating film, a channel layer of a TFT, and a TEOS-CVD film, an interlayer insulating film 74 is formed.

Next, in this embodiment, the interlayer insulating film 74 composed of the reflow film is heat-treated and flattened. At this time, impurities (for example, arsenic) contained in the emitter extraction electrode 72 diffuse into the surface of the intrinsic base region 68, and an emitter region 75 is formed. After that, the interlayer insulating film 74
Then, contact holes 76, 78, 80, 82 are formed. The contact hole 76 is provided in the base extraction electrode 52.
Is a contact hole for exposing a part of the surface of the substrate and making contact connection thereto. The contact hole 78 is a contact hole for exposing a part of the surface of the emitter extraction electrode 72 and making a contact connection therewith. The contact hole 80 is a contact hole for exposing a part of the surface of the collector extraction region 33 and making a contact connection thereto. The contact hole 82 is a contact hole for exposing a part of the surface of the wiring layer 54 in the MOS transistor formation region and making a contact connection thereto.

Next, as shown in FIG. 17, a barrier metal layer 83 is formed in each of the contact holes 76, 78, 80, 82.
Is formed, and buried with a tungsten plug, a Ti layer 84 and an aluminum wiring layer 86 containing copper Cu are formed by a sputtering method or the like. As the barrier metal layer 83, Ti and TiN can be used by sequentially laminating them.

Thereafter, the wiring layer 86 and the Ti layer 84 are patterned to form a base electrode 88, an emitter electrode 90, a collector electrode 92, and a MOS electrode 94. Next, as shown in FIG. 18, after forming an interlayer insulating film 96, a second aluminum wiring layer (not shown) is formed, and an overcoat film 98 is formed thereon. I do. The overcoat film 98 is made of, for example, plasma C
It is composed of a silicon nitride film formed by the VD method.

The BiCMOS semiconductor device and the method of manufacturing the same according to the present embodiment have the same functions as those of the first embodiment, and also have the following functions. In this embodiment, as shown in FIG. 14, since the etching stop detection layer 100 is formed on the reflow film 58 and the CVD film 60 as the planarization and offset insulating film, the insulating sidewall 70 is formed. During the etching process (eg, during RIE), the end point of the etching process of the insulating film for forming the sidewall can be detected. That is, when the insulating film for forming the sidewall is etched, the etching stop detecting layer 100 is exposed at the timing of the end point, and the insulating film on the etching stop detecting layer that occupies most of the insulating film for forming the sidewall is formed. The loss of the film can be detected by an etching device (RIE device). As a result, the thickness of the insulating sidewall 70 formed on the side of the base / emitter opening 64 can be controlled well. Therefore, it is possible to manufacture a bipolar transistor with stable emitter / base insulation and stable characteristics.

Further, in the present embodiment, on the reflow film 58 and the CVD film 60 as a planarization and offset insulating film and below the emitter extraction electrode, FIGS.
As shown in FIG. 6, the etching stop detection layer 100 remains. For this reason, the CVD film 60 below the etching stop detection layer 100 becomes a barrier layer, and from the reflow film 58,
Through the emitter extraction electrode 72, the emitter region 75
This prevents diffusion of impurities such as phosphorus. When the impurity diffusion occurs, it becomes difficult to control the depth of the emitter region 75, but in the present embodiment, such a situation can be effectively avoided.

Further, the etching stop detecting layer 100
(For example, a polysilicon layer), as shown in FIGS.
As shown in FIG. 7, the thickness of the emitter extraction electrode 72 can be increased at the time of etching when the emitter electrode 90 is connected to the emitter extraction electrode 72, so that it is possible to compensate for excessive excavation of the emitter extraction electrode 72.

Further, the etching stop detecting layer 100 other than the portion where the emitter extraction electrode is formed is simultaneously removed when the emitter extraction electrode is etched.
The etching stop detection layer 100 itself does not become a factor for increasing the level difference. Note that the present invention is not limited to the above-described embodiments, and can be variously modified within the scope of the present invention.

[0067]

As described above, according to the present invention, as the offset insulating film of the bipolar transistor, the planarization insulating film for mainly planarizing the MOS transistor formation region is used. Eliminates the need to separately form a planarizing insulating film. As a result, the total thickness of the insulating film is reduced, and an increase in the level difference on the surface of the insulating film can be prevented.

Therefore, a TFT is formed on the surface of the insulating film.
Alternatively, the wiring layer can be satisfactorily formed with a high-precision pattern without causing a disconnection phenomenon of the wiring. Further, since the thickness of the insulating film becomes thinner in total, the contact resistance of the contact portion formed in the insulating film is reduced, the manufacturing process is stabilized, and the characteristics of the obtained transistor are also stabilized.

Further, when a reflow film such as BPSG is used as the flattening / offset insulating film, the reflow film is sandwiched between non-doped insulating films such as a TEOS-CVD film to reduce impurities contained in the reflow film. ,
Diffusion to the base extraction electrode on the lower layer side and the emitter extraction electrode on the upper layer side can be effectively prevented. Impurities
When diffused into these, there is a possibility that the characteristics of the transistor may fluctuate, but in the present invention, there is no such fear.

Further, by using a polycide film as the base extraction electrode, the polycide film can be
Can also be used as a wiring layer in the transistor formation area,
This simplifies the manufacturing process and reduces steps, and further improves the bipolar transistor characteristics in the high-injection region by reducing the base resistance (the collector current can be increased).

Further, in the manufacturing method of the present invention, the second
Excessive over-etching is not required when etching the second conductive layer (for example, a polycide film and becomes a base extraction electrode), so that the amount of etching excavation on the surface of the semiconductor substrate on which the base and the emitter are formed is minimized. Can be minimized. Over-etching is unnecessary because the second conductive layer is patterned separately from the MOS transistor formation region.

In particular, in the present invention in which the etching stop detecting layer is formed on the flattening and offset insulating film, the etching for forming the insulating sidewall (for separating the emitter / base) in the base / emitter opening. At the time of processing (for example, at the time of RIE), the end point of the etching processing of the insulating film for forming a sidewall can be detected.
That is, when the insulating film for forming the sidewall is etched, the etching stop detecting layer is exposed at the timing of the end point, and the etching device (RIE device) is used.
Can be detected. As a result, the thickness of the insulating sidewall formed on the side of the base / emitter opening can be controlled well. Therefore, it is possible to manufacture a bipolar transistor with stable emitter / base insulation and stable characteristics.

Further, in this case, the above-mentioned etching stop detection layer remains on the flattening / offset insulating film and below the emitter electrode. It is possible to prevent impurities such as phosphorus from diffusing.
When the impurity diffusion occurs, it becomes difficult to control the depth of the emitter, but such a situation can be avoided in the present invention.

Furthermore, the presence of the etching stop detection layer (for example, a polysilicon layer) allows the thickness of the emitter extraction electrode to be increased during the etching process for connecting the emitter electrode on the emitter extraction electrode. Over-digging can be compensated.

Further, since the etching stop detecting layer is shaved at the same time as the etching of the emitter electrode, the etching stop detecting layer itself does not become a factor for increasing the level difference.

[Brief description of the drawings]

FIG. 1 is a diagram showing a BiCMOS according to a first embodiment of the present invention;
FIG. 3 is a cross-sectional view of a main part of the semiconductor device of the first embodiment.

FIG. 2 is a fragmentary cross-sectional view showing a manufacturing process of the BiCMOS semiconductor device shown in FIG. 1;

FIG. 3 is an essential part cross sectional view showing a step that follows the step shown in FIG. 2;

FIG. 4 is a fragmentary cross-sectional view showing a step that follows the step shown in FIG. 3;

FIG. 5 is an essential part cross sectional view showing a step continued from FIG. 4;

FIG. 6 is an essential part cross sectional view showing a step that follows the step shown in FIG. 5;

FIG. 7 is an essential part cross sectional view showing a step that follows the step shown in FIG. 6;

FIG. 8 is an essential part cross sectional view showing a step that follows the step shown in FIG. 7;

FIG. 9 is an essential part cross sectional view showing a step that follows the step shown in FIG. 8;

FIG. 10 is an essential part cross sectional view showing a step that follows the step shown in FIG. 9;

FIG. 11 is an essential part cross sectional view showing a step subsequent to that of FIG. 10;

FIG. 12 is a diagram illustrating a BiCM according to another embodiment of the present invention.
FIG. 10 is a cross-sectional view of a principal part illustrating a manufacturing process of the OS-type semiconductor device.

FIG. 13 is a fragmentary cross-sectional view showing a step that follows the step shown in FIG. 12;

FIG. 14 is an essential part cross sectional view showing a step that follows the step shown in FIG. 13;

FIG. 15 is an essential part cross sectional view showing a step that follows the step shown in FIG. 14;

FIG. 16 is an essential part cross sectional view showing a step that follows the step shown in FIG. 15;

FIG. 17 is an essential part cross sectional view showing a step continued from FIG. 16;

FIG. 18 is an essential part cross sectional view showing a step continued from FIG. 17;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 12 ... Bipolar transistor formation area 14 ... MOS transistor formation area 20 ... Semiconductor device 22 ... Semiconductor substrate 24 ... Epitaxial layer 26 ... Collector buried layer 28 ... Element isolation insulating film (LOCOS) 36 ... Gate electrode 52 ... Base extraction electrode 54 ... Wiring Layers 56, 60 TEOS-CVD film 58 Reflow film (flattening and offset insulating film) 62 Graft base region 64 Base / emitter opening 68 Intrinsic base region 70 Insulating sidewall 72 Emitter extraction electrode 100 ... Etching stop detection layer

──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Koichi Tabira 6-7-35 Kita Shinagawa, Shinagawa-ku, Tokyo Inside Sony Corporation (56) References JP-A-4-3233862 (JP, A) JP-A Heihei 3-49234 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) H01L 21/8249 H01L 27/06 H01L 21/822

Claims (10)

(57) [Claims] 1. A method of manufacturing a BiCMOS type semiconductor device in which a MOS transistor and a bipolar transistor are formed on a semiconductor substrate, wherein a first conductive layer is formed on a surface of the semiconductor substrate via a gate insulating layer. A step of etching the first conductive layer to form a gate electrode of the MOS transistor in the MOS transistor formation region; a step of forming an interlayer insulating film on the gate electrode; Forming a second conductive layer on the film; etching the second conductive layer; forming a base extraction electrode in a bipolar transistor formation region;
Forming a wiring layer connected to the source / drain region of the MOS transistor in the OS transistor formation region; and forming an emitter and a bipolar transistor of the bipolar transistor on the second conductive layer forming the base extraction electrode and the wiring layer.
Offset for forming the base in a self-aligned manner
The bets, forming a flat Kaken offset insulating film, a step of flattening the surface of the flat Kaken offset insulating film, to solid-phase diffusing impurities contained in the base take-out electrode on the surface of the semiconductor substrate Forming a base region in a self-aligned manner; and etching the flattening / offset insulating film and the base extraction electrode located in the bipolar transistor formation region to expose a surface of the semiconductor substrate.
Forming an emitter opening; forming an insulating sidewall on the inner wall of the base / emitter opening; and forming a base / emitter opening on which the insulating sidewall is formed, A method for manufacturing a BiCMOS type semiconductor device, comprising: a step of forming an emitter extraction electrode so as to enter therein; and a step of forming an emitter region in a self-aligned manner on a surface of a semiconductor substrate by diffusing impurities from the emitter extraction electrode. 2. The flattening / offset insulating film is composed of a reflow film containing impurities, and a flattening process is performed by heat-treating the reflow film.
2. The BiCMO according to claim 1 , wherein the base region is formed in a self-aligned manner by simultaneously diffusing impurities contained in the base extraction electrode into the surface of the semiconductor substrate.
A method for manufacturing an S-type semiconductor device. 3. The method of manufacturing a BiCMOS semiconductor device according to claim 2 , wherein a non-doped insulating film containing no impurity is formed at least below the reflow film. Claim 3, characterized in that said non-doped insulating film is formed by CVD method using TEOS
3. The method for manufacturing a BiCMOS semiconductor device according to 1. 5. at least one of the first conductive layer and the second conductive layer, claim to the polysilicon film, and forming a polycide film which is a laminated structure of a silicide layer 1-4 The method for manufacturing a BiCMOS semiconductor device according to any one of the above. 6. A method for manufacturing a BiCMOS type semiconductor device in which a MOS transistor and a bipolar transistor are formed on a semiconductor substrate, wherein a first conductive layer is formed on a surface of the semiconductor substrate via a gate insulating layer. A step of etching the first conductive layer to form a gate electrode of the MOS transistor in the MOS transistor formation region; a step of forming an interlayer insulating film on the gate electrode; Forming a second conductive layer on the film; etching the second conductive layer; forming a base extraction electrode in a bipolar transistor formation region;
Forming a wiring layer connected to the source / drain region of the MOS transistor in the OS transistor formation region; and forming an emitter and a bipolar transistor of the bipolar transistor on the second conductive layer forming the base extraction electrode and the wiring layer.
Offset for forming the base in a self-aligned manner
The bets, forming a flat Kaken offset insulating film, a step of flattening the surface of the flat Kaken offset insulating film, to solid-phase diffusing impurities contained in the base take-out electrode on the surface of the semiconductor substrate Forming a base region in a self-aligned manner; forming an etching stop detection layer on the planarization / offset insulating film; etching stop detection layer located in the bipolar transistor formation region; Etching the insulating film and the base extraction electrode to form a base / emitter opening exposing the surface of the semiconductor substrate; and forming a sidewall forming insulating film so as to enter the base / emitter opening. Forming the insulating film for forming a sidewall, and forming the insulating film for sidewall formation on the surface of the etching stop detecting layer. Forming an insulating sidewall on the inner wall portion of the base / emitter opening until it is detected that the base / emitter is exposed; and a base / emitter having the insulating sidewall formed thereon. A step of forming an emitter extraction electrode in the opening, and removing the etching stop detection layer in a portion other than the lower part of the emitter extraction electrode during the etching of the emitter extraction electrode; Forming a self-aligned emitter region on the surface of the semiconductor substrate by impurity diffusion. 7. The flattening / offset insulating film is composed of a reflow film containing impurities, and a flattening process is performed by heat-treating the reflow film.
7. The BiCMO according to claim 6 , wherein the base region is formed in a self-aligned manner by simultaneously diffusing impurities contained in the base extraction electrode into the surface of the semiconductor substrate.
A method for manufacturing an S-type semiconductor device. 8. The method of manufacturing a BiCMOS semiconductor device according to claim 7 , wherein a non-doped insulating film containing no impurity is formed at least below the reflow film. 9. The method of claim 8, characterized in that said non-doped insulating film is formed by CVD method using TEOS
3. The method for manufacturing a BiCMOS semiconductor device according to 1. 10. at least one of the first conductive layer and the second conductive layer, and the polysilicon film, claim and forming a polycide film which is a laminated structure of a silicide layer 6-9 BiCMOS according to any of the above
Of manufacturing a semiconductor device.