JP3216716B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the manufacture of a semiconductor device such as a BiCMOS incorporating a vertical PNP and / or NPN bipolar transistor (hereinafter referred to as V-PNP and V-NPN) which can easily reduce the element size. About the method.

[0002]

2. Description of the Related Art Hitherto, in a BiCMOS process incorporating V-PNP and V-NPN, high-concentration impurities are diffused from a substrate surface to form respective bipolar collector leading regions.

A conventional manufacturing method will be described with reference to FIGS. First, as shown in FIG. 11A, after a field oxide film 102 for defining an element region is formed on a P-type silicon substrate 101, the surface of the substrate 101 is oxidized to form an oxide film 103 having a thickness of 5 to 20 nm. To form. Thereafter, heat treatment is performed after high-concentration boron or phosphorus ions are implanted to form a V-PNP P-type collector lead-out region 104 and a V-NPN N-type collector lead-out region 105.

[0004] Next, as shown in FIG.
S P well 106, PMOS N well 107, V−
PNP N-type isolation region 108 and P-type collector region 1
Further, an N-type base region 110, an N-type collector region 111 of V-NPN, and a P-type base region 112 are formed.

Next, as shown in FIG. 11C, the polycrystalline silicon layer having a thickness of 200 to 300 nm grown on the entire surface is patterned to form gate electrodes 113 and 114 in the CMOS portion. Also, a polycrystalline silicon layer serving as a mask layer 115 is left on the N-type base region 110 of the V-PNP.

Next, as shown in FIG. 12A, an oxide film 116 having a thickness of 50 to 100 nm is formed on the entire surface.
To form the NPN emitter contact 117, the oxide film 116 in that portion is etched to expose the silicon substrate surface.

Next, as shown in FIG. 12B, a polycrystalline silicon layer 118 having a thickness of 200 to 300 nm is grown on the entire surface, and arsenic of 1 to 2 × 10 ¹⁶ cm ^-2 is ion-implanted into the polycrystalline silicon layer 118. .

Next, as shown in FIG. 12C, the polysilicon layer 118 is etched using the resist 120 as a mask to form a V-NPN emitter electrode 119.

Next, after removing the resist 120, FIG.
As shown in FIG. 2A, after an oxide film (not shown) having a thickness of 50 to 100 nm is grown on the entire surface, anisotropic dry etching is performed to form CMOS gate electrodes 113 and 11.
4, the V-PNP mask layer 115, and the V-NPN emitter electrode 119 on the side walls 121, 1
22, 123 and 124 are formed. Thereafter, the NMOS gate electrode 113 and the source / drain regions 125,
Arsenic is ion-implanted into the external base region 128 of the V-PNP at a dose of 2 to 4 × 10 ¹⁵ cm ⁻² . Meanwhile, PMO
S gate electrode 114 and source / drain region 12
6. V-PNP emitter region 127 and V-NPN
Ions of boron or BF ₂ are implanted into the P-type external base region 130 at a dose of 1 to 5 × 10 ¹⁵ cm ⁻² . Thereafter, a heat treatment is performed so that the V-NPN emitter electrode 11 is formed.
Arsenic diffuses from the polycrystalline silicon layer 9 into the base region 112 to form an N-type emitter region 129.

Next, after opening a contact in the interlayer insulating film 131 formed on the element formed in the above-described process, a plug 132 is formed with tungsten or the like, and each metal wiring 133 is formed.
Is obtained, the semiconductor device shown in FIG. 13B is obtained.

In the above method, a high concentration impurity is diffused from the surface of the substrate to form each bipolar collector leading region. This requires not only a lithography step, an ion implantation step, and a heat treatment step, but also the spacing and size of elements must be increased because impurities diffuse in the collector extraction region in the lateral direction.

[0012]

SUMMARY OF THE INVENTION The present invention provides a V-PNP
Another object of the present invention is to solve the problems in the conventional BiCMOS process incorporating V-NPN and V-NPN, to provide a manufacturing method capable of reducing the number of steps and reducing the element size.

[0013]

According to the present invention, at least (1) a method for manufacturing a BiCMOS incorporating a vertical PNP and an NPN bipolar transistor is provided.
Forming a field oxide film defining an element region on a P-type silicon substrate, and then forming a first oxide film on the substrate surface; (2) forming a CMOS gate electrode and a V-PNP having an ion-implanted emitter structure; Forming a polycrystalline silicon layer including one or more oxide films therein as a mask for the region; (3) forming a second oxide film on the entire surface of the substrate including the CMOS gate electrode and the mask; Removing the first and second oxide films at the collector contact and emitter contact formation sites of the transistor; (4) removing the polysilicon layer in the V-PNP emitter contact portion when patterning the polysilicon layer; Etching the silicon of the NPN and the collector of the PNP at the same time. The emitter contact portion of the PNP has polycrystalline silicon layer comprising a thin oxide film layer described above,
By protecting the lower silicon substrate, not only the number of steps but also the transistor size can be reduced.

The present invention also relates to a capacitor and a V-PNP.
In a method of manufacturing a BiCMOS incorporating (i), at least (1) a step of forming a field oxide film defining an element region on a P-type silicon substrate and then forming a first oxide film on a surface of the substrate; Forming a polycrystalline silicon layer including one or more oxide films therein as a gate electrode, a mask of a V-PNP formation region having an ion-implanted emitter structure, and a lower electrode of a capacitor element; (3) the CMOS gate Forming a second oxide film on the entire surface of the substrate including the electrodes and the mask, and removing at least the first and second oxide films at the collector contact and emitter contact formation portions of the bipolar transistor; (4) the polycrystalline silicon layer At the same time as removing the polycrystalline silicon layer at the emitter contact portion of the V-PNP at the time of patterning, Etching the silicon Kuta part, relating to the manufacturing method having the city.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment will be described with reference to FIGS. First, as shown in FIG. 1A, a field oxide film 2 defining an element region is formed on a P-type silicon substrate 1 in the same manner as in a conventional manufacturing method, and then a 5 to 20 nm thick film is formed on the surface of the substrate 1. An oxide film 3 is formed. Thereafter, the NMOS P-well 4, the PMOS N-well 5, the V-PNP N-type isolation region 6 and the P-type collector region 7, the N-type base region 8, the V-NPN N-type collector region 9, and the P-type base region Form 10.

Next, as shown in FIG. 1B, a 200-300 nm-thick polycrystalline silicon layer (not shown) grown on the entire surface is patterned to form a gate electrode 1 in the CMOS portion.
1 and 12 are formed. Also, a polycrystalline silicon layer serving as a mask layer 13 is left on the N-type base region 8 of the V-PNP. Here, the polycrystalline silicon layer includes a plurality of oxide films having a thickness of 1 to 2 nm (two oxide film layers in FIG. 1B). The oxide film layer and the polycrystalline silicon layer can be continuously grown by changing gas conditions when growing the polycrystalline silicon layer.

Next, as shown in FIG. 1C, after an oxide film 14 having a thickness of 50 to 100 nm is formed on the entire surface, the oxide film 14 is selectively etched to form a V-PNP collector contact opening. 15 and an upper opening 16 of the mask layer 13;
A V-NPN collector contact opening 17 and an emitter contact opening 18 are formed to expose the silicon substrate surface.

Next, as shown in FIG. 2 (a), growing a polycrystalline silicon layer 19 having a thickness of 200~300nm on the entire surface, this to 1~2 × 10 ¹⁶ cm ^-2 of arsenic is ion-implanted .

Next, as shown in FIG. 2B, using the resist 20 as a mask, the polycrystalline silicon layer 19 is etched to form a V-NPN emitter electrode 21. Also, an over-etch is performed to form a mask layer 1 in the V-PNP portion.
The emitter contact 22 is formed by etching the polycrystalline silicon layer 3 to the surface of the oxide film 3. Further, the silicon substrate is dug down to form V-PNP and V-NPN collector contacts 23 and 24. Mask layer 13
An oxide film layer (having a thickness of 1 to 2 nm) having a lower etching rate than the polycrystalline silicon layer is present therein, and this serves as a protective film for etching.
VP even when etched to a depth of ~ 800 nm
It is possible to prevent the oxide film 3 of the NP emitter contact 22 from being etched back so that the silicon layer thereunder is not dug.

Next, after removing the resist, as shown in FIG. 2C, an oxide film (not shown) having a thickness of 50 to 100 nm is grown on the entire surface, and anisotropic dry etching is performed. CMOS gate electrodes 11 and 12 and V-
PNP mask layer 13, V-NPN emitter electrode 21
Side walls 25, 26, 27, 28 are formed on the side walls of the. Thereafter, the NMOS gate electrode 11 and the source / drain region 29, and the V-PNP external base region 3
3. Arsenic is ion-implanted into the V-NPN N-type collector extraction region 34 at a dose of 2 to 4 × 10 ¹⁵ cm ⁻² . On the other hand, boron or BF ₂ is supplied to the gate electrode 12 and the source / drain region 30 of the PMOS, the emitter region 32 of the V-PNP, the P-type collector lead-out region 31 and the P-type external base region 36 of the V-NPN with a dose of 1 to 5 ×
Ion implantation at 10 ¹⁵ cm ^-2 . Thereafter, by performing a heat treatment, arsenic is diffused from the polycrystalline silicon layer which is the V-NPN emitter electrode 21 to the base region 10, and the N-type emitter region 35 is formed.

Next, after opening a contact in the interlayer insulating film 37 formed on the element formed in the above-described process, a plug 38 is formed with tungsten or the like, and each metal wiring 39 is formed, as shown in FIG. A semiconductor device is obtained.

In FIG. 2B, the polycrystalline silicon layer 19 is etched using the resist 20 as a mask, and VN
Overetching is performed at the same time as the formation of the PN emitter electrode 21, and etching of the mask layer 13 and formation of trenches in the collector contacts 23 and 24 are performed. As the etching conditions, reactive ion etching using a mixed gas of chlorine and oxygen is desirable, and by setting the gas mixture ratio and pressure to predetermined values, the etching rate of the oxide film can be reduced to 1/100 that of the polycrystalline silicon layer. It can be easily set to 20 to 1/150. The mask layer 13 includes an oxide film layer having a thickness of 1 to 2 nm, which serves as a protective layer at the time of etching the polycrystalline silicon layer and the silicon substrate. However, since the oxide film has an insufficient thickness to completely stop etching, it is preferable to provide a plurality of layers.

In FIG. 3, the electrode is directly drawn out from the collector lead-out regions 29 and 30 of the collector portion where the trench is formed by using the plug 38. Since there is no lateral diffusion of impurities compared to the conventional method of diffusing a high concentration of impurities from the substrate surface, it is easy to reduce the transistor size and spacing. 4 and 5 show the withstand voltage between the collectors of adjacent V-PNPs, and it can be seen that the gap between the collectors can be narrowed by 0.6 μm as compared with the conventional method. 6 and 7 show the breakdown voltage between the external base and the collector. In the conventional example, the gap is 0.8 μm.
It can be seen that the breakdown voltage sharply decreases at the time of, whereas the invention can suppress the reduction of the breakdown voltage.

According to this embodiment, not only the number of steps can be reduced, but also the size and interval of the bipolar transistor can be reduced.

Referring to the manufacturing process sectional views of FIGS.
An embodiment will be described.

First, as shown in FIG. 8A, a field oxide film 2 for defining an element region is formed on a P-type silicon substrate 1 in the same manner as in the first embodiment. An oxide film 3 having a thickness of 5 to 20 nm is formed. After that, NMO
An S-type P well 4, a PMOS N-well 5, a V-PNP N-type isolation region 6, a P-type collector region 7, and an N-type base region 8 are formed.

Next, as shown in FIG. 8B, a 200-300 nm-thick polycrystalline silicon layer (not shown) grown on the entire surface is patterned to form a gate electrode 1 in the CMOS portion.
1 and 12 are formed. Also, a polycrystalline silicon layer serving as a mask layer 13 is left on the N-type base region 8 of the V-PNP. Further, a polycrystalline silicon layer serving as the lower electrode 40 of the capacitive element is also left on the field oxide film 2. Here, as in the first embodiment, the polycrystalline silicon layer includes a plurality of thin (1-2 nm) oxide film layers.

Next, as shown in FIG. 8C, after an oxide film 14 having a thickness of 50 to 100 nm is formed on the entire surface, the oxide film 14 is selectively etched to form a V-PNP collector contact. The surface of the silicon substrate is exposed through the opening 15 and the upper opening 16 of the mask layer 13.

Next, as shown in FIG. 9A, a polycrystalline silicon layer 19 having a thickness of 200 to 300 nm is grown on the entire surface, and arsenic of 1 to 2 × 10 ¹⁶ cm ⁻² is ion-implanted into the polycrystalline silicon layer 19. .

Next, as shown in FIG. 9B, using the resist 41 as a mask, the polycrystalline silicon layer 19 is etched to form the upper electrode 42 of the capacitor. Further, an overetch is performed, and the polycrystalline silicon layer of the mask layer 13 in the V-PNP is etched to the surface of the oxide film 3 to form the emitter contact 22. At the same time, V-PNP
The silicon substrate is dug down to form the collector contact 23 of FIG. The mask layer 13 has a thin oxide film layer as described above, and has a collector contact of 400 to 800 nm.
Does not etch back the oxide film 3 on the bottom of the V-PNP emitter contact 22.

Next, after removing the resist, an oxide film (not shown) having a thickness of 50 to 100 nm is grown on the entire surface as shown in FIG. Gate electrodes 11 and 12 and V-
Sidewalls are formed on the PNP mask layer 13 and on the sidewalls of the upper and lower electrodes 40 and 42 of the capacitor. Thereafter, arsenic is ion-implanted into the NMOS gate electrode 11, the source / drain region 29, and the V-PNP external base region 33 at a dose of 2 to 4 × 10 ¹⁵ cm ⁻² . on the other hand,
Dose of boron or BF ₂ is 1 for the PMOS gate electrode 12 and the source / drain region 30, the V-PNP emitter region 32 and the P-type collector lead-out region 31.
Ion implantation is performed at about 5 × 10 ¹⁵ cm ⁻² .

Next, after a contact is opened in the interlayer insulating film 37 formed on the element formed in the above-described process, a plug 38 is formed with tungsten or the like, and each metal wiring 39 is formed, as shown in FIG. A semiconductor device is obtained.

According to the above-described manufacturing method, it is possible to form a capacitance element without increasing the number of steps in the CMOS, V-PNP, and V-NPN shown in the first embodiment.

[Brief description of the drawings]

FIG. 1 is a sectional manufacturing process view of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a sectional manufacturing process view of the semiconductor device, following FIG. 1;

FIG. 3 is a cross-sectional view of a semiconductor device obtained as a result of the manufacturing steps shown in FIGS. 1 and 2;

FIG. 4 is a schematic cross-sectional view for explaining a collector interval.

FIG. 5 is a graph comparing the relationship between the collector interval and the transistor breakdown voltage between the present invention and a conventional example.

FIG. 6 is a schematic cross-sectional view for explaining an external base-collector interval.

FIG. 7 is a graph comparing the relationship between the external base-collector distance and the transistor breakdown voltage between the present invention and a conventional example.

FIG. 8 is a sectional manufacturing process view of the semiconductor device according to the second embodiment of the present invention.

FIG. 9 is a sectional manufacturing process view of the semiconductor device, following FIG. 8;

FIG. 10 is a cross-sectional view of a semiconductor device obtained as a result of the manufacturing steps shown in FIGS. 8 and 9;

FIG. 11 is a sectional process view showing a manufacturing process of a conventional example.

FIG. 12 is a sectional process view showing a manufacturing process of a conventional example.

FIG. 13 is a cross-sectional view of a semiconductor device obtained by a conventional manufacturing method.

[Explanation of symbols]

 Reference Signs List 1 substrate 2 field oxide film 3 oxide film 4 P well 5 N well 6 N-type isolation region of V-PNP 7 P-type collector region of V-PNP 8 N-type base region of V-PNP 9 N-type collector of V-NPN Region 10 P-type base region of V-NPN 11, 12 Gate electrode 13 Mask layer 14 Oxide film 15 Collector contact opening 16 Upper mask layer 17 Collector contact opening of V-NPN 18 Emitter contact opening of V-NPN 19 Many Crystal silicon layer 20 Resist 21 V-NPN emitter electrode 22 V-PNP emitter contact 23 V-PNP collector contact 24 V-NPN collector contact 25 Sidewall 26 Sidewall 27 Sidewall 28 Sidewall 29 NMOS source / Drain region Reference Signs List 30 Source / drain region of PMOS 31 P-type collector lead-out part 32 Emitter region of V-PNP 33 External base region of V-PNP 34 N-type collector lead-out region of V-NPN 36 P-type external base region of V-NPN 35 N Type emitter region 37 interlayer insulating film 38 contact plug 39 metal wiring 40 lower electrode 41 resist 42 upper electrode 43 sidewall

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification code FI H01L 27/04 H01L 29/72 P 27/06 29/44 B 27/082 21/302 J 29/41 29/732

Claims (6)

(57) [Claims] 1. A vertical PNP and NPN bipolar transistor (hereinafter referred to as V-PNP and V-NP).
N), a step of (1) forming at least (1) a field oxide film defining an element region on a P-type silicon substrate and then forming a first oxide film on the substrate surface; 2) a step of forming a polycrystalline silicon layer including one or more oxide films therein as a mask for a CMOS gate electrode and a V-PNP formation region having an ion-implanted emitter structure; (3) the CMOS gate electrode and Forming a second oxide film on the entire surface of the substrate including the mask, and removing at least the first and second oxide films at the collector contact and emitter contact formation sites of the bipolar transistor; (4) patterning the polycrystalline silicon layer At the same time, the polycrystalline silicon layer at the emitter contact portion of the V-PNP is removed and simultaneously the NPN
And etching silicon at the collector of the PNP. 2. The method according to claim 1, wherein the oxide film in the polycrystalline silicon layer formed as the mask has a thickness of 1 to 2 nm. 3. The first oxide film has a thickness of 5 to 20 nm.
The method according to claim 1, wherein: 4. A method of manufacturing a BiCMOS incorporating a capacitor and a V-PNP, wherein at least (1) P
Forming a field oxide film defining an element region on a silicon substrate, and then forming a first oxide film on the surface of the substrate; (2) forming a gate electrode of a CMOS and a V-PNP formation region of an ion implantation emitter structure; Forming a polycrystalline silicon layer including one or more oxide films therein as a mask and a lower electrode of the capacitor element portion; (3) forming a second oxide film on the entire surface of the substrate including the CMOS gate electrode and the mask; Forming and removing at least the first and second oxide films in the collector contact and emitter contact formation sites of the bipolar transistor; (4) the polycrystalline V-PNP emitter contact portion when patterning the polycrystalline silicon layer. At the same time as removing the silicon layer, the PNP
Etching the silicon of the collector part of the above. 5. The method according to claim 4, wherein the thickness of the oxide film in the polycrystalline silicon layer formed as the mask is 1 to 2 nm. 6. The first oxide film has a thickness of 5 to 20 nm.
The method according to claim 4, wherein: