JP3254549B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device using a MOSFET, and more particularly to a CMOS type semiconductor integrated circuit device having a long wiring.

[0002]

2. Description of the Related Art As semiconductor integrated circuits are miniaturized, MOS
As the gate oxide of FETs has become thinner, the gate oxide has become more susceptible to damage during the manufacturing process. If the gate oxide film is damaged, problems such as a change in the threshold voltage of the MOSFET and a decrease in reliability occur.

[0003] Such a problem is likely to occur when a long wiring is connected to the gate electrode. As a cause of the gate oxide film being damaged, it is considered that the wiring connected to the gate electrode is charged during the manufacturing process, and the gate oxide film is broken down.

It is considered that the wiring is charged during the manufacturing process because the aspect ratio of the opening of the resist mask on the wiring layer is increased, and the amount of positive charges entering the opening exceeds the amount of electrons. Even if the opening has a high aspect ratio, if a process in which the amounts of positive and negative charges are equal can be realized, charging of the wiring can be prevented. However, it is very difficult to realize such a process.

To reduce the damage of the gate oxide film,
The peripheral length and area of the wiring connected to the gate electrode may be limited. However, this is practically difficult for the following reasons.

FIG. 12B shows a CMOS type NAND circuit. A parallel circuit of the pMOS transistors PM1 and PM2 and a series circuit of the nMOS transistors NM1 and NM2 are connected in series.

One input signal IN1 is applied to the gate electrodes of the MOS transistors PM1 and NM1.
The other input signal IN2 is supplied to the gate electrodes of the transistors PM2 and NM2. An interconnection point between the parallel circuit composed of the pMOS transistors PM1 and PM2 and the series circuit composed of the nMOS transistors NM1 and NM2 forms and outputs an output signal OUT.

The four transistors shown in FIG. 12B are usually formed in regions adjacent to each other on the substrate.
However, the pre-stage circuits that generate the input signals IN1 and IN2 are not always formed close to each other.
Therefore, when the NAND circuit in FIG. 12B is arranged near the preceding circuit that generates one input signal, the wiring for the other input signal becomes longer. As described above, it is difficult to arrange circuits such that all input wirings of a circuit having a plurality of input contacts are short.

Another means is to connect a diode for protecting the gate electrode. When charge is accumulated in the wiring, the charge is discharged through the diode. FIG.
2A shows a circuit according to a conventional example for preventing charging of a wiring connected to a gate electrode.

[0010] A pMOS transistor PM3 and an nMOS transistor NM3 are connected in series.
A signal is input to the gate electrodes of M3 and NM3 from the preceding circuit PS via a long input wiring. Transistor PM
3, the gate electrode of NM3 is connected via a protection diode D1 to the n-type well in which the pMOS transistor PM3 is formed, and via the protection diode D2 the nMOS
It is connected to a p-type well in which the transistor NM3 is formed. Each of the diodes D1 and D2 is connected in a direction which is always reverse-biased at a normal operating voltage.

When the input wiring is charged and a positive high voltage is generated, a current flows through the protection diode D1 to the n-type well, and when a negative high voltage is generated, a current flows from the p-type well through the protection diode D2. As described above, the charge stored in the input wiring is transferred to the protection diode D1 or D2.
Through the wells. Therefore, application of a high electric field to the gate oxide film can be prevented.

[0012]

As shown in FIGS. 12A and 12B, the input wiring of a CMOS circuit usually has nM
It is connected to both the OS transistor and the pMOS transistor. As shown in FIG. 12A, when a protection diode is provided for each of the nMOS transistor and the pMOS transistor, two protection diodes are required for one input wiring. For this reason, the area occupied by the CMOS circuit increases, which is against the demand for high integration.

An object of the present invention is to provide a semiconductor device capable of effectively suppressing damage to a gate oxide film of a MOSFET. Another object of the present invention is to provide a MOSF of a CMOS type circuit without occupying a large area.
An object of the present invention is to provide a semiconductor device capable of effectively suppressing damage to a gate oxide film of ET.

[0014]

According to one aspect of the present invention, a semiconductor substrate of a first conductivity type and a well of a second conductivity type opposite to the first conductivity type formed on the surface of the semiconductor substrate are provided. ,
A first MOS transistor having a gate electrode formed on a surface of a first conductivity type region of the semiconductor substrate via a gate oxide film, and a first MOS transistor having a gate electrode formed on the surface of the well via a gate oxide film; Two MOS transistors, a wiring connected to a gate electrode of the first MOS transistor and a gate electrode of the second MOS transistor, and a wiring formed in a first conductivity type region of the semiconductor substrate. Forming a pn junction with the second conductivity type region and the second conductivity type region which are electrically connected to each other;
A protection diode including a high impurity concentration first conductivity type region having an impurity concentration higher than a channel region below a gate electrode of the transistor; and another diode formed in the first conductivity type region of the semiconductor substrate. The wiring and the well are not electrically connected directly, and the distance between the protection diode and the transistor formed closest thereto is the same as the distance between the protection diode and the transistor formed closest thereto. A semiconductor device is provided which is longer than or equal to the distance between the transistor and the transistor.

By inserting a protection diode between the gate electrode and the semiconductor substrate, if the gate electrode is charged in a direction in which the protection diode is forward-biased,
A forward current flows through the protection diode, and the charge accumulated in the gate electrode can be discharged to the substrate. When the gate electrode is charged in a direction in which the protection diode is reversely biased, a reverse current flows when a voltage equal to or higher than the reverse breakdown voltage is applied to the protection diode, and the charge stored in the gate electrode is reduced. Can be discharged to the substrate.

Since the substrate has a large capacitance, the fluctuation of the potential is small even if the electric charge is accumulated. Therefore, the voltage applied to the gate oxide film can be reduced by discharging the charge accumulated in the gate electrode to the substrate. As a result, dielectric breakdown of the gate oxide film can be prevented.
Variations in the threshold voltage of the OS transistor can be suppressed.

When the area of the wiring connected to the gate electrode is 500 times or more the area of the gate electrode on the gate oxide film, the gate oxide film is particularly easily damaged. Therefore, when such a wiring is connected to the gate electrode, the effect of inserting the protection diode is particularly large.

The wiring is formed of a multi-layer wiring layer, and a wiring formed by sequentially connecting upwardly from the gate electrodes of the first and second MOS transistors in the wiring of each wiring layer forming the wiring. May be 500 times or more the sum of the areas of the gate electrodes on the gate oxide films of the first and second MOS transistors.

When the wiring is charged in the plasma processing step of forming the wiring, the lower wiring covered with the interlayer insulating film does not cause charging. Therefore, a portion of the wiring composed of the multilayer wiring layer that is not connected to the gate electrode at the time of patterning does not damage the gate oxide film. Further, it is considered that the damage received by the gate oxide film is accumulated for each patterning of each wiring layer. Therefore, when calculating the area of the wiring, only the wiring portion that can be sequentially traced from the gate electrode to the upper layer may be considered.

Further, the semiconductor substrate has a plurality of active regions surrounded by a field oxide film on the surface of the semiconductor substrate.
It may be made equal to the smallest one of the impurity-added regions formed on the surface of the semiconductor substrate.

Even if the area of the protection diode is as small as the design rule, it is effective. The area occupied by the protection diode can be made as small as possible by making the protection diode the minimum size in the design rule.

A length along the wiring between the protection diode and the gate electrode of the first MOS transistor, and a length along the wiring between the protection diode and the gate electrode of the second MOS transistor. It is preferable that both the lengths are equal to or less than 全長 of the entire length of the wiring.

By connecting the protection diode to the gate electrode side rather than the intermediate point of the wiring connected to the gate electrode, it is possible to more efficiently suppress the damage to the gate oxide film.

The impurity concentration in the vicinity of the pn junction in the first conductivity type region of the protection diode may be higher than that in the channel region below the gate electrode of the second MOS transistor.

When the impurity concentration at the pn junction of the protection diode is increased, the reverse breakdown voltage decreases. For this reason,
The charge charged on the gate electrode can be more efficiently discharged to the substrate.

The semiconductor device further includes another diode formed in the first conductivity type region of the semiconductor substrate, and a distance between the protection diode and a transistor formed closest to the protection diode is different from that of the other diode. It is preferable that the distance be longer than or equal to the distance between the transistor and the transistor formed closest thereto.

A protection diode having a high impurity concentration is
By arranging the MOS transistors away from other MOS transistors or the like, it is possible to prevent a change in the threshold voltage of the MOS transistor due to a change in the impurity concentration.

In the method of manufacturing a semiconductor device according to the present invention, a step of ion-implanting a first conductivity type impurity into a diode formation region of a first conductivity type semiconductor substrate such that an average implantation depth becomes the first depth. Heat-treating the semiconductor substrate to activate the first conductivity type impurity and diffuse the impurity to a second depth;
Ion-implanting a conductive-type impurity such that an average implantation depth is greater than the first depth and is a third depth smaller than the second depth; and Activating the second conductivity type impurity.

In order to increase the impurity concentration of the protection diode, a region having the same conductivity type as the substrate and a higher impurity concentration may be formed at the interface between the substrate and the impurity region of the opposite conductivity type. The depth of the ion implantation for forming the region having a high impurity concentration is made shallower than the depth of the ion implantation for forming the impurity region of the opposite conductivity type to the substrate, and the pn is deeply diffused by heat treatment. Generation of crystal defects in the junction region can be suppressed. Since the occurrence of crystal defects can be suppressed, the leak current of the protection diode can be suppressed.

According to another aspect of the present invention, a semiconductor chip having an internal region surrounded by scribe lines, a plurality of diffusion regions formed in the semiconductor surface of the internal region and doped with impurities, A plurality of MOS transistors each including a pair of diffusion regions among the diffusion regions and having an insulated gate structure formed on a surface of a semiconductor chip therebetween; and a gate electrode of each of the plurality of MOS transistors and the plurality of MOS transistors. A plurality of wirings connected to at least another one of the plurality of diffusion regions, a distance from each gate electrode of the plurality of MOS transistors to a nearest scribe line, and a wiring connected to the gate electrode Is the distance from the closest to the gate electrode to the closest scribe line among one diffusion region or a plurality of diffusion regions to which is connected. Approximately equal the semiconductor integrated circuit device is provided.

Points within the substrate that are approximately the same distance from the scribe line have approximately the same potential during processing. According to still another aspect of the present invention, a semiconductor chip having an internal region surrounded by scribe lines, a plurality of impurity-doped diffusion regions formed in a semiconductor surface of the internal region, and A plurality of MOS transistors each including a pair of diffusion regions among the diffusion regions and having an insulated gate structure formed on a surface of a semiconductor chip therebetween, each gate electrode of the plurality of MOS transistors and the plurality of MOS transistors; A plurality of wirings connected to at least one of the diffusion regions; and a pseudo scribe line formed in the internal region and exposing a semiconductor surface or a conductor surface formed on the semiconductor surface at a level equal to or lower than the wiring. And a semiconductor integrated circuit device having the following. During the process, the pseudo scribe lines are electrically exposed, and the potential difference in the substrate is reduced.

[0032]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A CMOS circuit device is often formed by forming a first conductivity type well and a second conductivity type well in a substrate and forming an opposite conductivity type MOSFET in each well. .

The damage to the gate oxide film due to the charging of the wiring during the manufacturing process is caused by the occurrence of a potential difference between the gate electrode and the well. In order to prevent this potential difference from occurring, conventionally, a protection diode has been inserted between each well and the wiring. The well of the same conductivity type as the substrate may be omitted. In this case, the protection diode was formed similarly.

Among the semiconductor integrated circuit devices, the substrate whose potential hardly fluctuates during the manufacturing process is the substrate having the largest capacitance. Therefore, it is expected that the generation of a potential difference between the gate electrode and the well can be suppressed only by inserting the protection diode into the substrate.

Hereinafter, a device configuration according to the embodiment will be described with reference to FIGS. 1 and 2 taking a CMOS circuit using a p-type substrate as an example. FIG. 1 shows a cross section of a CMOS circuit device. FIG. 2 shows two CMOs including the CMOS circuit of FIG.
4 shows an in-plane layout of an S circuit. The right part of FIG.
1 shows the CMOS circuit shown in FIG.
1 shows a circuit. FIG. 1 focuses on the electrical connection between the gate electrode and the protection diode, and does not correspond to any one of the cross sections in FIG.

As shown in FIG. 1, a p-type well 3 and an n-type well 4 are formed on the surface of a p-type silicon substrate 1, and an active region surrounded by a field oxide film 2 is defined on the surface of each well. Have been. In the active region of the p-type well 3, an nMOS transistor having a gate electrode 7 formed through a gate oxide film and n ⁺ -type source and drain regions 5 and 6 is formed. In the active region of the n-type well 4, A pMOS transistor having a gate electrode 10 formed via a gate oxide film and p ⁺ -type source and drain regions 9 and 8 is formed.

A p ⁺ -type well contact 11 is formed in another active region of the p-type well 3. The well contact 11 and the source region 5 are connected to the ground potential by the first layer wiring 14. In the other active region of the n-type well 4, an n ⁺ -type well contact 12 is formed.
The well contact 12 and the source region 9 are the first layer wiring 1
5 is connected to the power supply voltage.

In the other active region of the p-type well 3, n
^{A +} type region 13 is formed, and a pn junction diode 20 is formed with the p type well 3. Gate electrodes 7, 10
The n ⁺ -type region 13 is connected to the n ⁺ -type region 13 by a second-layer wiring 16. Since the p-type well 3 and the p-type substrate 1 are in ohmic contact, the gate electrodes 7 and 10 are connected to the p-type substrate 1 by the protection diode 20 including the n ⁺ -type region 13 and the p-type well 3. . Furthermore, the second layer wiring 16
Are connected to a long third-layer wiring 17.

As described above, in the CMOS circuit shown on the right side of FIGS. 1 and 2, the protection diode 20 is formed only in the p-type well 3 of the same conductivity type as the substrate 1, and the protection diode 20 is formed in the n-type well 4. Is not formed.

As shown on the right side of FIG. 2, source and drain regions 9 and 8 are arranged in n-type well 4 so as to sandwich gate electrode 10, and source region 9 is connected to power supply wiring via contact hole H9. 15. The well contact 12 formed in the n-type well 4 is connected to a power supply wiring 15 via a contact hole H12.

Source and drain regions 5 and 6 are arranged in the p-type well 3 so as to sandwich the gate electrode 7, and the source region 5 is connected to a ground line 14 via a contact hole H5. The well contact 11 formed in the p-type well 3 is connected to the ground line 1 via the contact hole H11.
4 is connected.

The drain regions 6 and 8 are connected to a wiring 21 via contact holes H6 and H8, respectively. The wiring 21 is connected to an input terminal of a subsequent circuit (not shown).

The protection diode 20 is provided in the p-type well 3.
N ⁺ -type region 13 is arranged to constitute a. The n ⁺ type region 13 and the gate electrodes 7 and 10 are connected to the wiring 16 via contact holes H13, H7, and H10, respectively. The wiring 16 is connected to a long wiring 17 via a contact hole H16.

The long wiring 17 is connected to the output contact (the drain region 6 of the two MOS transistors) of the preceding CMOS circuit.
a, 8a). The preceding CMOS circuit,
Except that the protection diode 20 is not provided, the subsequent C
It has the same configuration as the MOS circuit. It should be noted that each component of the first-stage CMOS circuit is indicated by adding “a” to the reference numeral of the corresponding component of the second-stage CMOS circuit.

Next, the effect of suppressing damage to the gate oxide film when the CMOS circuit has the structure shown in FIG. 1 will be described with reference to FIGS. FIG. 3A shows a circuit diagram used in an experiment for confirming a damage suppressing effect. Long wiring 3 for the gate electrode of MOS transistor 30
1 is connected. The gate electrode 30 is connected to a ground potential, that is, a p-type substrate via a protection diode 32. The experiment was performed only on the p-type substrate. Therefore, the protection diode 32 is formed in a p-type well, and the gate electrode 30 side is a cathode and the substrate side is an anode.

In the experiment, the MOS transistor 30 has the nMO
The test was performed for both the S transistor and the pMOS transistor. The circuit used for the experiment is different from the CMOS circuit of FIG. 1 in that only one transistor is formed.
When it is a transistor, it is equivalent to a pMOS transistor including the gate electrode 7 of FIG. 1, and when it is an nMOS transistor, it is equivalent to an nMOS including the gate electrode 10 of FIG.
It is equivalent to a MOS transistor.

FIG. 3B shows a layout of the circuit shown in FIG. Four wirings 35 are drawn out from the MOS transistor formation region 33, and each wiring 35 is connected to a pad 34.
It is connected to the. Further, a long wiring 31 extends from the MOS transistor formation region 33 below the figure. The long wiring 31 is formed in a zigzag shape as shown in the figure.

FIG. 3C is an enlarged view of the MOS transistor formation region 33 of FIG. Gate electrode 40,
A MOS transistor 30 having source and drain regions 41 and 42 is formed. The gate electrode 40 is connected to the first-layer long wiring 31 formed on the interlayer insulating film. A protection diode 32 is formed near the connection between the long wiring 31 and the gate electrode 40.

The protection diode 32 comprises a pn junction between an n ⁺ -type region formed in the p-type well and the p-type well. A well contact 43 is formed near the MOS transistor 30. Source area 4
1, the well contact 43, the drain region 42, and the gate electrode 40 are formed by wirings 35a, 35b, 35c,
The pads 35a, 34b, 34c, 34d are connected by 35d.

When the MOS transistor 30 is an nMOS transistor, the MOS transistor 30 and the well contact 43 are formed in the same p-type well as the protection diode 32. MOS transistor 30 is pMOS
In the case of a transistor, the MOS transistor 30 and the well contact 43 are formed in an n-type well different from the protection diode 32.

FIG. 3D is an enlarged view of the long wiring 31. As shown in the drawing, wirings having a width W of 1.0 μm are arranged in a zigzag manner at substantially equal intervals. FIG. 4 shows the state shown in FIG.
MOS due to the connection of the long wiring 31 shown in FIG.
The shift amount of the threshold voltage of the transistor is shown for the case where the protection diode 32 is inserted and for the case where it is not inserted.

4A to 4D, the horizontal axis represents the distance from the center of the wafer to the MOS transistor 30 in units of cm. The used wafer is 6 inches.
The vertical axis of the graph represents Vth-Vth0 in units of V, where Vth is the threshold voltage of a MOS transistor to which a long wiring is connected and Vth0 is the threshold voltage of a MOS transistor to which no long wiring is connected. Represent. Hereinafter, Vth-V
th0 is called a threshold voltage shift amount.

Generally, the threshold voltage fluctuates due to variations in the manufacturing process. By measuring the shift amount of the threshold voltage as shown in FIG. 4, it is possible to remove the influence of the change of other parameters and evaluate the influence only by connecting the long wiring. The shift amount of the threshold voltage is an index of the damage of the gate oxide film.

FIGS. 4A and 4C show the case where the protection diode 32 shown in FIGS. 3A and 3C is inserted, and FIGS. 4B and 4D do not insert the protection diode. Show the case. 4A and 4B show the case of an nMOS transistor, and FIGS. 4C and 4D show the case of a pMOS transistor. The circuit used in the experiment has a ratio of the area of the bottom of the long wiring to the area of the active region of the gate electrode (hereinafter, referred to as antenna ratio) of 1,000. The channel length is 0.8 μm and the channel width is 10
μm, and the gate oxide film thickness is 10 nm.

As shown in FIGS. 4B and 4D, when the protection diode is not provided, the distance from the center of the wafer is 5 mm.
The shift amount of the threshold voltage of the MOS transistor formed in the peripheral region exceeding cm is large. On the other hand, when the protection diode is provided, the shift amount of the threshold voltage is extremely small over the entire surface of the wafer and almost zero.
It is. As described above, by inserting the protection diode, the shift amount of the threshold voltage can be reduced for both the n-channel and p-channel MOS transistors.

From this, by inserting one protection diode for one CMOS inverter,
It can be seen that damage to the gate oxide films of both the n and pMOS transistors can be suppressed.

When the protection diode is not inserted, the shift amount of the threshold voltage in the peripheral portion of the wafer becomes large because ions or electrons are obliquely formed in the peripheral portion in the plasma processing step for forming a long wiring. It is considered that light is incident from the direction and the long wiring is easily charged.

FIG. 5 shows the shift amount of the threshold voltage when the antenna ratio is changed without inserting the protection diode. The MOS transistor used was an n-channel MOS transistor. FIGS. 5A to 5E show antenna ratios of 100, 300, 500, 1000, and 400, respectively.
Indicates the case of 0.

As shown in FIGS. 5A and 5B, when the antenna ratio is 100 and 300, the shift amount of the threshold voltage is almost zero over the entire surface of the wafer without inserting a protection diode. . When the antenna ratio becomes 500, the shift amount of the threshold voltage starts to increase in the peripheral region where the distance from the wafer center is 5 cm or more, and when the distance from the wafer center becomes about 7 cm, the shift amount becomes about 0.1 V. Become. As shown in FIGS. 5D and 5E, when the antenna ratio is further increased and becomes 1000 and 4000, the shift amount of the threshold voltage is further increased.

This indicates that the gate oxide film is easily damaged when the antenna ratio is increased. In this experiment, if the antenna ratio is 300 or less, the damage to the gate oxide film is small enough to cause no problem even if the protection diode is not used. It can be seen that the effect of inserting the protection diode is particularly large when the antenna ratio is 500 or more. In addition, CM
When two or more gate electrodes are connected to one gate wiring as in the case of an OS or the like, the antenna ratio is defined with respect to the sum of the areas of the gate electrodes.

When the long wiring is composed of a plurality of wiring layers, it is considered that the gate oxide film is damaged because the long wiring is charged in the plasma processing step for forming the long wiring as described above. . Only the uppermost wiring layer in the plasma process is exposed to the plasma, and the lower layer is protected by the interlayer insulating film, so that it does not become a factor for charging the long wiring.

The damage to the gate oxide film is as follows:
It is considered to depend on the accumulated tunnel current. Therefore, it is considered that the damage of the gate oxide film is accumulated for each patterning of each wiring layer. Therefore, the area of the long wiring when calculating the antenna ratio may be obtained by accumulating the area of only the part of the wiring part of each wiring layer which is sequentially connected from the gate electrode to the upper layer.

For example, the pad 34 shown in FIG.
Is formed by the first wiring layer. The gate electrode pad 34d is connected to the gate electrode 40 via a second-layer wiring 35d. Therefore, it is considered unnecessary to consider the area of the pad 34d in the calculation of the antenna ratio.

However, when it is considered that there is a factor that causes the long wiring to be charged even in a step other than the plasma processing for forming the long wiring, it is preferable to consider the total area of each wiring layer of the long wiring.

Next, with reference to FIGS. 6 and 7, the effect of a change in the linear distance between the MOS transistor and the protection diode on the wafer on the damage suppression effect of the gate oxide film will be described.

FIG. 6A shows a case where the distance between the MOS transistor and the protection diode 32 is 100 μm. The protection diode 32 is formed at a portion connecting the MOS transistor formation region 33 and a portion of the long wiring 31 formed in a zigzag.

FIG. 6B shows that the distance L between the MOS transistor and the protection diode 32 is 500 μm and 1 mm.
The case of is shown. A part of the long wiring 31 is extended downward in the drawing, and a protection diode 32 is formed at the tip of the extension. The protection diode 32 and the MOS transistor 33
A circuit having a linear distance L of 500 μm and 1 mm was prepared.

Both FIGS. 6A and 6B have the same configuration as FIGS. 3B and 3C except for the place where the protection diode is formed. Note that, with the same configuration as in FIGS. 3B and 3C, the distance between the protection diode and the MOS transistor is 10 μm.
m circuit was also prepared.

FIGS. 7A to 7D show that the linear distance between the protection diode and the MOS transistor is 10 μm.
The shift amount of the threshold voltage when m, 100 μm, 500 μm, and 1 mm is shown.

As shown in FIG. 7A, when the distance between the protection diode and the MOS transistor is 10 μm, the shift amount of the threshold voltage is almost 0 over the entire surface of the wafer. When the distance between the protection diode and the MOS transistor becomes 100 μm, the shift amount of the threshold voltage slightly varies in a peripheral region exceeding 5 cm from the center of the wafer as shown in FIG. 7B.

As shown in FIG. 7C, when the distance between the protection diode and the MOS transistor becomes 500 μm,
The shift amount of the threshold voltage is large at a peripheral portion of 5 cm or more from the center of the wafer, and may be 0.1 V. When the distance between the protection diode and the MOS transistor becomes 1 mm, the shift amount of the threshold voltage further increases,
It may be 0.15V.

This is because the potential is not uniform within the wafer,
It is considered that when the protection diode and the MOS transistor are arranged apart from each other, a potential difference occurs transiently in the gate oxide film. Therefore, it is preferable to arrange the protection diode and the MOS transistor as close as possible, and it is preferable that the distance be 100 μm or less.

When the MOS transistor is far from the protection diode, particularly when the distance is 100 μm or more, it is considered preferable to reduce the reverse breakdown voltage of the protection diode in order to suppress the damage to the gate oxide film. Can be

Next, with reference to FIG. 8 and FIG. 9, the effect when the reverse breakdown voltage of the protection diode is reduced will be described. FIG. 8 is a sectional view of a CMOS circuit device in which a protection diode is inserted. Except for the structure of the protection diode 20, the configuration is the same as that of the CMOS circuit device shown in FIG. The protection diode 20 is formed in the n ⁺ -type region 13 formed in the p-type well 3 and between the n ⁺ -type region 13 and the p-type well 3 and has a higher impurity concentration than the p-type well 3. It is composed of a high concentration region 18. As described above, the reverse breakdown voltage can be reduced by increasing the impurity concentration of the p-type region of the pn junction.

Hereinafter, a method for manufacturing the CMOS structure shown in FIG. 8 will be described. LOC on the surface of p-type silicon substrate 1
A field oxide film 2 is formed by the OS method to define an active region. Next, by ion implantation and activation annealing, p
A mold well 3 and an n-type well 4 are formed. p-type well 3
Represents B, n-type well 4 represents P, and accelerating energy 20
Ion implantation is performed under the conditions of 0 keV and a dose of 1 × 10 ¹³ cm ⁻² , and activation annealing is performed in a nitrogen atmosphere at 1000 ° C. for 3 hours.

Next, B for forming the p-type region 18 is applied with an acceleration energy of 10 keV to the region where the protection diode 20 is to be formed.
Ion implantation. The dose amount is 1 × 10 ¹⁴ cm ^-2 and 5
A case of × 10 ¹³ cm ^-2 was prepared.

A 10-nm-thick gate oxide film is formed on the surface of the active region by thermal oxidation at a temperature of 1000 ° C. for 16 minutes. B implanted by this heat treatment step is driven deeply. A 200 nm-thick polysilicon film is grown by CVD. A through oxide film having a thickness of 5 nm is formed on the surface of this polysilicon film, and the gate electrode is formed as n.
In order to make a mold, the acceleration energy is 20 keV and the dose is 1
P ions are implanted over the entire surface of the polysilicon film under the condition of × 10 ¹⁶ cm ^-2 . After the ion implantation, the gate electrodes 7 and 10 are formed by patterning the polysilicon film.

A through oxide film having a thickness of 5 nm is formed in the active region, a resist pattern covering a region other than the nMOS transistor formation region is formed, and an LDD (lightly doped drain) is formed by using the gate electrode 7 and the resist pattern as a mask.
As for region formation is ion-implanted under the conditions of an acceleration energy of 20 keV and a dose of 2 × 10 ¹³ cm ⁻² . After removing the resist pattern, a resist pattern covering a region other than the pMOS transistor formation region is formed, and BF ₂ ⁺ for forming an LDD region is accelerated with an energy of 20 keV and a dose of 1 × 10 4 using the gate electrode 10 and the resist pattern as a mask. Ion implantation is performed under the condition of ¹³ cm ^-2 . afterwards,
The resist pattern is removed.

Next, a thickness of 10
A SiO ₂ film of 0 nm is deposited and anisotropically etched by reactive ion etching (RIE) to form a sidewall 19.

A through oxide film having a thickness of 5 nm is formed, and n ⁺
Form a resist pattern covering the area other than the mold area forming part,
Source / drain regions 5, 6 of the nMOS transistor
In order to form the n ⁺ -type region 13 and the well contact 12 of the protection diode 20, As is ion-implanted under the conditions of an acceleration energy of 30 keV and a dose of 2 × 10 ¹⁵ cm ⁻² using a resist pattern and a gate structure as a mask. After that, the resist pattern is removed. Similarly, a resist pattern is formed, and the source / drain regions 9 and 8 of the pMOS transistor and the well contact 11 are formed.
BF ₂ ⁺ ions are implanted under the conditions of an acceleration energy of 20 keV and a dose of 5 × 10 ¹⁵ cm ⁻² .

Activation annealing is performed in an N ₂ atmosphere at 800 ° C. for 20 minutes to activate the ion-implanted impurities. According to a known method, the interlayer insulating film and the wirings 14, 1
5, 16, and 17 are formed.

FIG. 9 shows the effect of suppressing damage to the gate oxide film when the impurity concentration of the p-type high concentration region 18 is changed. FIG. 9A shows a case where B for forming the p-type high concentration region 18 is ion-implanted under the conditions of an acceleration energy of 10 keV and a dose of 1 × 10 ¹⁴ cm ⁻² . FIG. 9B shows an acceleration energy of 10 keV. The case where ion implantation is performed under the condition of a dose amount of 5 × 10 ¹³ cm ⁻² is shown. FIG. 9C shows a case where the p-type high concentration region 18 is not formed. The distance between the MOS transistor and the protection diode is about 300 μm, and the antenna ratio is 4000.

As shown in FIGS. 9A and 9B, when the p-type high concentration region 18 is formed, the shift amount of the threshold voltage is almost 0 over the entire surface of the wafer. In contrast,
As shown in FIG. 9C, when the p-type high-concentration region 18 is not formed, the shift amount of the threshold voltage becomes large in the peripheral region exceeding 5 cm from the center of the wafer, and may exceed 0.2 V in some cases. .

From these results, it can be seen that it is effective to reduce the reverse breakdown voltage of the protection diode in order to suppress the damage to the gate oxide film. As shown in FIG. 7, when the distance between the protection diode and the MOS transistor is 100 μm or less, the shift amount of the threshold voltage is almost 0 over the entire surface of the wafer. This is particularly effective when the distance between the MOS transistor and the protection diode is 100 μm or more.

When the wafer temperature is high, the reverse leakage current of the protection diode is considered to be quite large. Therefore, at the time of the high-temperature process, it is considered that the protection diode fulfills the function of preventing charging of the gate electrode regardless of the magnitude of the reverse breakdown voltage. Reducing the reverse breakdown voltage of the protection diode and improving the effect of suppressing the damage to the gate oxide film means that the potential breakdown occurs in the wafer in a low-temperature process in which the reverse breakdown voltage has significance, and It is considered that a high voltage was applied to the gate oxide film at the beginning.

The ion implantation for forming the p-type high-concentration region 18 is preferably performed before the formation of the gate oxide film as described above. By performing ion implantation before forming the gate oxide film, damage due to ion implantation can be recovered by heat treatment at the time of forming the gate oxide film.

It is preferable that the impurity for forming p-type high-concentration region 18 is implanted shallower than the impurity for forming n ⁺ -type region 13. Even if the depth of the ion implantation is shallow, the impurity for forming the p-type high-concentration region 18 experiences a heat treatment at the time of forming the gate oxide film, and thus can be diffused deeper than the impurity for forming the n ⁺ -type region 13. Therefore, n ⁺ type region 1
A p-type high concentration region 18 is formed between the p-type well 3 and the p-type well 3.

Normally, when ion implantation is performed, crystal defects tend to occur at positions slightly shallower than the depth at which the ions are implanted. By implanting ions for forming the p-type high-concentration region 18 to be slightly shallower than the ion implantation depth for forming the n ⁺ -type region 13 and deeply diffusing it by heat treatment, crystal defects occur at the pn junction of the protection diode 20. Can be suppressed.

As described above, the occurrence of crystal defects at the pn junction due to ion implantation is suppressed, and the crystallinity is restored by the heat treatment after ion implantation, whereby the leakage current can be reduced. Further, since the impurity concentration of only the pn junction is increased, there is an effect that the impurity concentration of the entire well can be suppressed.

When the p-type high-concentration region 18 is formed, the protection diode 20 is preferably formed as far as possible from MOS transistors formed in other regions in the same well. By keeping the distance, it is possible to prevent the impurity concentration of the well from being increased by the ion implantation for forming the diode and to prevent the threshold voltage of the MOS transistor from fluctuating. More specifically,
It is preferable that the distance between the diode in which the p-type high-concentration region is not formed and the MOS transistor formed closest to the diode is larger than that of the diode.

Next, with reference to FIGS. 10 and 11, the relationship between the mounting position of the protection diode in the long wiring and the effect of suppressing the damage of the gate oxide film will be described. FIG.
Indicates schematically the mounting position of the protection diode. The ratio of the length from the gate electrode along the long wiring 31 to the length from the isolated tip (hereinafter referred to as the internal division ratio) is substantially 0: 1, 1: 3, 1: 1, 3: 1, 1 A circuit was prepared in which a protection diode was connected at the position of: 0. The circuit whose internal division ratio is approximately 0: 1 has the same configuration as that of FIGS. 3B and 3C.

The protection diodes 32a, 32b,
32c and 32d have an internal division ratio of 1: 3, 1: 1 and
The case of 3: 1, 1: 0 is shown. Thus, the linear distance between the MOS transistor and the protection diode is made substantially constant even when the internal division ratio changes. The antenna ratio was 4000 for all internal division ratios.

FIGS. 11A to 11E show the shift amounts of the threshold voltage when the internal division ratio is approximately 0: 1, 1: 3, 1: 1, 3: 1, and 1: 0, respectively. Show. FIG. 11 (A),
As shown in (B), when the internal division ratio is approximately 0: 1 and 1: 3, the shift amount of the threshold voltage is substantially zero over the entire surface of the wafer. As shown in FIG. 11C, when the internal division ratio is 1: 1, the shift amount of the threshold voltage is about 0.05 V in the peripheral region of 6 cm or more from the center of the wafer, which is slightly larger.

As shown in FIG. 11D, the internal division ratio is 3:
When it is 1, the shift amount of the threshold voltage is further increased in the peripheral region distant from the center of the wafer by 5 cm or more, and may be about 0.2 V in the peripheral region distant from the wafer center by 6 to 7 cm.

As shown in FIG. 11E, the internal division ratio is 1:
In the case of 0, the shift amount of the threshold voltage is further increased to about 0.3 V in a peripheral region distant from the center of the wafer by 5 cm or more.

As can be seen from FIGS. 11A to 11E,
It is preferable to minimize the length along the long wiring between the protection diode and the gate electrode as much as possible. In particular, it is preferable to dispose the protection diode closer to the gate electrode than the middle point of the long wiring.

Even if the area of the protection diode was extremely small, the effect of suppressing the damage of the gate oxide film could be obtained. More specifically, a sufficient effect can be obtained even with the minimum design rule. In order to effectively utilize the area of the wafer, it is preferable that the area of the diffusion region of the protection diode be the minimum area of the active region surrounded by the field oxide film in the wafer.

In the above embodiment, the case where the protection diode and the nMOS transistor are formed in the p-type well has been described.
It may be formed on the surface of the mold substrate. It will be apparent to those skilled in the art that the same result may be obtained by inverting all conductivity types.

As described above, it was found that damage to the gate oxide film could be suppressed. However, when a plurality of chips were formed in a semiconductor wafer, test elements satisfying the above conditions were arranged in each chip, and an experiment was conducted, it was found that damage to the gate oxide film occurred partially.

FIG. 13A is a schematic top view of a semiconductor wafer on which chips are formed. A plurality of chips CH are arranged in a matrix on the semiconductor wafer W, and adjacent chips are separated by scribe lines SL.
When an experiment was conducted by forming a gate oxide film damage suppressing structure together with other elements in such a semiconductor chip CH, the gate oxide film was found to be damaged in spite of satisfying the above conditions. It turned out that there was.

Further, as shown in FIG. 13B, when all the scribe lines SL of the wafer were covered with the resist mask RM, no damage was caused on the gate oxide film. The inventor considered the above phenomenon as follows.

FIG. 14A schematically shows the structure of one semiconductor chip. The outer peripheral area of the semiconductor chip CH is constituted by scribe lines SL. In the scribe line SL, the semiconductor surface is usually exposed throughout the entire process.

In the plasma processing step, if there is an opening having a high aspect ratio, a positive charge is injected into the substrate via the MOS capacitor structure or the diffusion layer. The scribe line is wide and is exposed to plasma, so that either positive or negative charges can be captured. Even if the substrate is positively charged, charge neutralization will occur at the scribe line. From another point of view, in each chip, a current flows from the internal region toward the scribe line. The current in the substrate forms a potential distribution in the substrate. This potential distribution can cause gate oxide film damage. If the entire scribe line is covered with an insulating film such as a resist, the current in the substrate becomes difficult to flow. Therefore, the current distribution in the substrate is hardly formed, and the gate oxide film is hardly damaged.

Various semiconductor elements are formed in an internal region surrounded by scribe lines SL. The input / output pad P is connected to an internal circuit via an input / output protection transistor Tr. In the internal circuit, a MOS transistor Q2 having a gate electrode connected to the above-described long wiring W2 is arranged. In another region of the semiconductor chip, a MOS transistor Q1 is formed, and a wiring W1 connected from its gate electrode to a diffusion layer D such as a drain of another transistor is formed. Here, the distance of the MOS transistor Q1 from the scribe line SL is d1
And the distance of the diffusion region D from the scribe line SL is d2.

When the electric charge is accumulated in the long wiring W2, the electric charge flows into the substrate of the semiconductor chip CH through the gate insulating film of the transistor Q2 or through the diffusion region connected to the wiring W2. This current forms a potential distribution in the substrate as it flows through the semiconductor substrate. MO
If the potential in the substrate under the S transistor Q1 is significantly different from the potential in the substrate in the diffusion region D, a large voltage will be applied to both sides of the gate insulating film of the MOS transistor Q1. The potential distribution in the substrate will depend on the distance to the scribe line.

FIG. 14B is a schematic sectional view of the configuration of FIG. A transistor including a diffusion region D is arranged on the left side of the drawing, and a MOS transistor Q1 is arranged at the center, and a wiring W1 is connected therebetween. The right side of the drawing shows a MOS transistor Q2 in which a long wiring W2 is connected to the gate electrode. When electric charge flows into the substrate from the long wiring W2 via the gate oxide film, a current flows in the lateral direction of the substrate.

Since the surface of the scribe line SL is exposed, it can serve as an outlet for current. That is, when the plasma including the positive charge and the negative charge is in contact with the scribe line SL, the positive charge flowing in the substrate can be combined with the negative charge in the scribe line SL to neutralize the charge.

In the internal region, since excess positive charges enter the window portion having a high aspect ratio, the positive charges are injected into the substrate. Since this positive charge becomes a current in the substrate, a potential distribution occurs in the lateral direction of the substrate. In the configuration shown, between the channel portion immediately below the gate electrode of MOS transistor Q1 and diffusion region D (since this is connected to the gate electrode, the potential of diffusion region D becomes the gate potential of Q1 as it is). When the potential distribution ΔV in the substrate occurs, the voltage Δ is applied to the gate insulating film of the MOS transistor Q1.
V will be applied. That is, even if the charge collected by the wiring W1 is small, the gate insulating film may be deteriorated due to the potential distribution in the substrate. The generated voltage ΔV is the distance d
One will depend on the difference from d2.

FIGS. 15A and 15B are diagrams for explaining an experiment performed to confirm the above analysis.
FIG. 15A is a plan view schematically showing a configuration of an experimental sample. A plurality of MOS transistors M1, M2,
.. Mk are arranged at a fixed distance from the scribe line SL, in this sample, 250 μm. The protection diodes PD1 to PDi are formed at positions of 100, 120, 140,..., 240 μm from the scribe line. The corresponding MOS transistor M and the protection diode PD are connected by wirings W11 to Wii.

For MOS transistor Mj, diffusion region PD is located 100 μm from scribe line SL.
j to form an insulated gate electrode and this diffusion region into a wiring Wj.
j, and another protection diode Da was connected at a position of about 10 μm from the gate electrode of the MOS transistor.

For MOS transistor Mk, a protection diode PDk is formed at a position 100 μm from scribe line SL, and a gate electrode and wiring Wkk are formed.
Connected with. Further, a pseudo scribe line QSL exposing the semiconductor surface was formed near the MOS transistor Mk.

[0112] Such a sample was exposed to a plasma process, and damage generated in the gate oxide film of the MOS transistor M was measured. FIG. 15B shows MOS transistors M1 to Mk measured using the sample of FIG.
6 is a graph showing the threshold voltage Vth of FIG. The horizontal axis represents the distance from the scribe line SL of the protection diode PD in μm.
Indicated by The distance between the MOS transistor and the protection diode is also shown in parentheses. The vertical axis indicates the threshold voltage Vth in unit V.

The two plots on the right side of the figure show the measured values of the test elements Mj and Mk. That is, Mj has a protection diode at a distance of 100 μm from the scribe line and also connects another protection diode Da at a distance of 10 μm from the insulated gate electrode. Also, the test element Mk
Has a protection diode connected to the scribe line at a distance of 100 μm and a pseudo scribe line QSL near the insulated gate electrode.

As is clear from the graph of FIG. 15B, the threshold voltage of the MOS transistor gradually increases as the protection diode moves away from the MOS transistor. In particular, when the protection diode is separated from the gate electrode of the MOS transistor by 70 μm or more, the change in the threshold voltage becomes remarkable.

On the other hand, even if the protection diode is far from the MOS transistor, if another protection diode is connected near the MOS transistor, the change in the threshold voltage is small as seen from the measurement result of test element Mj. Become. Also, when a pseudo scribe line is formed in the vicinity of the MOS transistor, the change in the threshold voltage is significantly reduced, as is apparent from the results of the test elements M1 and Mk.

As shown in FIG. 14A, a plurality of input / output protection transistors Tr are usually formed in a semiconductor chip. The size of the protection transistor Tr is designed to be larger than other transistors. Assuming that the gate length of the protection transistor Tr is L and the gate width is W, the device is designed so that no potential distribution occurs in the substrate at the larger distance, usually the gate width W. Therefore, it is considered that the potential distribution in the substrate is negligible if it is within the size of the largest transistor in the semiconductor chip. For example, the gate length GL is 0.5
μm, and the gate width GW is 50 μm. In this case, the potential distribution in the substrate is almost negligible if the distance is up to a gate width of 50 μm.

The experimental result shown in FIG. 15B shows a result consistent with this idea. That is, in a sample in which the distance between the MOS transistor and the protection diode is up to 50 μm, the change in the threshold voltage is negligible.

In a semiconductor chip as shown in FIG. 14A, a MOS transistor Q having a long wiring W2
The distribution of 2 is not constant. However, when a plurality of MOS transistors having long wires are formed in the semiconductor chip, it can be considered that the current in the substrate flows substantially from the center of the chip toward the scribe line.

Then, the relationship between the MOS transistor to be protected and the protection diode may be determined based on the distance from scribe line SL. That is, if the distance from the scribe line is equal, the potential in the substrate at that position can be considered to be substantially equal. Therefore, MOS transistor Q and protection diode D connected to its gate wiring may be arranged at the same distance from scribe line SL.

The potential drop in the semiconductor substrate is as follows:
Since it is almost negligible within the gate width of the largest transistor, the difference between the distance from the scribe line between the insulated gate electrode of the MOS transistor and the protection diode connected to its wiring is the same It suffices if the width is equal to or less than the width.

The wiring connected to the gate electrode is often connected to the drain region of another MOS transistor. In this case, the drain region can serve as a protection element. Therefore, the protection diode may be replaced with a drain region. These are collectively called a diffusion region.

FIG. 16 schematically shows a configuration example of a semiconductor chip. In the semiconductor chip CH, the MOS transistor Q
1 and a drain diffusion region D1 of another MOS transistor.

The gate electrode of the MOS transistor Q1 is
It is arranged at a distance of 250 μm from scribe line SL. The drain region D1 of another MOS transistor is arranged at a distance of 200 μm from the scribe line SL. Both are connected by a wiring W1.

In this case, the distance from the scribe line SL of the gate electrode of the MOS transistor Q1 (250 μm)
m) and the distance (200 μm) from the scribe line of the drain diffusion region D1 are different only by 50 μm. If the gate width of the largest transistor in this chip is 50 μm as described above, it is considered that the potential in the substrate of the drain diffusion region D1 and the potential of the channel region of the MOS transistor Q1 are substantially equal. Therefore, the gate insulating film of MOS transistor Q1 is hardly damaged.

FIG. 17 shows another configuration example of the semiconductor chip. A MOS transistor Q1 and a drain diffusion region D1 of another MOS transistor are formed in a semiconductor chip CH, and both are connected by a wiring W. MOS transistor Q1 is 250 μm from scribe line SL
And the drain diffusion region D1 is formed at a position 100 μm from the scribe line SL.

In this case, the difference between the two distances from the scribe line SL is 250-100 = 150 μm, which is significantly larger than the gate width (50 μm) of the largest transistor in the chip. In the case of such a configuration, FIG.
As shown by the characteristic M1 in (B), the threshold voltage tends to fluctuate greatly.

Accordingly, it is preferable to form another protection diode Da in the middle of the wiring W. The protection diode Da is, for example, a distance 260 from the scribe line SL.
Connect to μm position.

According to this structure, the voltage applied to the gate electrode of MOS transistor Q1 becomes substantially equal to the potential in the substrate of protection diode Da, thereby preventing an excessive voltage from being applied to the gate oxide film. it can. Although a large potential can be generated between the drain diffusion layer D1 and the protection diode Da, this potential can be compensated for by a current flowing between the drain diffusion region D1 and the protection diode Da.

Note that the above-described current in the substrate is caused by the long wiring W
2 is generated by receiving a positive charge from the plasma. Therefore, in a semiconductor integrated circuit device having a long wiring, it is effective to adjust the relationship between the MOS transistor arranged in the chip and the protective diffusion region as described above.

Note that the potential distribution in the substrate is generated by the charge invading the substrate from the plasma flowing toward the scribe line in the internal region of the semiconductor chip. If the potential of the scribe line is used as a reference, the longer the distance to the scribe line, the higher the resistance and the greater the potential difference generated.

If there is a region in the internal region of the semiconductor chip which can be directly coupled to the electric charge in the plasma as in the scribe line, the potential in that region will be equivalent to the potential of the scribe line. Such an area is hereinafter referred to as a pseudo scribe line. By distributing pseudo scribe lines in the internal region of the semiconductor chip and shortening the distance from each MOS transistor to the scribe line or pseudo scribe line, the potential difference generated in the substrate is reduced, and the damage to the gate insulating film is reduced. Should be.

The test element M shown in FIGS. 15A and 15B
k is based on this idea, and has a pseudo scribe line QSL near the MOS transistor.
Due to the provision of the pseudo scribe line, the change in the threshold voltage is remarkably reduced as compared with the test element M1 having the same other conditions.

Such a pseudo scribe line may be any as long as the semiconductor surface can be electrically exposed to the upper space in each wiring layer forming step. When the semiconductor surface is directly exposed and when a conductive layer such as a metal is formed on the semiconductor surface, the conductive layer or the conductive layer and the remaining semiconductor surface may be exposed to the upper space. In addition,
After forming the uppermost layer wiring, in the step of forming the cover film, the pseudo scribe line may be covered.

FIGS. 18A, 18B and 18C show the structure of a semiconductor chip having pseudo scribe lines. FIG. 18A is a plan view of a semiconductor chip, and FIG.
(B) is an enlarged plan view of one pseudo scribe line, and FIG. 18 (C) is a chain line 18C-18 in FIG. 18 (A).
It is sectional drawing which follows C.

In FIG. 18A, the semiconductor chip C
A scribe line SL is formed around H, and a plurality of pseudo scribe lines QSL are arranged in a distributed manner in an internal region thereof. A large number of MOS transistors Q are formed in the internal region according to the circuit design.

As shown in FIG. 18B, the pseudo scribe line has, for example, a rectangular shape. In the illustrated configuration, pseudo scribe line QSL has a size of, for example, 10 μm × 60 μm. Even when an upper structure is formed, a semiconductor surface of about 8 μm × 50 μm is exposed in insulator structure IS. Note that the dimensions described above are merely examples, and can be changed as appropriate in accordance with the circuit design and the like. Further, the shape of the pseudo scribe line can be arbitrarily changed. In order to make good electrical contact with the plasma, what conditions were required were tested in the following experiments.

FIG. 23A shows the shape of a sample.
0.5 μm thick metal layer 101 on a thick insulating film 100
Was formed thereon, and a resist pattern 102 having a thickness of 0.5 μm was formed thereon. Metal layer 101 is connected to an insulated gate electrode of an n-channel or p-channel MOS transistor. The resist pattern 102 has a width of 0.5 μm
And the space width s between adjacent patterns 102 was changed. These resist patterns 10
The metal layer 101 was etched using 2 as an etching mask. At the end of etching, width s height 1μ between patterns
m openings are formed.

If positive / negative unbalanced charges flow into the metal layer 101 during etching, the threshold voltage of the MOS transistor changes. N-channel MOS transistor and p-channel M for various space widths s
A sample of the OS transistor was measured.

FIG. 23B shows the result of an n-channel MOS transistor. Samples with a space width of 1.2 μm or more show almost no change in threshold voltage, but when the space width s is 0.9 μm or less, the threshold voltage greatly increases.

FIG. 23C shows the result of a p-channel MOS transistor. Samples with a space width s of 1.4 μm or more show almost no change in threshold voltage, but when the space width s is 1.2 μm or less, the threshold voltage is greatly reduced.

Considering the aspect ratio at the end of the etching, in the case of an n-channel MOS transistor, 1/1.
2 or less, for p-channel MOS transistors 1/1.
If it is 4 or less, the change in threshold voltage is negligible. Therefore, if a structure having an aspect ratio of 1 / 1.4 or less is formed as a pseudo scribe line, the substrate and the plasma can be brought into good electrical contact.

More preferably, only the resist pattern is considered, and the pseudo scribe line has an aspect ratio of 1 /.
It should be 2.8 or less. Also, considering only the width of the pseudo scribe line, the width is preferably 1.4 μm or more. More preferably, the width of the pseudo scribe line is at least four times the thickness of the wiring layer. This is to prevent the positive and negative charges in the plasma from being blocked by the resist in the wiring layer of the scribe line during the etching.

FIG. 18C is a cross-sectional view taken along a chain line C- in FIG.
The cross-sectional structure along C is shown. On the surface of the silicon semiconductor substrate 1, a field oxide film OX is selectively formed. The field oxide film OX is not formed around the chip, the semiconductor surface is exposed, and the scribe line SL is exposed.
Is formed. Also in pseudo scribe line QSL, the surface of semiconductor substrate 1 is exposed.

The opening of field oxide film OX is an active region for forming an element. In the case of the configuration shown, MOS transistor Q is formed in the active region. MOS transistor Q includes a source region S, a drain region D formed in semiconductor substrate 1, and an insulated gate electrode G formed on a channel region sandwiched between the source and drain regions.

The source region S and the drain region D
Are connected to a source electrode SE and a drain electrode DE, respectively. A gate electrode G and a source electrode SE,
The insulating film IS covering the drain electrode DE is not formed in the scribe line SL and the pseudo scribe line QSL, and the semiconductor surface is exposed. The insulating film IS is formed of, for example, phosphorus silicate glass (PSG).

FIG. 19 shows another example of the semiconductor structure. In the figure, parts that are the same as those shown in FIG. In this configuration example, the source electrode SE and the drain electrode DE of the MOS transistor Q are formed of an embedded metal region P such as a tungsten plug and a wiring layer W formed on the surface thereof. The tungsten plug P is formed by forming a contact hole, forming a conformal tungsten layer on the entire surface, and performing etch back. In the step of depositing and etching back the tungsten layer, the tungsten layer is deposited also in the area of the scribe line SL and the pseudo scribe line QSL. The tungsten region RW that has not been completely removed by the etch-back remains on the side surface of the insulating film whose side wall is almost vertical.

FIGS. 20A, 20B, and 20C show a semiconductor integrated circuit device in which input / output transistors also serve as pseudo scribe lines. FIG. 20A is a plan view of a semiconductor chip. A scribe line SL is formed in a peripheral area of the semiconductor chip CH. In its internal area,
A semiconductor integrated circuit is formed.

In this integrated circuit device, the input / output transistors Tr are formed not only in the peripheral region but also in the entire chip. For example, this structure has bumps over the entire surface of the chip and is suitable for a semiconductor integrated circuit device that is face-down bonded. MOS of internal circuit
Many transistors Q are formed in the internal region in addition to those shown.

FIG. 20 (B) shows the input / output transistor Tr
Is shown in an enlarged manner. The source region S has a width of about 0.5 μm in the current direction. Drain region D has a dimension in the current direction set to, for example, 60 μm. The dimension (channel width) of the source region S and the drain region D in the direction parallel to the gate electrode G is about 50 μm. A pseudo scribe line QSL of, for example, 30 μm × 40 μm is defined inside the drain region. The drain contact is formed outside the pseudo scribe line QSL. Note that a case where three contact holes are formed in each of the source region and the drain region is illustrated.

FIG. 20 (C) is a view similar to FIG.
20 shows a cross-sectional structure along 20C. The same parts as those in the above-described embodiment are denoted by the same reference numerals, and description thereof will be omitted. MOS transistor Q of the internal circuit is, for example, approximately 0.5 μm.
It has a gate length of m. The input / output transistor Tr has dimensions as described with reference to FIG. 20B, and a conductive region E such as a metal is formed in the pseudo scribe line QSL.

FIGS. 21 (A) to (C) and FIGS. 22 (D) to
(F) shows a manufacturing process for creating a structure as shown in FIGS. 19 and 20 (C). In FIG. 21A,
Field oxide film OX on the surface of silicon semiconductor substrate 1
Is created by the LOCOS method. Field oxide film O
The transistor Q of the internal circuit and the transistor Tr of the input / output circuit are created in the active region defined by X.

First, a gate electrode is formed by forming a gate oxide film on the surface of the active region, forming a polycide layer composed of a laminate of polycrystalline silicon and silicide, and patterning. Next, the first interlayer insulating film 51 is formed by burying the gate electrode G. The first interlayer insulating film is formed by, for example, PSG.

After the first interlayer insulating film 51 is formed, planarization may be performed by chemical mechanical polishing (CMP). The illustrated configuration shows a configuration in which the surface is flattened by CMP. The thickness of the first interlayer insulating film is, for example, about 2 μm from the substrate surface.

As shown in FIG. 21B, a resist mask is formed on first interlayer insulating film 51, and the first interlayer insulating film is etched to expose a desired region of the substrate surface. The figure shows
This shows a state where the resist mask has been removed. Note that a region serving as a contact hole of the transistor is an opening having a diameter of 0.8 μm, and a wide opening at the center is a portion serving as a pseudo scribe line QSL. The contact hole in this etching step has a high aspect ratio, and excessive positive charges are injected.

As shown in FIG. 21C, a tungsten film 53 is deposited on the entire surface of the substrate by CVD. The thickness of the tungsten film 53 is such that the hole is completely filled back in the contact hole portion. For example, a tungsten film having a thickness of about 1.5 times the diameter of the contact hole is deposited.

Next, as shown in FIG. 22D, the deposited tungsten film 53 is etched back. Etchback can be performed by plasma etching, CMP, or the like. For example, etch back is performed by CMP.
Then, the tungsten film 53 on the surface of the first interlayer insulating film 51a is almost completely removed. Note that, in the concave portion of pseudo scribe line QSL, tungsten film 53 is only chemically etched, so that a portion thereof 53R is formed.
Remains.

As shown in FIG. 22E, an aluminum alloy layer 55 is deposited as a wiring layer on the flattened surface by sputtering or the like. For example, an aluminum alloy having a thickness of about 1 μm is deposited.

As shown in FIG. 22F, a resist mask or the like is formed on aluminum layer 55, and aluminum layer 55 is patterned by plasma etching or the like (resist mask is not shown). Note that the pseudo scribe line QSL is not covered with the resist mask but is exposed.

In such plasma etching,
When the positive charge is excessively incident on the exposed wiring layer, the positive charge is injected into the substrate 1 from a contact portion or an insulated gate electrode portion connected to the wiring layer. This charge flows in the substrate and combines with positive and negative charges in the upper space at the scribe line and the pseudo scribe line to perform charge neutralization.

Even if a current flows in the substrate, if the distance between the current injection position and the current outlet is short, the potential difference generated in the substrate is small. Therefore, the threshold voltage of the gate electrode of the MOS transistor is rarely changed.

After forming the first wiring layer in this way, the surface is covered with the second interlayer insulating film, and the second wiring layer is formed. These steps can be realized in the same steps as the formation of the first interlayer insulating film and the formation of the first wiring layer. Note that wiring of three or more layers can be realized by the same process.

The present invention has been described in connection with the preferred embodiments.
The present invention is not limited to these. For example, it will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

[0163]

As described above, according to the present invention,
An increase in the chip area can be suppressed as much as possible, and damage to the gate oxide film due to charging of the wiring connected to the gate electrode during the manufacturing process can be suppressed. This makes it possible to improve the reliability of the semiconductor device and achieve higher integration.

[Brief description of the drawings]

FIG. 1 is a sectional view of a CMOS circuit according to an embodiment.

FIG. 2 is a plan view of a CMOS circuit according to an embodiment.

3A and 3B are a circuit diagram and a plan view of a circuit used in an experiment for confirming an effect of the embodiment.

FIG. 4 is a graph showing the relationship between the distance from the center of the wafer to the MOS transistor and the shift amount of the threshold voltage for each case of the presence or absence of the protection diode and the channel conductivity type of the MOS transistor.

FIG. 5 is a graph showing the relationship between the distance from the wafer center to the MOS transistor and the shift amount of the threshold voltage for each antenna ratio when the antenna ratio is changed.

FIG. 6 is a plan view of a circuit for showing the arrangement of the protection diodes when the distance between the protection diode and the MOS transistor is changed.

FIG. 7 is a graph showing the relationship between the distance from the center of the wafer to the MOS transistor and the shift amount of the threshold voltage for each distance when the distance between the protection diode and the MOS transistor is changed.

FIG. 8 is a sectional view of a CMOS circuit according to another embodiment.

FIG. 9 shows the case where the reverse breakdown voltage is changed by changing the impurity concentration of the p-type region of the protection diode.
9 is a graph showing a relationship between a distance from a wafer center to a MOS transistor and a shift amount of a threshold voltage.

FIG. 10 is a plan view of a circuit for showing a mounting position of the protection diode when the mounting position of the protection diode to the long wiring is changed.

FIG. 11 is a graph showing the relationship between the distance from the center of the wafer to the MOS transistor and the shift amount of the threshold voltage for each of the mounting positions of the protection diode.

FIG. 12 is a circuit diagram showing a method of inserting a protection diode in a CMOS circuit according to a conventional example, and NA of a CMOS configuration.
It is a circuit diagram of an ND gate.

FIG. 13 is a plan view showing the structure of an experimental sample.

14A and 14B are a plan view and a cross-sectional view illustrating a structure of a chip.

FIG. 15 is a plan view of a sample used in the experiment and a graph showing the experiment result.

FIG. 16 is a plan view showing a configuration of a chip according to an example.

FIG. 17 is a plan view showing a configuration of a chip according to an example.

FIG. 18 is a plan view and a cross-sectional view illustrating a configuration of a chip according to an example.

FIG. 19 is a cross-sectional view illustrating a configuration of a chip according to an example.

FIG. 20 is a plan view and a cross-sectional view illustrating a configuration of a chip according to an example.

FIG. 21 is a cross-sectional view showing a step of manufacturing a chip according to an example.

FIG. 22 is a cross-sectional view showing a step of manufacturing a chip according to an example.

FIG. 23 is a cross-sectional view and a graph showing an experimental result.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 p-type substrate 2 field oxide film 3 p-type well 4 n-type well 5 p ⁺ -type source region 6 p ⁺ -type drain region 7, 10 gate electrode 8 n ⁺ -type drain region 9 n ⁺ -type source region 11, 12 well contact 13 n ⁺ type region 14, 15 First layer wiring 16 Second layer wiring 17 Third layer wiring 18 P type high concentration region 19 Side wall 20 Protection diode 21 Wiring 30 MOS transistor 31 Long wiring 32 Protection diode 33 MOS transistor formation region 34a-34d Pad 35a-35d Wiring 40 Gate electrode 41 Source region 42 Drain region QSL Pseudo scribe line

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 21/8238 H01L 27/092 H01L 29/78

Claims (8)

(57) [Claims] A first conductivity type semiconductor substrate, a second conductivity type well opposite to the first conductivity type formed on the semiconductor substrate surface, and a first conductivity type region of the semiconductor substrate. A first MOS transistor having a gate electrode formed via a gate oxide film, a second MOS transistor having a gate electrode formed on the well surface via a gate oxide film, and the first MOS transistor A wiring connected to the gate electrode and the gate electrode of the second MOS transistor; a second conductivity type region formed in the first conductivity type region of the semiconductor substrate and electrically connected to the wiring; A protection diode including a pn junction with the second conductivity type region and a high impurity concentration first conductivity type region having an impurity concentration higher than a channel region below a gate electrode of the first MOS transistor; And another diode formed in the first conductivity type region of the semiconductor substrate, wherein the wiring and the well are not electrically directly connected, and A semiconductor device in which a distance between the formed transistor is longer than or equal to a distance between the other diode and the transistor formed closest thereto. 2. The semiconductor device according to claim 1, further comprising a plurality of active regions surrounded by a field oxide film on a surface of the semiconductor substrate, wherein an area of the second conductivity type region of the protection diode in the substrate surface is formed on the surface of the semiconductor substrate. 2. The semiconductor device according to claim 1, wherein the semiconductor device is equal to the smallest one of the impurity doped regions. 3. The protection diode and the first MOS.
Both the length along the wiring between the gate electrode of the transistor and the length between the protection diode and the gate electrode of the second MOS transistor along the wiring is 1/1 of the total length of the wiring. 3. The method according to claim 1, wherein the number is 2 or less.
3. The semiconductor device according to claim 1. 4. A first conductive type semiconductor substrate is provided with a first MO.
A step of forming an S transistor; a step of forming a second MOS transistor in a well of a second conductivity type opposite to the first conductivity type formed in the semiconductor substrate; and the first and second MOS transistors Forming a wiring connected to the gate electrode of the semiconductor substrate; implanting an impurity of the first conductivity type into the diode formation region of the semiconductor substrate so that an average implantation depth is the first depth; Heat-treating the substrate to activate the first conductivity type impurity and diffuse it to a second depth; and implanting the second conductivity type impurity into the diode formation region with an average implantation depth of the first depth. Implanting ions so as to have a third depth deeper than the second depth and shallower than the second depth; heat-treating the semiconductor substrate to activate the impurities of the second conductivity type; A method for manufacturing a semiconductor device including: 5. A semiconductor chip having an internal region surrounded by a scribe line, a plurality of diffusion regions formed in a semiconductor surface of the internal region and doped with impurities, each of which includes one of the diffusion regions. A plurality of MOS transistors each including a pair of diffusion regions and having an insulated gate structure formed on the surface of the semiconductor chip therebetween; and a gate electrode of each of the plurality of MOS transistors and at least another of the plurality of diffusion regions. A plurality of wirings connected to one; a distance from each gate electrode of the plurality of MOS transistors to a nearest scribe line; and one wiring connected to the wiring connected to the gate electrode. A semiconductor device having a distance from a diffusion region or a plurality of diffusion regions closest to the gate electrode to a closest scribe line; Circuit device. 6. A plurality of diffusion regions are connected to each of a part of the plurality of wirings, and a diffusion region closest to a gate electrode among the plurality of diffusion regions constitutes a protection diode. Semiconductor integrated circuit device. 7. A semiconductor chip having an internal region surrounded by a scribe line, a plurality of impurity regions formed in a semiconductor surface of the internal region and doped with impurities, each of which includes one of the diffusion regions. A plurality of MOS transistors each including a pair of diffusion regions and having an insulated gate structure formed on a surface of a semiconductor chip therebetween; each gate electrode of the plurality of MOS transistors; and at least one of the plurality of diffusion regions A plurality of wirings connected to the semiconductor substrate; and a cover on at least the uppermost wiring of the insulating layer covering the semiconductor substrate surface or the conductor surface formed on the semiconductor substrate surface and connected to the semiconductor substrate surface. And a pseudo scribe line from which an insulating layer other than the film has been removed. 8. The semiconductor integrated circuit device according to claim 7, wherein said pseudo scribe line is formed on a diffusion region of an input / output protection circuit.