CN115954355B

CN115954355B - Semiconductor device with a semiconductor layer having a plurality of semiconductor layers

Info

Publication number: CN115954355B
Application number: CN202310224859.XA
Authority: CN
Inventors: 宫本正文
Original assignee: Nexchip Semiconductor Corp
Current assignee: Nexchip Semiconductor Corp
Priority date: 2023-03-06
Filing date: 2023-03-06
Publication date: 2023-06-09
Anticipated expiration: 2043-03-06
Also published as: CN115954355A

Abstract

The invention provides a semiconductor device. In the semiconductor device, the n-type doped region forming the first protection diode is electrically connected with the first grid electrode in the NMOS transistor, the p-type doped region forming the second protection diode is electrically connected with the second grid electrode in the PMOS transistor, static electricity entering the first grid electrode and the second grid electrode generated in the manufacturing process of the semiconductor device can be eliminated through the first protection diode and the second protection diode respectively, damage of static electricity generated in the manufacturing process of the semiconductor device to the grid dielectric layers in the NMOS transistor and the PMOS transistor is effectively reduced, and the current capacity of the second protection transistor is larger than that of the first protection transistor, so that protection of both NMOS and PMOS by the protection diode is more effective, and the integral antistatic function of the semiconductor device can be improved.

Description

Semiconductor device with a semiconductor layer having a plurality of semiconductor layers

Technical Field

The invention relates to the technical field of semiconductors, in particular to a semiconductor device.

Background

Process Induced Damage (PID) is a significant problem in MOSFET manufacturing processes. Currently, many process steps employ plasmas for dielectric deposition and dry etching, wherein the gate dielectric layer of the MOSFET is susceptible to damage from static electricity. In addition, overpolishing during CMP can also cause electrostatic damage to the gate dielectric layer due to triboelectrification. Therefore, the structure of the semiconductor device needs to be optimized to effectively solve the problem of electrostatic damage of the semiconductor process to the gate dielectric layer.

Disclosure of Invention

In order to solve the problem of electrostatic damage to a gate dielectric layer by a semiconductor process, the invention provides a semiconductor device which comprises an NMOS transistor and a PMOS transistor formed on the surface area of a semiconductor substrate; and, the semiconductor device further includes:

a first protection diode including a p-type well region formed in the semiconductor substrate and an n-type doped region formed in the p-type well region; and

a second protection diode including an n-type well region formed in the semiconductor substrate and a p-type doped region formed in the n-type well region;

the NMOS transistor has a first gate electrically connected to an n-type doped region constituting the first protection diode, the PMOS transistor has a second gate electrically connected to a p-type doped region constituting the second protection diode, and a current capacity of the second protection diode is larger than that of the first protection diode.

Optionally, the orthographic projection area of the p-type doped region on the surface of the semiconductor substrate is larger than the orthographic projection area of the n-type doped region on the surface of the semiconductor substrate.

Optionally, the dopant concentration of the p-type doped region is greater than the dopant concentration of the n-type doped region.

Optionally, the dopant concentration in the n-type doped region and the p-type doped region is 1×10 or more ¹⁹ /cm ³ And less than or equal to 1X 10 ²¹ /cm ³ 。

Optionally, the semiconductor device further includes a first contact electrode, and the first contact electrode connects the first gate and the n-type doped region.

Optionally, the semiconductor device further includes a second contact electrode, and the second contact electrode connects the second gate and the p-type doped region.

Optionally, the first gate extends to the n-type doped region and is directly connected with the n-type doped region; and/or the second gate extends to the p-type doped region to be directly connected with the p-type doped region.

Optionally, a source region and a drain region of the NMOS transistor are formed in the p-type well region; and/or, the source region and the drain region of the PMOS transistor are formed in the n-type well region.

Optionally, the semiconductor substrate is a p-type doped substrate.

Optionally, the semiconductor device further comprises an n-type deep well region formed in the semiconductor substrate, the p-type well region is formed in the n-type deep well region, and the n-type well region is formed in the p-type well region.

In the semiconductor device provided by the invention, the n-type doped region forming the first protection diode is electrically connected with the first grid electrode in the NMOS transistor, so that static electricity entering the first grid electrode generated in the manufacturing process of the semiconductor device can be eliminated through the first protection diode, the p-type doped region forming the second protection diode is electrically connected with the second grid electrode in the PMOS transistor, so that static electricity entering the second grid electrode generated in the manufacturing process of the semiconductor device can be eliminated through the second protection diode, and the damage of static electricity generated in the manufacturing process of the semiconductor device to the grid dielectric layers in the NMOS transistor and the PMOS transistor can be effectively reduced.

The research shows that the static electricity generated in the manufacturing process of the semiconductor device has different influence degrees on the gate dielectric layers in the NMOS transistor and the PMOS transistor, and the influence degrees on the PMOS transistor are relatively larger.

Drawings

Fig. 1 is a schematic plan view showing a basic structure of a semiconductor device according to an embodiment of the present invention.

Fig. 2 is a schematic cross-sectional view of a basic structure of a semiconductor device in an embodiment of the present invention.

Fig. 3 is a functional explanatory diagram of a protection diode of a semiconductor device in an embodiment of the present invention.

Fig. 4 is a schematic plan view showing a basic structure of a semiconductor device according to another embodiment of the present invention.

Fig. 5 is a schematic cross-sectional view of a basic structure of a semiconductor device in another embodiment of the present invention.

Fig. 6 is a functional explanatory diagram of a protection diode of a semiconductor device in another embodiment of the present invention.

Fig. 7 is a schematic plan view showing a basic structure of a semiconductor device according to still another embodiment of the present invention.

Fig. 8 is a schematic cross-sectional view of the basic structure of a semiconductor device in yet another embodiment of the present invention.

Fig. 9 is a functional explanatory view of a protection diode of a semiconductor device in still another embodiment of the present invention.

Fig. 10 is a schematic cross-sectional view of a semiconductor substrate after forming a well region and an element isolation insulating layer in the semiconductor substrate according to an embodiment of the present invention.

Fig. 11 is a schematic cross-sectional view of a semiconductor substrate after forming NMOS and PMOS gate dielectric layers and gates thereon in accordance with an embodiment of the present invention.

Fig. 12 is a schematic cross-sectional view of a semiconductor substrate after an interlayer dielectric layer and a contact electrode are formed thereon in accordance with an embodiment of the present invention.

Reference numerals illustrate:

10: a semiconductor substrate; 12: a deep well region; 14: a first well region; 16: a second well region; 18n: a first heavily doped region; 18p: a second heavily doped region; 20n: a first gate dielectric layer; 20p: a second gate dielectric layer; 22n: a first gate; 22p: a second gate; 24n: a first contact electrode; 24p: a second contact electrode; 26: an element isolation insulating layer; 28: a side wall; 30: a dielectric layer; 32n: NMOS source drain contact electrode; 32p: PMOS source-drain contact electrodes; 100. 102, 104: a semiconductor device.

Detailed Description

The semiconductor device of the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are not to scale precisely, but merely to facilitate a clear description of embodiments of the invention, which should not be considered as being limited to the particular shape of the regions shown in the drawings. For clarity, in all the drawings for assisting in the description of the embodiments of the present invention, the same reference numerals are given to the same components in principle, and the repetitive description thereof will be omitted.

Fig. 1 is a schematic plan view showing a basic structure of a semiconductor device according to an embodiment of the present invention. The schematic cross-sectional view shown in fig. 2 is taken, for example, along line A-A in fig. 1.

The semiconductor device 100 has the basic structure of the first embodiment of the present invention. As shown in fig. 1, the semiconductor device 100 includes an N-type MOSFET (NMOS transistor, hereinafter NMOS) and a P-type MOSFET (PMOS transistor, hereinafter PMOS). The semiconductor device 100 of the present embodiment is not limited to any particular purpose of use, but may be used for MOSFETs used in DDIC (display driving chip) platforms.

The semiconductor device 100 includes a semiconductor substrate 10, a first well region 14, a second well region 16, a first heavily doped region 18n, a second heavily doped region 18p, a first gate dielectric layer 20n, a second gate dielectric layer 20p, a first gate 22n, a second gate 22p, a first contact electrode 24n, a second contact electrode 24p, an element isolation insulating layer 26, a sidewall 28, an interlayer dielectric layer 30, an NMOS source drain contact electrode 32n, and a PMOS source drain contact electrode 32p.

The semiconductor device 100 is formed in a surface region of the semiconductor substrate 10. The semiconductor substrate 10 is, for example, a silicon substrate. The semiconductor substrate 10 has a first conductivity type. The semiconductor substrate 10 is, for example, a p-type substrate.

The first well region 14 is formed in the semiconductor substrate 10 and extends to the surface of the semiconductor substrate 10. The first well region 14 has a higher dopant concentration than the semiconductor substrate 10. The first well region 14 has a first conductivity type. The first well region 14 is doped with, for example, p-type boron (B) dopant. The dopant concentration of the first well region 14 is, for example, 1×10 or more ¹⁶ /cm ³ And less than or equal to 5×10 ¹⁷ /cm ³ 。

The second well region 16 is formed in the semiconductor substrate 10 and extends to the surface of the semiconductor substrate 10. The second well region 16 has a higher dopant concentration than the semiconductor substrate 10. The second well region 16 has a second conductivity type opposite to the first conductivity type. The second well region 16 is doped with, for example, n-type phosphorus (P) or arsenic (As) dopants. The dopant concentration of the second well region 16 is, for example, 1×10 or more ¹⁶ /cm ³ And less than or equal to 5×10 ¹⁷ /cm ³ 。

The first heavily doped region 18n serves as part of a first protection diode, here an NMOS protection diode, hereinafter referred to as an NMOS protection diode. The first heavily doped region 18n is formed in the first well region 14. The dopant concentration of the first heavily doped region 18n is higher than the dopant concentration of the first well region 14. The first heavily doped region 18n has the second conductivity type. Since the first well region 14 has the first conductivity type, the first heavily doped region 18n and the first well region 14 constitute a diode. The first heavily doped region 18n is doped with, for example, an n-type phosphorus (P) or arsenic (As) dopant. Dopant concentration of first heavily doped region 18n The degree is, for example, 1X 10 or more ¹⁹ /cm ³ And less than or equal to 1X 10 ²¹ /cm ³ 。

The first well region 14 forms therein a source region and a drain region of an NMOS in addition to the first heavily doped region 18 n. In the plane of the semiconductor substrate 10, the source region and the drain region of the NMOS are located on both sides of the first gate 22n, respectively, and are connected to the NMOS source-drain contact electrode 32n.

The second heavily doped region 18p serves as part of a second protection diode, here a PMOS protection diode, hereinafter referred to as PMOS protection diode. A second heavily doped region 18p is formed within the second well region 16. The dopant concentration of second heavily doped region 18p is higher than the dopant concentration of second well region 16. The second heavily doped region 18p has the first conductivity type. Since the second well region 16 has the second conductivity type, the second heavily doped region 18p and the second well region 16 constitute a diode. The second heavily doped region 18p is doped with, for example, a p-type boron (B) dopant. The dopant concentration of the second heavily doped region 18p is, for example, 1×10 or more ¹⁹ /cm ³ And less than or equal to 1X 10 ²¹ /cm ³ 。

As shown in fig. 1, the formation region of the second heavily doped region 18p occupies a larger surface area of the semiconductor substrate 10 than the formation region of the first heavily doped region 18 n. That is, the orthographic projection area of the second heavily doped region 18p on the surface of the semiconductor substrate 10 is larger than the orthographic projection area of the first heavily doped region 18n on the surface of the semiconductor substrate 10 when viewed from the surface side of the semiconductor device 100.

In addition, the second well region 16 forms a source region and a drain region of the PMOS in addition to the second heavily doped region 18 p. In the plane of the semiconductor substrate 10, the source region and the drain region of the PMOS are located on both sides of the second gate 22p, respectively, and are connected to the PMOS source-drain contact electrode 32p.

The first gate dielectric layer 20n is a dielectric layer disposed between the gate of the NMOS and the semiconductor substrate 10. The first gate dielectric layer 20n is disposed in a region between the source region and the drain region of the surface NMOS of the semiconductor substrate 10. The first gate dielectric layer 20n may be a silicon oxide layer (SiO ₂ ) A silicon nitride layer (SiN) or a silicon oxynitride layer (SiO) _x N _y ). In the semiconductor device 100, when the thickness of the first gate dielectric layer 20n is 10nm or less, more preferably 5nm or less, the improvement effect of the semiconductor device 100 is more remarkable. The thickness of the first gate dielectric layer 20n may be set according to the characteristics required for the semiconductor device 100.

The second gate dielectric layer 20p is a dielectric layer disposed between the gate of the PMOS and the semiconductor substrate 10. A second gate dielectric layer 20p is provided in a region between the source and drain regions of the surface PMOS of the semiconductor substrate 10. The second gate dielectric layer 20p may be a silicon oxide layer (SiO ₂ ) A silicon nitride layer (SiN) or a silicon oxynitride layer (SiO) _x N _y ). In the semiconductor device 100, when the thickness of the second gate dielectric layer 20p is 10nm or less, more for example, 5nm or less, the improvement effect of the semiconductor device 100 is more remarkable. The thickness of the second gate dielectric layer 20p may be set according to the characteristics required for the semiconductor device 100.

The first gate 22n is used to apply a voltage to the gate of the NMOS. The first gate 22n is formed on the first gate dielectric layer 20 n. The first gate 22n is, for example, a polysilicon layer, a metal layer, a silicide or a stacked structure thereof. In the semiconductor device 100, the thickness of the first gate 22n is, for example, 50nm or more and 500nm or less, and may be specifically set according to the characteristics required for the semiconductor device 100.

The second gate 22p is used to apply a voltage to the gate of the PMOS. The second gate 22p is formed on the second gate dielectric layer 20 p. The second gate 22p is, for example, a polysilicon layer, a metal layer, a silicide or a stacked structure thereof. In the semiconductor device 100, the thickness of the second gate 22p is, for example, 50nm or more and 500nm or less. The thickness of the second gate 22p may be set according to the characteristics required for the semiconductor device 100.

The first contact electrode 24n serves as a contact electrode for the NMOS protection diode. The first contact electrode 24n is disposed in electrical connection with the first heavily doped region 18n and the first gate 22 n. Specifically, the first contact electrode 24n is formed in a contact hole formed in the interlayer dielectric layer 30, and the first heavily doped region 18n formed from the adjacent NMOS extends on the sidewall 28 and is finally connected to the first gate 22 n. The first contact electrode 24n is, for example, a stacked structure of one or two or more of a polysilicon layer, a metal layer, and a silicide layer. Specifically, the first contact electrode 24n is, for example, a titanium (Ti)/titanium nitride (TiN)/tungsten (W) metal laminate structure.

The second contact electrode 24p serves as a contact electrode for the PMOS protection diode. The second contact electrode 24p is disposed in electrical connection with the second heavily doped region 18p and the second gate 22 p. Specifically, the second contact electrode 24p is formed in a contact hole provided in the interlayer dielectric layer 30, and the second heavily doped region 18p formed from the adjacent PMOS extends on the sidewall 28 and is finally connected to the second gate 22 p. The second contact electrode 24p is, for example, a stacked structure of one or two or more of a polysilicon layer, a metal layer, and a silicide layer. Specifically, the second contact electrode 24p is, for example, a titanium (Ti)/titanium nitride (TiN)/tungsten (W) metal laminated structure.

The element isolation insulating layer 26 is an insulating region for insulating adjacent elements. The element isolation insulating layer 26 is provided to surround the NMOS, PMOS, and protection diode adjacent to each other, respectively, to electrically insulate them. The element isolation insulating layer 26 may be a shallow trench isolation (STI: shallow Trench Isolation) region.

The sidewall 28 covers the sides of the first gate dielectric layer 20n and the first gate 22n, and the sides of the second gate dielectric layer 20p and the second gate 22 p. The sidewall 28 may be a silicon oxide layer (SiO ₂ ) Silicon nitride layer (SiN) and silicon oxynitride layer (SiO) _x N _y ) A laminated structure of one or more of the layers. The thickness and width of the side wall 28 are, for example, 2nm or more and 10nm or less, and more preferably 3nm or more and 6nm or less.

The interlayer dielectric layer 30 covers the surface of the semiconductor device 100 and serves to electrically insulate the first contact electrode 24n, the second contact electrode 24p, the NMOS source drain contact electrode 32n, the PMOS source drain contact electrode 32p, and the like while mechanically protecting the semiconductor device 100. The interlayer dielectric layer 30 may be a silicon oxide layer (SiO ₂ ) Silicon nitride layer (SiN) and silicon oxynitride layer (SiO) _x N _y ) One or more of the layersA laminated structure.

The NMOS source and drain contact electrode 32n is used to make electrical contact with the source and drain regions of the NMOS. The NMOS source-drain contact electrode 32n is formed in a contact hole provided in the interlayer dielectric layer 30 in such a manner as to be electrically connected to the source region and the drain region of the NMOS. The NMOS source drain contact electrode 32n is, for example, a stacked structure of one or two or more of a polysilicon layer, a metal layer, and a silicide layer. Specifically, the NMOS source-drain contact electrode 32n has a titanium (Ti)/titanium nitride (TiN)/tungsten (W) metal stacked structure, for example.

The PMOS source drain contact electrode 32p is used to make electrical contact with the PMOS source and drain regions. PMOS source-drain contact electrodes 32p are formed in contact holes provided in the interlayer dielectric layer 30 in such a manner as to be electrically connected to the source and drain regions of the PMOS. The PMOS source drain contact electrode 32p is, for example, a stacked structure of one or two or more of a polysilicon layer, a metal layer, and a silicide layer. Specifically, the PMOS source drain contact electrode 32p has a titanium (Ti)/titanium nitride (TiN)/tungsten (W) metal stack structure, for example.

Fig. 3 is a functional explanatory diagram of a protection diode of a semiconductor device in an embodiment of the present invention. As shown in fig. 3, the first heavily doped region 18n and the first well region 14 constitute a protection diode PDN (i.e., a first protection diode). In the protection diode PDN, the first well region 14 side is the anode, and the first heavily doped region 18n side is the cathode. In addition, the second heavily doped region 18p and the second well region 16 constitute a protection diode PDP (i.e., a second protection diode). In the protection diode PDP, the second heavily doped region 18p side is an anode, and the second well region 16 side is a cathode. In addition, the second well region 16 and the semiconductor substrate 10 constitute a protection diode NWPs. In the protection diode NWPs, the semiconductor substrate 10 side is an anode, and the second well region 16 side is a cathode.

Positive or negative charges may be generated during sputtering, CVD, CMP, metal etching, ILD deposition, and the like in the fabrication process of the semiconductor device 100. The protection diode PDN, PDP, NWPs has a function of protecting the semiconductor device 100 against the electric charges thus generated.

That is, when positive charges are generated on the surface side of the semiconductor device 100, the protection diode PDP provided on the PMOS side is forward biased so that the positive charges are discharged through the second heavily doped region 18p and the second well region 16. At the same time, the protection diode NWPs is in a high resistance state due to reverse bias, so that the voltage applied to the second gate dielectric layer 20p is relieved. In this way, damage to the PMOS can be reduced. At this time, although the protection diode PDN on the NMOS side is reverse biased, the induced voltage equal to or greater than the diode reverse withstand voltage may be discharged through the first heavily doped region 18n and the first well region 14. In this way, damage to the NMOS can be reduced to some extent.

In addition, when negative charges are generated on the surface side of the semiconductor device 100, although the protection diode PDP provided on the PMOS side is reverse biased, for an induced voltage equal to or greater than the diode reverse withstand voltage, discharge may be performed via the second heavily doped region 18p and the second well region 16. In this way, damage to the PMOS can be reduced to some extent. Meanwhile, the protection diode PDN provided at one side of the NMOS is forward biased to discharge negative charges through the first heavily doped region 18n and the first well region 14, thereby reducing damage to the NMOS.

Wherein, by making the formation region of the second heavily doped region 18p larger than the surface area of the semiconductor substrate 10 occupied by the formation region of the first heavily doped region 18n as described above, the junction area and the junction capacitance of the protection diode PDP (i.e., the second protection diode) are respectively larger than the junction area and the junction capacitance of the protection diode PDN (i.e., the first protection diode), the current allowed to pass by the protection diode PDP is made larger than the protection diode PDN, i.e., the current capacity of the protection diode PDP is made larger than the current capacity of the protection diode PDN, so that the amount of charge that the protection diode PDP can alleviate is made larger than the amount of charge that the protection diode PDN can alleviate. Thus, the protection of the PMOS can be enhanced with respect to the NMOS, so that the PMOS which is more likely to be damaged than the NMOS is properly protected.

In addition, although the current capacity of the protection diode PDP is made larger than that of the protection diode PDN by making the formation region of the second heavily doped region 18p larger than the surface area of the semiconductor substrate 10 occupied by the formation region of the first heavily doped region 18n in the present embodiment, the present invention is not limited thereto. That is, any configuration that can make the current capacity of the protection diode PDP larger than that of the protection diode PDN may be adopted. For example, by making the dopant concentration of the second heavily doped region 18p larger than the dopant concentration of the first heavily doped region 18n, the current capacity of the protection diode PDP is made larger than the current capacity of the protection diode PDN, specifically, when the dopant concentration of the second heavily doped region 18p is larger than the dopant concentration of the first heavily doped region 18n, the conductivity of the second heavily doped region 18p is stronger, the impedance is smaller, the junction capacity of the protection diode PDP is larger, so that the current allowed to pass by the protection diode PDP is larger than the protection diode PDN, i.e., so that the current capacity of the protection diode PDP is larger than the current capacity of the protection diode PDN.

Fig. 4 is a schematic plan view showing a basic structure of a semiconductor device according to another embodiment of the present invention. The schematic cross-sectional view shown in fig. 5 is taken, for example, along line B-B in fig. 4.

The semiconductor device 102 has the basic structure of the second embodiment of the present invention. As shown in fig. 4, the semiconductor device 102 includes an N-type MOSFET (hereinafter referred to as NMOS) and a P-type MOSFET (hereinafter referred to as PMOS). The semiconductor device 102 of the present embodiment is not limited to any particular purpose of use, but may be used for MOSFETs used in DDIC platforms.

Similar to the semiconductor device 100, the semiconductor device 102 includes a semiconductor substrate 10, a first well region 14, a second well region 16, a first heavily doped region 18n, a second heavily doped region 18p, a first gate dielectric layer 20n, a second gate dielectric layer 20p, a first gate 22n, a second gate 22p, a first contact electrode 24n, a second contact electrode 24p, an element isolation insulating layer 26, a sidewall 28, an interlayer dielectric layer 30, an NMOS source drain contact electrode 32n, and a PMOS source drain contact electrode 32p.

The semiconductor device 102 is different from the semiconductor device 100 in that the connection structures of the first contact electrode 24n and the second contact electrode 24p for the first heavily doped region 18n and the second heavily doped region 18p, respectively, are different. Therefore, a description of the rest of the structure is omitted here, and only the structural differences from the semiconductor device 100 will be described.

The first gate dielectric layer 20n is a dielectric layer disposed between the gate of the NMOS and the semiconductor substrate 10. The first gate dielectric layer 20n is disposed in a region between the source region and the drain region of the surface NMOS of the semiconductor substrate 10. In the semiconductor device 102, the first gate dielectric layer 20n is formed to further cover the formation region of the first heavily doped region 18n, and then a portion of the first gate dielectric layer 20n above the first heavily doped region 18n is removed by etching or the like. In this way, a structure in direct contact with the first heavily doped region 18n can be achieved.

The second gate dielectric layer 20p is a dielectric layer disposed between the gate of the PMOS and the semiconductor substrate 10. A second gate dielectric layer 20p is provided in a region between the source and drain regions of the surface PMOS of the semiconductor substrate 10. In the semiconductor device 102, the second gate dielectric layer 20p is formed to further cover the formation region of the second heavily doped region 18p, and then a portion of the second gate dielectric layer 20p over the second heavily doped region 18p is removed by etching or the like. In this way, a structure in direct contact with the second heavily doped region 18p can be realized.

The first gate 22n is formed to span from the first gate dielectric layer 20n to the first heavily doped region 18n. In addition, a second gate 22p is formed to cross from the second gate dielectric layer 20p to the second heavily doped region 18p.

The first contact electrode 24n is electrically connected to the first heavily doped region 18n via the first gate 22 n. Specifically, the first contact electrode 24n is formed in a contact hole provided in the interlayer dielectric layer 30 above a formation region of the first heavily doped region 18n formed adjacent to the NMOS. The second contact electrode 24p is electrically connected to the second heavily doped region 18p via the second gate 22 p. Specifically, the second contact electrode 24p is formed in a contact hole provided in the interlayer dielectric layer 30 above a formation region of the second heavily doped region 18p formed adjacent to the PMOS.

Further, as shown in fig. 4, in the semiconductor device 102, the formation region of the second heavily doped region 18p occupies a surface area of the semiconductor substrate 10 that is also larger than the formation region of the first heavily doped region 18 n. That is, the orthographic projection area of the second heavily doped region 18p on the surface of the semiconductor substrate 10 is larger than the orthographic projection area of the first heavily doped region 18n on the surface of the semiconductor substrate 10 when viewed from the surface side of the semiconductor device 100.

Fig. 6 is a functional explanatory diagram of a protection diode of a semiconductor device in another embodiment of the present invention. As shown in fig. 6, a protection diode is provided in the semiconductor device 102, and functions of the protection diode are the same as those in the semiconductor device 100. The first heavily doped region 18n and the first well region 14 constitute a protection diode PDN (i.e., a first protection diode). In the protection diode PDN, the first well region 14 side is the anode, and the first heavily doped region 18n side is the cathode. In addition, the second heavily doped region 18p and the second well region 16 constitute a protection diode PDP (i.e., a second protection diode). In the protection diode PDP, the second heavily doped region 18p side is an anode, and the second well region 16 side is a cathode. In addition, the second well region 16 and the semiconductor substrate 10 constitute a protection diode NWPs. In the protection diode NWPs, the semiconductor substrate 10 side is an anode, and the second well region 16 side is a cathode.

When positive charges are generated on the surface side of the semiconductor device 102, the protection diode PDP provided on the PMOS side is forward biased so that the positive charges are discharged through the second heavily doped region 18p and the second well region 16. At the same time, the protection diode NWPs is in a high resistance state due to reverse bias, so that the voltage applied to the second gate dielectric layer 20p is relieved. In this way, damage to the PMOS can be reduced. At this time, although PDN on the NMOS side is reverse biased, the induced voltage equal to or greater than the diode reverse withstand voltage may be discharged through the first heavily doped region 18n and the first well region 14. In this way, damage to the NMOS can be reduced to some extent.

In addition, when negative charges are generated on the surface side of the semiconductor device 102, the protection diode PDP provided on the PMOS side is reverse biased, but for an induced voltage equal to or greater than the diode reverse withstand voltage, discharge may be performed via the second heavily doped region 18p and the second well region 16. In this way, damage to the PMOS can be reduced to some extent. Meanwhile, the protection diode PDN provided at one side of the NMOS is forward biased to discharge negative charges through the first heavily doped region 18n and the first well region 14, thereby reducing damage to the NMOS.

In the semiconductor device 102, the current capacity of the protection diode PDP is made larger than the current capacity of the protection diode PDN by making the formation region of the second heavily doped region 18p larger than the surface area of the semiconductor substrate 10 occupied by the formation region of the first heavily doped region 18n, so that the amount of charge that the protection diode PDP can mitigate is made larger than the amount of charge that the protection diode PDN can mitigate. Thus, the protection of the PMOS can be enhanced with respect to the NMOS, so that the PMOS which is more likely to be damaged than the NMOS is properly protected.

In addition, although the current capacity of the protection diode PDP is made larger than the current capacity of the protection diode PDN in the semiconductor device 102 by making the formation region of the second heavily doped region 18p larger than the surface area of the semiconductor substrate 10 occupied by the formation region of the first heavily doped region 18n, the present invention is not limited thereto. That is, any configuration that can make the current capacity of the protection diode PDP larger than that of the protection diode PDN may be adopted. For example, the current capacity of the protection diode PDP may be made larger than the current capacity of the protection diode PDN by making the dopant concentration of the second heavily doped region 18p larger than the dopant concentration of the first heavily doped region 18n, or the like.

Fig. 7 is a schematic plan view showing a basic structure of a semiconductor device according to still another embodiment of the present invention. The schematic cross-sectional view of fig. 8 is taken, for example, along line C-C in fig. 7.

The semiconductor device 104 has the basic structure of the third embodiment of the present invention. As shown in fig. 7, the semiconductor device 104 includes an N-type MOSFET (hereinafter referred to as NMOS) and a P-type MOSFET (hereinafter referred to as PMOS). The semiconductor device 104 of the present embodiment is not limited to any particular purpose of use, but may be used for MOSFETs used in DDIC platforms.

The semiconductor device 104 includes a semiconductor substrate 10, a deep well region 12, a first well region 14, a second well region 16, a first heavily doped region 18n, a second heavily doped region 18p, a first gate dielectric layer 20n, a second gate dielectric layer 20p, a first gate 22n, a second gate 22p, a first contact electrode 24n, a second contact electrode 24p, an element isolation insulating layer 26, a sidewall 28, an interlayer dielectric layer 30, an NMOS source drain contact electrode 32n, and a PMOS source drain contact electrode 32p.

The semiconductor device 104 differs from the semiconductor device 100 and the semiconductor device 102 in the structure in that the semiconductor device 104 is provided with the deep well region 12. Therefore, description of the rest of the structure is omitted here, and only the structural differences from the semiconductor device 100 and the semiconductor device 102 will be described.

A deep well region 12 is formed within the semiconductor substrate 10. The deep well region 12 has a higher dopant concentration than the semiconductor substrate 10. The deep well region 12 has the second conductivity type. The deep well region 12 is doped with, for example, n-type phosphorus (P) or arsenic (As) dopants. The dopant concentration of the deep well region 12 is, for example, 1×10 or more ¹⁶ /cm ³ And less than or equal to 5×10 ¹⁷ /cm ³ 。

The first well region 14 is formed in a surface region of the semiconductor substrate 10. The first well region 14 is formed in the deep well region 12 in a region shallower than the deep well region 12 below the surface of the semiconductor substrate 10. The first well region 14 has a first conductivity type. The first well region 14 is doped with, for example, p-type boron (B) dopant. The dopant concentration of the first well region 14 is higher than that of the deep well region 12. The dopant concentration of the first well region 14 is, for example, 1×10 or more ¹⁶ /cm ³ And less than or equal to 5×10 ¹⁷ /cm ³ 。

The second well region 16 is formed in a surface region of the semiconductor substrate 10. The second well region 16 is formed in the first well region 14 in a region shallower than the first well region 14 below the surface of the semiconductor substrate 10. The second well region has a second conductivity type. The second well region 16 is doped with, for example, n-type phosphorus (P) or arsenic (As) dopants. The second well region 16 has a higher dopant concentration than the first well region 14. The dopant concentration of the second well region 16 is, for example, 1×10 or more ¹⁶ /cm ³ And less than or equal to 5×10 ¹⁷ /cm ³ 。

In accordance with the semiconductor device 100, a first heavily doped region 18n and a second heavily doped region 18p are formed within the first well region 14 and within the second well region 16, respectively. In the semiconductor device 104, as shown in fig. 7, the formation region of the second heavily doped region 18p occupies a larger surface area of the semiconductor substrate 10 than the formation region of the first heavily doped region 18 n. That is, the orthographic projection area of the second heavily doped region 18p on the surface of the semiconductor substrate 10 is larger than the orthographic projection area of the first heavily doped region 18n on the surface of the semiconductor substrate 10 when viewed from the surface side of the semiconductor device 104.

Fig. 9 is a functional explanatory view of a protection diode of a semiconductor device in still another embodiment of the present invention. As shown in fig. 9, the first heavily doped region 18n and the first well region 14 constitute a protection diode PDN (i.e., a first protection diode). In the protection diode PDN, the first well region 14 side is the anode, and the first heavily doped region 18n side is the cathode. The first well region 14 and the deep well region 12 constitute a protection diode DPWDNW. In the protection diode DPWDNW, the first well region 14 side is an anode, and the deep well region 12 side is a cathode. The deep well region 12 and the semiconductor substrate 10 constitute a protection diode DNWPs. In the protection diode DNWPs, the semiconductor substrate 10 side is an anode, and the deep well region 12 side is a cathode.

In addition, the second heavily doped region 18p and the second well region 16 constitute a protection diode PDP (i.e., a second protection diode). In the protection diode PDP, the second heavily doped region 18p side is an anode, and the second well region 16 side is a cathode. The second well region 16 and the first well region 14 constitute a protection diode DNWPW. In the protection diode DNWPW, the first well region 14 side is an anode, and the second well region 16 side is a cathode. The first well region 14 and the deep well region 12 constitute a protection diode DPWDNW. In the protection diode DPWDNW, the first well region 14 side is an anode, and the deep well region 12 side is a cathode. The deep well region 12 and the semiconductor substrate 10 constitute a protection diode DNWPs. In the protection diode DNWPs, the semiconductor substrate 10 side is an anode, and the deep well region 12 side is a cathode.

The protection diode PDN, DPWDNW, DNWPs, PDP and DNWPW have a function of protecting the semiconductor device 100 from the generation of electric charges.

That is, when positive charges are generated on the surface side of the semiconductor device 100, the protection diode PDP provided on the PMOS side is forward biased so that the positive charges are discharged through the second heavily doped region 18p and the second well region 16. At the same time, the protection diodes DNWPW and DNWPs are in a high resistance state due to reverse bias, so that the voltage applied to the second gate dielectric layer 20p is relieved. In this way, damage to the PMOS can be reduced. At this time, although PDN on the NMOS side is reverse biased, the induced voltage equal to or greater than the diode reverse withstand voltage may be discharged through the first heavily doped region 18n and the first well region 14. At the same time, the protection diode DNWPs is in a high resistance state due to reverse bias, so that the voltage applied to the first gate dielectric layer 20n is relieved. In this way, damage to the NMOS can be reduced.

In addition, when negative charges are generated on the surface side of the semiconductor device 100, although the protection diode PDP provided on the PMOS side is reverse biased, for an induced voltage equal to or greater than the diode reverse withstand voltage, discharge may be performed via the second heavily doped region 18p and the second well region 16. At the same time, the protection diode DPWDNW is in a high resistance state due to reverse bias, so that the voltage applied to the second gate dielectric layer 20p is relieved. Thus, damage to the PMOS can also be reduced. At this time, the protection diode PDN provided at one side of the NMOS is forward biased, so that negative charges are discharged through the first heavily doped region 18n and the first well region 14, and damage to the NMOS can be reduced.

Wherein, by making the surface area of the semiconductor substrate 10 occupied by the formation region of the second heavily doped region 18p larger than the surface area of the semiconductor substrate 10 occupied by the formation region of the first heavily doped region 18n as described above, the current capacity of the protection diode PDP is made larger than the current capacity of the protection diode PDN, so that the amount of charge that the protection diode PDP can mitigate is made larger than the amount of charge that the protection diode PDN can mitigate. Thus, the protection of the PMOS can be enhanced with respect to the NMOS, so that the PMOS which is more likely to be damaged than the NMOS is properly protected.

In addition, although the current capacity of the protection diode PDP is made larger than the current capacity of the protection diode PDN by making the formation region of the second heavily doped region 18p larger than the surface area of the semiconductor substrate 10 occupied by the formation region of the first heavily doped region 18n in the present embodiment, the present invention is not limited thereto. That is, any configuration that can make the current capacity of the protection diode PDP larger than that of the protection diode PDN may be adopted. For example, the current capacity of the protection diode PDP may be made larger than the current capacity of the protection diode PDN by making the dopant concentration of the second heavily doped region 18p larger than the dopant concentration of the first heavily doped region 18n, or the like.

A method of manufacturing the semiconductor device 104 is described below with reference to fig. 10 to 12. Note that fig. 10 to 12 emphasize the respective portions constituting the semiconductor device 104, and the dimensions of the respective portions in the planar direction and the dimensions in the thickness direction are not drawn to actual scale in some cases.

Hereinafter, the semiconductor substrate 10 is exemplified as a p-type doped silicon substrate as the first conductivity type.

Fig. 10 is a schematic cross-sectional view of a semiconductor substrate after forming a well region and an element isolation insulating layer in the semiconductor substrate according to an embodiment of the present invention. As shown in fig. 10, a deep well region 12, a first well region 14, a second well region 16, and an element isolation insulating layer 26 are formed within a semiconductor substrate 10.

The element isolation insulating layer 26 may be formed by an existing STI process using a mask. In the STI process, silicon oxide (SiO ₂ ) And silicon nitride (SiN) as a mask, after etching a trench in the peripheral region of the device region, a dielectric layer is filled in the trench by a high-density plasma CVD or the like, and then the region is planarized by a Chemical Mechanical Polishing (CMP) method, thereby forming the element isolation insulating layer 26.

The deep well region 12 is formed by implanting n-type dopant (phosphorus P or arsenic As) ions into the surface of the semiconductor substrate 10. The deep well region 12 is formed in the NMOS and PMOS arrangement regions. For example, in ion implantation, an ion implantation energy of 2600keV is used to implant a material of 1.0X10 or less ¹³ /cm ² Right and left phosphorus (P). The ion implantation density, implantation depth, and the like of the dopant may be appropriately set according to the size and characteristics of the semiconductor device 100.

As shown in fig. 7 and 10, the first well region 14 and the second well region 16 are formed in regions corresponding to NMOS and PMOS, which are isolated by the element isolation insulating layer 26.

The first well region 14 is formed on the surface of the semiconductor substrate 10Implantation of p-dopants (boron B or boron difluoride BF ₂ ) Ions are formed. The first well region 14 is formed in the formation region of the deep well region 12. For example, an energy of about 270keV and 2.0X10 are provided in the semiconductor substrate 10 ¹³ /cm ² Density of about 120keV and 8.0X10 ¹² /cm ² Density of about 40keV and energy of 2.0X10 ¹² /cm ² Is implanted with boron (B) ions in steps. The ion implantation density, implantation depth, and the like of the dopant may be appropriately set according to the size and characteristics of the semiconductor device 100.

The second well region 16 is formed by implanting n-type dopant (phosphorus P or arsenic As) ions into the surface of the semiconductor substrate 10. The second well region 16 is formed in the formation region of the first well region 14. For example, at an energy of around 400keV and 2.0X10 ¹³ /cm ² Density of about 240keV and 8.0X10 ¹² /cm ² Density of about 60keV and energy of 2.0X10) ¹³ /cm ² Is implanted with boron phosphorus (P) ions in steps. The second well region 16 may be shallower than the first well region 14, the second well region 16 may be formed to be surrounded by the first well region 14, and the ion implantation density, implantation depth, and the like of the dopant may be appropriately set according to the size and characteristics of the semiconductor device 104.

After ion implantation, ion diffusion treatment is performed. After the implantation of the dopant into the deep well region 12, the semiconductor substrate 10 is annealed at about 1000 ℃. The heating temperature and the heating time may be appropriately set according to the size and characteristics of the semiconductor device 104.

Fig. 11 is a schematic cross-sectional view of a semiconductor substrate after forming NMOS and PMOS gate dielectric layers and gates thereon in accordance with an embodiment of the present invention. As shown in fig. 11, subsequently, a first heavily doped region 18n, a second heavily doped region 18p, a first gate dielectric layer 20n, a second gate dielectric layer 20p, a first gate 22n, a second gate 22p, and a sidewall 28 are formed.

First, a first gate dielectric layer 20n and a second gate dielectric layer 20p are formed. Wherein the first gate dielectric layer 20n and the second gate dielectric layer 20p can be formed by using oxygen (O ₂ ) Oxygen-containing gas or nitrogen（N ₂ ) And the nitrogen-containing gas is formed by a thermal oxidation method. The first gate dielectric layer 20n is formed in a first well region 14 forming region on the surface of the semiconductor substrate 10 so as to straddle the source region and the drain region of the NMOS. In addition, the second gate dielectric layer 20p is formed in a manner to cross the source region and the drain region of the PNMOS in the second well region 16 formation region of the surface of the semiconductor substrate 10. The thicknesses of the first gate dielectric layer 20n and the second gate dielectric layer 20p are, for example, 10nm or less, more for example, 5nm or less. The thicknesses of the first gate dielectric layer 20n and the second gate dielectric layer 20p may be appropriately set according to the size and characteristics of the semiconductor device 104. For example, the first gate dielectric layer 20n and the second gate dielectric layer 20p having a thickness of 10nm or less are formed by supplying an oxidizing gas in a state where the semiconductor substrate 10 is heated at a temperature of 1050 ℃.

The first gate 22n and the second gate 22p are formed on the first gate dielectric layer 20n and the second gate dielectric layer 20p, respectively. The forming method of the first gate 22n and the second gate 22p is not particularly limited. In the case of a polysilicon layer, a method using silane (SiH ₄ ) Chemical Vapor Deposition (CVD) of silicon-containing gases. In the case where the first gate electrode 22n and the second gate electrode 22p are metal layers, a vapor deposition method, a sputtering method, a Chemical Vapor Deposition (CVD) method, or the like may be used. The thickness of the first gate 22n and the second gate 22p is, for example, 50nm or more and 500nm or less. For example, the thickness of the first gate 22n and the second gate 22p is 100nm.

Subsequently, the first and second

gate dielectric layers

20n and 20p and the first and

second gates

22n and 22p are patterned. The first and second

gate dielectric layers

20n and 20p and the first and

second gates

22n and 22p are patterned in desired regions of the semiconductor device 100 by conventional photolithographic and etching techniques. That is, a photoresist layer may be formed on the first and second

gate dielectric layers

20n and 20p and the first and

second gates

22n and 22p, then the photoresist layer may be patterned by a photolithography technique, and then the first and second

gate dielectric layers

20n and 20p and the first and

second gates

22n and 22p of the undesired region may be removed by an etching technique using the photoresist layer as a mask, thereby achieving patterning.

After this, the side wall 28 is formed. Wherein a silicon oxide layer (SiO) is formed extending from the top surfaces of the first gate 22n and the second gate 22p to cover the side surfaces of the first gate dielectric layer 20n and the first gate 22n and the second gate dielectric layer 20p and the second gate 22p and the surface of the semiconductor substrate 10 ₂ ). The silicon oxide layer (SiO) ₂ ) May be formed by Chemical Vapor Deposition (CVD) using Tetraethoxysilane (TEOS). In addition, the silicon oxide layer (SiO ₂ ) It can also be formed by Chemical Vapor Deposition (CVD) using an oxygen-containing gas such as oxygen or a nitrogen-containing gas such as nitrogen. Subsequently, the silicon oxide layer (SiO ₂ ) Etching is performed to form side walls 28 covering the sides of the first gate dielectric layer 20n and the first gate 22n, and the second gate dielectric layer 20p and the second gate 22 p. The sidewall 28 has a width of, for example, about 2nm or more and 10nm or less from the end portions of the first gate dielectric layer 20n and the first gate 22n and the second gate dielectric layer 20p and the second gate 22 p.

In addition, LDD regions may be formed as needed before forming the spacers 28. The LDD region is provided near the drain regions of the NMOS and PMOS, and the dopant concentration is lower than that of the drain regions. By providing an LDD region having a lower dopant concentration, a depletion layer can be expanded in the LDD region, thereby reducing the electric field strength and reducing the generation of hot carriers.

After forming the spacers 28, the source and drain regions of the NMOS and the first heavily doped region 18n are formed. Wherein a photoresist layer is first formed on the surface of the semiconductor substrate 10, and then a portion of the photoresist layer is removed by a photolithography technique to form an opening region in the regions of the source and drain regions and the first heavily doped region 18n of the NMOS to be formed. Then, ion implantation is performed using the photoresist layer As a mask and n-type phosphorus (P) or arsenic (As) As a dopant. Wherein, for example, the ion implantation energy is 23keV and 3×10 ¹⁵ /cm ² Arsenic (As) ions are implanted. The ion implantation density, implantation depth, and the like of the dopant may be appropriately set according to the size and characteristics of the semiconductor device 100. And after the ion implantation process is finished, removing the photoresist layer.

Thereafter, the source and drain regions of the PMOS are formed, and the second heavily doped region 18p. Wherein a photoresist layer is first formed on the surface of the semiconductor substrate 10, and then a portion of the photoresist layer is removed by a photolithography technique to form an opening region in the regions of the source and drain regions and the first heavily doped region 18n of the NMOS to be formed. Then, ion implantation is performed using the photoresist layer as a mask and p-type boron (B) as a dopant. Wherein, for example, the ion implantation energy is 13keV and 2×10 ¹⁵ /cm ² Is injected with boron fluoride (BF ₂ ) Ions. The ion implantation density, implantation depth, and the like of the dopant may be appropriately set according to the size and characteristics of the semiconductor device 100. And after the ion implantation process is finished, removing the photoresist layer.

After that, dopants within the semiconductor substrate 10 are activated by spike annealing (heating) at high temperatures. Spike annealing is performed at a temperature of about 1000 ℃.

Fig. 12 is a schematic cross-sectional view of a semiconductor substrate after an interlayer dielectric layer and a contact electrode are formed thereon in accordance with an embodiment of the present invention. As shown in fig. 12, subsequently, an interlayer dielectric layer 30 is formed to cover the surface of the semiconductor device 100. In which silicon oxide (SiO) covering the surface of the semiconductor device 100 is formed by a process such as plasma CVD ₂ ) And a silicon nitride (SiN) dielectric layer.

Subsequently, the first contact electrode 24n, the second contact electrode 24p, the NMOS source-drain contact electrode 32n, and the PMOS source-drain contact electrode 32p are formed. Wherein contact holes are formed in the interlayer dielectric layer 30 using photolithography techniques. The contact holes are formed as openings at regions where the first contact electrode 24n, the second contact electrode 24p, the NMOS source drain contact electrode 32n, and the PMOS source drain contact electrode 32p are to be provided, respectively. Thereafter, a filled titanium (Ti)/titanium nitride (TiN)/tungsten (W) metal stack structure is deposited within the contact holes formed in the interlayer dielectric layer 30. Thereafter, the excess metal is removed by Chemical Mechanical Polishing (CMP), thereby completing the fabrication of the semiconductor device 104.

Semiconductor device 100 and semiconductor device 102 may be formed in a similar manner as semiconductor device 104.

The foregoing description is only illustrative of the preferred embodiments of the present invention, and is not intended to limit the scope of the claims, and any person skilled in the art may make any possible variations and modifications to the technical solution of the present invention using the method and technical content disclosed above without departing from the spirit and scope of the invention, so any simple modification, equivalent variation and modification made to the above embodiments according to the technical matter of the present invention fall within the scope of the technical solution of the present invention.

Claims

1. A semiconductor device comprising an NMOS transistor and a PMOS transistor formed in a surface region of a semiconductor substrate, the semiconductor substrate being a p-type doped substrate; and, the semiconductor device further includes:

An n-type deep well region formed within the semiconductor substrate, the p-type well region formed within the n-type deep well region, the n-type well region formed within the p-type well region;

2. The semiconductor device of claim 1, wherein an orthographic projected area of the p-type doped region at a surface of the semiconductor substrate is greater than an orthographic projected area of the n-type doped region at the surface of the semiconductor substrate.

3. The semiconductor device of claim 1, wherein a dopant concentration of the p-type doped region is greater than a dopant concentration of the n-type doped region.

4. The semiconductor device according to claim 1, wherein a dopant concentration in the n-type doped region and the p-type doped region is 1 x 10 or more ¹⁹ /cm ³ And less than or equal to 1X 10 ²¹ /cm ³ 。

5. The semiconductor device according to claim 1, further comprising:

And the first contact electrode is connected with the first grid electrode and the n-type doped region.

6. The semiconductor device according to claim 1, further comprising:

and the second contact electrode is connected with the second grid electrode and the p-type doped region.

7. The semiconductor device of claim 1, wherein the first gate extends to the n-doped region directly connected thereto; and/or the second gate extends to the p-type doped region to be directly connected with the p-type doped region.

8. The semiconductor device of claim 1, wherein source and drain regions of the NMOS transistor are formed within the p-type well region; and/or, the source region and the drain region of the PMOS transistor are formed in the n-type well region.