JP3042804B2 - Element isolation method and semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device isolation method, and more particularly, to a reduction in the device isolation region.

[0002]

2. Description of the Related Art In manufacturing a semiconductor device, when a plurality of elements are formed on a semiconductor substrate, element isolation is performed in an initial step so that each element can be controlled independently. On the surface of the substrate on which the element isolation has been performed, the area where the element is to be formed is surrounded by the element isolation area. The LOCOS (Local Oxidation of Silicon) method is widely and well known as an element isolation region forming method. Hereinafter, an element isolation method using the LOCOS method will be described.

FIGS. 4A to 4C and FIG. 5 are cross-sectional views of a semiconductor substrate for illustrating the element isolation process. As shown in FIG. 4A, the prepared P-type silicon wafer 1 is
Thermally oxidized at about 1000 ° C. to form a silicon oxide film 23 of about 0.1 μm
Is formed, and then a silicon nitride film (Si ₃
N ₄ ) 25 is formed to a thickness of about 0.1 μm.

[0006] Next, as shown in FIG. 4B, a resist pattern 27 is formed on the upper surface of the silicon nitride film 25. This resist pattern 27 is for determining the position of the region where the element is to be formed. The silicon nitride film 25 is etched using the formed resist pattern 27 as a mask. Further, using the resist pattern 27 as a mask, boron (B
+). Here, boron is implanted to ensure element isolation by element isolation regions formed in the following steps. Here, in order to form the resist pattern 27, a technique called lithography using a photographic technique is used. Hereinafter, a pattern forming method using lithography will be described with reference to FIG.

As shown in FIG. 6A, a photosensitive material 37 called a photoresist is applied to the entire surface of a material 35 to be processed formed on the upper surface of the substrate. Next, as shown in FIG. 6B, on the upper surface of the photoresist 37, a material 35 is formed.
After overlapping the glass mask 41 on which the light-shielding pattern 39 in which the portion to be removed is removed is drawn, baking is performed by irradiation with ultraviolet rays. Thus, an exposed portion 43 and a non-exposed portion 45 are formed on the material 35.

When the wafer thus exposed is applied to a developing solution, only the resist in the exposed portion 43 dissolves as shown in FIG. 6C, leaving only the surface of the portion of the material 35 to be removed while leaving the unexposed portion 45. Will be exposed.

Returning to FIG. 4, the resist pattern 27 is changed to O ₂
After removal by plasma treatment, the wafer
By oxidizing for about 6 to 7 hours in a water vapor (H ₂ 0) atmosphere at 00 ° C., a portion of the upper surface of the substrate where the silicon oxide film 23 is exposed grows into a silicon oxide film 29 having a thickness of about 1 μm. The silicon nitride film 25 is made of H ₂ O
The silicon oxide film 23 in the portion covered with the silicon nitride film 25 hardly grows, and becomes a silicon oxide film 21 because it becomes a barrier against the diffusion of the silicon nitride film 25. However, since this oxidative growth proceeds in each direction in the silicon substrate, the silicon oxide film 29 grows so as to penetrate the substrate portion covered with the silicon nitride film 25. At this time, FIG.
Boron ions implanted in the step B are located below the silicon oxide layer 29 and form the P ^{− type} stop layer 31 (see FIG. 4C).

Finally, the remaining silicon nitride film 25 and silicon oxide film 21 are sequentially removed (see FIG. 5).

As described above, by forming the device isolation region by the silicon oxide film 29, the upper surface of the substrate can be divided into a plurality of device formation regions 33 which can be controlled completely independently.

[0010]

SUMMARY OF THE INVENTION However, LOC
The conventional device isolation method using the OS method has the following problems.

In response to the demand for integration with the development of the semiconductor industry, integration of various element formation regions in a semiconductor device has been attempted. Under these circumstances, the area ratio between the element formation region and the element isolation region on the upper surface of the substrate of the semiconductor device has been reduced to about one to one with the reduction in the element formation region. Therefore, when considering further integration of a semiconductor device, it has become important to consider not only the reduction of the element formation region but also the reduction of the element isolation region.

However, in the conventional device isolation using the LOCOS method, there is a limit in reducing the device isolation region for the following reasons.

The width of the element isolation region formed on the upper surface of the substrate is determined by the width d of the resist pattern 27 (see FIG. 4B). However, there is a limit in reducing the width d due to the problem of accuracy, and it is impossible to reduce the width d to 0.5 μm or less.

An object of the present invention is to solve the above-mentioned problems and to provide an element isolation method capable of reducing the element isolation region.

[0015]

According to a first aspect of the present invention, there is provided an element isolation method for isolating a semiconductor substrate into a plurality of element formation regions, wherein the upper surface of the semiconductor substrate has oxidation resistance. After depositing the film, a first film formation forming step of forming a first film formed by selectively removing the film, and the upper surface of the formed first film and the upper surface of the substrate An insulating film forming step of depositing an insulating film on the exposed surface, and a sidewall forming step of removing the insulating film while leaving the insulating film located on the side surface of the formed first film as an element isolation side wall, A second film forming step of depositing a second film having oxidation resistance on the upper surface of the substrate exposed in the side wall forming step while exposing a part of the element isolation side wall; and a first film forming step Film forming process and second film forming process Forming an oxide layer by removing the element isolation side wall while leaving the second film formed, and exposing the upper surface of the substrate exposed in the side wall removal step, and exposing the upper surface of the substrate. And an oxide layer forming step of separating into a plurality of element formation planned regions.

An element isolation method according to a second aspect of the present invention is an element isolation method for isolating a semiconductor substrate into a plurality of element formation planned regions, wherein an oxide film forming step of forming an oxide film on an upper surface of the semiconductor substrate; A first film forming step of forming a first film formed by selectively removing the film after depositing a film having oxidation resistance on the upper surface of the oxide film; and An insulating film forming step of depositing an insulating film on the upper surface of the first film and the exposed surface of the oxide film, and leaving the insulating film located on the side surface of the formed first film as an element isolation side wall; A sidewall forming step of removing the insulating film;
A second film forming step of depositing a second film having oxidation resistance on the upper surface of the oxide film exposed in the side wall forming step while exposing a part of the element isolation side wall; Removing the element isolation side wall while leaving the first film formed by the step and the second film formed by the second film formation step, and exposing the upper surface of the substrate; Forming an oxide layer by oxidizing the upper surface of the substrate exposed by the method, and separating the oxide layer into a plurality of element formation planned regions.

According to a third aspect of the present invention, in the element isolation method, the oxidation-resistant film which is non-selective to the etching solution having a selectivity for the insulating film is used, and the film is removed in the side wall forming step. Anisotropic etching is used as a method, and as a method of forming an oxidation-resistant film formed in the second film formation step, an oxidation-resistant film is once deposited on the entire surface of the substrate and then etched to form a sidewall for element isolation. The method is characterized in that a part of the insulating film is exposed and etching with a selective etching solution is used for the insulating film as a removing method in the side wall removing step. 5. The semiconductor device according to claim 4, wherein a first film formed by depositing a film having oxidation resistance on the upper surface of the semiconductor substrate is formed by selectively removing the film, and forming the first film. Depositing an insulating film on the upper surface of the formed first film and the exposed surface of the upper surface of the substrate, and leaving the insulating film located on the side surface of the formed first film as an element isolation side wall; Is removed, and a second film having oxidation resistance is deposited on the exposed upper surface of the substrate while exposing a part of the device isolation side wall, and the first film and the second film are left, and the device is removed. The separation sidewall is removed to expose the upper surface of the substrate, and the exposed upper surface of the substrate is oxidized to form an oxide layer, thereby separating the substrate into a plurality of element formation regions.

[0018]

In the device isolation method and the semiconductor device according to claim 1 and claim 4, after forming the first film having oxidation resistance, the upper surface of the first film and the semiconductor film are formed by the insulating film forming step. An insulating film is temporarily deposited on the exposed surface of the upper surface of the substrate, and the insulating film is selectively removed by the next side wall forming step, and the insulating film in a portion located on the side surface of the first film is used as an element isolation side wall. I try to leave. The width of the element isolation side wall can be adjusted by the thickness of the deposited insulating film.

Next, after forming a second film on the upper surface of the substrate exposed in the side wall forming step while exposing a part of the element isolation side wall, the element isolation side wall is removed. Thus, an opening having the same width as the element isolation side wall can be formed on the upper surface of the substrate, and the upper surface of the substrate other than the opening can be covered with the first and second oxidation-resistant films.

Next, by oxidizing in the oxide layer forming step, an element isolation region corresponding to the width of the opening can be formed on the upper surface of the substrate.

According to the second aspect of the present invention, the oxide film formed in the oxide film forming step protects a substrate region during the element separating step.

After the first film having oxidation resistance is formed, an insulating film is temporarily deposited on the upper surface of the first film and the exposed surface of the oxide film by the insulating film forming step. The insulating film is selectively removed by the side wall forming step, and a portion of the insulating film located on the side surface of the first film is left as a side wall for element isolation. The width of the element isolation side wall can be adjusted by the thickness of the deposited insulating film.

Next, after forming a second film on the oxide film exposed in the side wall forming step while exposing a part of the element isolation side wall, the element isolation side wall is removed. Thus, an opening having the same width as the element isolation side wall can be formed on the upper surface of the substrate, and the upper surface of the substrate other than the opening can be covered with the first and second oxidation-resistant films.

Next, by oxidizing in the oxide layer forming step, an element isolation region corresponding to the width of the opening can be formed on the upper surface of the substrate.

According to a third aspect of the present invention, in the device isolation method, the side wall forming step and the side wall removal are performed by using a film having oxidation resistance which is non-selective to an etching solution having selectivity for the insulating film. The manufacturing process can be facilitated by using etching, which is a general method, as a method of removing the process.

In the second film formation step, the manufacturing process can be simplified by using etching, which is a general method, to expose a part of the element isolation side wall.

Further, by using anisotropic etching as a removing method in the side wall forming step, the insulating film can be uniformly removed in the vertical direction. Therefore, the width of the element isolation side wall can be adjusted by the thickness of the formed insulating film.

[0028]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of element isolation using the element isolation method according to the present invention will be described. 1A to 1C, 2A to 2C, and 3A to 3C are schematic cross-sectional views showing the manufacturing process of the above-described embodiment.

As shown in FIG. 1A, a silicon wafer 1 prepared as a semiconductor substrate is thermally oxidized at 900 to 1000 ° C. to form a silicon oxide film 3 of about 0.1 μm. Next, as shown in FIG. 1B, a low-pressure silicon nitride (SiN) film, which is a film having oxidation resistance by a low-pressure CVD (LP-CVD) method, is formed on the entire upper surface of the silicon oxide film 3 by 300.
After depositing nm, the silicon nitride film is etched by using the resist pattern 7 as a mask to form a low-pressure silicon nitride film 9 to be the first film. next,
After removing the resist 7 as shown in FIG.
A silicon oxide film 11 as an insulating film is deposited to a thickness of about 300 nm by a method. Next, as shown in FIG. 2A, the silicon oxide film 11 is etched back by reactive ion etching (RIE) which is anisotropic, and the width r of the silicon nitride film 9 is about 0.1 μm on the side surface. Element isolation side wall 1
Form 3 The width r of the isolation sidewall 13 is determined by the thickness of the silicon oxide film 11, and is proportional to the thickness. Further, the thickness of the silicon oxide film 11 can be accurately controlled. Therefore, the width r of the isolation sidewall 13 can be accurately controlled.

Next, as shown in FIG.
A silicon nitride (SiN) film 15 which is a film having oxidation resistance is deposited to a thickness of 250 nm by an (LP-CVD) method.
Next, as shown in FIG. 2C, etching is performed with phosphoric acid at a high temperature (about 150 ° C.) to thereby form the side wall 1 for element isolation.
The upper part 14 of 3 is exposed. As described above, the silicon oxide film 15 is once deposited on the entire surface of the substrate and then etched to expose a part of the side wall 13 for element isolation, thereby forming a second silicon nitride film on the exposed surface of the silicon oxide film 3. The film 16 can be formed.

Next, as shown in FIG. 3A, the element isolation side wall 13 which is a silicon oxide film is removed by etching using an HF solution. In this manner, as can be seen from FIG. 3A, the silicon nitride films 9 and 16 having the openings 5 having a smaller width than the conventional one can be formed on the upper surface of the substrate having the oxide film formed on the surface. After that, B (boron) as a stopper may be implanted or diffused so that the element isolation is not insufficient.

Next, as shown in FIG. 3B, thermal oxidation (950
(100 ° C. for 100 minutes) to grow the silicon oxide layer 17 as an element isolation region. Since the silicon nitride films 9 and 16 have oxidation resistance, an element isolation region is formed in the opening 5.

Finally, as shown in FIG. 3C, the CDE (Ch
silicon nitride films 9, 16 by emical dry etching) method.
Is removed, and the silicon oxide film 3 is further removed.

The width W of the element isolation region formed in this manner is determined by the width r of the element isolation side wall 13.
The width r can be accurately controlled by the thickness of the silicon oxide film 11. Therefore, the size of the element isolation region can be reduced.

In the above embodiment, the silicon oxide film 3 is provided first. Thereby, the silicon substrate region can be protected during the element isolation process.

In the above embodiment, a silicon nitride (SiN) film is used as a film having oxidation resistance.
Any other film may be used as long as the film has oxidation resistance.

In the above embodiment, a silicon oxide film is used as the insulating film. However, any other film may be used as long as the film has oxidation resistance and can be selectively etched.

In the above embodiment, the method of using the silicon nitride films 9 and 16 which are non-selective with respect to the etching solution having the selectivity for the insulating film 11 and removing the element-forming side walls 13 is employed. The etching using an etching solution having selectivity for the insulating film 11 is used. However, another method may be used as long as the element isolation side wall 13 can be removed while leaving the first film 9 and the second film 16.

[0039]

According to the element isolation method and the semiconductor device according to the first and fourth aspects, the element isolation side wall whose width can be easily adjusted is formed on the upper surface of the substrate, and the element isolation side wall other than the element isolation side wall is formed. The upper surface of the substrate can be covered with the first film and the second film having oxidation resistance. Therefore, an element isolation region having a width corresponding to the width of the opening can be formed on the upper surface of the substrate by the subsequent oxidation.

Therefore, it is possible to form a device isolation region which is smaller than the conventional device.

In the device isolation method according to the second aspect, the substrate region is protected during the device isolation process by the oxide film formed in the oxide film forming process. In addition, the device isolation side wall whose width can be easily adjusted is formed on the oxide film upper surface, and the upper surface of the oxide film other than the device isolation side wall is formed by oxidation-resistant first film formation and second film formation. Can be covered with a membrane. Therefore, an element isolation region having a width corresponding to the width of the opening can be formed on the upper surface of the substrate by the subsequent oxidation.

Accordingly, it is possible to form a device isolation region which is smaller than the conventional device.

According to a third aspect of the present invention, in the element isolation method, the side wall forming step and the side wall forming step are performed by using the oxidation-resistant film which is non-selective to an etching solution having a selectivity for the insulating film. Etching, which is a general method, is used as a removing method in the side wall removing step. Also, in the second film formation step, etching, which is a general method, is used to expose a part of the element isolation side wall. Therefore, the manufacturing process can be facilitated.

Accordingly, it is possible to easily implement an element isolation method capable of reducing the element isolation region.

Further, by using anisotropic etching as a removing method in the side wall forming step, it is possible to adjust the width of the element isolation side wall according to the thickness of the formed insulating film.

Therefore, an opening having a smaller width than the conventional one can be easily formed in the oxidation-resistant film.

[Brief description of the drawings]

FIG. 1 is a manufacturing process diagram for illustrating a device isolation method according to an embodiment of the present invention.

FIG. 2 is a manufacturing process diagram showing a device isolation method according to an embodiment of the present invention.

FIG. 3 is a manufacturing process diagram for illustrating an element isolation method according to an embodiment of the present invention.

FIG. 4 is a manufacturing process diagram showing a conventional element isolation method.

FIG. 5 is a manufacturing process diagram showing a conventional element isolation method.

FIG. 6 is a diagram for explaining a lithography technique.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... P-type silicon wafer 3 ... Silicon oxide film 9 ... Silicon nitride film 11 ... Silicon oxide film 13 ... Side wall for element isolation 16 ... Silicon nitride film 17 ... Silicon oxide Film 19: Device formation area

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/76 H01L 21/316

Claims (4)

(57) [Claims] 1. An element isolation method for isolating a semiconductor substrate into a plurality of element formation planned regions, wherein an oxidation-resistant film is deposited on an upper surface of the semiconductor substrate, and the film is selectively removed. A first film forming step of forming a first film formed by performing, an insulating film forming step of depositing an insulating film on an exposed surface of the upper surface of the formed first film and the upper surface of the substrate, A side wall forming step of removing the insulating film while leaving the insulating film located on a side surface of the formed first film formation as a side wall for element isolation; and forming the element on the upper surface of the substrate exposed by the side wall forming step. A second film formation step of depositing a second film having oxidation resistance while exposing a part of the separation side wall; and a first film formation and a second film formation formed by the first film formation step Separation of elements while leaving the second film formed by the process Removing a sidewall and exposing a top surface of the substrate; and an oxide layer forming step of oxidizing the top surface of the substrate exposed in the sidewall removal process to form an oxide layer and separating it into a plurality of element formation planned regions. A device isolation method, comprising: 2. An element isolation method for isolating a semiconductor substrate into a plurality of element formation regions, comprising: an oxide film forming step of forming an oxide film on an upper surface of the semiconductor substrate; After depositing a film having a first film forming step of forming a first film formed by selectively removing the film, and forming an upper surface of the first film formed and An insulating film forming step of depositing an insulating film on an exposed surface of the oxide film; and a side wall forming step of removing the insulating film while leaving the insulating film located on a side surface of the formed first film as an element isolation side wall. A second film forming step of depositing a second film having oxidation resistance on the upper surface of the oxide film exposed by the side wall forming step while exposing a part of the element isolation side wall; The first film and the second film formed by the film forming process Removing a sidewall for element isolation while leaving the second film formed in the forming step, exposing a top surface of the substrate; and oxidizing the top surface of the substrate exposed in the sidewall removal step to form an oxide layer. An oxide layer forming step of forming an oxide layer to be separated into a plurality of element formation planned regions. 3. The device isolation method according to claim 1, wherein the oxidation-resistant film which is non-selective with respect to an etching solution having a selectivity for the insulating film is used. Anisotropic etching is used as a removing method in the side wall forming step. As an oxidation resistant film forming method formed in the second film forming step, etching is performed after temporarily depositing an oxidation resistant film on the entire surface of the substrate. Exposing a part of the side wall for element isolation by using an etching solution having a selectivity to the insulating film as a removing method in the side wall removing step. 4. A first film formed by depositing a film having oxidation resistance on the upper surface of the semiconductor substrate, and selectively removing the film to form a first film formed by the first method. Depositing an insulating film on the upper surface of the film and the exposed surface of the upper surface of the substrate, removing the insulating film while leaving the insulating film located on the side surface of the formed first film as an element isolation side wall, On the exposed upper surface of the substrate, a second film having oxidation resistance is deposited while exposing a part of the device isolation sidewall, and the device isolation sidewall is left except for the first film and the second film. A semiconductor device manufactured by removing an upper surface of the substrate, exposing the upper surface of the substrate, oxidizing the exposed upper surface of the substrate to form an oxide layer, and separating the oxidized layer into a plurality of element formation planned regions.