JP2892348B1 - Semiconductor unit and semiconductor element mounting method - Google Patents
Semiconductor unit and semiconductor element mounting methodInfo
- Publication number
- JP2892348B1 JP2892348B1 JP10155552A JP15555298A JP2892348B1 JP 2892348 B1 JP2892348 B1 JP 2892348B1 JP 10155552 A JP10155552 A JP 10155552A JP 15555298 A JP15555298 A JP 15555298A JP 2892348 B1 JP2892348 B1 JP 2892348B1
- Authority
- JP
- Japan
- Prior art keywords
- sealing resin
- semiconductor element
- circuit board
- electrode
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Abstract
【要約】
【課題】 半導体素子をフェースダウンで回路基板に実
装した半導体ユニットにおいて、半導体素子と回路基板
の接続の信頼性を向上させる。
【解決手段】 半導体素子1をフェースダウンで回路基
板4に導電性接着剤3を用いて実装する半導体素子1の
実装体において、ポーラスな導電性接着剤の接合層6の
ポーラスな空間13に液状の封止樹脂7を含浸させるこ
とにより、ボイドなく完全充填された封止樹脂の充填層
10を得る。Abstract: PROBLEM TO BE SOLVED: To improve reliability of connection between a semiconductor element and a circuit board in a semiconductor unit in which a semiconductor element is mounted face down on a circuit board. SOLUTION: In a mounting body of the semiconductor element 1 in which the semiconductor element 1 is mounted face down on a circuit board 4 using a conductive adhesive 3, a liquid is filled in a porous space 13 of a bonding layer 6 of the porous conductive adhesive. Is impregnated with the sealing resin 7 to obtain a sealing resin filling layer 10 completely filled without voids.
Description
【0001】[0001]
【発明の属する技術分野】本発明は、半導体素子をフェ
ースダウン状態で回路基板上に実装してなる半導体ユニ
ットおよびそれに適する半導体素子の実装方法に関する
ものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor unit in which a semiconductor element is mounted on a circuit board in a face-down state, and a method for mounting a semiconductor element suitable for the semiconductor unit.
【0002】[0002]
【従来の技術】従来、半導体素子を回路基板上へ実装す
る際には、半田付けが広く利用されていた。しかし、近
年、半導体素子のパッケージの小型化及び接続端子数の
増加により接続端子間隔が狭くなり、従来の半田付け技
術で対処することが次第に困難になってきた。2. Description of the Related Art Conventionally, when a semiconductor element is mounted on a circuit board, soldering has been widely used. However, in recent years, the space between the connection terminals has been narrowed due to the miniaturization of the package of the semiconductor element and the increase in the number of connection terminals, and it has become increasingly difficult to deal with the conventional soldering technology.
【0003】そこで、裸の半導体素子を回路基板上に直
付けし、実装面積の小型化と効率的使用を図ろうとする
方法が考えだされた。例えば、半導体素子を回路基板に
接続する際、あらかじめ半導体素子の端子電極上に密着
金属や拡散防止金属の蒸着膜を形成し、さらにその上に
メッキにより形成した半田の突起電極を構成する。次
に、半導体素子をフェースダウンにし、高温に加熱して
半田を回路基板の接続電極に融着させる。この実装方法
は、接続後の機械的強度が強く、接続が一括にできるこ
となどから有効な方法であるとされている(例えば、工
業調査会、1980年1月15日発行、日本マイクロエ
レクトロニクス協会編、『IC化実装技術』)。[0003] Therefore, a method has been devised in which a bare semiconductor element is directly mounted on a circuit board to reduce the mounting area and to efficiently use it. For example, when connecting a semiconductor element to a circuit board, a vapor deposition film of an adhesion metal or a diffusion preventing metal is formed in advance on a terminal electrode of the semiconductor element, and a solder bump electrode formed by plating is formed thereon. Next, the semiconductor element is placed face down and heated to a high temperature to fuse the solder to the connection electrodes of the circuit board. This mounting method is considered to be an effective method because the mechanical strength after connection is high and the connection can be made at once (for example, the Industrial Research Council, published on January 15, 1980, edited by the Japan Microelectronics Association) , “IC mounting technology”).
【0004】さらに、米国特許5121190号や特開
平6−61303号公報等に示されるように、半田によ
る接合部の安定性を確保するために、封入剤を用いた実
装方法および半導体ユニットが提案されている。以下、
図5を参照しながら、この従来の半導体素子の実装方法
及びそれにより実装された半導体ユニットについて説明
する。図5は、フェースダウンで実装された従来の半導
体ユニットの要部断面図である。Further, as shown in US Pat. No. 5,121,190 and Japanese Patent Application Laid-Open No. 6-61303, a mounting method using an encapsulant and a semiconductor unit have been proposed in order to secure the stability of a joint portion by soldering. ing. Less than,
With reference to FIG. 5, a description will be given of this conventional semiconductor element mounting method and a semiconductor unit mounted thereby. FIG. 5 is a sectional view of a main part of a conventional semiconductor unit mounted face down.
【0005】図5に示すように、フェースダウンで実装
された従来の半導体ユニットは、半導体素子1と、半導
体素子1の端子電極2と、回路基板4と、回路基板4の
表面に形成された接続電極5と、接続電極5と端子電極
2を接合した半田接合部15と、半導体素子1を封止し
た封止樹脂16等で構成されている。As shown in FIG. 5, a conventional semiconductor unit mounted face down includes a semiconductor element 1, a terminal electrode 2 of the semiconductor element 1, a circuit board 4, and a surface of the circuit board 4. The semiconductor device 1 includes a connection electrode 5, a solder joint 15 that joins the connection electrode 5 and the terminal electrode 2, and a sealing resin 16 that seals the semiconductor element 1.
【0006】次に、図6を参照しながら、上記従来の半
導体ユニットを形成するための半導体素子の実装方法を
説明する。まず、半田の突起電極17を有する半導体素
子1をフェースダウン状態で回路基板4に搭載し、半田
の突起電極17を接続端子5の所定の位置に位置合わせ
を行う(図6(a))。次に、200〜300℃の高温
に加熱して半田を溶融し、半田の突起電極17と接続端
子5を接合し、半導体素子1を半田接合部15により回
路基板4に固定する(図6(b))。その後、半導体素
子1と回路基板4との間隙に液状の封止樹脂7を流し込
み(図6(c))、液状の封止樹脂を充填し、120℃
程度で加熱硬化することにより、封止樹脂を固化させる
(図6(d))。このようにして、半導体素子1の回路
基板4への実装が完了する。Next, a method for mounting a semiconductor element for forming the above-mentioned conventional semiconductor unit will be described with reference to FIG. First, the semiconductor element 1 having the solder projecting electrodes 17 is mounted on the circuit board 4 in a face-down state, and the solder projecting electrodes 17 are positioned at predetermined positions of the connection terminals 5 (FIG. 6A). Next, the solder is melted by heating to a high temperature of 200 to 300 ° C., the protruding electrode 17 of the solder is joined to the connection terminal 5, and the semiconductor element 1 is fixed to the circuit board 4 by the solder joint 15 (FIG. 6 ( b)). Thereafter, a liquid sealing resin 7 is poured into a gap between the semiconductor element 1 and the circuit board 4 (FIG. 6C), and the liquid sealing resin is filled.
The sealing resin is solidified by being heat-cured to a degree (FIG. 6D). Thus, the mounting of the semiconductor element 1 on the circuit board 4 is completed.
【0007】[0007]
【発明が解決しようとする課題】しかしながら、上記従
来の半導体ユニットおよび半導体素子の実装方法におい
ては、次のような問題がある。However, the conventional methods of mounting a semiconductor unit and a semiconductor element have the following problems.
【0008】第1に、半田接合部15は金属塊で半導体
素子1と回路基板4との間隙に液状の封止樹脂7を流し
込む際に、半田接合部15の後ろ(液状の封止樹脂7の
進行方向に対して)に液状の封止樹脂が廻り込まない空
隙18ができたり、その液状の封止樹脂が廻り込まない
空隙18が分断されて液状の封止樹脂中の気泡19とな
ったりする。そのため、半導体素子1と回路基板4との
間隙に充填した液状の封止樹脂はボイドを含んだ液状の
封止樹脂20となり、これを熱硬化する際に、ボイドの
熱膨張により生じる熱応力が半田接合部15に加わり、
大きな内部歪が生ずる。First, when the liquid sealing resin 7 is poured into the gap between the semiconductor element 1 and the circuit board 4 as a metal lump, the solder bonding portion 15 is placed behind the solder bonding portion 15 (the liquid sealing resin 7). The gap 18 in which the liquid sealing resin does not go around is formed, or the gap 18 in which the liquid sealing resin does not go around is divided into bubbles 19 in the liquid sealing resin. Or Therefore, the liquid sealing resin filled in the gap between the semiconductor element 1 and the circuit board 4 becomes the liquid sealing resin 20 containing voids, and when this is thermally cured, thermal stress caused by thermal expansion of the voids is reduced. Joins the solder joint 15,
Large internal distortion occurs.
【0009】第2に、半導体ユニットを使用する際に、
半導体素子1と回路基板4の間隙にはボイドを残したま
ま硬化した封止樹脂の充填層21が存在しており、この
封止樹脂の充填層中のボイドの熱膨張により生ずる熱応
力が半田接合部15に加わり、特に半導体ユニットを放
置後に高温領域(例えば、半田付けなど作業時)で使用
する際には、半導体素子1と回路基板4との間隙のボイ
ドを残したまま硬化した封止樹脂の充填層21のボイド
中の湿気が水蒸気となって熱膨張することにより生じる
新たな熱応力が半田接合部15に加わる。Second, when using a semiconductor unit,
In the gap between the semiconductor element 1 and the circuit board 4, there is a sealing resin filling layer 21 which is cured while leaving voids, and the thermal stress generated by the thermal expansion of the voids in the sealing resin filling layer causes soldering. When the semiconductor unit is used in a high-temperature region (for example, at the time of work such as soldering) after leaving the semiconductor unit unattended, it is hardened while leaving a void in the gap between the semiconductor element 1 and the circuit board 4. A new thermal stress caused by the moisture in the voids of the resin filling layer 21 becoming water vapor and thermally expanding is applied to the solder joint 15.
【0010】上記問題により、従来の半導体素子の実装
方法及びそれにより実装された半導体ユニットは、半導
体素子1と回路基板4との接続の信頼性が低く、あまり
実用的とはいえなかった。とくに、近年の半導体素子の
多端子化に対応する半導体素子の端子電極の二次元的な
エリア配置化(従来は、半導体装置の四辺での一次元的
な配置であった)の場合には、半導体素子1と回路基板
4との接続点が半導体装置1の内部にまで多く存在する
こととなり、上記のような問題点はますます深刻化す
る。Due to the above problem, the conventional semiconductor element mounting method and the semiconductor unit mounted by the method have low reliability of connection between the semiconductor element 1 and the circuit board 4 and are not very practical. In particular, in the case of a two-dimensional area arrangement of terminal electrodes of a semiconductor element corresponding to the recent increase in the number of terminals of a semiconductor element (conventionally, a one-dimensional arrangement of four sides of a semiconductor device) Many connection points between the semiconductor element 1 and the circuit board 4 exist inside the semiconductor device 1, and the above-mentioned problems become more serious.
【0011】本発明は、上記従来例の問題点を解決する
ためになされたものであり、半導体素子と回路基板との
接続の信頼性を向上させる半導体ユニットおよび半導体
素子の実装方法を提供することを目的とするものであ
る。SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the prior art, and provides a semiconductor unit and a method of mounting a semiconductor element which improve the reliability of connection between a semiconductor element and a circuit board. It is intended for.
【0012】[0012]
【課題を解決するための手段】上記目的を達成するた
め、第1の本発明(請求項1に記載の本発明に対応)
は、回路基板と、前記回路基板にフェースダウン状態で
実装された半導体素子と、前記半導体素子の端子電極と
前記回路基板の接続電極とを電気的及び機械的に接続す
る接合層と、前記半導体素子と前記回路基板との間隙に
充填された封止樹脂の充填層とを備え、前記接合層は、
ポーラスな導電性材料部と、前記導電性材料部のポーラ
スな空間に存在する前記封止樹脂の一部とから構成され
ていることを特徴とする半導体ユニットである。To achieve the above object, a first present invention (corresponding to the first aspect of the present invention).
A circuit board, a semiconductor element mounted face-down on the circuit board, a bonding layer for electrically and mechanically connecting a terminal electrode of the semiconductor element and a connection electrode of the circuit board, An element and a filling layer of a sealing resin filled in a gap between the circuit board, the bonding layer,
A semiconductor unit comprising a porous conductive material portion and a part of the sealing resin present in a porous space of the conductive material portion.
【0013】第2の本発明(請求項2に記載の本発明に
対応)は、前記半導体素子が、前記端子電極と前記接合
層との間に突起電極を有することを特徴とする第1の本
発明の半導体ユニットである。A second aspect of the present invention (corresponding to the second aspect of the present invention) is characterized in that the semiconductor element has a protruding electrode between the terminal electrode and the bonding layer. 3 is a semiconductor unit of the present invention.
【0014】第3の本発明(請求項3に記載の本発明に
対応)は、前記接合層の熱膨張係数が、前記充填層の熱
膨張係数と実質的に等しいことを特徴とする第1または
第2の本発明の半導体ユニットである。According to a third aspect of the present invention (corresponding to the third aspect of the present invention), the thermal expansion coefficient of the bonding layer is substantially equal to the thermal expansion coefficient of the filling layer. Or it is the semiconductor unit of the second invention.
【0015】第4の本発明(請求項4に記載の本発明に
対応)は、前記封止樹脂が、少なくとも有機樹脂および
無機フィラーを含むことを特徴とする第1〜第3のいず
れかの本発明の半導体ユニットである。According to a fourth aspect of the present invention (corresponding to the fourth aspect of the present invention), the sealing resin contains at least an organic resin and an inorganic filler. 3 is a semiconductor unit of the present invention.
【0016】第5の本発明(請求項5に記載の本発明に
対応)は、前記無機フィラーが、その大きさが前記ポー
ラスな空間よりも大きいものを含むことを特徴とする第
4の本発明の半導体ユニットである。A fifth aspect of the present invention (corresponding to the fifth aspect of the present invention) is characterized in that the inorganic filler includes one whose size is larger than the porous space. 3 is a semiconductor unit according to the invention.
【0017】第6の本発明(請求項6に記載の本発明に
対応)は、前記ポーラスな空間に存在する前記封止樹脂
の一部が、前記有機樹脂を含み、前記無機フィラーを含
まないことを特徴とする第5の本発明の半導体ユニット
である。According to a sixth aspect of the present invention (corresponding to the sixth aspect of the present invention), a part of the sealing resin present in the porous space contains the organic resin and does not contain the inorganic filler. A fifth aspect of the present invention is the semiconductor unit according to the fifth aspect.
【0018】第7の本発明(請求項7に記載の本発明に
対応)は、前記無機フィラーが、その大きさが前記ポー
ラスな空間よりも小さなものを含むことを特徴とする第
4の本発明の半導体ユニットである。According to a seventh aspect of the present invention (corresponding to the seventh aspect of the present invention), the inorganic filler includes a filler whose size is smaller than that of the porous space. 3 is a semiconductor unit according to the invention.
【0019】第8の本発明(請求項8に記載の本発明に
対応)は、前記ポーラスな空間に存在する前記封止樹脂
の一部が、前記有機樹脂および前記無機フィラーを含む
ことを特徴とする第7の本発明の半導体ユニットであ
る。An eighth aspect of the present invention (corresponding to the eighth aspect of the present invention) is characterized in that a part of the sealing resin present in the porous space contains the organic resin and the inorganic filler. 7 is a semiconductor unit according to a seventh aspect of the present invention.
【0020】第9の本発明(請求項9に記載の本発明に
対応)は、前記ポーラスな導電性材料部の主成分は、導
電性接着剤であることを特徴とする第1〜第8のいずれ
かの本発明の半導体ユニットである。A ninth aspect of the present invention (corresponding to the ninth aspect of the present invention) is characterized in that a main component of the porous conductive material portion is a conductive adhesive. Or the semiconductor unit of the present invention.
【0021】第10の本発明(請求項10に記載の本発
明に対応)は、前記ポーラスな導電性材料部の主成分
が、ポーラスな金属であることを特徴とする第1〜第8
のいずれかの本発明の半導体ユニットである。According to a tenth aspect of the present invention (corresponding to the tenth aspect of the present invention), the main component of the porous conductive material portion is a porous metal.
Or the semiconductor unit of the present invention.
【0022】第11の本発明(請求項11に記載の本発
明に対応)は、半導体素子をフェースダウン状態で回路
基板に実装する半導体素子の実装方法において、前記半
導体素子の端子電極と前記回路基板の接続電極とをポー
ラスな導電性材料を用いて電気的に接続することによっ
て、ポーラスな導電性材料部を形成する電極接続工程
と、前記電極接続工程の後、前記半導体素子と前記回路
基板との間隙に液状の封止樹脂を充填する樹脂充填工程
と、前記樹脂充填工程と同時に、前記液状の封止樹脂を
前記ポーラスな導電性材料部のポーラスな空間に含浸さ
せる含浸工程と、前記含浸工程の後、前記液状の封止樹
脂を硬化させる樹脂硬化工程とを含むことを特徴とする
半導体素子の実装方法である。An eleventh invention (corresponding to the invention according to claim 11) is a method for mounting a semiconductor element on a circuit board in a face-down state, wherein the terminal electrode of the semiconductor element and the circuit An electrode connection step of forming a porous conductive material portion by electrically connecting a connection electrode of the substrate using a porous conductive material; and after the electrode connection step, the semiconductor element and the circuit board A resin filling step of filling the gap with a liquid sealing resin, and simultaneously with the resin filling step, an impregnation step of impregnating the liquid sealing resin into a porous space of the porous conductive material portion, And a resin curing step of curing the liquid sealing resin after the impregnation step.
【0023】第12の本発明(請求項12に記載の本発
明に対応)は、半導体素子をフェースダウン状態で回路
基板に実装する半導体素子の実装方法において、前記半
導体素子の端子電極と前記回路基板の接続電極とを、導
電性接着剤を用いて電気的に接続する電極接続工程と、
前記電極接続工程の後、前記導電性接着剤を硬化して、
ポーラスな導電性材料部を形成する導電性材料部形成工
程と、前記導電性材料部形成工程の後、前記半導体素子
と前記回路基板との間隙に液状の封止樹脂を充填する樹
脂充填工程と、前記樹脂充填工程と同時に、前記液状の
封止樹脂を前記ポーラスな導電性材料部のポーラスな空
間に含浸させる含浸工程と、前記含浸工程の後、前記液
状の封止樹脂を硬化させる樹脂硬化工程とを含むことを
特徴とする半導体素子の実装方法である。A twelfth aspect of the present invention (corresponding to the twelfth aspect of the present invention) is a method of mounting a semiconductor element on a circuit board in a face-down state, wherein the terminal electrode of the semiconductor element and the circuit An electrode connection step of electrically connecting a connection electrode of the substrate with a conductive adhesive,
After the electrode connection step, the conductive adhesive is cured,
A conductive material portion forming step of forming a porous conductive material portion, and a resin filling step of filling a gap between the semiconductor element and the circuit board with a liquid sealing resin after the conductive material portion forming step. An impregnating step of impregnating the porous space of the porous conductive material portion with the liquid sealing resin simultaneously with the resin filling step, and a resin curing step of curing the liquid sealing resin after the impregnation step And a step of mounting the semiconductor element.
【0024】第13の本発明(請求項13に記載の本発
明に対応)は、前記導電性接着剤が、少なくとも溶剤
と、有機樹脂と、導電フィラーを含むことを特徴とする
第12の本発明の半導体素子の実装方法である。According to a thirteenth aspect of the present invention (corresponding to the thirteenth aspect of the present invention), the conductive adhesive comprises at least a solvent, an organic resin, and a conductive filler. 4 is a mounting method of the semiconductor element of the present invention.
【0025】第14の本発明(請求項14に記載の本発
明に対応)は、前記液状の封止樹脂が、硬化後の前記導
電性接着剤に対して溶解性を有しないことを特徴とする
第13の本発明の半導体素子の実装方法である。A fourteenth aspect of the present invention (corresponding to the fourteenth aspect of the present invention) is characterized in that the liquid sealing resin has no solubility in the conductive adhesive after curing. A thirteenth method of mounting a semiconductor device according to the present invention.
【0026】第15の本発明(請求項15に記載の本発
明に対応)は、前記液状の封止樹脂が、少なくとも有機
樹脂および無機フィラーを含むことを特徴とする第11
〜第14のいずれかの本発明の半導体素子の実装方法で
ある。A fifteenth aspect of the present invention (corresponding to the fifteenth aspect of the present invention) is characterized in that the liquid sealing resin contains at least an organic resin and an inorganic filler.
A mounting method of a semiconductor device according to any one of the present invention.
【0027】第16の本発明(請求項16に記載の本発
明に対応)は、前記含浸工程において、前記ポーラスな
空間に、前記無機フィラーが含浸しないように、前記液
状の封止樹脂を含浸させることを特徴とする第15の本
発明の半導体素子の実装方法である。According to a sixteenth aspect of the present invention (corresponding to the sixteenth aspect of the present invention), in the impregnating step, the liquid sealing resin is impregnated so that the porous space is not impregnated with the inorganic filler. A fifteenth aspect of the present invention is a method for mounting a semiconductor device according to the present invention.
【0028】第17の本発明(請求項17に記載の本発
明に対応)は、前記含浸工程において、前記ポーラスな
空間に、前記有機樹脂および前記無機フィラーが含浸す
るように、前記液状の封止樹脂を含浸させることを特徴
とする第15の本発明の半導体素子の実装方法である。According to a seventeenth aspect of the present invention (corresponding to the seventeenth aspect of the present invention), in the impregnation step, the liquid sealing is performed such that the organic resin and the inorganic filler are impregnated in the porous space. A fifteenth aspect of the present invention is a method for mounting a semiconductor element according to the present invention, which comprises impregnating a sealing resin.
【0029】第18の本発明(請求項18に記載の本発
明に対応)は、前記電極接続工程の前に、前記端子電極
上に突起電極を形成する突起電極形成工程を含み、前記
電極接続工程においては、前記端子電極と前記接続電極
とを、前記突起電極を介して、電気的に接続することを
特徴とする第11〜第17のいずれかの本発明の半導体
素子の実装方法である。An eighteenth aspect of the present invention (corresponding to the eighteenth aspect of the present invention) includes, before the electrode connecting step, a projecting electrode forming step of forming a projecting electrode on the terminal electrode. The method according to any one of the eleventh to seventeenth aspects, wherein in the step, the terminal electrode and the connection electrode are electrically connected to each other via the protruding electrode. .
【0030】[0030]
【発明の実施の形態】本発明の半導体ユニットおよびそ
れに適する半導体素子の実装方法は、半導体素子を回路
基板にフェースダウン状態で搭載し、半導体素子の端子
電極と回路基板の接続電極とを導電性材料を用いて接続
し、前記導電性材料にポーラスな空間を形成した状態
で、接合層半導体素子と回路基板との間隙に充填する液
状の封止樹脂を導電性材料のポーラスな空間に含浸さ
せ、この液状の封止樹脂を硬化させる。それにより、半
導体素子と回路基板との間隙に液状の封止樹脂を流し込
む際に、液状の封止樹脂がポーラスな導電性材料を通過
することができるため、導電性材料による接合部の後ろ
(液状の封止樹脂の進行方向に対して)にも液状の封止
樹脂が充填でき、液状の封止樹脂の中に空隙や気泡のな
い充填層が得られる。その結果、液状の封止樹脂を熱硬
化する際に、空隙や気泡のボイドの熱膨張により生じる
熱応力が導電性材料による接合部に加わることを全く無
くすることができ、半導体素子と回路基板の接合を確実
なものとすることができる。また、半導体素子と回路基
板との間隙にはボイドのない封止樹脂の充填層が得られ
るため、半導体ユニットを使用する際にも、ボイドの熱
膨張により生ずる熱応力や高温領域でのボイド中の湿気
が水蒸気となって熱膨張することにより生ずる新たな熱
応力が導電性材料による接合部に加わることを全く無く
することができ、接合の安定性を極めて向上させること
ができる。DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor unit and a method of mounting a semiconductor element suitable for the present invention are mounted on a circuit board in a face-down state, and a terminal electrode of the semiconductor element and a connection electrode of the circuit board are electrically conductive. In a state where a porous space is formed in the conductive material, a liquid sealing resin filling a gap between the bonding layer semiconductor element and the circuit board is impregnated in the porous space of the conductive material. Then, the liquid sealing resin is cured. Accordingly, when the liquid sealing resin is poured into the gap between the semiconductor element and the circuit board, the liquid sealing resin can pass through the porous conductive material. The liquid sealing resin can also be filled (with respect to the direction in which the liquid sealing resin travels), and a filling layer without voids or bubbles can be obtained in the liquid sealing resin. As a result, when the liquid sealing resin is thermally cured, thermal stress generated by thermal expansion of voids and voids of bubbles can be completely eliminated from being applied to the joint made of the conductive material, and the semiconductor element and the circuit board can be eliminated. Can be surely joined. In addition, since a void-free sealing resin filling layer is obtained in the gap between the semiconductor element and the circuit board, even when a semiconductor unit is used, thermal stress caused by thermal expansion of the void and voids in a high-temperature region may be generated. It is possible to completely eliminate the application of new thermal stress caused by the thermal expansion of the moisture as water vapor into the joint made of the conductive material, and to significantly improve the stability of the joint.
【0031】以下に、本発明の実施の形態を図面を参照
して説明する。An embodiment of the present invention will be described below with reference to the drawings.
【0032】(第1の実施の形態)まず、本発明の第1
の実施の形態を図面を参照して説明する。(First Embodiment) First, the first embodiment of the present invention will be described.
An embodiment will be described with reference to the drawings.
【0033】図1は、本発明の第1の実施の形態におけ
る半導体素子の実装方法の工程を示す断面図であり、同
時に図1(e)は、本発明の第1の実施の形態における
半導体ユニットの構成を示す要部断面図である。また、
図2はポーラスな導電性接着剤の接合層を示す要部断面
図であり、図3はポーラスな導電性接着剤の接合層に液
状の封止樹脂が含浸された状態を示す要部断面図であ
る。FIG. 1 is a cross-sectional view showing steps of a method for mounting a semiconductor device according to a first embodiment of the present invention, and FIG. 1 (e) shows a semiconductor device according to the first embodiment of the present invention. FIG. 3 is a sectional view of a main part showing a configuration of a unit. Also,
FIG. 2 is a cross-sectional view of a main part showing a bonding layer of a porous conductive adhesive, and FIG. 3 is a cross-sectional view of a main part showing a state in which a liquid sealing resin is impregnated in the bonding layer of the porous conductive adhesive. It is.
【0034】図1(e)に示すように、本実施の形態に
おける半導体ユニットは、半導体素子1と、半導体素子
1に形成された端子電極2と、回路基板4と、回路基板
4の表面に形成された接続電極5と、端子電極2と接続
電極5とを電気的及び機械的に接続する接合層と、半導
体素子1と回路基板4との隙間に完全充填された封止樹
脂の充填層10等で構成されている。なお、図1(a)
〜(d)中、3は半導体素子1を実装するのに用いる溶
剤型の導電性接着剤、6はポーラスな導電性接着剤の接
合層、7は液状の封止樹脂、8は液状の封止樹脂7が含
浸した導電性接着剤の接合層、9は半導体素子1と回路
基板4との隙間に完全充填された液状の封止樹脂であ
る。As shown in FIG. 1E, the semiconductor unit according to this embodiment includes a semiconductor element 1, a terminal electrode 2 formed on the semiconductor element 1, a circuit board 4, and a surface of the circuit board 4. The formed connection electrode 5, a bonding layer for electrically and mechanically connecting the terminal electrode 2 and the connection electrode 5, and a sealing resin filling layer completely filled in a gap between the semiconductor element 1 and the circuit board 4. 10 or the like. FIG. 1 (a)
In (d), 3 is a solvent-type conductive adhesive used for mounting the semiconductor element 1, 6 is a bonding layer of a porous conductive adhesive, 7 is a liquid sealing resin, and 8 is a liquid sealing resin. The bonding layer 9 of the conductive adhesive impregnated with the sealing resin 7 is a liquid sealing resin completely filled in the gap between the semiconductor element 1 and the circuit board 4.
【0035】次に、本実施の形態における半導体素子の
実装方法について説明する。まず、あらかじめ半導体素
子1の端子電極2に溶剤型の導電性接着剤3を塗布して
おく。溶剤型の導電性接着剤3は、少なくとも溶剤(例
えばBCA)と有機樹脂(例えばフェノキシ樹脂)と導
電フィラー(例えばAg粉)とを含む組成物である。溶
剤型の導電性接着剤3としては、例えば、ナミックス
(株)製の「ユニメックH9806−1」が代表例であ
る。そして、この半導体素子1をフェースダウン(下向
き)にして回路基板4の接続電極5に位置合わせを行
い、回路基板4上に半導体素子1を搭載し、半導体素子
1の端子電極2と回路基板4の接続電極5を導電性接着
剤3によって電気的に接続する(図1(a))。位置合
わせ以降の工程は、本発明の電極接続工程に対応するも
のである。Next, a method of mounting the semiconductor device according to the present embodiment will be described. First, a solvent-type conductive adhesive 3 is applied to the terminal electrodes 2 of the semiconductor element 1 in advance. The solvent-type conductive adhesive 3 is a composition containing at least a solvent (for example, BCA), an organic resin (for example, phenoxy resin), and a conductive filler (for example, Ag powder). A typical example of the solvent-type conductive adhesive 3 is “UNIMEC H9806-1” manufactured by Namics Corporation. Then, the semiconductor element 1 is positioned face down (downward) to be aligned with the connection electrode 5 of the circuit board 4, the semiconductor element 1 is mounted on the circuit board 4, and the terminal electrode 2 of the semiconductor element 1 is connected to the circuit board 4. Are electrically connected by the conductive adhesive 3 (FIG. 1A). The steps after the alignment correspond to the electrode connecting step of the present invention.
【0036】その後、溶剤型の導電性接着剤3を硬化さ
せる(図1(b))。このとき溶剤型の導電性接着剤3
を硬化させることにより含有する溶剤が蒸発し、図2に
示すように、導電フィラー11と有機樹脂12が残り、
ポーラスな空間13を有するポーラスな導電性接着剤の
接合層6が形成される。本工程は、本発明の導電性材料
部形成工程に対応するものである。Thereafter, the solvent-type conductive adhesive 3 is cured (FIG. 1B). At this time, the solvent type conductive adhesive 3
By curing, the solvent contained evaporates, and as shown in FIG. 2, the conductive filler 11 and the organic resin 12 remain,
A bonding layer 6 of a porous conductive adhesive having a porous space 13 is formed. This step corresponds to the conductive material part forming step of the present invention.
【0037】次に、半導体素子1と回路基板4との間隙
に液状の封止樹脂7(例えばビスフェノールF型液状樹
脂とフェノール化合物の硬化剤とシリカフィラーとを含
む組成物)を充填する(図1(c))。液状の封止樹脂
7としては、例えば、ナミックス(株)製の「チップコ
ート8408」が代表例である。このとき、液状の封止
樹脂7はポーラスな導電性接着剤の接合層6のポーラス
な空間13に含浸され、液状の封止樹脂7が含浸した導
電性接着剤の接合層8が得られる。同時に、液状の封止
樹脂7はポーラスな導電性接着剤の接合層6を通過して
流れるため、液状の封止樹脂が含浸した導電性接着剤の
接合層8の後ろ(液状の封止樹脂7の進行方向に対し
て)にも液状の封止樹脂7が充填でき、空隙や気泡のな
い完全充填された液状の封止樹脂9の充填層が得られる
(図1(d))。このとき、導電性接着剤による電気的
接続を保つために、液状の封止樹脂7には導電性接着剤
に対して溶解性を持たないものを用いる。本工程は、本
発明の樹脂充填工程および含浸工程に対応するものであ
る。Next, the gap between the semiconductor element 1 and the circuit board 4 is filled with a liquid sealing resin 7 (for example, a composition containing a bisphenol F type liquid resin, a phenolic compound curing agent, and a silica filler) (FIG. 1). 1 (c)). A typical example of the liquid sealing resin 7 is “Chipcoat 8408” manufactured by Namics Corporation. At this time, the liquid sealing resin 7 is impregnated in the porous space 13 of the bonding layer 6 of the porous conductive adhesive, and the bonding layer 8 of the conductive adhesive impregnated with the liquid sealing resin 7 is obtained. At the same time, since the liquid sealing resin 7 flows through the porous conductive adhesive bonding layer 6, the liquid sealing resin 7 is impregnated with the conductive adhesive bonding layer 8 impregnated with the liquid sealing resin (liquid sealing resin 8). 7 (in the direction of travel of 7), the liquid sealing resin 7 can be filled, and a filling layer of the completely filled liquid sealing resin 9 without voids and bubbles can be obtained (FIG. 1D). At this time, in order to maintain electrical connection by the conductive adhesive, a liquid sealing resin 7 having no solubility in the conductive adhesive is used. This step corresponds to the resin filling step and the impregnation step of the present invention.
【0038】このとき、液状の封止樹脂7に含まれるシ
リカフィラーを、接合層のポーラスな空間13よりも大
きくすると、接合層のポーラスな空間13には液状の封
止樹脂7に含まれる有機樹脂のみが含浸される。この場
合には、導電性接着剤による電気的な接合を全く阻害し
ないといった効果が得られる。At this time, if the silica filler contained in the liquid sealing resin 7 is made larger than the porous space 13 of the bonding layer, the organic resin contained in the liquid sealing resin 7 is filled in the porous space 13 of the bonding layer. Only the resin is impregnated. In this case, an effect is obtained that the electrical bonding by the conductive adhesive is not hindered at all.
【0039】その後、完全充填された液状の封止樹脂9
の硬化を行うことにより、半導体素子1と回路基板4と
の間隙に空隙や気泡のない完全充填された硬化後の封止
樹脂の充填層10が得られると同時に、封止樹脂と一体
化した導電性接着剤の接合層が得られる(図1
(e))。このとき封止樹脂と一体化した導電性接着剤
の接合層においては、図3に示すように、ポーラスな導
電性接着剤のポーラスな空間13に封止樹脂が含浸され
た状態となる。そのため、封止樹脂の充填層10と一体
化した半導体ユニットが得られる。本工程は、本発明の
樹脂硬化工程に対応するものである。Thereafter, the completely filled liquid sealing resin 9
By hardening, a completely filled cured sealing resin filling layer 10 having no voids or bubbles in the gap between the semiconductor element 1 and the circuit board 4 is obtained, and is integrated with the sealing resin. A bonding layer of a conductive adhesive is obtained (FIG. 1).
(E)). At this time, in the bonding layer of the conductive adhesive integrated with the sealing resin, the sealing resin is impregnated into the porous space 13 of the porous conductive adhesive as shown in FIG. Therefore, a semiconductor unit integrated with the sealing resin filling layer 10 is obtained. This step corresponds to the resin curing step of the present invention.
【0040】樹脂充填工程においては、ポーラスな導電
性接着剤の接合層6のポーラスな空間13に含浸した液
状の封止樹脂7が、液状の封止樹脂が含浸した導電性接
着剤の接合層8の後ろ(液状の封止樹脂7の進行方向に
対して)にも流れるために、完全充填された液状の封止
樹脂9が得られる。このため、液状の封止樹脂7の硬化
工程においては、半導体素子1と回路基板4との間隙の
完全充填された液状の封止樹脂9には空隙や気泡のボイ
ドが無いために、硬化工程中に生じるボイドの熱膨張に
よる接合部への熱応力を全く無くすることができ、半導
体素子1と回路基板4の接合を確実なものとすることが
できる。In the resin filling step, the liquid sealing resin 7 impregnated in the porous space 13 of the porous conductive adhesive bonding layer 6 is replaced with the conductive adhesive bonding layer impregnated with the liquid sealing resin. Since it also flows behind (in the direction of travel of the liquid sealing resin 7) 8, a completely filled liquid sealing resin 9 is obtained. Therefore, in the curing step of the liquid sealing resin 7, since the liquid sealing resin 9 completely filled in the gap between the semiconductor element 1 and the circuit board 4 has no voids or voids of air bubbles, the curing step is performed. Thermal stress on the joint due to thermal expansion of voids generated therein can be completely eliminated, and the joining between the semiconductor element 1 and the circuit board 4 can be ensured.
【0041】以上のようにして形成された半導体ユニッ
トにおいて、半導体素子1の端子電極2と回路基板4の
接続電極5との接合層において、ポーラスであった空間
が封止樹脂により充填され、かつ、半導体素子1と回路
基板4との間隙には硬化後の封止樹脂の充填層10が空
隙や気泡のボイドが無く完全充填されている。そのた
め、半導体ユニットを使用する際にも、封止樹脂の充填
層中のボイドの熱膨張により生ずる熱応力が接合層に加
わることもなく、さらに、半導体ユニットを長時間放置
後に半田付け作業などの高温領域で使用する際にも、ボ
イド中に侵入した湿気が水蒸気となって熱膨張すること
により生ずる新たな熱応力が接合層に加わることも全く
無くすることができるため、半導体素子1と回路基板4
の接続の信頼性の高い半導体ユニットが得られる。In the semiconductor unit formed as described above, the porous space in the bonding layer between the terminal electrode 2 of the semiconductor element 1 and the connection electrode 5 of the circuit board 4 is filled with a sealing resin, and The gap between the semiconductor element 1 and the circuit board 4 is completely filled with the cured sealing resin filling layer 10 without any voids or voids. Therefore, even when the semiconductor unit is used, the thermal stress generated by the thermal expansion of the voids in the filling layer of the sealing resin is not applied to the bonding layer. Even when used in a high-temperature region, it is possible to completely eliminate the new thermal stress generated by the moisture that has penetrated into the voids and become a water vapor and thermally expanded, thereby completely eliminating the semiconductor element 1 and the circuit. Substrate 4
A highly reliable semiconductor unit can be obtained.
【0042】このとき、封止樹脂と一体化した導電性接
着剤の接合層と半導体素子1と回路基板4との間隙の封
止樹脂の充填層10の熱膨張係数が同じとなるように封
止樹脂中のシリカフィラーの配合量を調整することが望
ましい。At this time, the sealing is performed such that the bonding layer of the conductive adhesive integrated with the sealing resin and the sealing resin filling layer 10 in the gap between the semiconductor element 1 and the circuit board 4 have the same coefficient of thermal expansion. It is desirable to adjust the compounding amount of the silica filler in the resin.
【0043】(第2の実施の形態)次に、本発明の第2
の実施の形態を図面を参照して説明する。本実施の形態
における半導体ユニットは、その半導体素子が本発明の
突起電極を有することに関する点以外は、上述した第1
の実施の形態における半導体ユニットと同様である。し
たがって、本実施の形態において、第1の実施の形態と
基本的に同様のものについては、同一符号を付与し、説
明を省略する。また、特に説明のないものについては、
第1の実施の形態と同じとする。(Second Embodiment) Next, a second embodiment of the present invention will be described.
An embodiment will be described with reference to the drawings. The semiconductor unit according to the present embodiment is the same as the first unit except that the semiconductor element has the bump electrode of the present invention.
This is the same as the semiconductor unit in the embodiment. Therefore, in the present embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted. Also, unless otherwise specified,
It is the same as the first embodiment.
【0044】図4は、本発明の第2の実施の形態に係る
半導体ユニットの構成を示す要部断面図である。上述し
た第1の実施の形態の場合と比較して、半導体素子1の
端子電極2に突起電極14を形成されている点が異なる
他は、第1の実施の形態の場合と実質的に同じ構成であ
る。FIG. 4 is a sectional view showing a main part of a semiconductor unit according to a second embodiment of the present invention. Substantially the same as the first embodiment, except that the projecting electrode 14 is formed on the terminal electrode 2 of the semiconductor element 1 as compared with the above-described first embodiment. Configuration.
【0045】次に、本実施の形態における半導体素子の
実装方法について説明する。本実施の形態における半導
体素子の実装方法は、第1の実施の形態における半導体
素子の実装方法の電極接続工程の前に、端子電極2上に
突起電極14を形成する突起電極形成工程を含み、電極
接続工程においては、端子電極2と接続電極5とを、突
起電極14を介して、接合層により電気的に接続するこ
と以外は、第1の実施の形態の場合と実質的に同じ手順
である。Next, a method of mounting the semiconductor device according to the present embodiment will be described. The method for mounting a semiconductor element in the present embodiment includes, before the electrode connecting step of the method for mounting a semiconductor element in the first embodiment, a step of forming a bump electrode 14 on the terminal electrode 2, In the electrode connecting step, the procedure is substantially the same as that of the first embodiment, except that the terminal electrode 2 and the connecting electrode 5 are electrically connected to each other by the bonding layer via the bump electrode 14. is there.
【0046】突起電極14の材料としては、Au等を用
いる。端子電極2に突起電極14を形成することによ
り、上記第1の実施の形態の効果に加えて、半導体素子
1を回路基板4に実装する際の導電性接着剤3の広がり
を規制することができ、微細ピッチでの接合が可能にな
る。また、突起電極14の高さ分だけ半導体素子1と回
路基板4との隙間を広くすることができ、熱応力をより
緩和させることができる。Au or the like is used as the material of the bump electrode 14. By forming the protruding electrodes 14 on the terminal electrodes 2, in addition to the effects of the first embodiment, it is possible to restrict the spread of the conductive adhesive 3 when the semiconductor element 1 is mounted on the circuit board 4. And bonding at a fine pitch becomes possible. Further, the gap between the semiconductor element 1 and the circuit board 4 can be widened by the height of the protruding electrode 14, and the thermal stress can be further reduced.
【0047】なお、上述した第1および第2の実施の形
態における半導体素子の実装方法では、導電性接着剤3
を半導体素子1側に塗布するとして説明したが、回路基
板4の接続電極5側に導電性接着剤3を塗布しても同様
の効果が得られる。In the mounting method of the semiconductor element according to the first and second embodiments, the conductive adhesive 3
Is applied to the semiconductor element 1 side, but the same effect can be obtained by applying the conductive adhesive 3 to the connection electrode 5 side of the circuit board 4.
【0048】また、導電性接着剤3は溶剤型の導電性接
着剤に限られず、その硬化後にポーラスな空間を有し、
かつ電気的導通を有するものであればいかなるものであ
ってもよい。The conductive adhesive 3 is not limited to a solvent-type conductive adhesive, but has a porous space after curing.
Any material may be used as long as it has electrical continuity.
【0049】さらに、半導体素子1を回路基板4に接合
する材料はポーラスな導電性接着剤に限られたものでな
く、いかなるポーラスな導電性部材でよく、例えば、ポ
ーラスな金属であってもよい。加えて、熱膨張係数を調
整するために封止樹脂層9に配合するシリカ等の無機フ
ィラーの大きさとして、ポーラスな導電性接着剤のポー
ラスな空間13よりも小さなものを含んで用いると導電
性接着剤の接合層の後ろにも無機フィラーを含んだ封止
樹脂の充填層が形成でき、さらにその効果を発揮するこ
とができる。The material for joining the semiconductor element 1 to the circuit board 4 is not limited to the porous conductive adhesive, but may be any porous conductive member, for example, a porous metal. . In addition, if the size of the inorganic filler such as silica mixed with the sealing resin layer 9 to adjust the thermal expansion coefficient is smaller than the size of the porous space 13 of the porous conductive adhesive, the use of the inorganic filler becomes conductive. The filling layer of the sealing resin containing the inorganic filler can be formed behind the bonding layer of the adhesive, and the effect can be further exhibited.
【0050】なお、上述した第1および第2の実施の形
態における半導体素子の実装方法では、半導体素子の端
子電極と回路基板の接続電極とを、導電性接着剤を用い
て電気的に接続する電極接続工程と、前記電極接続工程
の後、前記導電性接着剤を硬化して、ポーラスな導電性
材料部を形成する導電性材料部形成工程とを含むとして
説明したが、上記電極接続工程および導電性材料部形成
工程の替わりに、ポーラスな空間を有するとともに接着
性を有する導電性材料を用いて、半導体素子の端子電極
と回路基板の接続電極とを電気的に接続することによっ
て、ポーラスな導電性材料部を形成する工程を含むとし
ても、同様の効果が得られる。In the method of mounting a semiconductor element according to the first and second embodiments, the terminal electrodes of the semiconductor element and the connection electrodes of the circuit board are electrically connected using a conductive adhesive. The electrode connection step and, after the electrode connection step, have been described as including a conductive material part forming step of curing the conductive adhesive to form a porous conductive material part. Instead of the step of forming the conductive material portion, a porous material having a porous space and an adhesive property is used to electrically connect the terminal electrode of the semiconductor element and the connection electrode of the circuit board, thereby forming a porous material. A similar effect can be obtained even if a step of forming the conductive material portion is included.
【0051】[0051]
【発明の効果】以上説明したところから明らかなよう
に、本発明は、半導体素子と回路基板との接続の信頼性
を向上させる半導体ユニットおよび半導体素子の実装方
法を提供することができる。As is apparent from the above description, the present invention can provide a semiconductor unit and a method for mounting a semiconductor element which improve the reliability of connection between the semiconductor element and the circuit board.
【0052】すなわち、本発明の半導体ユニットは、半
導体素子と回路基板との接合部と半導体素子と回路基板
との間隙の充填部とが一体化されたものである。これに
より、半導体ユニットを使用する際にも、ボイドの熱膨
張により生ずる熱応力や高温領域でのボイド中の湿気が
水蒸気となって熱膨張することにより生ずる新たな熱応
力が導電性部材による接合部に加わることを全く無くす
ることができ、半導体素子と回路基板の接合を確実なも
のとすることができる。また、接合部の導電性部材は、
封止樹脂によりポーラスであった空間が充填されるた
め、半導体素子と回路基板の導電性部材による接合部の
強度や密着力が増し、接合の安定性を向上させることが
できる。That is, in the semiconductor unit of the present invention, the joint between the semiconductor element and the circuit board and the filling part of the gap between the semiconductor element and the circuit board are integrated. As a result, even when the semiconductor unit is used, thermal stress caused by thermal expansion of the void and new thermal stress caused by thermal expansion of moisture in the void in a high-temperature region as steam become bonded by the conductive member. It is possible to completely prevent the semiconductor element and the circuit board from being joined to each other. In addition, the conductive member of the joint portion,
Since the space that has been porous is filled with the sealing resin, the strength and adhesion of the joint between the semiconductor element and the conductive member of the circuit board can be increased, and the joining stability can be improved.
【0053】また、半導体素子の端子電極上に突起電極
を設けることにより、半導体素子を回路基板に実装する
際の導電性部材の広がりを規制することができ、微細ピ
ッチでの接合が可能になる。また、突起電極の高さ分だ
け半導体素子と回路基板との隙間を広くすることがで
き、熱応力をより緩和させることができる。Further, by providing the protruding electrode on the terminal electrode of the semiconductor element, the spread of the conductive member when the semiconductor element is mounted on the circuit board can be restricted, and bonding at a fine pitch can be performed. . In addition, the gap between the semiconductor element and the circuit board can be widened by the height of the protruding electrode, and the thermal stress can be further reduced.
【0054】また、接合層と封止樹脂層の熱膨張係数を
同じにすることにより、接合層と封止樹脂層の界面にお
ける剥離やひび割れ等の発生を防止することができる。Further, by making the thermal expansion coefficients of the bonding layer and the sealing resin layer the same, it is possible to prevent the occurrence of peeling or cracking at the interface between the bonding layer and the sealing resin layer.
【0055】また、封止樹脂層に、ポーラスな導電性部
材のポーラスな空間よりも大きな無機フィラーを含める
ことにより、接合層と封止樹脂層の熱膨張係数の調整が
容易になる。Further, by including an inorganic filler larger than the porous space of the porous conductive member in the sealing resin layer, it becomes easy to adjust the thermal expansion coefficient of the bonding layer and the sealing resin layer.
【0056】一方、本発明の半導体素子の実装方法は、
本発明の半導体ユニットを容易に製造することができ
る。On the other hand, the mounting method of the semiconductor device of the present invention is as follows.
The semiconductor unit of the present invention can be easily manufactured.
【0057】また、ポーラスな導電性部材として、少な
くとも溶剤と、有機樹脂と、導電フィラーを含む溶剤型
の導電性接着剤を硬化させることにより、溶剤の揮発に
より容易にポーラスな空間を形成することができる。Further, as a porous conductive member, a solvent-type conductive adhesive containing at least a solvent, an organic resin, and a conductive filler is cured to easily form a porous space by volatilization of the solvent. Can be.
【0058】また、液状の封止樹脂として、硬化後の導
電性接着剤に対して溶解性を有しないものを用いること
により、封止樹脂の注入によっていったん形成された結
合層の破損を防止することができる。Further, by using a liquid sealing resin which does not dissolve in the conductive adhesive after curing, damage of the bonding layer once formed by injection of the sealing resin is prevented. be able to.
【図1】本発明の第1の実施の形態における半導体素子
の実装方法の工程を示す要部断面図である。FIG. 1 is a fragmentary cross-sectional view showing a step in a method for mounting a semiconductor device according to a first embodiment of the present invention.
【図2】本発明の第1の実施の形態におけるポーラスな
導電性接着剤の接合層を示す要部断面図である。FIG. 2 is a cross-sectional view of a main part showing a bonding layer of a porous conductive adhesive according to the first embodiment of the present invention.
【図3】本発明の第1の実施の形態におけるポーラスな
導電性接着剤の接合層に液状の封止樹脂が含浸された状
態を示す要部断面図である。FIG. 3 is an essential part cross-sectional view showing a state in which a liquid sealing resin is impregnated in a bonding layer of a porous conductive adhesive according to the first embodiment of the present invention.
【図4】本発明の第2の実施の形態に係る半導体ユニッ
トの構成を示す要部断面図である。FIG. 4 is a fragmentary cross-sectional view showing a configuration of a semiconductor unit according to a second embodiment of the present invention.
【図5】フェースダウンで実装された従来の半導体ユニ
ットの構成を示す要部断面図である。FIG. 5 is a sectional view of a main part showing a configuration of a conventional semiconductor unit mounted face-down.
【図6】従来の半導体素子の実装方法の工程を示す要部
断面図である。FIG. 6 is a cross-sectional view of a main part showing steps of a conventional method for mounting a semiconductor element.
1 半導体素子 2 端子電極 3 溶剤型の導電性接着剤 4 回路基板 5 接続電極 6 ポーラスな導電性接着剤の接合層 7 液状の封止樹脂 8 液状の封止樹脂が含浸した導電性接着剤の接合層 9 完全充填された液状の封止樹脂 10 硬化後の封止樹脂の充填層 11 導電フィラー 12 有機樹脂 13 ポーラスな空間 14 突起電極 15 半田接合部 16 封止樹脂 17 半田の突起電極 18 液状の封止樹脂が廻り込まない空隙 19 液状の封止樹脂中の気泡 20 ボイドを含んだ液状の封止樹脂 21 ボイドを残したまま硬化した封止樹脂の充填層 DESCRIPTION OF SYMBOLS 1 Semiconductor element 2 Terminal electrode 3 Solvent type conductive adhesive 4 Circuit board 5 Connection electrode 6 Porous conductive adhesive bonding layer 7 Liquid sealing resin 8 Conductive adhesive impregnated with liquid sealing resin Bonding layer 9 Completely filled liquid sealing resin 10 Filled layer of cured sealing resin 11 Conductive filler 12 Organic resin 13 Porous space 14 Protruding electrode 15 Solder joint 16 Sealing resin 17 Solder protruding electrode 18 Liquid Voids in which the sealing resin does not flow around 19 Bubbles in the liquid sealing resin 20 Liquid sealing resin containing voids 21 Filling layer of the sealing resin cured while leaving voids
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.6,DB名) H01L 21/60 311 H01L 23/28 ──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 6 , DB name) H01L 21/60 311 H01L 23/28
Claims (18)
ウン状態で実装された半導体素子と、前記半導体素子の
端子電極と前記回路基板の接続電極とを電気的及び機械
的に接続する接合層と、前記半導体素子と前記回路基板
との間隙に充填された封止樹脂の充填層とを備え、前記
接合層は、ポーラスな導電性材料部と、前記導電性材料
部のポーラスな空間に存在する前記封止樹脂の一部とか
ら構成されていることを特徴とする半導体ユニット。1. A circuit board, a semiconductor element mounted face-down on the circuit board, and a bonding layer for electrically and mechanically connecting a terminal electrode of the semiconductor element and a connection electrode of the circuit board. And a filling layer of a sealing resin filled in a gap between the semiconductor element and the circuit board, wherein the bonding layer exists in a porous conductive material portion and a porous space of the conductive material portion. A semiconductor unit comprising a part of the sealing resin.
接合層との間に突起電極を有することを特徴とする請求
項1に記載の半導体ユニット。2. The semiconductor unit according to claim 1, wherein the semiconductor element has a protruding electrode between the terminal electrode and the bonding layer.
の熱膨張係数と実質的に等しいことを特徴とする請求項
1または2に記載の半導体ユニット。3. The semiconductor unit according to claim 1, wherein a thermal expansion coefficient of the bonding layer is substantially equal to a thermal expansion coefficient of the filling layer.
よび無機フィラーを含むことを特徴とする請求項1〜3
のいずれかに記載の半導体ユニット。4. The sealing resin according to claim 1, wherein the sealing resin contains at least an organic resin and an inorganic filler.
The semiconductor unit according to any one of the above.
ポーラスな空間よりも大きいものを含むことを特徴とす
る請求項4に記載の半導体ユニット。5. The semiconductor unit according to claim 4, wherein the inorganic filler includes a filler whose size is larger than that of the porous space.
樹脂の一部は、前記有機樹脂を含み、前記無機フィラー
を含まないことを特徴とする請求項5に記載の半導体ユ
ニット。6. The semiconductor unit according to claim 5, wherein a part of the sealing resin present in the porous space contains the organic resin and does not contain the inorganic filler.
ポーラスな空間よりも小さなものを含むことを特徴とす
る請求項4に記載の半導体ユニット。7. The semiconductor unit according to claim 4, wherein the inorganic filler includes a filler whose size is smaller than that of the porous space.
樹脂の一部は、前記有機樹脂および前記無機フィラーを
含むことを特徴とする請求項7に記載の半導体ユニッ
ト。8. The semiconductor unit according to claim 7, wherein a part of the sealing resin existing in the porous space contains the organic resin and the inorganic filler.
は、導電性接着剤であることを特徴とする請求項1〜8
のいずれかに記載の半導体ユニット。9. The method according to claim 1, wherein a main component of the porous conductive material portion is a conductive adhesive.
The semiconductor unit according to any one of the above.
は、ポーラスな金属であることを特徴とする請求項1〜
8のいずれかに記載の半導体ユニット。10. The method according to claim 1, wherein a main component of the porous conductive material portion is a porous metal.
9. The semiconductor unit according to any one of 8.
路基板に実装する半導体素子の実装方法において、前記
半導体素子の端子電極と前記回路基板の接続電極とをポ
ーラスな導電性材料を用いて電気的に接続することによ
って、ポーラスな導電性材料部を形成する電極接続工程
と、前記電極接続工程の後、前記半導体素子と前記回路
基板との間隙に液状の封止樹脂を充填する樹脂充填工程
と、前記樹脂充填工程と同時に、前記液状の封止樹脂を
前記ポーラスな導電性材料部のポーラスな空間に含浸さ
せる含浸工程と、前記含浸工程の後、前記液状の封止樹
脂を硬化させる樹脂硬化工程とを含むことを特徴とする
半導体素子の実装方法。11. A method of mounting a semiconductor element on a circuit board in a face-down state, wherein a terminal electrode of the semiconductor element and a connection electrode of the circuit board are electrically connected using a porous conductive material. By connecting, an electrode connection step of forming a porous conductive material portion, and after the electrode connection step, a resin filling step of filling a gap between the semiconductor element and the circuit board with a liquid sealing resin, Simultaneously with the resin filling step, an impregnating step of impregnating the porous space of the porous conductive material portion with the liquid sealing resin, and a resin curing step of curing the liquid sealing resin after the impregnating step And a method for mounting a semiconductor element.
路基板に実装する半導体素子の実装方法において、前記
半導体素子の端子電極と前記回路基板の接続電極とを、
導電性接着剤を用いて電気的に接続する電極接続工程
と、前記電極接続工程の後、前記導電性接着剤を硬化し
て、ポーラスな導電性材料部を形成する導電性材料部形
成工程と、前記導電性材料部形成工程の後、前記半導体
素子と前記回路基板との間隙に液状の封止樹脂を充填す
る樹脂充填工程と、前記樹脂充填工程と同時に、前記液
状の封止樹脂を前記ポーラスな導電性材料部のポーラス
な空間に含浸させる含浸工程と、前記含浸工程の後、前
記液状の封止樹脂を硬化させる樹脂硬化工程とを含むこ
とを特徴とする半導体素子の実装方法。12. A method of mounting a semiconductor element on a circuit board in a face-down state, wherein a terminal electrode of the semiconductor element and a connection electrode of the circuit board are connected to each other.
An electrode connection step of electrically connecting using a conductive adhesive, and after the electrode connection step, a curing of the conductive adhesive to form a conductive material portion forming a porous conductive material portion, After the conductive material portion forming step, a resin filling step of filling the gap between the semiconductor element and the circuit board with a liquid sealing resin, and simultaneously with the resin filling step, the liquid sealing resin is A method for mounting a semiconductor device, comprising: an impregnation step of impregnating a porous space of a porous conductive material portion; and a resin curing step of curing the liquid sealing resin after the impregnation step.
と、有機樹脂と、導電フィラーを含むことを特徴とする
請求項12に記載の半導体素子の実装方法。13. The method according to claim 12, wherein the conductive adhesive contains at least a solvent, an organic resin, and a conductive filler.
導電性接着剤に対して溶解性を有しないことを特徴とす
る請求項13に記載の半導体素子の実装方法。14. The method according to claim 13, wherein the liquid sealing resin has no solubility in the cured conductive adhesive.
機樹脂および無機フィラーを含むことを特徴とする請求
項11〜14のいずれかに記載の半導体素子の実装方
法。15. The method according to claim 11, wherein the liquid sealing resin contains at least an organic resin and an inorganic filler.
な空間に、前記無機フィラーが含浸しないように、前記
液状の封止樹脂を含浸させることを特徴とする請求項1
5に記載の半導体素子の実装方法。16. The method according to claim 1, wherein in the impregnating step, the liquid sealing resin is impregnated into the porous space so as not to be impregnated with the inorganic filler.
6. The mounting method of the semiconductor element according to 5.
な空間に、前記有機樹脂および前記無機フィラーが含浸
するように、前記液状の封止樹脂を含浸させることを特
徴とする請求項15に記載の半導体素子の実装方法。17. The semiconductor according to claim 15, wherein in the impregnating step, the liquid sealing resin is impregnated into the porous space so that the organic resin and the inorganic filler are impregnated. Element mounting method.
極上に突起電極を形成する突起電極形成工程を含み、前
記電極接続工程においては、前記端子電極と前記接続電
極とを、前記突起電極を介して、電気的に接続すること
を特徴とする請求項11〜17のいずれかに記載の半導
体素子の実装方法。18. The method according to claim 18, further comprising: a step of forming a projecting electrode on the terminal electrode before the electrode connecting step. In the electrode connecting step, the terminal electrode and the connection electrode are connected to the projecting electrode. The method for mounting a semiconductor device according to claim 11, wherein the semiconductor device is electrically connected to the semiconductor device via a wire.
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JP10155552A JP2892348B1 (en) | 1998-06-04 | 1998-06-04 | Semiconductor unit and semiconductor element mounting method |
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