JP2738159B2 - Clock signal control circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock signal control circuit, and more particularly to a clock signal control circuit for an integrated circuit device having a clock signal generation circuit.

[0002]

2. Description of the Related Art In recent years, with the advance of integrated circuit technology, high-density semiconductor integrated circuits (hereinafter, referred to as LSIs) have rapidly become CMOS. Accordingly, the LSI is in a non-operating state (standby) to take advantage of the low power consumption characteristics of the CMOS.
In some cases, an LSI having a clock signal control circuit having a function of stopping original oscillation of a clock signal generation circuit, inhibiting operation of an internal circuit, and minimizing power consumption has been developed.

In particular, many CMOS microcomputers (hereinafter referred to as microcomputers) have the above-described clock signal control function. In these microcomputers, it is general that the instruction of the microcomputer is executed by a user program to set the clock signal control circuit in a standby state.

Although these LSIs are applied to various electronic devices, a plurality of such LSIs are often used, for example, a microcomputer and a gate array. In this case, each L
Since it is uneconomical to use a resonator for an SI, it is common to supply a clock pulse from another LSI even if the LSI has an oscillation circuit.

The conventional clock signal control circuit releases the standby state set on the assumption that the resonator is used, and when the circuit is restarted, the clock is supplied to the internal circuit within the settling time at the rise of the oscillation circuit. It was configured not to supply a signal.

[0006]

In this conventional clock signal control circuit, the clock signal is stopped during the stabilization time when the oscillation circuit rises, so that a clock pulse is externally supplied without using a resonator. Even in such a case, there is a problem that responsiveness is poor because the operation is not restarted until after the above-mentioned oscillation stabilization time has elapsed.

An object of the present invention is to solve the above problems,
Provide a clock signal control circuit that can secure the oscillation stabilization time when using a resonator and can release the standby state without wasting waiting time when receiving a clock signal from the outside. It is.

[0008]

The clock signal control circuit of the present invention, in order to solve the problem] is provided with a clock signal generating circuit for generating a clock signal based on the said oscillating signal and the oscillation circuit you outputs an oscillation signal using a resonator in the clock signal control circuit, a first control circuit which is controlled by the external control signal and the reset signal for outputting a first control signal for controlling the operation of the oscillation circuit, the external control signal and the first Control signal
The first operation is to perform a logical operation with the signal and output the first logical signal.
A logic circuit, a counter circuit for outputting a count signal upon reaching a initialized predetermined count value counted No. the calling fusin in response to the supply of the first logic signal, initially at power-on
And is set in response to the supply of a predetermined command signal.
The second control circuit and the count value to output a second control signal
And a logical operation of the second control signal and the second logical signal
A second logic circuit that outputs a second logic signal;
Supply of the first control signal reset in response to the supply
And a third control circuit of a set priority type which outputs a third control signal which is set in response to the control signal and controls the operation of the clock signal generation circuit.

[0009]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a clock signal control circuit according to the present invention.

This embodiment shows an example applied to a clock signal control circuit of a microcomputer.

The clock signal control circuit according to the present embodiment has the configuration shown in FIG.
As shown in FIG. 1, the circuit includes flip-flops 1, 4, 5, an oscillator 2, a counter 3, a clock signal generating circuit 6, an inverter A1, and OR gates A2, A3.

The flip-flop 1 is an RS flip-flop, which is set by a stop signal S which is a stop command signal of the microcomputer, and is reset by R which is obtained by inverting a low active reset signal RI inputted from a reset terminal TR by an inverter A1. The operation of the oscillator 2 is controlled by the output.

The counter 3 has an oscillation output OSC of the oscillator 2.
Is counted, and after reaching a predetermined count value after a lapse of a predetermined time, an overflow signal (OVF) is output.

The flip-flop 4 is a power-on flip-flop (POF) that is initialized to logic "0" when the power is turned on and set by executing a specific instruction.

The flip-flop 5 is a set-priority RS flip-flop.
The output of the OR gate A3 is input, and the output controls the operation of the clock signal generation circuit 6.

The clock signal generation circuit 6 outputs clock signals CK1 and CK2 based on the output OSC of the oscillator 2.

Next, the operation of this embodiment will be described.

FIG. 2 is a time chart for explaining the operation when the resonator of the present invention is used, and the operation will be described below with reference to FIGS.

First, the power is turned on at time t0, and when the reset signal RI becomes "0", the flip-flop 1, the counter 3, and the logic circuit inside the LSI are initialized. Also, the flip-flop 4 becomes '0'. Regardless of whether the flip-flop 5 is “0” or “1”, the reset signal RI at the time of turning on the power is normally 10 to 10 which is necessary for stable oscillation.
There is no particular problem because it is set to "0" for 50 ms, but is set to "1" for convenience of explanation. Therefore, even if the oscillator 2 oscillates, the clock signal generation circuit 6 is in a stopped state.

Next, the reset signal RI becomes "1" at time t1, but the clock signals CK1 and CK2 are not output because the output of the flip-flop 5 is "1".

When the OVF signal of the counter 3 is output at time t2, the OR gate A3 becomes "1" and the flip-flop 5 is reset, so that the clock signals CK1 and CK are output.
2 is output, and the internal operation of the LSI starts.

When the stop signal S is input at time t3, the flip-flops 1 and 5 are set, the oscillator 2 is stopped, the counter 3 is initialized, and the clock signals CK1 and CK2 are stopped. Therefore, LSI
Power consumption becomes extremely small.

When the reset signal RI becomes "0" at time t4, the flip-flop 1 is reset and the oscillator 2 operates. When the reset signal RI becomes "1", the counter 3
Operates to count a predetermined number of times, that is, time t
5, the OVF signal is output, the flip-flop 5 is reset, and the clock signals CK1 and CK2 are output.

As described above, the output P of the flip-flop 4
By setting OF to '0', it is possible to secure the oscillation stabilization time when a resonator is used.
Can be reliably operated.

Next, a case where a clock pulse is supplied from the outside will be described with reference to FIG.

Here, only the differences from the aforementioned FIG. 2 will be described. First, at time t6, flip-flop 4 is set by a command signal.

Next, to set the standby state at t7, when the stop signal S is output, the flip-flops 1 and 5 are set, the output OSC of the oscillator 2 and the clock signals CK1 and CK2 are stopped, and the power consumption is minimized. Become. Here, the output POF of the flip-flop 4 is “1”,
The output of the OR gate A3 is also "1", but the output of the flip-flop 5 remains "1" due to the set priority.

When the reset signal RI becomes "0" at time t8, the outputs of the flip-flops 1 and 5 immediately become "0", and the oscillator 2 and the clock signal generating circuit 6 operate to output the clock signals CK1 and CK2. I do. For this reason,
There is no useless oscillation stabilization time, and the reset signal RI is '1'
Then, the internal operation of the LSI becomes effective immediately.

Although the embodiments of the present invention have been described above, the present invention is not limited to the above embodiments, and various modifications can be made.

For example, instead of a power-on flip-flop initialized to logic "0" at power-on, the output logic value is set to "1" when a clock pulse is supplied from outside in advance, and Is used, it is needless to say that the present invention can be applied to a ROM set to "0" by a photomask without departing from the gist of the present invention.

[0032]

As described above, the clock signal control circuit of the present invention secures a stabilization time at the time of rising of an oscillation circuit using a resonator and receives a supply of a clock pulse from the outside. This has the effect of eliminating wasted waiting time for oscillation stabilization and improving responsiveness.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a clock signal control circuit of the present invention.

FIG. 2 is a time chart illustrating an example of an operation when a resonator is used in the clock signal control circuit according to the present embodiment.

FIG. 3 is a time chart illustrating an example of an operation of the clock signal control circuit according to the present embodiment when a clock pulse is supplied from the outside;

[Explanation of symbols]

 1, 4, 5 flip-flop 2 oscillator 3 counter 6 clock signal generation circuit A1 inverter A2, A3 OR gate

Claims (2)

(57) [Claims] 1. A clock signal control circuit and a clock signal generating circuit based on the oscillation circuit and the oscillation signal you output an oscillation signal using a resonator and for generating a clock signal, the external control signal and a reset A first control circuit that is controlled by a signal and outputs a first control signal that controls the operation of the oscillation circuit; and performs a logical operation of the external control signal and the first control signal.
And a first logic circuit for outputting a first logic signal, and initialized in response to the supply of the first logic signal, and
A counting circuit for outputting a count signal upon reaching a predetermined count value counted No. fusin, is initialized in response to the supply of a predetermined command signal at power-on
A second control circuit that is set to output a second control signal, and performs a logical operation on the count value and the second control signal.
A second logic circuit that outputs a second logic signal, and is reset in response to the supply of the second logic signal;
Is set in response to the supply of the first control signal exits the third control signal for controlling the operation of said clock signal generating circuit
And a third control circuit of a set priority type . 2. The control circuit according to claim 1 , wherein
Respond to supply of stop signal from a microcomputer
And reset in response to the supply of the reset signal.
An RS-type first flip-flop to be set, wherein the second control circuit is initialized when power is turned on, and
Power-on type second flip set by the
A flip-flop, wherein the third control circuit responds to the supply of the second logic signal.
Is reset in response to the supply of the first control signal.
Set-first third flip-flop
The clock signal according to claim 1, further comprising:
Control circuit.