JPH0651860A - Oscillation stablizing time guarantee circuit - Google Patents

Abstract

PURPOSE:To decrease the bit number of a counter, to reduce circuitry and to reduce energy consumption at the time of a normal operation as well by using an oscillation stablizing means having wide hysteresis width when a stop mode is canceled. CONSTITUTION:When a CLK is inputted from an oscillation circuit 1 to one input terminal, a Schmitt NAND circuit 12 outputs a CLKOUT at the time of setting the other input terminal at a prescribed level. When the CLK is inputted to one input terminal and the other input terminal is set at the prescribed level, a Schmitt NAND 9 of large hysteresis outputs this CLK at the time of turning this CLK to the prescribed hysteresis width. When the first clock is inputted from this NAND 9, an n-bit counter 10 performs a count output at the time of turning the count value of this clock to a prescribed value. The stop mode signal of the oscillation circuit 1 is inputted to a control circuit 11 so as to turn any one of the other input terminals of these Schmitt NAND 9 and 12 to the prescribed level. Thus, the size can be miniaturized.

Description

Detailed Description of the Invention

[0001]

The present invention relates to an oscillation stabilization time guarantee circuit,
More specifically, the present invention relates to an oscillation stabilization time guarantee circuit applied to an LSI having an oscillation circuit and a circuit that guarantees an oscillation stabilization time thereof, particularly a microcomputer having a stop mode.

[0002]

2. Description of the Related Art As is well known, in recent years, microcomputers have been used in various electronic devices. For example, when such a microcomputer is incorporated in a portable electronic device, it is particularly desirable to reduce power consumption as much as possible. Therefore, when the microcomputer is in a non-operating state (standby), a microcomputer having a stop mode (oscillation stop mode) that stops the operation of the internal circuit to reduce power consumption by stopping the clock supplied to the microcomputer Technology such as is being researched.

On the other hand, a microcomputer may run away if the clock is unstable, and it is necessary to always supply a stable clock. Therefore, for example, MSM
66201 User's Manual states that the oscillation stabilization applied to a microcomputer, etc. that has an oscillation stop mode in which the clock supplied to the microcomputer is stopped during standby, and after this is released, the oscillation stabilizes. A time guarantee circuit is disclosed.

FIG. 3 shows a conventional oscillation stabilization time guarantee circuit. As shown in the figure, the oscillation stabilization time guarantee circuit 8 includes a waveform shaping Schmitt inverter 2, a 16-bit counter 3, a flip-flop 4, a NAND gate 5,
It is composed of inverters 6 and 7.

FIG. 4 is a timing chart showing the operation of the oscillation stabilization time guarantee circuit 8 shown in FIG. The operation of the conventional technique will be described with reference to FIG. When the stop mode is entered (between A and B), the STOP signal becomes logic "1", the oscillation circuit 1 stops, and the 16-bit counter 3 and the flip-flop 4 are reset.

When the stop mode is released (B), ST
The OP signal becomes “0”, the oscillation circuit 1 starts oscillation,
The clock CLK is supplied to the oscillation stabilization time guarantee circuit 8.
The output waveform CLK of the oscillator circuit 1 is the Schmitt inverter 2
When the hysteresis width of (16) is exceeded (C), the clock a is supplied to the 16-bit counter 3, and the 16-bit counter 3 starts counting pulses.

The 16-bit counter 3 is a counter provided for ensuring a sufficient time for the oscillation of the oscillator circuit 1 to stabilize. When the counter 3 starts counting and counts a predetermined number of clocks a, the Q output C of the flip-flop 4 becomes logic "1" at the falling edge of the carry output b, and the NAND gate 5 and the inverters 6 and 7 are used. A stable clock CLKOUT is output from the oscillation stabilization time guarantee circuit 8.

As described above, after the oscillation stop mode is released, the period between B and D until the oscillation circuit 1 stabilizes and can output the clock CLKOUT again is the time for guaranteeing oscillation stabilization.

Also, for example, Japanese Patent Laid-Open No. 61-228725.
In the publication, another conventional example of such an oscillation stabilization time guarantee circuit is shown as an integrated circuit device. FIG. 5 shows a circuit diagram of this prior art. As shown in the figure, in this conventional technique, the output from the oscillator circuit (OSC) is directly input to the counter 70.

Therefore, in the case of this conventional technique, the distance between C and D is longer (the same between B and D) than in the conventional technique shown in FIG. 3, and the counter 70 is stabilized until the clock from the oscillation circuit becomes stable. Needs to count more clocks than the counter 3 in FIG. Therefore, in this conventional technique, since the Schmitt inverter 2 is not provided, a counter having a larger number of bits than that in FIG. 3 is required.

[0011]

As described above, in the conventional oscillation stabilization time guarantee circuit, when an oscillation stabilization time of 6.5 msec is to be obtained with a crystal oscillation circuit of 10 MHz, for example, a 16-bit counter or more bits are required. However, there is a problem in that the circuit scale becomes large because it requires the counter. For example, in the conventional technique shown in FIG. 3, the output of the Schmitt inverter 2 can be obtained after the amplitude of the oscillation waveform is increased by widening the hysteresis width of the Schmitt inverter 2.

If the output of the Schmitt inverter 2 can be obtained after the amplitude of the oscillation waveform is increased in this way, the counter 3 can count after the oscillation of the oscillation circuit 1 is relatively stable. It is possible to reduce the number. However, if the hysteresis width of the Schmitt inverter 2 is simply widened in the circuit configuration of FIG. 3, the current consumption during normal operation will increase, resulting in an increase in power consumption.

The present invention eliminates the drawbacks of the prior art and reduces the circuit scale by reducing the number of bits of the counter, and at the same time, the oscillation stabilization time guarantee circuit can reduce the power consumption during normal operation. The purpose is to provide.

[0014]

In order to solve the above problems, the present invention provides an oscillator circuit for outputting a first clock,
An oscillation stabilization time guarantee circuit having a stop mode of an oscillation circuit that outputs a second clock after the first clock that is output again after the oscillation circuit has stopped is stable. A waveform shaping means having a small hysteresis that inputs and outputs the second clock when the other input terminal has a predetermined level, and the first clock is input to one input terminal and the other input terminal has a predetermined level. At this time, when the first clock has a predetermined hysteresis width, the oscillation stabilizing means with a large hysteresis that outputs the first clock and the first clock is input from the oscillation stabilizing means,
Count output is performed when the count value of the clock reaches a predetermined value, and the counting means reset by the stop signal in the stop mode, the stop signal and the count output of the counting means are input, and in response to these, And a control means for setting either the other input terminal of the waveform shaping means or the other input terminal of the oscillation stabilizing means to a predetermined level.

In such an oscillation stabilization time guarantee circuit, the control means sets the other input terminal of the oscillation stabilization means to a predetermined level when the stop mode signal is input, and outputs the count output from the counting means after releasing the stop mode. When input, the other input terminal of the waveform shaping means is set to a predetermined level.

[0016]

According to the present invention, since the oscillation stabilizing means having a large hysteresis width is used when the stop mode is released, the counting can be started after the amplitude of the oscillation waveform becomes large, that is, the oscillation is stabilized.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of an oscillation stabilization time guarantee circuit according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a circuit diagram showing an embodiment of an oscillation stabilization time guarantee circuit according to the present invention. The oscillation stabilization time guarantee circuit 15 in the present embodiment, after releasing the STOP signal which is the oscillation stop signal, stabilizes the clock CLK from the oscillation circuit 1 sufficiently, and then sends a predetermined clock CLKOUT to an internal circuit of an LSI such as a microcomputer. It is a circuit to supply.

The oscillation stabilization time guarantee circuit 15 includes two Schmidt NANDs 9 and 12 having different hysteresis widths, and an n-bit counter 1 having a small number of bits.
0, the flip-flop 11 and the inverter 13 for controlling the outputs of the NANDs 9 and 12, and the inverter 14
It is composed by.

The oscillator circuit 1 connected to a crystal oscillator (not shown) or the like is a circuit for generating a basic clock during a normal operation in which the STOP signal is logic "0". The oscillator circuit 1 is
The Schmitt NAND 9 having a large hysteresis width and the Schmitt NAND 12 having a small hysteresis width are connected to one input terminal of the Schmitt NAND 9 and output the basic clock CLK to them. The output terminal of the Schmitt NAND 9 is connected to the clock input terminal of the n-bit counter 10 (n <16).
The Schmitt NAND 9 is a Schmitt circuit used for stabilizing the oscillation of the oscillator circuit 1.
D12 is a Schmitt circuit for waveform shaping.

The n-bit counter 10 is a counting circuit that is reset by the STOP signal, counts the pulses from the Schmitt NAND 9, and carries out a carry output when the count reaches a predetermined value. n-bit counter 1
0 carry output terminal is flip-flop with reset 1
1 is connected to the clock input terminal.

The reset flip-flop 11 is a control circuit for controlling the outputs of the Schmitt NANDs 9 and 12. The flip-flop 11 has an S terminal at the reset terminal R.
Input the TOP signal and VDD to the D input terminal,
During normal operation, an output of logic "1" is output from the output terminal Q, and logic "0" is output from the output terminal Q during the oscillation stop and oscillation stabilization guarantee time of the oscillation circuit 1. The output terminal Q of the flip-flop 11 is connected to the other input terminal of the Schmitt NAND 12 and the input terminal of the inverter 13.

The inverter 13 is a circuit for inverting the output signal of the output terminal Q, and the output terminal is connected to the other input terminal of the NAND 9. By the inversion control of the inverter 13, the NAND 12 is selected in the normal operation, and the Schmitt NAND 9 is selected for the oscillation stop and the oscillation stabilization guaranteed time of the oscillation circuit 1.

The output terminal of the Schmitt NAND 12 is connected to the input terminal of the inverter 14, and the inverter 1
A predetermined clock CLKOUT is supplied from an output terminal of 4 as an output of the oscillation stabilization time guarantee circuit 15 to an internal circuit such as a microprocessor.

FIG. 2 is a timing chart showing the operation of the embodiment shown in FIG. The operation of this embodiment will be described with reference to FIGS. 1 and 2.

In the normal operation, the output CLK of the oscillation circuit 1 is the Schmidt NAN with a small hysteresis width for waveform shaping.
Clock CLKOUT through D12 and inverter 14
Is output as.

When the stop mode is entered and the STOP signal becomes logic "1" as indicated by symbol E, the n-bit counter 10 and the flip-flop 11 are reset and the oscillation of the oscillator circuit 1 is stopped (EF). while). As a result, the clock CLKOUT from the inverter 14 becomes a logic "0" and the clock stops.

When the stop mode is released and the STOP signal becomes "0" again as indicated by the symbol F, the oscillation circuit 1
Initially starts unstable oscillation as shown in FIG. 2 (F-
Between G). At this time, the clock CLK of the oscillation circuit 1 is input to the Schmitt NAND 9 having a large hysteresis width and the Schmitt NAND 12 having a small hysteresis width. Therefore, the output of the Schmitt NAND 12 maintains the logic "1", and the output CLKOUT of the inverter 14 maintains the logic "0".

On the other hand, in the Schmitt NAND 9 having a large hysteresis width, since the output of the inverter 13 becomes the logic "1", the input clock CLK is input to the n-bit counter 1
Although it can be output to 0, since the hysteresis width is large, the oscillation is unstable and the amplitude of the clock CLK is small.
During −G, no output to the n-bit counter 10 is performed.

The oscillation of the oscillator circuit 1 is stabilized, and the clock CL
When the amplitude of K exceeds the hysteresis width of the Schmitt NAND 9, the output d of the Schmitt NAND 9 is input to the n-bit counter 10 and starts counting. When the n-bit counter 10 overflows and the carry output e is counted and output, as shown by the symbol H, the output f of the logic “1” is output from the output terminal Q of the flip-flop 11 at the falling edge thereof.
Is output to the other input terminal of the Schmitt 12. As a result, the clock CLK of the oscillation circuit 1 whose oscillation is stable
Is a Schmitt NAND 12 for waveform shaping and an inverter 1
It is output as a clock CLKOUT through 4.

If the time (between F and H) for guaranteeing the oscillation stability is constant, the interval between F and G can be set longer by widening the hysteresis width of the Schmidt NAND 9.
If the 16-bit counter is required to obtain the same oscillation stabilization time (between F and H) in the prior art, the number of bits of the n-bit counter 10 is 16 bits in the present invention. Can be less than.

[0032]

As described above in detail, according to the present invention, since the oscillation stabilizing means having a large hysteresis width is used when the stop mode is released, the oscillation waveform has a large amplitude, that is, the oscillation is stable. Then you can start counting. Therefore, since the counting time can be shortened, it is possible to use the counting means having a small number of bits of the counter, and it is possible to reduce the circuit scale. Further, according to the present invention, it is possible to select a Schmitt circuit having a small hysteresis width without considering the oscillation stabilization guaranteed time in the waveform shaping means, so that it is possible to reduce power consumption in the normal operation as compared with the related art.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of an oscillation stabilization time guarantee circuit according to the present invention,

FIG. 2 is a timing chart showing an operation example in the present embodiment shown in FIG.

FIG. 3 is a circuit diagram showing an oscillation stabilization time guarantee circuit in the prior art;

FIG. 4 is a timing chart showing the operation in the conventional technique of FIG.

FIG. 5 is a circuit diagram showing another example of the oscillation stabilization time guarantee circuit in the conventional technique.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Oscillation circuit 9,12 Schmidt NAND 10 n-bit counter 11 Flip-flop 13,14 Inverter 15 Oscillation stabilization time guarantee circuit

Claims (1)

[Claims] 1. An oscillator circuit for outputting a first clock,
In the oscillation stabilization time guarantee circuit having the stop mode of the oscillation circuit, which outputs the second clock after the first clock outputted again after the oscillation circuit is stopped is stabilized, A waveform shaping means having a small hysteresis, which inputs to the input terminal and outputs the second clock when the other input terminal has a predetermined level, and the first clock to one input terminal and the other input. When the first clock has a predetermined hysteresis width when the terminal is at a predetermined level, oscillation stabilizing means with a large hysteresis that outputs the first clock, and the first clock from the oscillation stabilizing means are input. Counting means for performing count output when the count value of the clock reaches a predetermined value, and resetting by a stop signal in the stop mode, Control means for inputting the stop signal and the count output of the counting means, and correspondingly setting either the other input terminal of the waveform shaping means or the other input terminal of the oscillation stabilizing means to the predetermined level; The control means sets the other input terminal of the oscillation stabilizing means to the predetermined level when the stop mode signal is input, and inputs the count output from the counting means after the stop mode is released. An oscillation stabilization time guarantee circuit, characterized in that the other input terminal of the waveform shaping means is set to the predetermined level.