JPS5858628A - Data processor - Google Patents

Abstract

PURPOSE:To obtain a device which realize low consumption electric power, and also is capable of executing the processing at a high speed, by providing both a control means for stopping generation of a clock signal and a control means for inhibiting a supply operation of the clock signal, and selectively using both of them. CONSTITUTION:A data processing part 1 which is timing-controlled by a clock signal 6 and processes a program, and a clock signal generating part 5 for generating the clock signal are provided. Also, a clock supplying part for supplying the clock signal 6 to the processing part 1, an inhibition controlling part for inhibiting its supply operation, a stop controlling part for stopping a generating operation of the clock signal 6 in the clock signal generating part 5, and a means for selecting these stop controlling part and the inhibition controlling part are provided. Also, supply stop and generation stop of the clock signal 6 are controlled by this selecting means. For instance, an oscillating circuit 11 is controlled through an FF 17 by a control signal 16, etc., and supply of a clock signal (a) is controlled through an FF 21 by a control signal 19, etc.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data processing device that operates using a black signal from an oscillation circuit as a control reference signal.

2. Description of the Related Art In recent years, with advances in LSI (Large Scale Integrated Circuit) manufacturing technology, electronic devices are being made smaller and have lower power consumption. This also contributes to energy conservation in keeping with the trends of the times. Also, in data processing devices, 5tFN electronic circuits and complementary field effect transistors (hereinafter referred to as "complementary field effect transistors") with low power consumption as elements.

0MO8) process technology is used.

Generally, the power consumption of a 0M08 circuit is the operating frequency f of the circuit.
i-f, stray capacitance tC1, operating voltage tV, fc
It is known that it is proportional to Vl. Therefore, if the oscillation behavior of the reference clock is changed to lower the effective frequency,
It is possible to reduce the power consumption of the entire device as much as possible.

Even in modern data processing devices, attempts have been made to temporarily stop the oscillation of black and white signals, which serve as control reference signals, in order to reduce power consumption. In order to restart the oscillation operation of the clock, a start signal must be input from outside the device.

In this case, the start signal is the one that sets the entire device to its initial state when the power tube is turned on, so the state of the device after the start of black and white oscillations is whether it will operate from the initial state or whether it is in a paused state. It was necessary to make a complete distinction as to whether it would work or not. Since this discrimination had to be performed by program processing such as checking the contents of the RAM, a very long time was required for the discrimination.

Furthermore, when a crystal oscillator or the like is used as a clock oscillation element, it takes approximately several tens of milliseconds from the start of one oscillation to obtain multistable oscillation due to the above-mentioned oscillation-specific characteristics. This temporary stop function cannot be provided in a processing device that requires a high response speed because data processing is interrupted or in a waiting state.

Furthermore, when one oscillation is stopped, the power consumption of the circuit operating with the black and white signals becomes almost zero, but no processing can be performed during the stopping period.

SUMMARY OF THE INVENTION An object of the present invention is to provide a data processing device that can perform high-speed processing while achieving low power consumption.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a data processing device according to an embodiment of the present invention. Data processing unit 1 is ROM, RAM
, ALU, and stores processing procedures, that is, programs. The command read out from here is decoded in the control section 2, and some of the control signals 3% and 4 generated as control signals control the BLACK 2 and RI signal generation sections 5. The clock signal generating section 5 includes a clock oscillation circuit and a clock supply circuit, and is configured such that a reference clock signal 6 is supplied to the data processing section 1 via the clock supply circuit. In order to generate the clock signal 6, it is necessary to connect an oscillation source such as a crystal oscillator to the clock oscillation circuit outside the device. 7 is the input line for the oscillation signal;! br and s are output lines for oscillation signals. 9 is the ninth external input signal for setting the initial state of the entire device. 10
is an external input signal requesting restart of clock oscillation.

FIG. 2 is a circuit diagram of a black signal generator 50 according to an embodiment of the present invention. The clock oscillation circuit 11 that generates the reference clock signal includes an inverter 15 and an AND gate 1.
It has 8. This oscillation circuit 11 includes, outside the device,
A resonant circuit consisting of a crystal diaphragm 12 and capacitors 13 and 14 is connected to the bubble.

16 is a control signal requesting the stop of oscillation of the gate and is outputted from the control section 2 of FIG. 1 by decoding the command. Oscillation stop clip 70 set by control signal 16
The knob 17 outputs a stop signal Ct ratio to the oscillation circuit 11. The stop signal C controls the opening and closing of the oscillation loop of the crystal resonator 12 and capacitors 13 and 14, which constitute the inverter 15° resonant circuit, via the AND gate 18.

Supply stop flip-flop 21 receives oscillation stop request signal 1
6 and the supply stop signal 19 through the DOR gate 20t- to suppress the reference clock hYr generated from the clock oscillation circuit 11 from being supplied to the data processing unit l in FIG. In this state, the reference clock is not supplied to the data processing section and the control section, so no data processing is performed, and therefore the entire data processing device stops operating and enters a low power consumption state.

Now, when the clock oscillation stop command is read out from the data processing section of FIG. 1, this command is decoded and the control section of FIG.
An oscillation stop request signal is generated from the oscillation stop request signal 16.The oscillation stop request signal C is set by this signal 16, and the oscillation stop signal C is sent to the oscillation circuit C. Meanwhile, at the same time, the supply is stopped.

AND gate 27 is set since Pu 70 Tsubu 21 is also set.
can also be closed.

Next, when the oscillation restart request signal 23 is applied from outside,
Oscillation is stopped 7 via the OR gate 24.

The flop flop 17 is reset and the oscillation output a is generated. However, the output signal a is inhibited by the AND gate 27, and the zero output resumption request signal 23, which is not supplied to the data processing section, is input to the falling edge output device 25 and becomes high level (logic 11). ”) to a low level (logic “0”) is detected. This detection signal is OR game h26? If the supply is stopped through the
70 Tsubu 21 meeting reset.

At this time, the 1-oscillation restart request signal 23 must be held at a high level until the oscillation circuit 11 stably oscillates. Specifically, although it varies depending on the crystal oscillator 12, the period is approximately several tens of z'J seconds. This detection signal stops the supply 7s, 70s. When the loop 21 is reset, the AND gate 27 is opened, and since the oscillation circuit 11 is already stably oscillating at this time, it is a good time to supply its output to the data processing section. Processing is thus restarted. The initial state input signal 22 functions in the same way as the oscillation restart request signal 23, and furthermore, this signal 22 is supplied to all circuits that require initial settings in the data processing device, and is used to set predetermined parts to the initial state. For example, the program counter is set to an initial value.

The intermittent operation in which the data processing is stopped by closing the AND gate 27 in the operating state of the oscillation circuit 11 will be described below. In this state, the oscillation circuit 11 is constantly operating, so the power consumption of that part increases, but the response speed for resuming data processing is fast, and moreover, when data processing is interrupted, only a small portion of the entire device operates. Therefore, power consumption can be reduced to less than half compared to when the entire device operates.

Now, 1 oscillation stop clip: y a v 7' 17 and supply stop knob 7 anchor knob 21 beam are set.

That is, the data processing device is in an operating state. The control signal 19 causes the supply to be stopped via the OR gate 201, and the supply is stopped via the OR gate 201. Set 21, stop supply 71J, turn 70. The pin 21 outputs a stop signal f to the AND gate and controls to stop supplying the 0 clock to the data processing section. As a result, even though the reference clock a from the oscillation circuit 11 is generated by the oscillation circuit 11, its supply to the data processing unit is prohibited. At this time, in order to re-supply the reference clock signal at to the data processing section, the oscillation restart request signal 23 can be input. , 21'fl: Reset. However, this signal 2
3, as explained earlier, there is no need to maintain the high level for several tens of milliseconds; simply stop the supply.
Since the purpose is only to set 1K-13, it can change to low level in a short time, so it can respond quickly to restarting the supply.

The above operation will be explained in more detail using the timing diagrams of FIGS. 3 and 4.

In FIG. 3, the control signal 16 causes the oscillation stop clip 70 tube 17 and the supply stop 711. In the operation stop state (4) in which both the flops 21 and 21 are set, the clock oscillation circuit 11 stops oscillating, and the reference clock,
If the oscillation restart request signal 23 is input during this operation stop state, the oscillation stop clip 70
The knob 17 is reset. As a result, the clock oscillation circuit 11 starts oscillating. However, as shown in the period t, the amplitude of the clock pulse is small and the oscillation is unstable.The 0 oscillation restart request signal 23 maintains a high level (logic 11) during this period of unstable oscillation.

When this signal changes from high level to low level, a high level output signal is outputted from the falling edge detector 25. As a result, the supply is stopped and the Tsuritsubukai flop 21
is reset, the AND gate 27 is opened, and the I2ing signal is supplied to the data processing section. As a result, the inside of the device enters a normal operating state (period number).

Next, the operation of the intermittent work state in which the supply of the timing signal to the data processing section is suppressed while the reference clock signal 9 is being generated from the clock oscillation circuit 11 will be explained using FIG. 4 during the 0 period. F*klstl is in the data processing state for periods tls1, . 1. is a processing abort state.

When setting a processing abort state, only the control signal 19 is generated. Therefore, the oscillation stop tree, PFLO, P17
remains reset, so the reference clock signal 1 remains reset.
is always occurring. That is, the clock oscillation circuit 11 executes a clock oscillation operation.

Now, when the supply stop 7 lip-flop 21 is set by the control signal 23, the timing signal is no longer supplied to the data processing section.

During this data processing stop state (period Fet4s!6), the black oscillation restart request signal 23 is input, and the high level (
When the logic level changes from logic ``l'') to low level (logic ``0''), a high level (logic ``l'') output signal is output and the supply is inhibited, and the P-flop 21 is turned off. As a result, the AND gate 27 is opened, a timing signal is supplied to the data processing section, and processing operation is started.

At this time, the black oscillation restart request signal 23 does not need to be generated for a long time to stabilize the oscillation, and the falling edge detector 2
The response time is fast because the detection time is only 5, and the detection time is 1g.
When the clock supply stop tree 21 is set again by the control signal 23 generated by the control section 2 in the figure g1, the above operation is repeated and the data processing section repeats the intermittent operation. .

According to the present invention, as explained above, in a data processing device that uses an oscillator such as a crystal oscillator, which takes several tens of milliseconds from the start of oscillation to stabilization of oscillation, as a reference clock signal generation source, Since it includes a first control means that stops signal generation itself and a second control means that prohibits only the supply of clock signals, low power consumption and high-speed processing response can be achieved by selectively using both. It is possible to improve both.

Further, according to the present invention, the data processing state of the data processing device can be easily selected from three types of control: normal operation, intermittent operation, and operation stop using an external input signal (which may be generated by program processing). , can be executed. In particular, the power consumption can be reduced from several tenths to several hundred times lower than in normal operation when the operation is stopped. Furthermore, since intermittent operation is determined by the time ratio between normal operation and stoppage of operation, it is easy to reduce power consumption. That is, 1
When the display section is driven intermittently, such as when displaying a clock, power consumption during operation can be saved by inhibiting the supply of black and white to the display section except during a predetermined period.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram of an embodiment of the present invention, FIG. 2 is a circuit configuration diagram showing an embodiment of the clock signal generation section of the present invention, and FIGS. 3 and 4 are operation timing diagrams, respectively. It is. 1... Data processing unit, 2... Control unit, 3.4...
Control signal, 5... Clock signal generator, 6... Clock signal %, 7... Oscillator clock input signal, 8.
... Output signal of the oscillator clock, 9.10... External input signal. 11... Black oscillation circuit, 12... Crystal oscillator,
13゜14... Capacitor, 15... Inverter,
16, i9... control signal, 20, 24.26...
OR gate, 18°27...AND gate, 17...
・Oscillation stop slip ・70 tube, 21...supply stop,
-Tree, booflop, 22...external input signal, 23
...Oscillation restart request signal t25...Detector at falling edge. z 1st evil □

Claims (1)

[Claims] a processing unit that processes a program under timing control by a clock signal; a clock generation unit that generates the clock signal; a relay unit that supplies the clock signal to the processing unit; and a relay unit that supplies the clock signal. means for selecting an inhibition control section for prohibiting the operation of supplying a clock signal to the processing section in the section and a spinning lock control section; A data processing device characterized by: