JP2731057B2 - comparator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in a comparator, and more particularly, to an improvement in a comparator with a small number of elements.

[0002]

2. Description of the Related Art FIG. 3 is a circuit diagram showing a main part of a conventional comparator, which includes a MOS transistor 1a and a current source 1b.
A first source follower circuit 1 composed of
It has a second source follower circuit 2 composed of a transistor 2a and a current source 2b, and a differential amplifier circuit 3 to which the outputs of the first and second source follower circuits are input. The current source 1b includes a MOS transistor 1c and a constant voltage source 1d, and the current source 2b includes a MOS transistor 2c and a constant voltage source 2d.

The MO of the first source follower circuit 1
First voltage A is input to the gate of the S transistor 1a, MOS transistor 1 of the second source follower circuits 2
b, the second voltage B is input to the gate of the differential amplifier 3
The output terminals 3A and 3B are connected to the input side of a logic circuit requiring the output of this comparator via a differential amplifier circuit and a latch circuit (not shown) at the next stage.

In such a configuration, the first source follower circuit 1 and the second source follower circuit 2 perform level adjustment and impedance conversion of the first voltage A and the second voltage B, and the first The difference between the outputs of the source follower circuit 1 and the second source follower circuit 2 is amplified by the differential amplifying circuit 3, and the magnitude relationship between the first voltage A and the second voltage B is determined based on the output of the comparator. it can.

[0005]

Although it is possible to determine the magnitude relationship between the first voltage A and the second voltage B even in the above-mentioned conventional configuration, since the number of elements is large, the device is not suitable. There is a disadvantage that it is difficult to reduce the size of the device. Particularly, in the case of a parallel type A / D converter using a large number of comparators, the size of the device is determined by the comparators. Therefore, in order to reduce the size of the A / D converter, a smaller comparator must be used. Must be used.

The present invention has been made in view of such unresolved problems of the prior art. In particular, in the configuration shown in FIG. 3, the current source 1b of the first source follower circuit 1 It is another object of the present invention to provide a comparator in which the size of the device can be reduced by eliminating the need for a constant voltage source for configuring the current source 2b of the second source follower circuit 2.

[0007]

In order to achieve the above object, the present invention provides a comparator for judging a magnitude relationship between first and second voltages, wherein the first source follower receives the first voltage. Circuit, a second source follower circuit to which the second voltage is input, and a differential amplifier circuit to which outputs of the first and second source follower circuits are input . The first source follower times
A first transistor whose output is supplied to the gate;
An output of the second source follower circuit is supplied to a gate.
And a second transistor
A first output corresponding to the first transistor;
Can output a second output corresponding to the second transistor
And outputs the first output to the first source follower circuit.
A positive feedback as a control voltage of a current source of the
The force was fed back as the control voltage of the current source of the second source follower circuit.

[0008]

The first output of the differential amplifier circuit is connected to the first source amplifier.
Positive feedback as a control voltage to the current source of the lower circuit,
When the second output of the width circuit is positively fed back to the current source of the second source follower circuit as a control voltage, for example, if the first voltage is larger than the second voltage, the first Since the current value of the current source of the source follower circuit decreases and the current value of the current source of the second source follower circuit increases, finally, the output of the first source follower circuit stabilizes at a high voltage level, The output of the source follower circuit is stabilized at a low voltage level. Conversely, when the second voltage is higher than the first voltage, the output of the first source follower circuit is stabilized at a low voltage level and the output of the second source follower circuit is high due to the reverse operation. Stabilizes at voltage level.

Therefore, the magnitude relationship between the first and second voltages can be determined based on the output of the differential amplifier circuit to which the outputs of the first and second source follower circuits are input.
The first output of the differential amplifier circuit is connected to the first source follower circuit.
Positive feedback as the control voltage of the current source
Even if the output of No. 2 is positively fed back as the control voltage of the current source of the second source follower circuit, the comparator operates normally.

[0010]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram of a comparator showing a configuration of one embodiment of the present invention. Note that the same components as those of the conventional comparator shown in FIG. 3 are denoted by the same reference numerals, and redundant description will be omitted.

That is, in this embodiment, of the output terminals 3A and 3B of the differential amplifier circuit 3, the output terminal 3A located on the drain side of the MOS transistor 3a to which the output of the first source follower circuit 1 is supplied, The first source follower circuit 1
The output terminal 3B located on the drain side of the MOS transistor 3b, to which the output of the second source follower circuit 2 is supplied, is connected to the gate of the MOS transistor 1c constituting the current source. MOS transistor 2 constituting a current source of second source follower circuit 2
The positive feedback circuit is formed by connecting to the gate of b. What
In this configuration, the MOS transistor 3a
The MOS transistor 3b is the second transistor as the first transistor.
The voltage of the output terminal 3A to the first output,
The voltage at the output terminal 3B corresponds to the second output.

The output of the differential amplifier circuit 3 is supplied to another differential amplifier circuit 4, and the output of the differential amplifier circuit 4 is supplied to a logic stage (not shown) via a latch circuit 5. ing. The gate of the MOS transistor 3c forming the current source of the differential amplifier circuit 3 and the gate of the MOS transistor 4c forming the current source of the differential amplifier circuit 4 generate an overlap pulse via the level shift circuit 6. The gate of the MOS transistor 5a connected to one output terminal 7A of the circuit 7 and constituting the current source of the latch circuit 5 is connected to the other output terminal 7B of the overlap pulse generation circuit 7 via the level shift circuit 8. Have been.

The overlap pulse generating circuit 7 includes a pair of NOR circuits 7a and 7
b and an inverter 7c, and the control signal C is
It is directly supplied to the NOR circuit 7a, and is supplied to the NOR circuit 7b via the inverter 7c. Therefore, the output of one output terminal 7A of the overlap pulse generating circuit 7 has the opposite phase to the control signal C, and the output of the other output terminal 7B has the same phase as the control signal C. However, the output of the NOR circuit 7a goes to the "L" level after the output of the NOR circuit 7b goes to the "H" level, and similarly, the output of the NOR circuit 7b becomes the "H" level of the output of the NOR circuit 7a. The signal which appears at the output terminals 7A and 7B of the overlap pulse generating circuit 7
"H" level states are signals that overlap each other.

The signal appearing at the output terminal 7A is adjusted in level by the level shift circuit 6, and then supplied to the gates of the MOS transistors 3c and 4c. That is, the differential amplifier circuits 3 and 4 are driven in synchronization with the output of the level shift circuit 6. The signal appearing at the output terminal 7B is supplied to the gate of the MOS transistor 5a after its level is adjusted by the level shift circuit 8. That is, the latch circuit 5 is driven in synchronization with the output of the level shift circuit 8.

Therefore, the overlap pulse generating circuit 7
Is a pulse signal which goes to “H” level in synchronization with the driving of the latch circuit 5. As a result,
The differential amplifier circuit drive signal D ₁ that is the output signal of the level shift circuit 6 becomes a pulse signal as shown in FIG. 2A, and the latch circuit drive signal D ₂ that is the output signal of the level shift circuit 8 is FIG. 2C shows a pulse signal as shown in FIG. 2B, showing the “H” level period of the differential amplifier circuit drive signal D ₁ , and FIG. 2C showing the “H” level period of the latch circuit drive signal D ₂ 2 (d), the “H” levels of both signals D ₁ and D ₂ overlap each other.

[0016] Incidentally, the differential amplifier circuit driving signal D ₁ and the latch circuit drive signal D ₂ is level adjusted by the level shift circuit 6, and 8 "H" value of level, MOS transistors 3c and 5a are driven by these Is an optimum value at which the maximum current value is obtained in the saturation region.
Now, towards the first voltage A When a higher potential than the second voltage B, the period differential amplifier drive signal D ₁ is at "H" level acts MOS transistor 3c is a constant current source Therefore, the MOS transistor 3a to which the output of the first source follower circuit 1 is supplied has a lower resistance than the MOS transistor 3b to which the output of the second source follower circuit 2 is supplied. And the output terminal 3B becomes high level.

Then, the current value of the MOS transistor 1c, which is the current source of the first source follower circuit 1, becomes smaller, the output of the first source follower circuit 1 becomes higher, and the current source of the second source follower circuit 2 becomes higher. MO
Since the current value of the S transistor 2c increases and the output of the second source follower circuit 2 further lowers,
The output terminal 3A is at a lower level, and the output terminal 3B is at a higher level.

As a result, finally, the output of the first source follower circuit 1 has substantially the same potential as the power supply _VDD, and the output of the second source follower circuit has substantially the ground potential. Further, the potential of the output terminal 3A stabilized at the power supply potential is supplied to the gate of the MOS transistor 4a of the differential amplifier circuit 4, and the potential of the output terminal 3B stabilized at the ground potential is set at the MOS potential of the differential amplifier circuit 4.
Since the voltage is supplied to the gate of the transistor 4b, the output terminal 4A of the differential amplifier circuit 4 goes to the "L" level, and the output terminal 4B
Attains an "H" level.

[0019] Then, before the differential amplifier circuit driving signal D ₁ becomes "L" level, since the latch circuit drive signal D ₂ is "H" level, the output of the differential amplifier circuit 4 to the latch circuit 5 Latched. That is, the comparator of this embodiment functions as a latched comparator having an output holding function. Further, the output of the latch circuit 5 is because while the latch circuit drive signal D ₂ is fed is maintained,
This is supplied to a logic stage (not shown) as an output of the comparator.

Therefore, in the logic stage, the magnitude relationship between the first voltage A and the second voltage B is determined based on the output of the latch circuit 5. After the latch circuit drive signal D ₂ is "H" level, if the differential amplifier circuit driving signal D ₁ is "L" level, the differential amplifier circuit 3 and 4 are cleared, then the differential The magnitude of the first voltage A and the second voltage B at the time when the amplifier circuit drive signal D ₁ has become “H” level is determined by the same operation as described above.

As described above, even in the configuration of the present embodiment, the output of the differential amplifier circuit 3 is positively fed back to the MOS transistor 1c of the first source follower circuit 1 and the MOS transistor 2c of the second source follower circuit 2. , Can operate normally as a comparator. Moreover, the number of elements is smaller than that of a conventional comparator which also uses a constant voltage source as a current source of the first source follower circuit 1 and the second source follower circuit 2, so that the size of the device can be reduced. For this reason, the comparator of the present embodiment is suitable for a parallel A / D converter and the like configured using a large number of comparators.

Further, as a result of forming the positive feedback circuit, even if the potential difference between the first voltage A and the second voltage B is very small, the outputs of the first source follower circuit 1 and the second source follower circuit are supplied to the power supply. Since the potential is stabilized at the potential or the ground potential, a high-precision comparator that can determine the magnitude relation of a minute potential difference can be provided.
Since it is unnecessary, the simplification of the differential amplifier circuit 4 can be achieved.
There are also advantages . Further, in the present embodiment, the differential amplifier circuit 3
And a differential amplifier circuit driving signal D ₁ that drives 4, since the latch circuit drive signal D ₂ that drives the latch circuit 5, a pulse signal is "H" level to each other and overlap, the operation of the latch circuit 5 There is an advantage that low power consumption can be achieved without any trouble.

[0023]

As described above, according to the present invention,
The first output of the differential amplifier is connected to the first source follower circuit.
Positive feedback as the control voltage of the current source
Due to the output of by the positive feedback as a control voltage of the current source of the second source follower circuit, an effect that with can be miniaturized devices become fewer elements, it can be determined to high accuracy the size relationship of the small potential difference is there.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of one embodiment of the present invention.

FIG. 2 is a waveform diagram of a differential amplifier circuit drive signal and a latch circuit drive signal.

FIG. 3 is a circuit diagram showing a main part of a conventional comparator.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 1st source follower circuit 1c MOS transistor (current source) 2 2nd source follower circuit 2c MOS transistor (current source) 3,4 Differential amplifier circuit 5 Latch circuit 6,8 Level shift circuit 7 Overlap pulse generation circuit

 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-61-120515 (JP, A) JP-A-57-111116 (JP, A)

Claims (1)

(57) [Claims] 1. A comparator for determining a magnitude relationship between first and second voltages, a first source follower circuit to which the first voltage is input, and a second source follower to which the second voltage is input. And a differential amplifier circuit to which the outputs of the first and second source follower circuits are input. The differential amplifier circuit includes an output of the first source follower circuit.
A first transistor in which a force is applied to a gate;
The output of the second source follower circuit is supplied to the gate.
And a transistor comprising:
A first output corresponding to a first transistor and the second output
Can output the second output corresponding to the
And the first output is a current source of the first source follower circuit.
Wherein the second output is positively fed back as a control voltage of a current source of the second source follower circuit.