JP2540767B2 - Differential amplifier circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a differential amplifier circuit,
In particular, it relates to a differential amplifier designed to reduce the power supply current.

[0002]

BACKGROUND OF THE INVENTION conventional differential amplifier circuit, for example, referring to FIG. 3 which shows a circuit diagram of a configuration includes an input stage 57 and output stage 58 and an output terminal 22, input stage 57 includes a source The drain electrode of the NMOS transistor 575 whose electrode is connected to the low potential power supply terminal 24 and the high potential power supply terminal 20
A first series connection circuit in which a PMOS transistor 571 and an NMOS transistor 572 are inserted in series and a PMOS transistor 573 and an NMOS transistor 574 are inserted in series between them, and this series connection point is used as the output end 551 of the input stage. A second series connection circuit. The series connection point of the first series connection circuit is commonly connected to the gate electrodes of the PMOS transistors 571 and 573, the gate electrode of the NMOS transistor 572 is the non-inverting input terminal, the gate electrode of the NMOS transistor 574 is the inverting input terminal, and the NMOS electrode 574 is the inverting input terminal. The gate electrodes of the transistors 575 are connected to the bias power supply, respectively, to form a differential amplifier.

The output stage 58 includes an NMOS transistor 581 between the high potential power supply terminal 20 and the low potential power supply terminal 24.
And 582 are inserted in series connection, and a fourth series connection circuit in which a PMOS transistor 583 and an NMOS transistor 584 are inserted in series and the series connection point is connected to the output terminal 22 is provided. . The series connection point of the third series connection circuit is connected to the gate electrode of the NMOS transistor 584, the gate electrodes of the NMOS transistor 581 and the PMOS transistor 583 are commonly connected to the output end 551 of the input stage, and the phase correction capacitance element 585 is connected. The gate electrode of the constant current source NMOS transistor 582 is also connected to the output terminal 22 via the.

This differential amplifier circuit is a level shift NM.
The idling current of the output transistor is determined by the potential difference between the gate and source electrodes of the OS transistor 581, and a low-current class AB differential amplifier circuit is obtained.

An example of another conventional differential amplifier circuit is described in Japanese Patent Application Laid-Open No. 60-90407. Referring to FIG. 4, this differential amplifier has an input stage 59 and an output stage 6
0, an output terminal 22, a first bias power supply 596 and a second bias power supply 597, a first output end 598 and a second output end 599.

In the input stage 59, the NMOS transistor 591 is inserted between the drain electrode of the NMOS transistor 593 whose source electrode is connected to the low power supply terminal 24 and the first output terminal 598, and the drain electrode of the NMOS transistor 593 and the second electrode The NMOS transistor 592 is inserted between the output terminals 599 of the
The gate electrode of 91 is connected to the non-inverting input terminal 594,
The gate electrode of the transistor 592 is the inverting input terminal 595.
In addition, the gate electrode of the NMOS transistor 593 is connected to the bias power source 597.

The output stage 60 includes a first series connection circuit in which PMOS transistors 601 and 602 and an NMOS transistor 603 are inserted in series between the high potential power supply terminal 20 and the low potential power supply terminal 24, a PMOS transistor 604 and a first series connection circuit. 605 and NMOS transistor 606
And a second series connection circuit in which and are inserted in series connection, a bias terminal 1, and an output terminal 22.

PMOS transistors 601 and 602
Is connected to the first output terminal 598 of the input stage through a PMOS.
The series connection points of the transistors 604 and 605 are connected to the second output terminal 599 of the input stage, respectively. The series connection point of the PMOS transistor 602 and the NMOS transistor 603 is the NMOS transistors 603 and 606.
Are commonly connected to the gate electrodes of the
05 and the NMOS transistor 606 are connected in series to the output terminal 22.

Further, the gate electrodes of the PMOS transistors 601 and 604 are connected to the bias terminal 1, and the gate electrodes of the PMOS transistors 602 and 605 are connected to the bias power source 596, respectively.

In this differential amplifier circuit, PMOS transistors 601, 602, 604, and 605 form a faulted cascade circuit, and output signals supplied from the first and second output terminals of the input stage are supplied to NMOS transistors 603 and 605, respectively. It leads to the active load circuit comprised by 606.

According to this structure, a differential amplifier circuit having a wide output voltage range at a low power supply voltage can be obtained.

[0012]

In the differential amplifier circuit shown in FIG. 3 described above, the idling current of the output transistor is the gate-source electrode voltage of the output PMOS transistor 583 and the level shift NMOS transistor 5.
Since it is determined by the sum of the gate-source voltage of 81 and the gate-source electrode voltage of the output NMOS transistor 584, it is affected by the fluctuation of the power supply voltage or the fluctuation of the threshold voltage of the transistor. Especially, when the power supply voltage is low, the influence is great, and it has been difficult to cope with the recent low power supply voltage.

On the other hand, in the differential amplifier shown in FIG. 4, it is difficult to reduce the current because the output circuit operates in class A.
Further, since the voltage amplifying stage is composed of one stage, it is difficult to obtain a high gain especially when the power source voltage is low.

The object of the present invention was made in view of the above-mentioned drawbacks, and the drawbacks of the prior art are eliminated, and when the power source voltage is low, the fluctuation of the power source voltage or the fluctuation of the threshold voltage of the transistor is small, and the power source current is small. It is to provide a differential amplifier circuit with reduced power consumption.

[0015]

The features of the differential amplifier circuit of the present invention are that an input stage for differentially amplifying an input signal, a driver stage for driving and outputting the amplified signal, and a push-pull for this driving output. An output stage that outputs in operation, a bias voltage generation circuit that supplies a bias voltage to the driver stage, a first current mirror circuit and a second current mirror that supply the output current of the input stage to the driver stage by a current mirror A first PMO between the high potential power supply terminal and the first current terminal of the first current mirror circuit.
A first series connection circuit in which an S transistor and a second PMOS transistor are inserted in series connection, and a third PMOS transistor and a third PMOS transistor are provided between the high potential power supply terminal and the second current terminal of the second current mirror circuit. And a second series connection circuit in which four PMOS transistors are inserted in series connection, the gate electrodes of the first and third PMOS transistors are respectively connected to a first bias terminal, and the second bias circuit is connected to the second bias circuit. And the gate electrodes of the fourth PMOS transistor are respectively connected to the second bias terminal, and the source electrode of the first NMOS transistor whose drain terminal is connected to the series connection point of the first series connection circuit and the source electrode of the first NMOS transistor. The source electrode of the second NMOS transistor having the drain electrode connected to the series connection point of the second series connection circuit is connected to each other. A third NMOS transistor is inserted between this connection point and the low potential power supply terminal, the gate electrode of the first NMOS transistor is a non-inverting input terminal, and the gate electrode of the second NMOS transistor is an inverting input terminal. , A gate electrode of the third NMOS transistor is connected to a third bias terminal, and the driver stage is connected between a high potential power supply terminal and a second current terminal of the first current mirror circuit. A third series connection circuit in which a fifth PMOS transistor and a fourth NMOS transistor are inserted in series connection, and a sixth PMOS transistor between the high potential power supply terminal and the second current terminal of the second current mirror circuit. And the fifth NM
A fourth series connection circuit in which an OS transistor is inserted in series connection, and the series connection point of the third series connection circuit is commonly connected to the gate electrodes of the fifth and sixth PMOS transistors. The gate electrodes of the fourth and fifth NMOS transistors are connected to the bias voltage output terminal of the bias voltage generating circuit,
The drain electrode of the fifth NMOS transistor is the first
Of the first NMOS transistor and the source electrode of the fifth NMOS transistor as a second output terminal of the first NMOS transistor.
In the current mirror circuit, the sixth, seventh and eighth NMOS transistors are respectively connected between the first, second and third current terminals and the low potential power supply terminal, and the sixth mirror is connected. The drain electrode and the gate electrode of the NMOS transistor are configured to be commonly connected to the gate electrodes of the seventh and eighth NMOS transistors, and the second current mirror circuit includes first, second and third current terminals. Between the low potential power supply terminal and the
MOS transistors are connected correspondingly, and the drain electrode and gate electrode of the ninth NMOS transistor are commonly connected to the gate electrodes of the tenth and eleventh NMOS transistors, and the output stage is A seventh PMOS transistor and a twelfth NMOS transistor are inserted in series between the high-potential power supply terminal and the low-potential power supply terminal, the series connection point is connected to the output terminal, and the gate electrode of the seventh PMOS transistor is connected. Are respectively connected to the output terminal via the first output end of the driver stage and the phase correction capacitance element, and the gate electrode of the twelfth NMOS transistor is connected to the second output end of the driver stage. The bias voltage generation circuit is configured to have a high potential power supply terminal and a low potential Together with the 8 PMOS transistors and the 13 NMOS transistor of between source terminal is inserted in series to the series connection point between the bias voltage output terminal, the high potential power supply terminal and the first 13 NMOS of
Fourteenth NM inserted between the gate electrodes of the transistor
The first electrode is also connected to the gate electrode of the OS transistor.
The gate electrode of the third NMOS transistor is commonly connected to the third current terminal of the first current mirror circuit and the third current terminal of the second current mirror circuit, and the eighth PMO
In that the gate electrode of the S transistor is configured to be connected to the first bias terminal.

[0016]

Embodiments of the present invention will now be described with reference to the drawings.

First, the related technology of the embodiment of the present invention will be described.
Bell. FIG. 1 is an equivalent circuit diagram showing this related technique . Referring to FIG. 1, this differential amplifier circuit includes an input stage 51, an output stage 52, and a bias voltage generation circuit 50 that supplies a bias voltage to the input stage 51 and the output stage 52.

The input stage 51 includes a PMOS transistor 11 between the high potential power supply terminal 20 and the low potential power supply terminal 24.
And PMOS transistor 15 and NMOS transistor 1
4 are inserted in series, and the PMOS transistor 16, the PMOS transistor 17, and the NMOS transistor 18 are inserted.
Are connected in series.

The gate electrodes of the NMOS transistors 14 and 18 are commonly connected to the drain electrode of the NMOS transistor 14, and the gate electrodes of the PMOS transistors 11 and 16 are connected to the first bias terminal 1 and P, respectively.
The gate electrodes of the NMOS transistors 15 and 17 are the bias voltage output terminals 50 of the bias voltage generation circuit 50.
1 are connected respectively.

Further, an NMOS having a drain electrode connected to the series connection point of the PMOS transistors 11 and 15
The source electrode of the transistor 8 and the source electrode of the NMOS transistor 12 whose drain terminal is connected to the series connection point of the PMOS transistors 16 and 17 are connected in common, and N is connected between this common connection point and the low potential power supply terminal 24.
The MOS transistor 13 is inserted. The gate electrode of the NMOS transistor 8 is connected to the non-inverting input terminal 9,
The gate electrode of the transistor 12 is connected to the inverting input terminal 10,
The gate electrode of the NMOS transistor 13 is connected to the second bias terminal 4 and the PMOS transistor 1
7 and the NMOS transistor 18 are connected in series as the signal output terminal 510 of the input stage, and the PMOS transistor 16
And a PMOS transistor 17 connected in series are used as the signal output terminal 511 of the input stage.

The output stage 52 includes a PMOS transistor 21 between the high potential power supply terminal 20 and the low potential power supply terminal 24.
And an NMOS transistor 23 are connected in series, and this series connection point is connected to the output terminal 22 and PM
The gate electrode of the OS transistor 21 is connected to the signal output terminal 511 of the input stage, and the gate electrode of the NMOS transistor 23 is connected to the output terminal 510 of the input stage and the output terminal 22 via the capacitive element 510, respectively. There is.

The bias voltage generating circuit 50 includes a first series connection circuit in which PMOS transistors 6 and 7 are inserted in series between the high potential power supply terminal 20 and the low potential power supply terminal 24, the PMOS transistor 2 and the NMOS transistor 3. And a second series connection circuit inserted in series connection.

The series connection point of the first series connection circuit is commonly connected to the drain electrode of the NMOS transistor 5 and the gate electrode of the PMOS transistor 2 whose source electrode is connected to the low potential power source 24, and the second series connection circuit is connected. Is connected to the gate electrode of the PMOS transistor 7 as the bias voltage output terminal 501.

Further, the gate electrode of the PMOS transistor 6 is connected to the first bias terminal 1, and the gate electrode of the NMOS transistor 3 is connected to the second bias terminal 4.

In this differential amplifier circuit, a differential input circuit is constituted by NMOS transistors 8, 12 and 13, and a PMO
The S transistors 11, 15, 16 and 17 form a faulted cascade circuit. NMOS transistors 14 and 18 are the active loads of the faulted cascade circuit.

The source and drain electrodes of the PMOS transistor 17 become the output of the input stage 51, and drive the output PMOS transistor 21 and the NMOS transistor 23, respectively, in the same phase.

The PMOS transistor 6 operates in cooperation with the PMOS transistors 11 and 16 in response to the voltage of the first bias terminal 1, and the PMOS transistor 7 is PM.
In response to the bias voltage output of the drain electrode of the OS transistor 2, the PMOS transistors 15 and 17 operate in cooperation with each other, and the PMOS transistor 5 operates in cooperation with the NMOS transistor 13 in response to the voltage of the second bias terminal 4.

Therefore, the potential of the source electrode of the PMOS transistor 7 is PM when the differential input voltage is 0 level.
It becomes equal to the potential of the source electrodes of the OS transistors 15 and 17.

From this, the bias voltage generating circuit 50
PMOS transistor 2 and PMOS of output stage 52
The drain current of the transistor 21 has a constant ratio,
The value obtained by multiplying this ratio by the drain current of the NMOS transistor 3 is controlled to be the idling current.

Next, an embodiment of the present invention will be described. FIG.
[Fig. 3] is an equivalent circuit diagram of one embodiment. Referring to FIG. 2, the differential amplifier circuit includes an input stage 54 for differentially amplifying an input signal of the differential amplifier, a driver stage 55 for driving and outputting the amplified signal, and a push-pull operation for outputting the driving output. Bias voltage generating circuit 53 for supplying bias voltage to output stage 56 and driver stage 55, and first current mirror circuit 57 and second current mirror circuit for supplying output current of input stage 54 to driver stage 55 by a current mirror. And 58.

The input stage 54 has a P terminal between the high potential power supply terminal 20 and the first current terminal 531 of the first current mirror circuit 57.
The MOS transistors 40 and 38 are inserted in series connection, and the high potential power supply terminal 20 and the second current mirror circuit 5 are inserted.
The PMOS transistors 41 and 39 are connected in series between the eight current terminals 541.

The gate electrodes of the PMOS transistors 40 and 41 are connected to the first bias terminal 48, and the gate electrodes of the PMOS transistors 38 and 39 are connected to the second bias terminal 47, respectively.

Further, an NMOS whose drain electrode is connected to the series connection point of the PMOS transistors 40 and 38
The source electrode of the transistor 8 and the source electrode of the NMOS transistor 12 whose drain electrode is connected to the series connection point of the PMOS transistors 41 and 39 are connected in common, and N is connected between this common connection point and the low potential power supply terminal 24.
The MOS transistor 13 is inserted. The gate electrode of the NMOS transistor 8 is connected to the non-inverting input terminal 10 by the NMO.
The gate electrode of the S transistor 12 is connected to the inverting input terminal 9,
The gate electrode of the NMOS transistor 13 is configured to be connected to the third bias terminal 4, respectively.

In the driver stage 55, the PMOS transistor 42 and the NMOS transistor 36 are connected in series between the high potential power supply terminal 20 and the second current terminal 532 of the first current mirror circuit 57, and the high potential power supply terminal 20 and The PMOS transistor 43 and the NMOS transistor 37 are connected in series between the second current terminals 542 of the second current mirror circuit 58.

The gate electrode and drain electrode of PMOS transistor 42 are commonly connected to the gate electrode of PMOS transistor 43, and the gate electrodes of NMOS transistors 36 and 37 are connected to the bias voltage output terminal of bias voltage generating circuit 53. The drain electrode of the NMOS transistor 37 becomes the output end 551,
The source electrode of the transistor 37 is configured to be the output terminal 552.

The first current mirror circuit 57 includes a first current mirror circuit 57 and a second current mirror circuit 57.
And NMOS transistors 30, 32 between the third current terminals 531, 532 and 533 and the low potential power supply terminal 22.
And 34 are correspondingly connected, and the drain electrode and the gate electrode of the NMOS transistor 30 are NMO.
The gate electrodes of S transistors 32 and 34 are commonly connected.

The second current mirror circuit 58 includes the first and second current mirror circuits.
And NMOS transistors 31, 33 between the third current terminals 541, 542 and 543 and the low potential power supply terminal 22.
And 35 are correspondingly connected, and the drain electrode and the gate electrode of the NMOS transistor 31 are NMO.
The gate electrodes of S transistors 33 and 35 are commonly connected.

In the output stage 56, the PMOS transistor 21 and the NMOS transistor 23 are inserted in series between the high potential power supply terminal 20 and the low potential power supply terminal 24, and the series connection point is connected to the output terminal 22 and P
The gate electrode of the MOS transistor 21 is connected to the output terminal 22 via the output end 551 of the driver stage and the phase correction capacitance element 19, and the NMOS transistor 2
3 gate electrodes are connected to the output 552 of the driver stage 55.

In the bias voltage generating circuit 53, a PMOS transistor 45 and an NMOS transistor 46 are inserted in series between the high-potential power supply terminal 20 and the low-potential power supply terminal 24, and the series connection point is used as a bias voltage output terminal and a high potential. It is also connected to the gate electrode of the NMOS transistor 44 inserted between the power supply terminal 20 and the gate electrode of the NMOS transistor 46.

The gate electrode of the NMOS transistor 46 is commonly connected to the source electrode of the NMOS transistor 44, the third current terminal 533 of the first current mirror circuit 57 and the third current terminal 543 of the second current mirror circuit 58. ,
The gate electrode of the PMOS transistor 45 is configured to be connected to the first bias terminal 48.

The differential amplifier circuit according to this configuration has the input stage 5
The NMOS transistors 8, 12 and 13 of FIG. 4 form a differential amplifier circuit, and the PMOS transistors 38, 39, 40 and 41 form a faulty cascade circuit, and the output current of the input stage 54 is current-mirrored to drive the driver stage 55. Communicate to.

The NMOS transistors 36 and 37 in the driver stage operate as a gate ground level shift circuit using the PMOS transistors 42 and 43 as active loads,
In response to the bias voltage output supplied from the bias voltage generating circuit 53, the drain and source electrodes of the NMOS transistor 37 push-pull-drive the output PMOS transistor 21 and the NMOS transistor 23, respectively.

The NMOS transistor 44 of the bias voltage generating circuit 53, the NMOS transistor 34 of the first current mirror circuit 57 and the NM of the second current mirror circuit 58.
The OS transistor 35 operates as a source follower circuit and serves as a negative feedback circuit for the NMOS transistor 46.
Steady state.

The NMOS transistor 44 operates in cooperation with the NMOS transistors 36 and 37 in the driver stage in response to the bias voltage output supplied from the series connection point of the PMOS transistor 45 and the NMOS transistor 46, and the NMOS transistor 44 of the first current mirror circuit 57 operates. The NMOS transistor 34 and the NMOS transistor 35 of the second current mirror circuit 58 are responsive to the drain voltages of the NMOS transistors 30 and 31, respectively.
And 33 together. Therefore, when the differential input voltage is 0 level, the potentials of the source electrodes of the NMOS transistors 44 and 37 are equal to each other.

Therefore, the drain currents of the NMOS transistor 44 of the bias voltage generating circuit 53 and the NMOS transistor 23 of the output stage have a constant ratio, and the value obtained by multiplying this ratio by the drain current of the PMOS transistor 45 of the bias voltage generating circuit 53 is obtained. , It is controlled so that the idling current of the output stage is obtained.

[0046]

As described above, in the differential amplifier circuit of the present invention, the idling current of the output stage transistor is
The gate-source voltage (Vgs1) of the output PMOS transistor, the gate-source voltage (Vgs2) of the output NMOS transistor, and the output PMOS
It is determined by the sum of the transistor and the source-drain voltage of the respective level shifting N MOS transistor inserted between a gate electrode of the NMOS transistor (Vds). That is, assuming that the gate-source voltage of the level shift is Vgs3, when comparing the idling current with the conventional example, in the case of the present invention, Vgs1 + Vgs2.
+ Vds In the case of the conventional example, Vgs1 + Vgs2 + Vgs
Since the absolute value of the source-drain voltage Vds is smaller than the absolute value of the gate-source voltage Vgs, the fluctuation of the power supply voltage or the threshold of the transistor in the recent low power supply voltage (3V) can be achieved. A great effect can be obtained in reducing the current of the differential amplifier circuit, which is less affected by voltage fluctuations.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a related technique of an embodiment of the present invention.

FIG. 2 is a circuit diagram showing an embodiment of the present invention.

FIG. 3 is a circuit diagram showing a conventional example.

FIG. 4 is a circuit diagram showing another conventional example.

[Explanation of symbols]

1 1st bias terminal 2,6,7,11,15-17,21,38-43
PMOS transistors 3, 5, 8, 12, 13, 14, 18, 23, 30 to 3
5, 36, 37, 44, 46 NMOS transistor 4 Second bias terminal 9 Inversion input terminal 10 Non-inversion input terminal 20 High potential power supply terminal 22 Output terminal 24 Low potential power supply terminal 50, 53 Bias voltage generation circuit 51, 54 Input Stage 52, 56 Output stage 55 Driver stage 57 First current mirror circuit 58 Second current mirror circuit

Claims (1)

(57) [Claims] 1. An input stage that differentially amplifies an input signal, a driver stage that drives and outputs the amplified signal, an output stage that outputs the drive output by a push-pull operation, and a bias voltage is supplied to the driver stage. A bias voltage generation circuit for
A first current mirror circuit and a second current mirror circuit that supply the output current of the input stage to the driver stage by a current mirror; the input stage has a high-potential power supply terminal and the first current mirror circuit. A first series connection circuit in which a first PMOS transistor and a second PMOS transistor are inserted in series between the first current terminals of, a high-potential power supply terminal and a second current of the second current mirror circuit. Third PMO between terminals
A second series connection circuit in which an S transistor and a fourth PMOS transistor are inserted in series connection, and gate electrodes of the first and third PMOS transistors are respectively connected to a first bias terminal. , The gate electrodes of the second and fourth PMOS transistors are respectively connected to the second bias terminal, and the drain terminal of the first NMOS transistor is connected to the series connection point of the first series connection circuit. A source electrode and a source electrode of a second NMOS transistor having a drain electrode connected to a series connection point of the second series connection circuit are connected to each other, and a third electrode is connected between this connection point and the low potential power supply terminal. N
A MOS transistor is inserted, and the gate electrode of the first NMOS transistor is connected to the non-inverting input terminal of the second NMOS transistor.
The gate electrode of the NMOS transistor is connected to the inverting input terminal and the gate electrode of the third NMOS transistor is connected to the third bias terminal, respectively. The driver stage includes a high potential power supply terminal and the first bias terminal. Of the third series connection circuit in which the fifth PMOS transistor and the fourth NMOS transistor are inserted in series between the second current terminals of the current mirror circuit, the high potential power supply terminal and the second current mirror circuit. A fourth series connection circuit in which a sixth PMOS transistor and a fifth NMOS transistor are inserted in series between the second current terminals, and the series connection point of the third series connection circuit is the fifth connection point. And the gate electrodes of the sixth PMOS transistor are commonly connected to the fourth and fifth NMOS transistors.
The gate electrode of each of the transistors is connected to the bias voltage output terminal of the bias voltage generating circuit, and the fifth N
The drain electrode of the MOS transistor serves as a first output terminal, and the source electrode of the fifth NMOS transistor serves as a second output terminal; the first current mirror circuit includes first, second, and Sixth, seventh, and eighth NMOS transistors are respectively connected between the third current terminal and the low-potential power supply terminal, and the drain electrode and the gate electrode of the sixth NMOS transistor are connected to the seventh electrode. And a common electrode connected to the gate electrodes of the eighth NMOS transistor; the second current mirror circuit includes an eighth circuit between the first, second and third current terminals and the low potential power supply terminal, 9th and 1st
0 NMOS transistors are correspondingly connected, and the drain electrode and the gate electrode of the ninth NMOS transistor are commonly connected to the gate electrodes of the tenth and eleventh NMOS transistors, respectively. Is a seventh PMOS transistor and a twelfth NMOS between the high potential power supply terminal and the low potential power supply terminal.
Transistors are inserted in series connection, the series connection point is connected to the output terminal, and the gate electrode of the seventh PMOS transistor is output through the first output end of the driver stage and the phase correction capacitance element. And a gate electrode of the twelfth NMOS transistor connected to a second output terminal of the driver stage. The bias voltage generating circuit includes a high potential power supply terminal and a low potential power supply terminal. An eighth PMOS transistor and a thirteenth NMOS transistor are inserted in series between them, and the series connection point serves as the bias voltage output terminal, and
The thirteenth NMOS is also connected to the high-potential power supply terminal and the gate electrode of the fourteenth NMOS transistor inserted between the gate electrodes of the thirteenth NMOS transistor.
A gate electrode of the transistor is commonly connected to a third current terminal of the first current mirror circuit and a third current terminal of the second current mirror circuit, and a gate electrode of the eighth PMOS transistor is connected to the first current terminal of the first current mirror circuit. A differential amplifier circuit configured to be connected to a bias terminal.