JP2638252B2 - High-speed bus circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus circuit that can operate at high speed in a semiconductor integrated circuit such as a microcomputer.

2. Description of the Related Art In recent years, increasing the speed of microcomputers is one of important issues, and bus circuits are also an object of this.

FIG. 3 is a block diagram showing a configuration example of a high-speed bus circuit in a conventional semiconductor integrated circuit. 200 is a positive logic bus, 201 is a negative logic bus, 202 is a bus output circuit, 203 is a precharge circuit, 204 is a level difference amplifier circuit, and 205 is an input latch. The relationship and operation of the above components will be described.

First, the pre-jurch circuit 203 equalizes the levels of the positive logic bus 200 and the negative logic bus 201 at, for example, an intermediate level between a high level and a low level. Next, the bus output circuit 202
Output a positive logic and a negative logic having a low output level to a positive logic bus 200 and a negative logic bus 201, respectively. Next, the positive logic and the negative logic whose output levels are low are input to the level difference amplifier circuit 204 from the positive logic bus and the negative logic bus, and are amplified to a normal high or low level. Capture data.

The reason why this bus circuit is high-speed is that the output levels of the positive logic and the negative logic output from the bus output circuit 202 are low, and the time required to reach the levels is shortened. In addition, when the low level positive logic and negative logic are taken into the input latch 205, they are compensated for by amplifying to a regular level by the level difference amplifying circuit 204.

Problems to be Solved by the Invention In such a conventional high-speed bus circuit, since two buses, a positive logic bus and a negative logic bus, are required, the amount of hardware increases, and particularly when the bus is built in a semiconductor integrated circuit. Has a problem that the chip area is increased and the cost is disadvantageous.

An object of the present invention is to provide a high-speed bus circuit which can operate at high speed and can be realized without greatly increasing the amount of hardware.

Means for Solving the Problems In order to achieve the above object, the present invention provides a high-speed bus circuit which controls a bus control circuit for generating a control signal and a precharge signal or a discharge signal from the bus control circuit. A level setting circuit for connecting a bus to a power supply or a ground; and an amplification enable signal from the bus control circuit as a control signal. A first input terminal and an output terminal are connected to the bus, and a second A differential amplifier having an input terminal connected to a switching circuit, a switching signal from the bus control circuit as a control signal, and one end connected to the bus or a second input terminal of the differential amplifier. A switching circuit for connecting a common terminal to one of the connected other ends, one end connected to the common terminal of the switching circuit, and the other end connected to ground. A level holding circuit, a bus output signal from the bus control circuit as a control signal, a bus output circuit having an output terminal connected to the bus, and an input enable signal from the bus control circuit as a control signal, A data latch circuit having an input terminal connected to the bus.

Operation With this configuration, before the data is input to the bus from the bus output circuit by the level setting circuit, the potential level of the bus and the level holding circuit is set to an intermediate level between the high level and the low level, and the level holding circuit The intermediate level is stored. Thereafter, data having a small level change is input from the bus output circuit to the bus, and a differential amplifier amplifies a level change of the input data with respect to an intermediate level stored in the level holding circuit, and amplifies the amplified bus level as data. It can be input to a latch circuit. Therefore, the level change of the data input from the bus output circuit to the bus may be small, so that the rise time of the input waveform of the bus output circuit is short, and even if the bus drive is performed with a small level change, the differential amplifier may be used. By amplifying, a bus level having a regular high level or low level with a large level change can be obtained.

Hereinafter, a high-speed bus circuit according to the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a high-speed bus circuit according to one embodiment of the present invention.

As shown, the transistor 101 is connected to the bus control circuit 1
The precharge signal 110 from 08 is used as a gate input, the drain is connected to the power supply, and the source is connected to the bus 100. The transistor 102 has a discharge signal 109 from the bus control circuit 108 as a gate input, a source connected to ground (earth), and a drain connected to the bus 100. These transistors 101 and transistor 1
02 constitutes a level setting circuit for setting the potential level of the bus 100.

The differential amplifier 105 uses the amplification enable signal 113 from the bus control circuit 8 as a control signal, has a first input terminal 115 (in-phase input terminal) and an output terminal connected to the bus 100, and has a second input terminal 116 ( The input terminal of the opposite phase) is connected to the changeover switch 103.

The changeover switch 103 uses a changeover signal 114 from the bus control circuit 108 as a control signal, and outputs one end connected to the bus 100 or the other end connected to the second input end 116 of the differential amplifier 105. It becomes a switching circuit for connecting a common terminal to one of them. One end of a capacitor 104 serving as a level holding circuit is connected to a common terminal of the changeover switch 103, and the other end of the capacitor 104 is connected to the ground.

The bus output circuit 106 uses a bus output signal 111 from the bus control circuit 108 as a control signal, and has an output terminal connected to the bus 100.

The data latch circuit 107 uses an input enable signal 112 from the bus control circuit 108 as a control signal, and has an input terminal connected to the bus 100.

The operation of the above configuration will be described with reference to FIG. FIG. 2 is a timing chart showing the operation of the embodiment. Hereinafter, a description will be given assuming that the high level of data on the bus 100 is 5 volts and the low level is 0 volts.

At the first timing, that is, at the rise of the precharge signal 110, the transistors constituting the level setting circuit
The gate of 101 is turned on, the bus 100 is connected to the power supply via the transistor 101, while the discharge signal as the gate input of the transistor 102 is turned off. Further, the capacitor 104 constituting the level holding circuit is connected to the bus 100 via the changeover switch 103. At this time, by connecting the bus 100 to the power supply via the transistor 101, the potential of the bus 100 and the potential of the capacitor 104 are set to an intermediate level between the high level and the low level, for example, 3 volts (timing ([A] section of the chart).

Subsequently, the second timing, that is, the bus output signal 111
At the same time, data is output from the bus output circuit 106 to the bus 100, and at the same time, the switching signal 114 from the bus control circuit 108 is turned on. And the level of the bus 100 before data is input from the bus output circuit 106 is input to the differential amplifier 105 (section [B] of the timing chart). At this time, when the data input from the bus output circuit 106 is at a high level, when the data input from the bus output circuit 106 is at a high level, the set level is further increased as shown in the bus state (when sending 5 V) as shown in the figure. Changes to further lower the set level as shown in the bus state (when sending 0V), but does not change up to 5 volts or 0 volts. The reason is that the output capability of the bus output circuit 106 is generally low, which is a common problem in the circuit configuration of a microcomputer or the like.

Subsequently, the differential amplifier 105 is operated at the third timing, that is, the rising timing of the amplification enable signal 113, and the level difference between the first input terminal 115 and the second input terminal 116, that is, the change from the intermediate level Amplify the minute and bath
Output to 100. This amplification amplifies small bus level changes and changes the bus level to 5 or 0 volts. At the same time, the input enable signal 112, which is a control signal for the data latch circuit 107, is turned on, and the level of the bus 100 is taken into the data latch circuit 107. This amplification operation has a very large gain because it performs positive feedback amplification.
Therefore, the voltage reaches 5 volts or 0 volts in a short time and is fixed to that level (section [C] of the timing chart).

Subsequently, at the fourth timing, that is, at the timing of the rise of the discharge signal 109, the gate of the transistor 102 constituting the level setting circuit is turned on, and the bus 100
Is connected to the ground via the transistor 102, and at the same time, the switching signal 114 from the bus control circuit 108 is turned off.
Connected to one end connected to 100. At this time,
The potential of the capacitor 104 and the bus 100 is
To 0 volts, that is, the ground potential (section [D] of the timing chart).

With the above continuous operation, for 1-bit data, data transmission from the bus output circuit and data capture to the data latch circuit are completed.

Thus, according to the embodiment of the present invention, the bus output circuit 10
Before the data is input from 6, the level of the bus 100 is set to an intermediate level between the high level and the low level, and a small level change of the bus 100 before and after the data input from the bus output circuit 106 is amplified by the differential amplifier 105. Since the amplified bus level is input to the data latch circuit 107, the change in the data level from the bus output circuit 106 can be small.
Even if the rise time of the input waveform of the bus output circuit 106 can be shortened and the bus drive is performed with a small level change,
By amplifying, a bus level having a regular high level or low level can be obtained.

In the above embodiment, the bus level before data is input from the bus output circuit is set to 3 volts. However, as will be understood from the description, the differential amplifier amplifies a small level change before and after data input and outputs data. It is needless to say that the level setting of the bus before data input may be another voltage level as long as the level is intermediate between the high and low levels of the input data.

As is clear from the above embodiment, the present invention sets the bus level to an intermediate level between the high level and the low level before data is input from the bus output circuit, and then changes the level of the bus from the bus output circuit to a small level change. Data input, and the differential amplifier amplifies a small level change of the bus before and after the data input, and inputs the amplified bus level to the data latch circuit. Therefore, the change in the data input level of the bus output circuit may be small. The rise time of the input waveform of the bus output circuit can be shortened, and even if the bus drive is performed with a small level change, a bus level having a regular high level or low level with a large change can be obtained by amplification. . Therefore, by shortening the rise time of the input waveform, high-speed operation of the bus circuit is enabled, and the bus circuit can be configured with one bus line, so that an effect that the circuit configuration is simplified can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of a high-speed bus circuit according to one embodiment of the present invention, FIG. 2 is a timing chart showing the operation of the high-speed bus circuit according to one embodiment of the present invention, and FIG. FIG. 3 is a block diagram illustrating a configuration of a circuit. 100 Bus 101 Transistor (level setting circuit) 102 Transistor (level setting circuit) 103 Switch (switching circuit) 104 Capacitor (level holding circuit) 105 Differential amplifier 106 Bus Output circuit 107 Data latch circuit 108 Bus control circuit 109 Discharge signal (control signal at fourth timing) 110 Precharge signal (control signal at first timing) 111 Bus output signal ( Control signal at second timing) 112 Input enable signal (control signal at third timing) 113 Amplifier enable signal (control signal at third timing) 114 Switching signal (control of second timing) Signal) 115... First input terminal of differential amplifier (in-phase input) 116... Second input terminal of differential amplifier (negative-phase input)

Claims (1)

(57) [Claims] A bus control circuit for generating a control signal; a level setting circuit for connecting a bus to a power supply or a ground by using a precharge signal or a discharge signal from the bus control circuit as a control signal; A differential amplifier having a first input terminal and an output terminal connected to the bus, and a second input terminal connected to a switching circuit; The switching signal is a control signal,
A switching circuit for connecting a common terminal to one of the one end connected to the bus or the other end connected to the second input terminal of the differential amplifier; and a common terminal of the switching circuit. A level holding circuit having one end connected to the other end and a ground, and a bus output signal from the bus control circuit as a control signal,
A bus output circuit having an output terminal connected to the bus; and a data latch circuit having an input terminal connected to the bus using an input enable signal from the bus control circuit as a control signal. And high-speed bus circuit.