JP2630863B2 - Manufacturing method of insulated gate semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing an insulated gate semiconductor device capable of reducing the input capacitance Ciss without complicating the process.

[0002]

2. Description of the Related Art An insulated gate transistor such as a power MOSFET or an IGBT has an advantage that a control circuit is simplified because voltage control is possible. Power MOSFET
A conventional example will be described with reference to FIG. Power MOSFET is
As shown in FIG. 10, an N ⁻ type silicon substrate (2) having a high concentration N ⁺ type layer (1) at the bottom is used as a drain, and a gate electrode (poly Si gate) is formed on the surface at a predetermined interval.
(3) is arranged, and a P-type diffusion region (4) and an N ⁺ -type source region (5) are formed on the surface of the base (2) so as to form a channel under the gate electrode (3). The MOSFET is operated so as to control the drain current I _DS passing through the P-type diffusion region (4) (channel portion) under the gate by applying a voltage to the gate.

In a power MOSFET, the parasitic capacitance between the gate electrode (3) and the drain substrate (2) acts as an input capacitance Ciss, and thus has a disadvantage of deteriorating high-frequency characteristics. Therefore, as described in JP-A-56-116669, a through hole (6) is formed in the gate electrode (3) facing the drain substrate (2) to reduce the area of the gate electrode (3). Thus, a technique for reducing the input capacitance Ciss is known.

[0004]

However, in order to form the through hole (6) in the gate electrode (3), one mask for forming the through hole (6) and the source region (5) are required. Another selection mask means is required to prevent impurities for formation from diffusing into the base body (2) through the through holes (6). Therefore, there was a disadvantage that the process became complicated.

A parasitic transistor having a source region (5) as an emitter, a P-type diffusion region (4) as a base and a base (2) as a collector due to a potential drop caused by a parasitic resistance (7) below the source region (5). Are easily turned on, so that in the power MOSFET, the device has an avalanche breakdown,
The GBT has a drawback that the element leads to latch-up.

[0006]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned drawbacks, and comprises a step of forming a gate electrode (14) on a substrate (11) and a part of the gate electrode (14). Forming a selection mask (16) having an opening in a part of the P-type diffusion region (12); ion-implanting oxygen through the selection mask (16); A step of forming oxide films (17) and (18); a step of forming source regions (19) using field oxide films (17) and (18) as a mask;
Removing the field oxide film (18) on the surface of the mold diffusion region (12) to form the source electrode (22), thereby increasing the number of masks without increasing the number of masks.
To obtain a structure equivalent to a structure in which a through hole is formed.

[0007]

According to the present invention, the gate electrode (14) opposed to the drain substrate (11) is converted into the field oxide film (17) which is an insulator, so that the gate electrode (1) is substantially removed.
The area of 4) can be reduced. Further, since the source electrode (22) contacts the surface of the dug portion (21), the resistance value of the parasitic resistance (7) below the source region (19) can be reduced.

Furthermore, the field oxide film (17) (1)
By utilizing 8), the source region (19) can be formed in a self-aligned manner.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below in detail with reference to the drawings. First, a deep portion of a P-type diffusion region (12) is formed by selective diffusion on the surface of an N-type substrate (11) serving as a common drain, and the surface of the substrate (11) is thermally oxidized to a thickness of 1 nm.
A gate oxide film (13) of about 000 ° is formed. Then, a non-doped polysilicon layer is deposited on the gate oxide film (13) by a CVD method and patterned to form a gate electrode (14) (FIG. 1).

Next, the patterned gate electrode (1
Using 4) as a mask, boron (B) for forming the channel portion (15) of the P-type diffusion region (12) is ion-implanted from the surface (FIG. 2). Next, a photoresist is applied to the entire surface, and is exposed and developed to form a selection mask (16). The selection mask (16) is provided with a gate electrode (14) as shown.
And a part of the P-type diffusion region (12) (FIG. 3).

Next, a portion of the gate electrode (14) facing the drain substrate (11) through the selection mask (16).
Then, oxygen (O ₂ ) is ion-implanted into the silicon surface of the P-type diffusion region (12) (FIG. 4). Next, after removing the selection mask (16), the whole substrate (11) is heated in a non-oxidizing atmosphere (N ₂ ), and the ion-implanted impurity (boron) is thermally diffused to form a channel portion (15). . At the same time, the part of the gate electrode (14) not covered with the selection mask (16) and the surface of the P-type diffusion region (12) are selectively oxidized by ion-implanted oxygen (FIG. 5).
In this step, the channel portion (15) is diffused below the gate electrode (14) by lateral diffusion. The polysilicon of the gate electrode (14) where oxygen has been ion-implanted is oxidized into a silicon oxide film (SiO ₂ ), which is integrated with the underlying gate oxide film (13) to form a field oxide film (1).
7) is formed. The surface of the P-type diffusion region (12) where oxygen was ion-implanted is also about 0.5 μm from the surface of the substrate (11).
Selectively oxidized to about the depth to form a field oxide film (18)
To form

Next, the field oxide film (17) (1)
8) and ion implantation of phosphorus (P) using the gate electrode (14) as a mask to form an N ⁺ type source region (19) (FIG. 6). Since the field oxide film (17) in the portion facing the drain substrate (11) is obtained by oxidizing the gate polysilicon, at least the gate electrode (1) is formed.
It has the same film thickness as in 4), and the film quality is denser than polysilicon. Therefore, it can be used as a mask for preventing phosphorus (P) from reaching the surface of the base (11). P-type diffusion region (1
2) The upper field oxide film (18) is also a gate oxide film (1).
Since it has a larger film thickness than 3), it can be used as a selection mask.

Next, a CVD oxide film (20) is formed so as to cover the gate electrode (14), and a contact hole for a source electrode is formed by a usual photoetching technique. At this time, both the CVD oxide film (20) and the field oxide film (18) are removed, and a dug portion (21) is formed on the surface of the P-type diffusion region (12) to a depth corresponding to the depth of the selective oxidation (FIG. 7). Since the source region (19) is formed using the field oxide film (18) as a mask, the recessed portion (2) is formed by removing the field oxide film (18).
The source region (19) can be exposed on the side wall of (1).

Next, Al or Al-Si is deposited by sputtering.
And pattern it to form a source electrode (22).
Thus, the structure shown in FIG. 8 is obtained. In addition, FIG.
N ⁺Power MOSFET having a mold layer (23)
9 shows IGBTs each having a P-type layer (24) on the remote surface.
Was. The structure obtained by the process described above
The gate polysilicon on the substrate (11) is an insulator.
The gate electrode was converted to a field oxide film (17).
The facing area between (14) and the drain substrate (11) can be reduced.
Therefore, the input capacitance Ciss associated with the gate capacitance can be reduced.

Further, the source region (1) is brought into contact with the dug portion (21) by the source electrode (22).
9) The resistance value of the lower parasitic resistance (7) can be reduced. Therefore, the ON operation of the parasitic transistor can be suppressed. Furthermore, the source region (1) exposed on the side wall of the dug portion (21)
Also in 9), the contact area can be increased by contacting the source electrode (22), so that the size of the contact hole can be reduced and higher integration can be achieved.

According to the manufacturing method of the present invention, the selection mask (16) used for ion implantation of oxygen in the step of FIG.
Although the number of photomasks for forming the mask increases by one, the source region (19) can be formed by self-alignment.
One photomask for forming the source region (19) can be omitted. Therefore, the present application can be performed with the same number of masks as the conventional number of masks, and cost increase and complicated processes can be avoided.

[0017]

As described above, according to the present invention, the parasitic capacitance between the gate and the drain can be reduced by oxidizing the polysilicon layer on the base (11), so that the input capacitance Ciss can be reduced and the high-frequency characteristics can be reduced. Has the advantage that it can be improved. Also, since the surface of the P-type diffusion region (12) is selectively oxidized to form the digging portion (21), the resistance value of the parasitic resistance (7) below the source region (19) can be reduced, and in a power MOSFET, The avalanche resistance of the element can be increased, and the latch-up resistance of the element can be increased in the IGBT.

Further, since the contact area between the source electrode (22) and the source region (19) can be increased by the dug portion (21), there is an advantage that the contact hole can be reduced and the degree of integration can be increased. Further, the above structure can be obtained without increasing the number of masks, and the source region (19)
Can be formed in a self-aligned manner, which has an advantage that the process can be simplified.

[Brief description of the drawings]

FIG. 1 is a first cross-sectional view for explaining a manufacturing method of the present invention.

FIG. 2 is a second cross-sectional view for explaining the manufacturing method of the present invention.

FIG. 3 is a third cross-sectional view for explaining the manufacturing method of the present invention.

FIG. 4 is a fourth cross-sectional view for explaining the manufacturing method of the present invention.

FIG. 5 is a fifth sectional view for explaining the manufacturing method of the present invention.

FIG. 6 is a sixth sectional view for explaining the manufacturing method of the present invention.

FIG. 7 is a seventh cross-sectional view for explaining the manufacturing method of the present invention.

FIG. 8 is an eighth sectional view for explaining the manufacturing method of the present invention.

FIG. 9 is a sectional view showing a second embodiment of the present invention.

FIG. 10 is a sectional view for explaining a conventional example.

Claims (3)

(57) [Claims] A step of forming a reverse conductivity type diffusion region on a surface of a semiconductor substrate of one conductivity type; a step of forming a gate insulating film on a surface of the substrate and forming a polysilicon layer thereon; Forming a gate electrode by etching a layer; forming a plurality of opposite conductivity type channel regions using the polysilicon layer as a mask; covering a part of the gate electrode and a source region forming portion of the diffusion region. forming a selective mask, the step of surface oxygen ion implantation into the portion between the opposite conductivity type diffusion region of the gate electrode of the selection mask in the mask, removing the selection mask, and annealing the substrate , into a polysilicon layer partially field oxide film of the gate electrode located on the semiconductor substrate between the front SL channel region and the channel region,且Forming a field oxide film in said diffusion region surface, formed as part of the field oxide film of the mask of the diffusion region surface, a source region in a surface of the diffusion region by introducing opposite conductivity type impurity Removing the field oxide film on the surface of the diffusion region to form a dug portion exposing the side surface of the source region; and forming a source electrode contacting both the source region and the diffusion region. A method of manufacturing the insulated gate semiconductor device, wherein the recessed portion has a depth at least equal to the diffusion depth of the source region. 2. The method of manufacturing an insulated gate semiconductor device according to claim 1, further comprising a high-concentration layer of one conductivity type on a back surface of said base. 3. The method of manufacturing an insulated gate semiconductor device according to claim 1, further comprising a reverse conductivity type high concentration layer on the back surface of said base.