JP2890509B2 - Method for manufacturing semiconductor device - Google Patents

Description

The present invention relates to a method for manufacturing a Bi-MOS integrated circuit.

[Conventional technology]

A conventional method for manufacturing a Bi-MOS integrated circuit will be described with reference to FIGS. 2 (a) to 2 (e).

First, as shown in FIG. 2A, a P ⁺ type buried layer 2 and an N ⁺ type buried layer 3 are formed on the surface of a P type silicon substrate 1. Subsequently, after growing an N-type epitaxial layer 4 on the entire surface, a P + -type insulating separation layer 5 and a P-well 6 are formed.

After the field oxide film 7 is further formed, the base 8
After the formation of a polysilicon layer,
Grow 10

Next, as shown in FIG. 2 (b), an oxide film 11a for a diffusion mask is provided on the emitter portion of the bipolar transistor, and phosphorus serving as an N-type impurity is diffused over the entire surface. At this time, an N ⁺ type contact layer 13c is formed.

Next, as shown in FIG. 2C, the polysilicon layer 10 is selectively etched by covering the gate electrode 10a of the MOS-FET and the bipolar transistor region with a photoresist 12a.

Next, as shown in FIG. 2D, the polysilicon layer 10 is selectively etched by covering the MOS-FET region and the emitter electrode 10b and the collector electrode 10c of the bipolar transistor with a photoresist 12b.

Thereafter, as shown in FIG. 2E, the emitter 13b and the source-drain 13a are formed by ion implantation, and then the aluminum electrode 14 is formed to complete the basic structure of the Bi-CMOS integrated circuit.

[Problems to be solved by the invention]

In prior art manufacturing methods, a polysilicon layer
After the growth of 10, the diffusion mask oxide film 11a is provided only on the emitter portion of the bipolar transistor to diffuse phosphorus over the entire surface, so that diffusion of phosphorus from above can be prevented. Could not be prevented.

Therefore, on the side surface of the emitter electrode 10b, polysilicon in which phosphorus was diffused was N ⁺ type.

This high-concentration phosphorus diffuses to the bottom of the base 8 through the emitter opening in a heat treatment process such as emitter indentation diffusion, thereby causing a short circuit between the collector and the emitter of the bipolar transistor and a decrease in breakdown voltage.

An object of the present invention is to obtain an emitter electrode in which a high concentration of phosphorus does not remain on a side surface.

[Means for solving the problem]

The method of manufacturing a semiconductor device according to the present invention comprises growing an epitaxial layer of another conductivity type on a semiconductor substrate of one conductivity type,
Bi-MO forming S-FET and bipolar transistor
In the method for manufacturing an S integrated circuit, after forming a well of a MOS-FET and an insulating separation layer and a base of a bipolar transistor in the epitaxial layer, a polysilicon layer covering the MOS-FET region with a surface insulating film interposed therebetween; Growing a polysilicon layer to be either the emitter electrode or the collector electrode of the bipolar transistor, and adding another conductivity type impurity to the polysilicon layer while covering the upper surface and side surfaces of the emitter electrode with an oxide film. The method includes a step of diffusing, and a step of forming a gate electrode by selectively etching a polysilicon layer covering the MOS-FET region in which the impurity is diffused.

〔Example〕

One embodiment of the present invention will be described with reference to FIGS. 1 (a) to 1 (e).

First, as shown in FIG. 1A, a P ⁺ -type buried layer 2 and an N ⁺ -type buried layer 3 are formed on the surface of a P-type silicon substrate 1, and an N-type epitaxial layer 4 having a thickness of 1.5 μm is grown. After that, the P ⁺ type insulating separation layer 5 and the P well 6 are formed.

After the field oxide film 7 is further formed, the base 8
After the formation of a polysilicon layer,
Grow 10

Next, as shown in FIG. 1B, the MOS-FET region, the emitter electrode 10b and the collector electrode 10c of the bipolar transistor are covered with a photoresist 12a, and a polysilicon layer is formed.
10 is selectively etched.

Next, as shown in FIG. 1 (c), after oxide films 11a and 11b for a diffusion mask are formed, phosphorus is diffused over the entire surface.

Next, as shown in FIG. 1 (d), after removing the oxide films 11a and 11b for the diffusion mask, the gate electrode 10a of the MOS-FET is covered with the photoresist 12b on the bipolar transistor region and the polysilicon layer. 10 is selectively etched.

Thereafter, as shown in FIG. 1 (e), an etching 13b and a source-drain 13a are formed by ion implantation, and then an aluminum electrode 14 is formed to complete the basic structure of the Bi-CMOS integrated circuit.

〔The invention's effect〕

The oxide film for the diffusion mask is not only
By covering the side surfaces, it is possible to eliminate the short-circuit between the collector and the emitter of the bipolar transistor and the decrease in the breakdown voltage due to the high concentration of phosphorus diffused through the emitter electrode made of polysilicon.

[Brief description of the drawings]

1 (a) to 1 (e) are cross-sectional views illustrating an embodiment of a method of manufacturing a semiconductor device according to the present invention in the order of steps, and FIGS.
(E) is sectional drawing explaining one Example of the manufacturing method of the semiconductor device by a prior art in order of a process. DESCRIPTION OF SYMBOLS 1 ... P type silicon substrate, 2 ... P + type buried layer, 3 ... N +
Buried layer, 4 ... N type epitaxial layer, 5 ... P + type insulating separation layer, 6 ... P well, 7 ... Field oxide film, 8 ...
Base, 9: gate oxide film, 10: polysilicon layer, 10a
... gate electrode, 10b ... emitter electrode, 10c ... collector electrode, 11a, 11b ... oxide film for diffusion mask, 12a, 12b ... photoresist, 13a ... source-drain, 13b ... emitter, 13c
... collector contact layer, 14 ... aluminum electrode.

Claims (1)

(57) [Claims] 1. A method for manufacturing a Bi-MOS integrated circuit in which a MOS-FET and a bipolar transistor are formed by growing an epitaxial layer of another conductivity type on a semiconductor substrate of one conductivity type, wherein: After forming a well of a MOS-FET and an insulating separation layer of one conductivity type of a bipolar transistor and a base, a polysilicon layer covering a MOS-FET region with a gate insulating film interposed therebetween, and a polysilicon serving as an emitter electrode and a collector electrode of a bipolar transistor. Forming a silicon layer, and depositing an oxide film serving as a diffusion mask on the entire surface, and then forming the MOS
Forming a hole exposing a polysilicon layer covering the FET region and the polysilicon layer serving as the collector electrode, and then diffusing impurities of another conductivity type; and forming a MOS-FET region in which the impurity is diffused. Forming a gate electrode by selectively etching a covering polysilicon layer.