JPH0618200B2 - Method of manufacturing lateral transistor semiconductor device - Google Patents
Method of manufacturing lateral transistor semiconductor deviceInfo
- Publication number
- JPH0618200B2 JPH0618200B2 JP59166352A JP16635284A JPH0618200B2 JP H0618200 B2 JPH0618200 B2 JP H0618200B2 JP 59166352 A JP59166352 A JP 59166352A JP 16635284 A JP16635284 A JP 16635284A JP H0618200 B2 JPH0618200 B2 JP H0618200B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- oxide film
- emitter
- polycrystalline semiconductor
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 62
- 238000004519 manufacturing process Methods 0.000 title claims description 15
- 239000012535 impurity Substances 0.000 claims description 28
- 239000000758 substrate Substances 0.000 claims description 8
- 238000005468 ion implantation Methods 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 75
- 238000009792 diffusion process Methods 0.000 description 25
- 230000015556 catabolic process Effects 0.000 description 23
- 238000000034 method Methods 0.000 description 9
- 230000000694 effects Effects 0.000 description 7
- 230000005684 electric field Effects 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 230000003321 amplification Effects 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000032683 aging Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 230000002040 relaxant effect Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/735—Lateral transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
Description
【発明の詳細な説明】 〔発明の利用分野〕 本発明は高耐圧集積回路に係り、特に高耐圧化・高周波
化に好適なラテラルｐｎｐトランジスタに関する。Description: FIELD OF THE INVENTION The present invention relates to a high breakdown voltage integrated circuit, and more particularly to a lateral pnp transistor suitable for high breakdown voltage and high frequency.
従来の、ラテラルｐｎｐトランジスタについては、たと
えば、IBM J.RES.DEVELOP VOL.23,No.6 NOVEMEER 1979
年におけるＳ．Ｊ．Gillespieによる“Stability of La
teral pnp Transistors During Accelerated Aging"と
題する文献において論じられている。上記論文ではラテ
ラルｐｎｐトランジスタのベース表面を安定化し、コレ
クタ・エミツタ間のパンチスルー耐圧を劣化させないた
めに、エミツタコンタクトに用いたＡｌでベース上を覆
う構造が有効であることが述べられている。しかし、前
記ベース上のＡｌは厚い酸化膜（例えば１μｍ程度）の
上の置かれているため、コレクタ・エミツタ間のパンチ
スルー耐圧を抑える効果が小さいという欠点があつた。Regarding the conventional lateral pnp transistor, for example, IBM J.RES.DEVELOP VOL.23, No.6 NOVEMEER 1979.
S. J. “Stability of La” by Gillespie
Teral pnp Transistors During Accelerated Aging "is discussed in the above article. In order to stabilize the base surface of the lateral pnp transistor and to prevent the punch-through breakdown voltage between the collector and the emitter from deteriorating, the Al used for the emitter contact is used. However, since the Al on the base is placed on a thick oxide film (for example, about 1 μm), the punch-through breakdown voltage between the collector and the emitter is described. There is a drawback that the effect of suppressing is small.
本発明の目的は、高周波・高電流利得で、なおかつ高耐
圧なラテラルｐｎｐトランジスタの製造方法を提供する
ことにある。An object of the present invention is to provide a method of manufacturing a lateral pnp transistor having high frequency, high current gain, and high breakdown voltage.
上記目的を達するために本発明の製造方法により製造さ
れた半導体装置では、(1) ラテラルｐｎｐトランジスタ
のベース上を覆う、エミツタと同電位の導電層下の酸化
膜厚をフイールド部より薄くし、ベース表面の反転を防
止し、ベースのパンチスル耐圧を向上する。(2)ベース
側のコレクタ部を低濃度にし、上記導電層とドレイン間
の電界増加によるコレクタ・ベース間のアバランシエ耐
圧劣化も防止するという特徴を有する。In the semiconductor device manufactured by the manufacturing method of the present invention in order to achieve the above object, (1) the oxide film thickness under the conductive layer covering the base of the lateral pnp transistor and having the same potential as the emitter is made thinner than the field portion, Prevents reversal of the base surface and improves the punch-through resistance of the base. (2) The collector portion on the base side is made to have a low concentration to prevent deterioration of the avalanche breakdown voltage between the collector and the base due to the increase of the electric field between the conductive layer and the drain.
本願で開示される代表的な実施形態は、 半導体基板に設けられた一導電形のベース領域に、互い
に離れて設けられた上記一導電形と反対導電形のエミッ
タ領域とコレクタ領域を有し、その間の領域を実効的に
働くベース領域とし、 上記実効的に働くベース領域の表面上に上記エミッタ領
域と実質的に同電位となる制御電極を有し、 上記実効的に働くベース領域の表面上の酸化膜がフィー
ルド部の厚い酸化膜より薄い部分を有するラテラルトラ
ンジスタ半導体装置の製造方法であって、 上記ベース領域(3)が形成された上記半導体基板(1)の表
面上に上記厚い酸化膜(6)を形成し、該上記厚い酸化膜
(6)のうち上記エミッタ領域と上記コレクタ領域と上記
実効的に働くベース領域となる部分の厚い酸化膜(6)を
選択的に除去し、該選択除去部分に薄い酸化膜を形成す
る第１の工程(第８図(a)参照)と、 上記薄い酸化膜の上に多結晶半導体層を被着した後、該
多結晶半導体装置のうち上記実効的に働くベース領域上
以外の多結晶半導体層を除去することにより上記実効的
に働くベース領域上に多結晶半導体電極(7)を形成する
第２の工程(第８図(b)参照)と、 上記第２の工程により形成された上記多結晶半導体電極
(7)をマスクとして不純物を導入することにより、上記
多結晶半導体電極(7)と自己整合で上記エミッタ領域お
よび上記コレクタ領域の部分に低濃度不純物層(9)を形
成する第３の工程(第８図(c)参照)と、 上記コレクタ領域の部分の上記低濃度不純物層(9)のう
ち上記多結晶半導体電極(7)に近接した部分上に厚いマ
スク酸化膜(6)を形成し、しかる後該厚いマスク酸化膜
(6)をマスクとして不純物を導入することにより、上記
コレクタ領域の部分のうち上記多結晶半導体電極(7)か
ら離間した部分にコレクタ高濃度不純物層(10b)を形成
するとともに上記多結晶半導体電極(7)と自己整合で上
記エミッタ領域の部分にエミッタ高濃度不純物層(10a)
を形成する第４の工程(第８図(c)参照)とを含み、 上記多結晶半導体電極(7)と上記エミッタ高濃度不純物
層(10a)とに電気的に接続されるエミッタ電極(12a)を形
成することを特徴とする。A typical embodiment disclosed in the present application has, in a base region of one conductivity type provided in a semiconductor substrate, an emitter region and a collector region of the opposite conductivity type provided separately from each other, A region between them is used as an effective working base region, and a control electrode having substantially the same potential as the emitter region is provided on the surface of the effective working base region, and on the surface of the effective working base region. A method of manufacturing a lateral transistor semiconductor device, wherein the oxide film has a portion thinner than the thick oxide film in the field part, wherein the thick oxide film is formed on the surface of the semiconductor substrate (1) on which the base region (3) is formed. (6) is formed, and the thick oxide film is formed.
First, a thick oxide film (6) in the emitter region, the collector region, and the effectively acting base region of (6) is selectively removed, and a thin oxide film is formed in the selectively removed region. (See FIG. 8 (a)), and after depositing a polycrystalline semiconductor layer on the thin oxide film, a polycrystalline semiconductor device of the polycrystalline semiconductor device other than on the effective base region A second step (see FIG. 8 (b)) of forming a polycrystalline semiconductor electrode (7) on the effective base region by removing the layer, and the above-mentioned step formed by the second step. Polycrystalline semiconductor electrode
The third step (3) of forming a low-concentration impurity layer (9) in the emitter region and the collector region by self-alignment with the polycrystalline semiconductor electrode (7) by introducing impurities using (7) as a mask 8 (c)), and a thick mask oxide film (6) is formed on a portion of the low-concentration impurity layer (9) in the collector region which is close to the polycrystalline semiconductor electrode (7). After that, the thick mask oxide film
By introducing impurities using (6) as a mask, a collector high-concentration impurity layer (10b) is formed in a portion of the collector region apart from the polycrystalline semiconductor electrode (7), and the polycrystalline semiconductor electrode is formed. The emitter high-concentration impurity layer (10a) is self-aligned with the emitter region (7).
And a fourth step (see FIG. 8 (c)) of forming the emitter electrode (12a) electrically connected to the polycrystalline semiconductor electrode (7) and the emitter high-concentration impurity layer (10a). ) Is formed.
上述の代表的な実施形態によるラテラルトランジスタ半
導体装置の製造方法によれば、 （１）実効的に働くベース領域と多結晶半導体電極(7)
との間の酸化膜がフィールド部の厚い酸化膜より薄いた
め、ベースのパンチスルー耐圧を向上できる、 （２）コレクタ領域の部分の低濃度不純物層(9)によ
り、コレクタ・ベース間のアバランシェ耐圧を向上でき
る、 （３）実効的に働くベース領域の幅(すなわち実効ベー
ス幅)が、第３の工程で多結晶半導体電極(7)と自己整合
で形成されるコレクタ低濃度不純物層(9)と第４の工程
で多結晶半導体電極(7)と自己整合で形成されるエミッ
タ高濃度不純物層(10a)との間隔(すなわち、ほぼ多結晶
半導体電極(7)の幅)で高精度に設定されるので、電流増
幅率のバラツキ、コレクタ・ベース間耐圧のバラツキ、
カットオフ周波数のバラツキ等を小さくできる、 （４）実効ベース幅を決定する多結晶半導体電極(7)は
Ａｌ(アルミニューム)等の通常の金属と比較して融点が
高いので、エミッタ及びコレクタの低濃度不純物層(9)
とエミッタ及びコレクタの高濃度不純物層(10a,10b)の
形成のための熱処理にも耐えることができる、 （５）上記（３）で説明したように実効ベース幅を自己
整合のプロセスで決定する多結晶半導体電極(7)それ自
体はエミッタ高濃度不純物層(10a)に接続できないが、
エミッタ電極(12a)を多結晶半導体電極(7)とエミッタ高
濃度不純物層(10a)とに電気的に接続することによっ
て、この多結晶半導体電極(7)をエミッタ領域と実質的
に同電位となる制御電極とすることができる、 等と言う顕著な作用・効果を奏する。According to the method for manufacturing the lateral transistor semiconductor device according to the representative embodiment, (1) the base region and the polycrystalline semiconductor electrode (7) that work effectively
Since the oxide film between and is thinner than the thick oxide film in the field, the punch-through breakdown voltage of the base can be improved. (2) The low-concentration impurity layer (9) in the collector region allows the avalanche breakdown voltage between the collector and the base. (3) The width of the base region that effectively works (that is, the effective base width) is formed in the third step by self-alignment with the polycrystalline semiconductor electrode (7). And in the fourth step, the interval between the polycrystalline semiconductor electrode (7) and the emitter high-concentration impurity layer (10a) formed in self-alignment (that is, substantially the width of the polycrystalline semiconductor electrode (7)) is set with high accuracy. Therefore, variations in current amplification factor, variations in collector-base breakdown voltage,
Variations in cutoff frequency can be reduced. (4) Polycrystalline semiconductor electrode (7), which determines the effective base width, has a higher melting point than ordinary metals such as Al (aluminum). Low concentration impurity layer (9)
Also, it can withstand the heat treatment for forming the high-concentration impurity layers (10a, 10b) of the emitter and collector. (5) As described in (3) above, the effective base width is determined by the self-alignment process. Although the polycrystalline semiconductor electrode (7) itself cannot be connected to the emitter high-concentration impurity layer (10a),
By electrically connecting the emitter electrode (12a) to the polycrystalline semiconductor electrode (7) and the emitter high-concentration impurity layer (10a), the polycrystalline semiconductor electrode (7) is made to have substantially the same potential as the emitter region. Can be used as the control electrode.
本発明のその他の特徴は、以下に説明する実施例から明
らかとなろう。Other features of the present invention will be apparent from the embodiments described below.
以下、本発明を参考例および実施例を参照して詳細に説
明する。第１図は本発明の原理を説明するための参考例
の半導体装置の構造断面図である。１０ａはラテラルpn
pトランジスタのエミツタ層となるｐ形拡散層、１０ｂ
はエミツタをリング状に囲んだコレクタとなるｐ形拡散
層、３はベースとなるＮ形半導体で、１１はベースコン
タクト用のｎ形拡散層である。１２ａはベース上のパン
チスルー降伏を防止するための電極であるが、酸化膜厚
を薄くし、Ｎ形ベース表面層のＰ形反転防止効果を増加
させるためにＡ部のように、ベース上の酸化膜を薄くし
た領域を設けてある。Hereinafter, the present invention will be described in detail with reference to Reference Examples and Examples. FIG. 1 is a structural sectional view of a semiconductor device of a reference example for explaining the principle of the present invention. 10a is lateral pn
p-type diffusion layer 10b serving as an emitter layer of a p-transistor
Is a p-type diffusion layer that serves as a collector surrounding the emitter in a ring shape, 3 is an N-type semiconductor that is a base, and 11 is an n-type diffusion layer for a base contact. Reference numeral 12a is an electrode for preventing punch-through breakdown on the base, but in order to reduce the oxide film thickness and increase the P-type inversion prevention effect of the N-type base surface layer, the electrode 12a on the base is formed. A region where the oxide film is thin is provided.
第２図は本発明の原理を説明するための他の参考例の半
導体装置の構造断面図である。１０ａがエミツタ、10b
がコレクタ、３がベースであることは第１図と同じであ
る。本参考例の特徴は、ベース上を覆う電極７をたとえ
ば1000Å程度以下の薄い酸化膜上に設けたことと、電極
７と高濃度コレクタ層１０ｂの間を離し、低濃度コレク
タ層９を設けてあることである。電極７は、従来フイー
ルド酸化膜のように厚い酸化膜上に形成していたが、本
発明では、薄い酸化膜上に形成するため、ベース表面が
Ｐ形に反転することを防止する効果が期待できる。この
ため、従来に比べ、ベース表面のパンチスルー耐圧を向
上できた。また、酸化膜を薄くすることにより、コレク
タと電極７の間の電界は増加するが、低濃度コレクタ層
９により、コレクタ・ベース間のアバランシエ耐圧劣化
を防止できた。このため、高周波・高電流利得の高耐圧
ラテラルpnpトランジスタを実現できる。特に、電極７
として多結晶半導体層を用いた場合には、第８図に示す
製造方法により、電極７と低濃度コレクタ層９を自己整
合で形成できるため、ベース表面を完全に覆い、かつ、
コレクタ層上へ導電層の張り出しを最小にできることか
ら、ベース表面の安定化，高耐圧化，微細化のたに最適
な構造にできる。FIG. 2 is a structural sectional view of a semiconductor device of another reference example for explaining the principle of the present invention. 10a is an emitter and 10b
Is the same as FIG. 1 in that the collector is 3 and the base is 3. The feature of this reference example is that the electrode 7 covering the base is provided on a thin oxide film of, for example, about 1000 Å or less, and the electrode 7 and the high-concentration collector layer 10b are separated from each other, and the low-concentration collector layer 9 is provided. There is. The electrode 7 is conventionally formed on a thick oxide film such as a field oxide film, but since it is formed on a thin oxide film in the present invention, an effect of preventing the base surface from reversing into a P-type is expected. it can. Therefore, the punch-through breakdown voltage on the surface of the base can be improved as compared with the conventional case. Although the electric field between the collector and the electrode 7 is increased by thinning the oxide film, the low-concentration collector layer 9 can prevent deterioration of the avalanche breakdown voltage between the collector and the base. Therefore, a high breakdown voltage lateral pnp transistor with high frequency and high current gain can be realized. In particular, the electrode 7
When a polycrystalline semiconductor layer is used as the electrode, the electrode 7 and the low-concentration collector layer 9 can be formed in a self-aligned manner by the manufacturing method shown in FIG. 8, so that the base surface is completely covered and
Since the protrusion of the conductive layer on the collector layer can be minimized, the structure can be optimized for stabilizing the base surface, increasing the breakdown voltage, and miniaturizing.
第３図は本発明の原理を説明するための他の参考例の半
導体装置の構造断面図である。本実施例では、第２図で
述べた、第２の参考例を、公知の技術（たとえば、特開
昭55−30844）を用いた高耐圧素子製造技術に適用させ
た場合を示した。ここで、１はＰ形基板、２は高濃度ｎ
形埋込層、３はＮ形エピタキシヤル層、４はＰ形アイソ
レーシヨン拡散層、５はベース抵抗低減のために用いる
ｎ形拡散層、６はフィールド酸化膜、７は多結晶半導体
層で、１２ａは電極によりエミツタと同電位に保つてあ
る。この実施例ではアイソレーシヨン拡散層４を深くし
なくても、厚いエピタキシヤル部につくつた素子を分離
できる。素子部のエピタキシヤル層を厚くすることによ
り、ベース・コレクタ間のリーチスルー耐圧を増加でき
る。FIG. 3 is a structural sectional view of a semiconductor device of another reference example for explaining the principle of the present invention. In the present embodiment, the case where the second reference example described in FIG. 2 is applied to the high breakdown voltage element manufacturing technology using a known technology (for example, Japanese Patent Laid-Open No. 55-30844) is shown. Here, 1 is a P-type substrate, 2 is a high concentration n
Type buried layer, 3 is an N type epitaxial layer, 4 is a P type isolation diffusion layer, 5 is an n type diffusion layer used for reducing the base resistance, 6 is a field oxide film, and 7 is a polycrystalline semiconductor layer. , 12a are kept at the same potential as the emitter by electrodes. In this embodiment, the element formed in the thick epitaxial portion can be separated without making the isolation diffusion layer 4 deep. By increasing the thickness of the epitaxial layer in the element portion, the reach-through breakdown voltage between the base and collector can be increased.
第４図は、本発明の原理を説明するための他の参考例の
半導体装置の構造断面図を示す。前記第３図の例との相
異は、エミツタとり出し用電極として用いる12aにあ
る。本参考例では、１２ａが、低濃度コレクタ層９上ま
できており、コレクタ９の端部における電界集中を緩和
させ耐圧を向上させる効果がある。FIG. 4 is a structural sectional view of a semiconductor device of another reference example for explaining the principle of the present invention. The difference from the example of FIG. 3 lies in 12a used as an electrode for extracting an emitter. In this reference example, 12a is formed on the low-concentration collector layer 9 and has the effect of relaxing the electric field concentration at the end of the collector 9 and improving the breakdown voltage.
第５図は、本発明の原理を説明するための他の参考例の
半導体装置の構造断面図を示した。第４図の参考例との
相異は、Ｎ形拡散層８を追加した点にある。このＮ形拡
散層８は、第８図に示すように、多結晶半導体層８をマ
スクにして形成できるがこれにより、パンチスルー耐圧
をさらに向上させることが可能である。FIG. 5 is a structural sectional view of a semiconductor device of another reference example for explaining the principle of the present invention. The difference from the reference example of FIG. 4 is that an N-type diffusion layer 8 is added. As shown in FIG. 8, the N-type diffusion layer 8 can be formed by using the polycrystalline semiconductor layer 8 as a mask, which makes it possible to further improve the punch-through breakdown voltage.
第６図は、本発明の原理を説明するための他の参考例の
半導体装置の構造断面図を示した。本参考例では、MOSF
ETの製造方法として公知のLOCOS プロセスで形成できる
フイールド酸化膜６直下のＰ形チヤネルストツパ１７を
コレクタの低濃度拡散層９のかわりに用いている。本参
考例では、高耐圧化用低濃度拡散層９を用いずに、本発
明の目的を達成できる。また、本参考例はLOCOS 構造の
小信号MOSFETとの共存が容易である。FIG. 6 is a structural sectional view of a semiconductor device of another reference example for explaining the principle of the present invention. In this reference example, MOSF
As the ET manufacturing method, a P-type channel stopper 17 directly below the field oxide film 6 that can be formed by the known LOCOS process is used instead of the low concentration diffusion layer 9 of the collector. In this reference example, the object of the present invention can be achieved without using the low-concentration diffusion layer 9 for increasing the breakdown voltage. In addition, this reference example is easy to coexist with a small-signal MOSFET having a LOCOS structure.
第７図は、本発明の原理を説明するための他の参考例の
半導体装置の構造断面図を示した。第６図に示した参考
例との相異は、エミツタとり出し用電極として用いる電
極１２ａにある。本参考例では電極１２ａが、低濃度コ
レクタ層１７上まできているため、電界集中を緩和させ
耐圧を向上させる効果が高い。FIG. 7 is a structural sectional view of a semiconductor device of another reference example for explaining the principle of the present invention. The difference from the reference example shown in FIG. 6 lies in the electrode 12a used as the emitter extraction electrode. In this reference example, since the electrode 12a is formed on the low-concentration collector layer 17, the effect of alleviating the electric field concentration and improving the breakdown voltage is high.
第８図（ａ）から第８図（ｃ）に、本発明の実施例の半
導体装置の製造方法の一例を、前記第５図の参考例に示
した装置について示した。FIGS. 8 (a) to 8 (c) show an example of a method of manufacturing a semiconductor device according to an embodiment of the present invention for the device shown in the reference example of FIG.
まず、第８図（ａ）に示す如く公知の技術（たとえば、
特開昭55−30844 に示した方法）により、凹みのあるｐ
基板に高濃度ｎ形埋込層２を形成し、ｎ形エピタキシヤ
ル層３を形成し、表面を平坦化する。次に、ｐ形アイソ
レーシヨン拡散層４とｎ形拡散層５と厚いフィールド酸
化膜６を形成する。次に、ラテラルｐｎｐトランジスタ
のエミツタ・コレクタ、及び、実効的に働くベース領域
となる部分の酸化膜６を選択的に除去し、1000Å程度の
薄い酸化膜の領域を作る。なお、この酸化膜は、同一チ
ツプ上のMOSFETのゲート酸化膜と同時に形成したものを
使用できる。First, as shown in FIG. 8 (a), a known technique (for example,
According to the method disclosed in JP-A-55-30844), the p
The high-concentration n-type buried layer 2 is formed on the substrate, the n-type epitaxial layer 3 is formed, and the surface is flattened. Next, the p-type isolation diffusion layer 4, the n-type diffusion layer 5 and the thick field oxide film 6 are formed. Next, the emitter collector of the lateral pnp transistor and the oxide film 6 in the portion which becomes the effective base region are selectively removed to form a thin oxide film region of about 1000 Å. This oxide film can be formed at the same time as the gate oxide film of the MOSFET on the same chip.
次に、第８図（ｂ）に示す如く、多結晶半導体層７をデ
ポジシヨンし、実効的に働くベース領域上以外の多結晶
半導体層を除去し、この多結晶半導体層７とホトレジス
トパターン１５をマスクにして、リンをイオン打込み
し、レジスト除去後の拡散によりｎ形拡散層８を形成で
きる。Next, as shown in FIG. 8 (b), the polycrystalline semiconductor layer 7 is deposited, and the polycrystalline semiconductor layer other than on the effective base region is removed to remove the polycrystalline semiconductor layer 7 and the photoresist pattern 15. Using the mask as a mask, phosphorus is ion-implanted, and the n-type diffusion layer 8 can be formed by diffusion after removing the resist.
次に、レジスト１５除去後、酸化膜６の厚い領域と、ポ
リシリコン７をマスクに、イオン打込法により、第８図
（ｃ）に示す如く低濃度ｐ形拡散層９を形成できる。次
に、低濃度コレクタ層９のうち多結晶半導体層７に近接
した部分の上に厚いマスク酸化膜６を形成し、しかる後
ラテラルｐｎｐトランジスタのエミツタとコレクタ及
び、ｐ形拡散層にコンタクトをとる部分に高濃度ｐ形拡
散層１０ａ，１０ｂ，１０ｃを形成する。Next, after removing the resist 15, a low concentration p-type diffusion layer 9 can be formed by ion implantation using the thick region of the oxide film 6 and the polysilicon 7 as a mask, as shown in FIG. 8 (c). Next, a thick mask oxide film 6 is formed on a portion of the low-concentration collector layer 9 close to the polycrystalline semiconductor layer 7, and then the emitter and collector of the lateral pnp transistor and the p-type diffusion layer are contacted. High-concentration p-type diffusion layers 10a, 10b, 10c are formed in the portions.
次に、高濃度ｎ形拡散層１１を形成し、通常の２層配線
工程を行なうことにより、第５図に示した構造が得られ
る。Next, a high-concentration n-type diffusion layer 11 is formed and a normal two-layer wiring process is performed to obtain the structure shown in FIG.
第６図，第７図に示した本発明の製造方法も本質的には
第８図に示した製造方法と同じである。第６図，第７図
のｐ形拡散層１７の製造方法は、第９図に示す如く、ホ
トレジストパターン１５′と、フイールド部形成を選択
酸化するためにパターン形成された耐酸化層１６をマス
クにして、ボロンのイオン打込み法により形成できる。The manufacturing method of the present invention shown in FIGS. 6 and 7 is essentially the same as the manufacturing method shown in FIG. As shown in FIG. 9, the p-type diffusion layer 17 shown in FIGS. 6 and 7 is manufactured by masking the photoresist pattern 15 'and the oxidation resistant layer 16 which is patterned to selectively oxidize the field portion formation. Then, it can be formed by a boron ion implantation method.
本発明によれば、 （１）実効的に働くベース領域と多結晶半導体電極(7)
との間の酸化膜がフィールド部の厚い酸化膜より薄く、
ベースのパンチスルー耐圧を向上できる、 （２）コレクタ領域の部分の低濃度不純物層(9)によ
り、コレクタ・ベース間アンバランシェ耐圧を向上でき
る、 （３）実効ベース幅が、コレクタ低濃度不純物層(9)と
エミッタ高濃度不純物層(10a)との間隔で自己整合のプ
ロセスで高精度に設定されるので、電流増幅率のバラツ
キ、コレクタ・ベース間耐圧のバラツキ、カットオフ周
波数のバラツキ等を小さくできる、 （４）実効ベース幅を決定する多結晶半導体電極(7)は
通常の金属と比較して融点が高いので、エミッタ及びコ
レクタの低濃度不純物層(9)とエミッタ及びコレクタの
高濃度不純物層(10a,10b)の形成のための熱処理にも耐
えることができる、 （５）実効ベース幅を自己整合プロセスで決定する多結
晶半導体電極(7)自体はエミッタ高濃度不純物層(10a)に
接続できないが、エミッタ電極(12a)と多結晶半導体電
極(7)およびエミッタ高濃度不純物層(10a)との間の電気
的接続によって、この多結晶半導体電極(7)をエミッタ
領域と実質的に同電位となる制御電極とできる、 と言う効果を奏する。According to the present invention, (1) an effective working base region and a polycrystalline semiconductor electrode (7)
The oxide film between and is thinner than the thick oxide film in the field,
The punch-through breakdown voltage of the base can be improved. (2) The low-concentration impurity layer (9) in the collector region can improve the avalanche breakdown voltage between the collector and the base. (3) The effective base width is a low-concentration collector layer. The gap between (9) and the emitter high-concentration impurity layer (10a) is set with high accuracy through a self-alignment process, so variations in current amplification factor, variations in collector-base breakdown voltage, variations in cutoff frequency, etc. (4) The melting point of the polycrystalline semiconductor electrode (7), which determines the effective base width, is higher than that of ordinary metals, so that the low concentration impurity layer (9) of the emitter and collector and the high concentration of the emitter and collector It can withstand the heat treatment for forming the impurity layers (10a, 10b). (5) The polycrystalline semiconductor electrode (7) itself, which determines the effective base width by the self-alignment process, has a high impurity concentration in the emitter. Although it cannot be connected to the layer (10a), the polycrystalline semiconductor electrode (7) can be connected to the emitter electrode (12a) by an electrical connection between the polycrystalline semiconductor electrode (7) and the emitter high-concentration impurity layer (10a). There is an effect that the control electrode can have substantially the same potential as the region.
第１〜７図は本発明の参考例を示すラテラルｐｎｐトラ
ンジスタの構造断面図、第８〜９図は本発明の実施例の
半導体装置の製造工程を説明する断面図である。 １……ｐ基板、２……高濃度ｎ形埋込層、３……ｎ形エ
ピタキシヤル層、４……ｐ形アイソレーシヨン拡散層、
５……ｎ＋埋込層、６……フィールド酸化膜、７……多
結晶半導体層等の導電層（電極）、８……ｎ形拡散層、
９……低濃度ｐ形拡散層、１０ａ，１０ｂ，１０ｃ……
高濃度ｐ形拡散層、１１……高濃度ｎ形拡散層、１２
ａ，１２ｂ，１２ｃ……第１電極、１３……層間絶縁
膜、１４……第２電極、１５，１５′……ホトレジス
ト、１６……シリコン窒化膜、１７……ｐ形拡散層。1 to 7 are sectional views of the structure of a lateral pnp transistor showing a reference example of the present invention, and FIGS. 8 to 9 are sectional views for explaining a manufacturing process of a semiconductor device of an embodiment of the present invention. 1 ... p substrate, 2 ... high-concentration n-type buried layer, 3 ... n-type epitaxial layer, 4 ... p-type isolation diffusion layer,
5 ... n + buried layer, 6 ... field oxide film, 7 ... conductive layer (electrode) such as polycrystalline semiconductor layer, 8 ... n-type diffusion layer,
9 ... Low-concentration p-type diffusion layer, 10a, 10b, 10c ...
High-concentration p-type diffusion layer, 11 ... High-concentration n-type diffusion layer, 12
a, 12b, 12c ... first electrode, 13 ... interlayer insulating film, 14 ... second electrode, 15,15 '... photoresist, 16 ... silicon nitride film, 17 ... p type diffusion layer.
Claims (2)
領域に、互いに離れて設けられた上記一導電形と反対導
電形のエミッタ領域とコレクタ領域を有し、その間の領
域を実効的に働くベース領域とし、 上記実効的に働くベース領域の表面上に上記エミッタ領
域と実質的に同電位となる制御電極を有し、 上記実効的に働くベース領域の表面上の酸化膜がフィー
ルド部の厚い酸化膜より薄い部分を有するラテラルトラ
ンジスタ半導体装置の製造方法であって、 上記ベース領域が形成された上記半導体基板の表面上に
上記厚い酸化膜を形成し、該上記厚い酸化膜のうち上記
エミッタ領域と上記コレクタ領域と上記実効的に働くベ
ース領域となる部分の厚い酸化膜を選択的に除去し、該
選択除去部分に薄い酸化膜を形成する第１の工程と、 上記薄い酸化膜の上に多結晶半導体層を被着した後、該
多結晶半導体層のうち上記実効的に働くベース領域上以
外の多結晶半導体層を除去することにより上記実効的に
働くベース領域上に多結晶半導体電極を形成する第２の
工程と、 上記第２の工程により形成された上記多結晶半導体電極
をマスクとして不純物を導入することにより、上記多結
晶半導体電極と自己整合で上記エミッタ領域および上記
コレクタ領域の部分に低濃度不純物層を形成する第３の
工程と、 上記コレクタ領域の部分の上記低濃度不純物層のうち上
記多結晶半導体電極に近接した部分上に厚いマスク酸化
膜を形成し、しかる後該厚いマスク酸化膜をマスクとし
て不純物を導入することにより、上記コレクタ領域の部
分のうち上記多結晶半導体電極から離間した部分にコレ
クタ高濃度不純物層を形成するとともに上記多結晶半導
体電極と自己整合で上記エミッタ領域の部分にエミッタ
高濃度不純物層を形成する第４の工程とを含み、 上記多結晶半導体電極と上記エミッタ高濃度不純物層と
に電気的に接続されるエミッタ電極を形成することを特
徴とするラテラルトランジスタ半導体装置の製造方法。1. A base region of one conductivity type provided on a semiconductor substrate, has an emitter region and a collector region of the opposite conductivity type of the one conductivity type, which are provided apart from each other. As a working base region, a control electrode having substantially the same potential as that of the emitter region is provided on the surface of the effectively working base region, and an oxide film on the surface of the effectively working base region is a field portion. A method of manufacturing a lateral transistor semiconductor device having a portion thinner than a thick oxide film, wherein the thick oxide film is formed on a surface of the semiconductor substrate on which the base region is formed, and the emitter of the thick oxide film is formed. A first step of selectively removing a thick oxide film in the region, the collector region, and a portion that effectively acts as a base region, and forming a thin oxide film in the selectively removed portion; After depositing the polycrystalline semiconductor layer on the oxide film, the polycrystalline semiconductor layer on the effectively operating base region is removed by removing the polycrystalline semiconductor layer other than on the effectively operating base region. A second step of forming a polycrystalline semiconductor electrode on the substrate, and introducing impurities by using the polycrystalline semiconductor electrode formed by the second step as a mask, so that the emitter region is self-aligned with the polycrystalline semiconductor electrode. And a third step of forming a low-concentration impurity layer in the collector region, and forming a thick mask oxide film on a part of the low-concentration impurity layer in the collector region near the polycrystalline semiconductor electrode. Then, by introducing impurities using the thick mask oxide film as a mask, the collector is formed in a portion of the collector region separated from the polycrystalline semiconductor electrode. A fourth step of forming a high concentration impurity layer and forming an emitter high concentration impurity layer in a portion of the emitter region in self-alignment with the polycrystalline semiconductor electrode, wherein the polycrystalline semiconductor electrode and the emitter high concentration impurity layer are included. A method of manufacturing a lateral transistor semiconductor device, which comprises forming an emitter electrode electrically connected to and.
上記コレクタ領域の部分に上記低濃度不純物層を形成す
るため上記不純物がイオン打込みにより導入されること
を特徴とする特許請求の範囲第１項に記載のラテラルト
ランジスタ半導体装置の製造方法。2. The impurity is introduced by ion implantation in order to form the low-concentration impurity layer in the portion of the emitter region and the collector region in the third step. Item 8. A method of manufacturing a lateral transistor semiconductor device according to item.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59166352A JPH0618200B2 (en) | 1984-08-10 | 1984-08-10 | Method of manufacturing lateral transistor semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59166352A JPH0618200B2 (en) | 1984-08-10 | 1984-08-10 | Method of manufacturing lateral transistor semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6146062A JPS6146062A (en) | 1986-03-06 |
| JPH0618200B2 true JPH0618200B2 (en) | 1994-03-09 |
Family
ID=15829784
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59166352A Expired - Lifetime JPH0618200B2 (en) | 1984-08-10 | 1984-08-10 | Method of manufacturing lateral transistor semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0618200B2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02142137A (en) * | 1988-11-22 | 1990-05-31 | Sony Corp | Lateral transistor and manufacture thereof |
| JP3041854B2 (en) * | 1988-11-22 | 2000-05-15 | ソニー株式会社 | Lateral transistor and method of manufacturing the same |
| FR2762139B1 (en) * | 1997-04-15 | 1999-07-02 | Sgs Thomson Microelectronics | LATERAL PNP TRANSISTOR IN BICMOS TECHNOLOGY |
| US6885522B1 (en) | 1999-05-28 | 2005-04-26 | Fujitsu Limited | Head assembly having integrated circuit chip covered by layer which prevents foreign particle generation |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57104254A (en) * | 1980-12-22 | 1982-06-29 | Hitachi Ltd | Lateral-transistor |
-
1984
- 1984-08-10 JP JP59166352A patent/JPH0618200B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6146062A (en) | 1986-03-06 |
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