JP2535825B2 - Print control circuit of dot tomato printer - Google Patents

Description

The present invention relates to a print control circuit for a dot matrix printer.

[Conventional technology]

Dot matrix printers are often used as output devices for OA equipment because they can print Chinese characters, but improvements in printing processing speed and printing density are required. In the past, printing control was performed by firmware processing by a microprocessor, but the processing speed is limited because the dot data to be handled increases.

FIG. 4 shows, as an example, an arrangement of dot pins of a dot impact type print head for forming a Chinese character of 24 × 24 dot matrix. In general, a method is used in which 24 pins are divided into two rows, an odd pin row and an even pin row, and arranged in a zigzag manner, and a dot row of one vertical row is printed on a printing paper. First, impact the odd-numbered pin row to print the odd-numbered dot row (Fig. 5), and then move the print head to the right to impact the even-numbered row when the even-numbered row comes directly above the odd-numbered row. By this, even dots are printed between odd dots (FIG. 6), and a vertical dot row of 24 dots is printed. If this is repeated 24 times to the right, Kanji characters can be printed using a dot matrix of 24 dots vertically and 24 dots horizontally (Fig. 7).

[Problems to be solved by the invention]

The dot matrix pattern shown in Fig. 7 is stored in the character generator memory in 8-bit units as shown in Fig. 8. This is read by the microprocessor and output to the 8-bit × 3 I / O ports to print the print head. Ink the dot pin. However, as mentioned above, it is necessary to control the odd pin and the even pin with a certain timing, and in order to process these with the firmware, when reading the dot data from the character generator memory, the odd dot and the even dot are Read separately and use logic so that they do not affect each other 8
Since it is necessary to output to three I / O ports, the number of processing steps increases and the print processing speed decreases.

[Means for solving problems]

The print control circuit of the dot matrix printer according to the present invention is the dot control data read from the character generator memory in which the print pattern is stored in the print control circuit of the dot matrix printer in which the dot rows of the print head are staggered. Of the dot row data latched in the data latch register and the data latch register having an output terminal for the dot data for temporarily latching and outputting each dot data to the outside It has an input terminal for each dot data connected to each output terminal of data,
The number of bits for writing dot data is the number of vertical dots / 2
In this case, two FIFO memories whose number of columns corresponds to odd number and even number of horizontal dots respectively are provided. Then, each dot row data read from the character generator memory is set in the data latch register, and 2
When writing to one FIFO memory and all writing of dot data is completed, the dot data of each FIFO memory is sequentially read separately at a predetermined timing cycle, and a control circuit for controlling each dot of the print head is provided.

In this way, by storing the odd-numbered dot data and the even-numbered dot data of the dot string data read from the character generator memory in the two FIFO memories via the data latch register and controlling the print head, The number of processing steps is reduced and the print processing speed is increased.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of a print control circuit of a dot matrix printer of the present invention, and FIG. 2 is a time chart of a sequence until dot data is input to the FIFO memories IC5 and IC6 in the embodiment of FIG. , FIG. 3 is a time chart of a sequence for reading and outputting data from the FIFO memories IC5 and IC6.

The data latch circuits IC1, IC2, and IC3 are all 8 bits, and the dot row data D1 for 24 vertical dots read by the microprocessor from a character generator memory (not shown) in which a Chinese character pattern of a 24 × 24 dot matrix is stored. ~ D8, D9 ~ D16, D17 ~ D24 are temporarily latched. FIFO (First In First Out) memory IC
5 and IC6 are all 12 bits x 24 columns, data latch circuit I
Dot row data D1, D2, ..., D2 latched by C1 to IC3
Of the four, odd-numbered dot data D1, D3, ..., D21, D23 and even-numbered dot data D2, D4, ..., D22, D24 are written respectively. The decoder IC4 sequentially sets the dot row data in the data latch circuits IC1, IC2, IC3 by using the write signals ▲ ▼, ▲ ▼, ▲ ▼ in 8-bit units under the control of the address signals ADR0, ADR1, and the write signal ▲ ▼. If the status signals ODROY and EVRDY indicating whether data can be input to the FIFO memory IC5 and IC6 are ready, the ready signal READY is output and the write signal ▲ ▼ is changed by the address signals ADR0, ADR1 and write control signal ▲ ▼. FIF the dot row data D1, D3, ..., D23, D2, D4, ..., D24 that are output and are latched in the data latch circuits IC1, IC2, IC3.
Write to O memory IC5, IC6. When the writing of all dot data is completed in this way, first, the dot data D1, D3, ..., D23 of the first column written in the FIFO memory IC5 is read by the read signal ▲ ▼, and the data D1, D
3, ..., D23, the odd-numbered dot pins of the print head shown in FIG. 4 are impacted to make odd-numbered dot data D1, D3 ,.
, And the odd numbered dot data D1, D3, ..., D23 are sequentially printed while the print head is sequentially moved to the right. When the printing of the odd-numbered dot data up to the fourth row is completed, the first row dot data D2, D4, ..., D24 written in the FIFO memory IC6 is read by the read signal ▲ ▼, and the data D2, At D4, ..., D24, the even dot pin of the print head is impacted to print the even numbered dots between the odd numbered dots, and the even numbered dot data is sequentially printed. After that, by repeating the same operation, the pattern of 24 × 24 dot matrix is finally printed. If the above sequence is repeated character by character, the characters are printed sequentially.

〔The invention's effect〕

As described above, according to the present invention, each dot row data is separated into odd-numbered dot data and even-numbered dot data, and these dot data are sequentially written in the two FIFO memories, and the prescribed timing cycle is set. By sequentially reading the odd-numbered dot data and the even-numbered dot data separately, and controlling the dots of the print head with that data, the part that was conventionally controlled by firmware processing is now partly hardware-based. In addition, the processing speed is increased, and the printing speed can be improved.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment of a print control circuit of a dot matrix printer of the present invention, and FIG. 2 is a time chart of a sequence until dot data is input to the FIFO memories IC5 and IC6 in the embodiment of FIG. , Fig. 3 shows FIFO memory
Time chart of the sequence of reading and outputting data from IC5, IC6, Fig. 4 is a dot array diagram of the print head, Figs. 5 and 6 are diagrams showing the printing process, and Fig. 7 is a 24 x 24 dot matrix pattern. FIG. 8 shows the contents of the character generator memory. IC1, IC2, IC3 ... Data latch circuit, IC4 ... Decoder, IC5, IC6 ... FIFO memory.

Claims (1)

(57) [Claims] 1. A print control circuit of a dot matrix printer, in which dot rows of a print head are arranged in a staggered manner, by temporarily latching dot row data read from a character generator memory in which a print pattern is stored. A data latch register having an output terminal for the dot data to be output for each dot data externally, and a dot connected to the output terminal of the odd-numbered dot data of the dot row data latched in the data latch register A first FIFO memory having an input terminal for each data, in which the dot data is written, the number of bits is the number of vertical dots in the print pattern / 2, and the number of columns is the number of horizontal dots in the print pattern; The output of the even-numbered dot data of the dot row data latched in the data latch register A second number of bits for writing the dot data, the number of bits being the number of vertical dots in the print pattern / 2, and the number of columns being the number of horizontal dots in the print pattern; FIFO memory and each dot string data read from the character generator memory is set in the data latch register, written in the first and second FIFO memories, and written in the first and second FIFO memories. When all writing of dot data is completed, the first data is written at a predetermined timing cycle.
The dot control data of the FIFO memory and the dot data of the second FIFO memory are read separately and sequentially, and a control circuit for controlling each dot of the print head is included, and the print control circuit of the dot matrix printer.