JP4329167B2 - Image processing apparatus and image output apparatus - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an image processing apparatus and an image output apparatus, and more particularly to an image processing apparatus and an image output apparatus that reduce the load on a CPU and increase the processing speed by executing image processing with hardware.
[0002]
[Prior art]
In recent years, printers that can receive digital image data and perform full-color printing have been used. Digital image data is subjected to image processing by an internal CPU, and full-color printing is performed on a recording sheet from, for example, an inkjet head. A resolution of 300 dpi or more has been used.
[0003]
Furthermore, a line head that simultaneously prints an image for one line has been proposed. Therefore, the amount of image data required for printing at a time has increased significantly, and the load on the processing apparatus for creating the image data has increased.
[0004]
[Problems to be solved by the invention]
In the conventional technology, the CPU processes the image data based on conditions such as the print position shift, the print method, and the head nozzle interval according to the head mounting position of each color. There was a problem that the processing speed was slowed down.
[0005]
In addition, there is a problem that the processing speed decreases due to the increase in the number of nozzles of the head in pursuit of higher image quality.
[0006]
The present invention has been made in view of such problems, and an object thereof is to provide an image processing apparatus and an image output apparatus that can increase the image processing speed.
[0007]
[Means for Solving the Problems]
  The object of the present invention is achieved by the following inventions.
  1. Memory for storing image data, memory control means for inputting image data and writing image data to the memory at a specified write or read timing, timing for writing or reading image data to the memory control means, and theseOf image dataA CPU for designating the number of data, and when the writing or reading timing and the number of data are designated by the CPU, the memory control unit writes the image data to the memory of the input data without interposing the CPU, Alternatively, the image processing apparatus reads out image data from the memory, and when reading out the image data from the memory, in order to prevent the data from being printed in a blank area formed by the recording paper and the print area, the reading 1 A margin insertion unit that performs processing for reading out data in a margin area as data “0” in units of data per address, and the margin insertion unit cannot perform processing when writing the image data to the memory.Per read addressAn image processing apparatus comprising: a non-image data writing unit that performs a process of writing non-image data for a margin less than the number of data.
  2. SaidThe margin is a margin in the main scanning direction.2. The image processing apparatus as described in 1 above.
  3. SaidThe main scanning direction is the scanning direction of the carriage on which the head is mounted.Said, characterized in that2The image processing apparatus described.
  4). SaidA memory control means for dividing the memory into at least three blocks or more and reading data from other blocks while writing data in one block is provided.
Write and read image data while sequentially switching the writing block and reading block in a ring shape.Characterized in that1The image processing apparatus described.
  5). SaidThe CPU manages the write address to the memory area divided into a plurality of blocks and the read address from the memory area, and controls the CPU not to write to the block being read.Characterized in that4The image processing apparatus described.
  6).The line head is divided into a plurality of blocks, and each block has a read address bus and data bus independently, and each block is read in parallel.Characterized in that4The image processing apparatus described.
[0025]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0026]
FIG. 1 is a block diagram showing an example of the overall configuration of the apparatus of the present invention, and shows a case where it is applied to a printer. In the figure, reference numeral 1 denotes a CPU for controlling a mechanic part and image transfer control according to the present invention. Reference numeral 2 denotes a read timing of the dual port RAM 3 in response to an instruction from the CPU 1 on which stage to read every other line. And a distribution memory access unit that performs write control to the dual port RAM 3 while performing distribution control of image data from the interface control buffer RAM 5. The distribution memory access unit 2 is configured by an FPGA (Field Programmable Gate Array).
[0027]
Reference numeral 3 denotes a dual port memory capable of simultaneously writing and reading image data, which characterizes the present invention. For example, a RAM is used. The dual port RAM 3 has at least three blocks of two blocks (banks) for reading and one block (bank) for writing. 4 is a main memory for storing a program, and 5 is a buffer RAM for temporarily holding image data input from an input interface. Reference numeral 6 denotes a data development unit that performs vertical / horizontal conversion to match the Y, M, C, and K grayscale data provided from the distribution memory access unit 2 with the inkjet line head. The data expansion unit 6 is also composed of an FPGA. Reference numeral 7 denotes a carriage having a line head that receives the output of the data development unit 6.
[0028]
8 is a signal processing unit that performs I / O expansion processing and encoder signal processing connected to various inputs and outputs, 9 is a carriage digital DC servo that is connected to the signal processing unit 8, and 10 is also connected to the signal processing unit 8. A digital DC servo for feeding, 11 is an operation unit having a key matrix and driving the LCD. The operation of the system configured as described above will be described as follows.
[0029]
The input image data is temporarily stored in the buffer RAM 5 and written to the dual port RAM 3 via the distribution memory access unit 2. By repeating such image data writing processing, image data is sequentially stored in the dual port RAM 3.
[0030]
When the image data is stored in the dual port RAM 3, the CPU 1 reads the image data from the read block, and the data development unit 6 performs vertical / horizontal conversion (XY conversion) suitable for the configuration of the line head and outputs it to the carriage 7. The carriage 7 discharges Y, M, C, and K dark and light inks from the nozzles while moving on a recording sheet (not shown) in the main scanning direction, outputs image data, and then moves in the sub scanning direction. An image is formed on the recording paper while repeating the operation. The carriage 7 is controlled by the digital DC servo 9 in the main scanning direction, and is controlled by the digital DC servo 10 in the sub scanning direction.
[0031]
FIG. 2 is a block diagram showing an embodiment of the main part of the present invention. The same components as those in FIG. 1 are denoted by the same reference numerals. In the figure, reference numeral 20 denotes a distribution memory access FPGA. The memory access FPGA 20 can be configured by, for example, an integrated circuit (IC). Input image data enters the buffer RAM 5. The image data stored in the buffer RAM 5 is input to a FIFO (first-in / first-out) memory 17 via the SCSI controller 16.
[0032]
The FIFO controller 22 reads image data from the FIFO 17. At this time, an instruction from the CPU 1 (reading from every row to every other row) is sent to the data input control unit 21 via the CPU interface unit 30. The data input control unit 21 receives the image data (16 bits) read from the FIFO 17 and gives it to the data distribution unit 23. The data distribution unit 23 distributes the input image data of each color Y, M, C, and K into dark data and light data (details will be described later).
[0033]
The image data output from the data distribution unit 23 enters the memory write request unit 24. The output of the memory write request unit 24 enters the memory controller 25. The memory controller 25 performs write control and read control on the dual port memory 3 (details will be described later). At this time, the memory controller 25 and the dual port memory 3 are connected with 32 bits.
[0034]
The dual port memory 3 is divided into three banks (blocks) from bank 0 to bank 2 here, and the capacity thereof is, for example, 64 MB × 3 or 32 MB × 3 although it varies depending on the image size. One of these banks is a write bank and the other two are read banks.
[0035]
The memory controller 25 reads image data from the already written bank. The read image data enters the XY conversion FPGA interface unit 28 via the memory controller 25 and the memory read request unit 26. At this time, the margin insertion unit 27 sets, in the image data, a margin for not placing an image dot in the margin due to the displacement of the mounting position of each color line head (details will be described later). The image data provided with the margin in this way enters the XY conversion FPGA interface 28 and is given to the XY conversion FPGA 6. The XY conversion FPGA 6 performs vertical / horizontal conversion of the image data, drives the line head, and forms an image on the recording paper. As described above, according to the present invention, the CPU 1 only issues a command to read out the image data for a total of how many lines from every line to every other line only during the initial operation, and the subsequent processing is all illustrated in the hardware. It is executed with the hardware. Therefore, by designating image data writing or reading timing from the CPU, it is possible to write image data to the memory and read image data from the memory later by a circuit other than the CPU. As a result, the load on the CPU is reduced and the processing speed can be improved.
[0036]
Next, the operation of the data distribution unit 23 will be described. FIG. 3 is a block diagram showing an embodiment of the data distribution unit 23. A 2-bit COLSEL signal, 4-bit gradation data, and a 16-bit LUT set signal are input to the EAB-RAM control unit 31. Upon receiving these signals, the EAB-RAM control unit 31 outputs a 3-bit address signal for light color and dark color and a write / read control signal for LUT data. These address signals and write / read signals enter the light color LUT 32 and the dark color LUT 33. These LUTs 32 and 33 contain 16-bit input data and are stored internally as LUT data.
[0037]
As a result, input data is output from the light color LUT 32 and the dark color LUT 33 as 16-bit LUT data selected by the address signal. These LUT data enter the LUT comparison unit 34. The LUT comparison unit 34 receives light color LUT data, dark color LUT data, and gradation data, converts 16-bit data into 2 bits for each light color and dark color, and outputs the converted data. At this time, the 4-bit gradation data is for determining which 2 bits of the 16-bit LUT data are to be selected. As shown in the figure, there are four types of 2-bit data: 00, 01, 10, and 11. It is possible to express 16 gradations with a total of 4 bits including light 2 bits and dark 2 bits. These 2-bit LUT outputs are given to the memory write request unit 24 (see FIG. 2).
[0038]
FIG. 4 is a diagram showing a bit configuration of the data distribution LUT. By pulling the matching values from the light color table (LUTKTL, LUTKTH) and the dark color table (LUTKNL, LUTKNH) to the 4-bit input data Kn, respectively, the light color and the dark color are converted into 2-bit data. Distribute. For example, when Kn = 7, the values of the LUTKL bits 15 and 14 are set as light color data, and the values of the LUTKNL bits 15 and 14 are set as dark color data. This is because the printing speed is improved when one piece of 4-bit data is printed in two shades of gray rather than in a single color head with gradation.
[0039]
Next, the operation of the margin insertion unit 27 will be described. FIG. 5 is a diagram for explaining the operation of the margin insertion unit 27. The horizontal direction is the main scanning direction, and the vertical direction is the sub-scanning direction. In the figure, P is a recording sheet, K is a printing area, and a space Q between the recording sheet P and the printing area K is a blank area Q. The print head has 16 bits per line, and in the figure, the margin area includes 16 bits of data in the main scanning direction per address A, B, and C, and an incomplete area D that is less than 16 bits. For areas A, B, and C, 0 is read at the time of printing by changing only the read control by “0” data output without changing the read address. Accordingly, margin control can be performed only in units of data amount (number of pixels) per address.
[0040]
According to this embodiment, when setting the initial position of the print head, it is possible to remove the blank area of the recording paper and write the image data from the print area.
[0041]
In the embodiment described above, when image data is read out and printed by the print head, the margin area in units of the number of data per address can only be processed. When image data is written in the memory, “0” can be written in advance in the portion constituting the margin area. As a result, the margin area of the recording paper can be removed and data can be written from the print area.
[0042]
The configuration of the blank area for the position correction of each color head with respect to the main scanning direction has been described above, but it can be configured with the same technique in the sub operation direction. That is, when reading from the address of the designated row of the dual port memory 3, the read address is not changed in advance, and only read control is performed with "0" data output. By combining the above, the upper, lower, left and right margins can be secured for head position correction.
[0043]
Next, the configuration of the dual port memory according to the present invention will be described. In the present invention, as shown in FIG. 2, the dual port memory 3 comprises three blocks (banks) or more. FIG. 6 is an explanatory diagram of the dual port memory operation. The dual port memory operation is performed by the memory controller 25 (see FIG. 2). In the figure, the memory controller 25 comprises a memory address multiplexer 25a, a memory access controller 25b, and a refresh timer 25c.
[0044]
Of the write address 32 bits and the write data 32 bits from the memory write request unit 24, the lower 24 bits of the address enter the memory address multiplexer 25a and the upper 8 bits enter the memory access controller 25b. Similarly, in the read address 32 bits and the read data 32 bits from the memory read request unit 26, the lower 24 bits of the address enter the memory address multiplexer 25a, and the upper 8 bits of the address enter the memory access controller 25b. The memory access controller 25b receives a write request signal from the memory write request unit 24 and outputs a write ACK corresponding thereto. A read request from the memory read request unit 26 is input, and a read ACK corresponding to the read request is output. The refresh timer 25c is in the memory access controller 25b. The memory address multiplexer 25a is connected to three memory banks, and the memory access controller 25b contains RAS, CAS, WE (write enable), and OE (out enable) signals for each of the memory banks. RAS and CAS are signals that determine which memory bank to select. The memory access controller 25b controls one of the three banks to operate as a write block and the remaining two banks as a read block. The address of the memory bank is 24 bits, but it is not accessed at the same time, but is divided into 12 bits and given twice.
[0045]
FIG. 7 is a diagram illustrating an example in which the memory bank performs read / write operations in a ring shape. Assume that the memory banks (blocks) are B0, B1, and B2. At first, as shown in (1), B0 and B1 are in the read mode (the first is R1, the next is R2), and B2 is the write mode. That is, the bank B2 is in the write mode while the image data is being read from the banks B0 and B1. Next, after reading out to the bank B1, as shown in (2), the image data is read from the bank B2 (read) mode. On the other hand, since reading of the bank B0 has already been completed, the bank B0 enters the write mode. By continuously performing the operation as described above, the banks B0 to B2 enter the write mode and the read mode in a ring shape, and operate as a dual port memory capable of performing writing and reading simultaneously.
[0046]
By the way, the memory 3 in FIG. 2 is divided into banks 1, 2, and 3, and each of them requires more than the memory capacity brought out by one carriage scan. That is, assuming a head in which 64 nozzles are vacant at intervals of 8 pixels, a memory of 512 lines or more (one head line) or more is required.
[0047]
Here, it is assumed that the number of banks of the memory 3 is increased and that there is a bank for each line. Then, as shown in FIG. 11, if the memory 3 has a memory capacity of 1 headline + a, an equivalent FIFO memory can be configured. If n is the number of head lines in FIG. 11, the carriage can be scanned as long as the first n lines are written in the memory.
[0048]
In addition, not all the n lines of data are printed in one scan, but a new line is added for each head line, and the data is printed in a superimposed manner. For this reason, it is sufficient that a memory for a fraction of a line is written before the next scan, and the CPU can grasp how far it has been read and how far it has been written.
[0049]
That is, if a is set to be equal to or larger than the memory capacity corresponding to one-fifth of this line, it can be configured without a memory capacity three times that of one headline. Note that a may be determined from the relationship between the number of nozzles in the head, the nozzle interval, and the print resolution.
[0050]
According to this embodiment, at least three blocks or more are formed even in a configuration for ink jet printing in which a plurality of lines are printed with a space between lines and then the memory reading is performed in a superimposed manner such that the empty lines are filled next. By providing a memory block (bank), a function as a dual port memory capable of simultaneous writing and reading can be provided.
[0051]
In addition, when the line head is very long, it takes time to transfer data if image data is sequentially written to and read from all the line heads. Therefore, in the case of a very long line head, the line head can be divided into several blocks, and image data can be written and read as described above for each divided block.
[0052]
FIG. 8 is an explanatory diagram of the processing operation of the long line head. In the figure, L1 to L4 are obtained by dividing the head into four parts. Then, by having a read address bus and a data bus independently for each block and performing parallel read from each block, the time required for data read can be reduced to ¼. The processing described above is used for processing in each block.
[0053]
In this case, writing is the same as described above, but the point that reading control is performed in parallel in each block is different. However, the address lines at the time of reading can be shared to some extent in each block.
[0054]
According to this embodiment, when a line head having a very large number of dots is driven, it can be driven at high speed.
[0055]
Next, the vertical / horizontal conversion of data will be described. Since the data comes in a line for each color, it is necessary to convert the data vertically and horizontally in the direction of the print head. As shown in FIG. 9, the print head moves in the main scanning direction and the sub-scanning direction. The head is composed of Y1, M1, C1, K1 for high density and Y2, M2, C2, K2 for low density. First, printing is performed with a head in a high density area, and then printing is performed with a low density head shifted by a half pitch. When the printing of one line is completed, the printing operation is continued by moving a predetermined distance in the sub-scanning direction.
[0056]
FIG. 10 is an explanatory diagram of vertical / horizontal conversion (XY conversion). The vertical / horizontal conversion is performed on the image data read by the XY conversion FPGA interface unit 28 of FIG. Since the image data arranged in a line for each color comes up to the print head, it is necessary to convert this image data in the vertical direction so as to fit the print head. As shown in the figure, dark black and light black are arranged as data in units of 16 bits. The 16-bit data arranged in the main scanning direction is rearranged in the vertical direction of 128 nozzles.
[0057]
In this way, the image data subjected to the vertical / horizontal conversion is transferred to the carriage 7 (see FIG. 1), and ink is ejected from the inkjet nozzles onto the recording paper. Thus, by designating the image data writing or reading timing from the CPU, the image data is written to the memory and the image data is read from the memory by a circuit excluding the CPU, and then output to an output device such as a printer. Can be output. That is, the image processing apparatus can also be used as an image output apparatus. In this case, techniques such as margin processing of the print area and read / write switching of the memory bank can be used as they are.
[0058]
Even if the speed of image processing by the distribution memory access unit as described above is increased, it is conceivable that the processing speed decreases if the number of head nozzles is further increased. Therefore, an example will be described below in which the distribution memory access unit 2 and the image memory unit 3 are each configured in parallel to cope with the increase in the number of nozzles and increase the speed.
[0059]
When the number of nozzles in the head is increased, the number of nozzles is increased in a row when the number of nozzles is relatively small. However, since the nozzle interval is not proportional to the resolution and cannot be made fine, and the head length becomes too long, if the number of nozzles exceeds a certain number, the arrangement shown in FIG. It is common. For the sake of explanation, FIG. 12 shows a unit head in which five nozzles spaced every four pixels are arranged in a row, and two sheets are bonded together in a configuration in which two pixels are shifted in the main scanning (line) direction and two pixels in the sub scanning direction. This is an example of a 10 nozzle head. The number of nozzles, the number of overlaps, and the number of unit heads to be used are not limited to this example.
[0060]
FIG. 13 shows a printing pattern by ink ejection for each scanning of each nozzle when printing is performed with the head having the configuration shown in FIG. A block configuration corresponding to such a multi-nozzle is shown in FIG. FIG. 14 has basically the same configuration as that of FIG. 1, and the same reference numerals indicate the same configuration, and thus description thereof is omitted. Here, a plurality of image memories 3 and distribution memory access units 2 are provided.
[0061]
The operation will be described with reference to these drawings. In this example, no. 1 to No. It is assumed that the image processing of the allocation memory access unit with 5 nozzles of 5 is almost the limit. In this case, no. 1 to No. The 10 nozzles should start discharging at the same time and should print 10 lines corresponding to the first scan in FIG. No. 1 to No. No. 5 is No. 1 access part, no. 6 to No. No. 10 is No. Processed by two access units. The data processed separately is subjected to parallel conversion in each data development unit. 1 to No. Head drivers connected to up to 5 nozzles, and No. 5 6 to No. Transfer to head driver connected to up to 10 nozzles.
[0062]
In the next scan, the head shown in FIG. 12 is shifted by one pixel in the sub-scanning direction, and data processed by each sort memory access unit is transferred to each head driver. In the configuration of FIG. 12, since all the lines are filled by the second scanning, the third scanning moves by 19 pixels.
Here, prior to reading from each image memory 3, the CPU 1 should write data in these memories in accordance with the print in FIG. That is, no. 1 is stored in the line No. 1 in the image memory 3. 1, No. 1 2, no. 5, no. 6, no. 9, no. The data of 10 ... In the image memory 3 of FIG. 3, No. 4, no. 7, no. 8, no. 11, no. 12 should be written as appropriate when the CPU 1 inputs image data.
[0063]
With the above configuration, a plurality of heads having a number of nozzles that cannot be processed by only one distribution access unit can be handled in parallel. Here, in the head configuration of FIG. 12, the nozzle interval of each row is every 4 pixels, but for example, if the configuration is every 8 pixels, No. No. 1 is the line to be written to the image memory. 1, No. 1 2, no. 3, No. 4, no. 9, no. No. 10 ... No. 2 is the line to be written to the image memory. 5, no. 6, no. 7, no. 8, no. 13, no. 14 ...
[0064]
Further, the number of columns can be increased by increasing the number of pairs of the image memory 3 and the distribution memory access unit. Further, in these combinations, the heads are overlapped in the main scanning direction, but the same applies when they are connected in the nozzle direction as shown in FIG.
[0065]
In the above-described embodiment, the case where the data width is 32 bits, 16 bits, and the gradation is 4 bits has been described. Can do.
[0066]
【The invention's effect】
As explained in detail above,
(1) According to the first invention, the memory for storing the image data, the memory control means for inputting the image data and writing the image data to the memory at the designated write or read timing, and the memory control means CPU for designating the timing of writing or reading image data and the number of these data, and specifying the timing of writing or reading and the number of data by the CPU, the memory control means can input without intervening the CPU. By writing image data to the memory or reading the image data from the memory, the timing for writing or reading the image data from the CPU is specified, and then the memory is transferred to the memory by a circuit other than the CPU. Write image data and image data from memory It can be read.
[0067]
(2) In this case, when the image data is read from the memory, a print head mounting position shift is caused by providing a blank insertion portion for preventing data from being printed in a blank area formed by the recording paper and the print area. As a response to the above, image data can be written from the position where each color matches.
[0068]
(3) In addition, when writing the image data into the memory, a non-image data writing unit for writing non-image data for the margin is provided so that the data is not ejected into the margin area composed of the recording paper and the print area. Thus, when writing the image data into the memory, 0 data can be written in the margin area corresponding portion, and the image data can be written from the position where each color matches in the main scanning direction pixel unit.
[0069]
(4) Further, when the image data is read from the memory, a blank insertion portion for additionally reading out the number of pixels corresponding to the blank position corresponding to the mounting position shift of each color head with “0” data is provided. Is read out from the memory, 0 data is written in the margin area corresponding portion so that the margin area of the recording paper is removed and the image data can be read out from the print area.
[0070]
(5) The memory is divided into at least three blocks and memory control means for reading data from other blocks while data is written to one block is provided, and the writing block and the reading block are in a ring shape. By simultaneously writing to and reading out the image data while switching sequentially, the simultaneous writing is also possible for superimposed reading in which a part of the reading area is gradually updated by providing at least three memory blocks. And a function as a dual port memory capable of reading.
[0071]
(6) The CPU manages a write address to the memory area divided into the plurality of blocks and a read address from the memory area, and controls the CPU not to write to the block being read. As a result, the memory capacity can be reduced.
[0072]
(7) Further, the line head is divided into a plurality of blocks, and the read address bus and the data bus are independently provided for each block, and each block is read in parallel. When a large line head is driven, data can be transferred at high speed.
[0075]
Thus, according to the present invention, it is possible to provide an image processing apparatus and an image output apparatus that can increase the image processing speed.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an example of the overall configuration of an apparatus according to the present invention.
FIG. 2 is a block diagram showing an embodiment of a main part of the present invention.
FIG. 3 is a block diagram illustrating an embodiment of a data distribution unit.
FIG. 4 is a diagram illustrating a bit configuration of a data distribution LUT.
FIG. 5 is an operation explanatory diagram of a margin insertion unit.
FIG. 6 is an explanatory diagram of a dual port memory operation.
FIG. 7 is a diagram illustrating an example in which a memory bank performs a read / write operation in a ring shape.
FIG. 8 is an explanatory diagram of a processing operation of a long line head.
FIG. 9 is an explanatory diagram of the print head in the scanning direction.
FIG. 10 is an explanatory diagram of vertical / horizontal conversion.
FIG. 11 is a schematic diagram showing a memory capacity.
FIG. 12 is a schematic diagram of a nozzle surface of a head in which two 4-line intervals are attached.
FIG. 13 is a schematic diagram showing a print position for each nozzle scan.
FIG. 14 is a configuration diagram of a multi-nozzle head.
FIG. 15 is a schematic diagram of a nozzle surface of a head in which two 4-line intervals are pasted in series.
[Explanation of symbols]
1 CPU
3 Dual port memory
5 Buffer RAM
6 XY conversion FPGA
16 SCSI controller
17 FIFO
20 Distribution / memory access FPGA
21 Data input control section
22 FIFO control section
23 Data distribution part
24 Memory write request part
25 Memory controller
26 Memory read request section
27 Margin insertion part
28 XY conversion FPGA interface
29 I / O register section
30 CPU interface

Claims (6)

A memory for storing image data;
Memory control means for inputting image data and writing the image data to the memory at a specified writing or reading timing;
A CPU for designating image data writing or reading timing to the memory control means and the number of data of these image data ;
When writing or reading timing and the number of data are specified by the CPU, the memory control means writes input data to the memory or reads image data from the memory without intervention of the CPU. An image processing apparatus,
When the image data is read from the memory, the data in the blank area is read as “0” data in units of the number of data per one read address in order not to print data in the blank area formed by the recording paper and the print area. A margin insertion unit that performs processing, and a process of writing non-image data for a margin that is less than the number of data per address of the read that cannot be performed by the margin insertion unit when the image data is written to the memory An image processing apparatus comprising: a non-image data writing unit. The image processing apparatus according to claim 1 , wherein the margin is a margin in a main scanning direction . The image processing apparatus according to claim 2 , wherein the main scanning direction is a scanning direction of a carriage on which a head is mounted . A memory control means for dividing the memory into at least three blocks and reading data from other blocks while writing data in one block;
The image processing apparatus according to claim 1, wherein the writing and reading of the image data while sequentially switching the write block and read block in a ring shape. The CPU manages a write address to a memory area divided into a plurality of blocks and a read address from the memory area, and controls the CPU not to write to a block being read. Item 5. The image processing apparatus according to Item 4 . 5. The image processing according to claim 4 , wherein the line head is divided into a plurality of blocks, and an address bus and a data bus for reading are independently provided for each block, and each block is read in parallel. apparatus.

Images