JP2580641B2 - Block synchronization circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to digital communication, and more particularly to a block synchronization circuit.

2. Description of the Related Art Conventionally, an example of this type of block synchronization circuit is to directly input an original code string from an input terminal 6 to a specific bit detection and synchronization circuit 5 as shown in FIG. And the synchronization circuit 5 has a synchronization protection circuit for connecting several necessary protection stages in series with a shift register.

This synchronization protection circuit has a number of stages as a front protection circuit (a circuit that truly determines whether or not synchronization has occurred) and a rear protection circuit (a circuit that truly determines whether or not synchronization has been restored). Have (For example, NTT Research and Application Report, Vol. 32, No. 3, 1983, 603-604
page).

Also, the number of stages Ne (the number of blocks) of the front protection circuit is calculated by the following equation.

It is.

Similarly number N _h of backward protection circuit is calculated by the following equation.

The number of shift registers required in the synchronization protection circuit depends on the larger of the number of front protection stages and the number of rear protection stages. Now, consider the following code string as an example (see FIG. 2A).

Transmission speed 2 Gbit / sec Block length 10 bit Specific bit “1” Code mark rate 1/2 Also, use the following values for parameters.

Calculation result is determined to be N _e 4.45 9.81N _h 10.0, and the forward protection 5-stage posterior direction 10 stages.

In this conventional block synchronization circuit, the original code string (mark rate
Since the synchronization detection is performed by directly inputting (1/2)), there is a disadvantage that the number of synchronization protection stages becomes as large as 10. This is particularly remarkable with respect to the number of rear protection stages, as seen in the example described above. When the number of protection stages is large, there is a disadvantage that the entire circuit scale becomes large and the price and power consumption increase.

[Problems to be solved by the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a block synchronization circuit which solves the above-mentioned drawbacks, that is, the problem that when the original code string is input as it is, the number of synchronization protection stages increases, and the price and power consumption increase.

[Means for Solving the Problems] In order to solve the above problems, the present invention provides a conventional synchronous circuit having a plurality of serial shift registers, a branching unit for branching an input code string into two branches. A configuration having N stages (N is an integer of 1 or more) including a delay circuit for delaying one of the branched n bits and a gate for obtaining a logical product or an OR of the output and the other input code string Is adopted.

[Action]

Since the present invention is configured as described above, when the input code string is a specific bit “1” and the other mark rate is 1/2, the specific bit is “1” by logical AND with the delay circuit once, and the other bit is “1”. The mark rate becomes 1/4, and by repeating this N times, the specific bit becomes “1” and the other mark rates become 1/2 ^a (a =
2 ⁿ ), and the number of protection stages in the block synchronization circuit can be reduced.

When the specific bit is "0" and the mark rate other than that is 1/2, the number of protection steps can be similarly reduced by using a logical talk instead of a logical product.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

Referring to FIG. 1 showing a circuit diagram of an embodiment of the present invention, a block synchronizing circuit of the present invention branches an input signal into two and delays one of them by n bits, and the output is branched to the output. An AND gate 1 for ANDing the other input signal, a delay circuit 4 for further separating this output into two and delaying one of them, and an AND gate 2 for ANDing this output and the output of the preceding stage; It comprises a specific bit detection and synchronization circuit 5 for introducing this output.

FIG. 2 is a waveform diagram showing a code string of each part in FIG.

Next, the operation of this embodiment will be described with reference to FIG. 1 and FIG.

First, consider a code string A having a specific bit “1” for every n bits and a mark rate other than 1/2. First
In the figure, the code string A is divided into two, and one of them is given an n-bit delay. When the logical product of the two is calculated, the code string B in which the specific bit “1” overlaps and the other mark rate is 1/4
Get. When this process is repeated N times, a code string having a mark ratio of 1 / ^22N other than the specific bit is obtained. In FIG. 1, a code string C having a mark rate 116 is formed twice. In this case, since the specific bit is “1”, a logical product is taken to reduce the other mark rates, but the specific bit is “0”.
In the case of (1), a logical sum is calculated to increase the other mark rates.

Next, consider the number of protection stages when block synchronization is performed by detecting a specific bit of the code string C.

In this example, four specific bits are detected in an overlapping manner, and the code error rate ε in the equations (1) and (2) needs to be replaced with 4ε, and the mark rate M of the code is 1/16.
It is.

Other variables are the same as those used in the description of the related art.

(1) is determined as (2) Calculating the protection stage from the equation N _e 5.24 2.45N _h 25 next forward protection 6-stage backward protection three stages.

In the example, by changing the mark ratio from 1/2 to 1/16, the number of rear protection steps could be reduced from 10 steps to 3 steps.

Although the number of front protection steps has increased from five to six, it is small compared to the decrease in rear protection steps. The reason for this is that the apparent increase in the bit error rate caused by viewing several specific bits in a superimposed manner is significantly smaller than the change in the mark rate.

Therefore, there is an advantage that the size of the synchronization protection circuit can be reduced from 10 stages to 6 stages as a whole, and the price and power consumption of the entire device can be reduced.

〔The invention's effect〕

As described above, according to the present invention, by providing an N-stage additional circuit including an n-bit delay circuit and a logic gate, the mark ratio of an input code string can be changed and the number of synchronization protection stages can be reduced. This has the effect of reducing the size of the device and reducing power consumption.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram of one embodiment of the present invention, FIG. 2 is a diagram showing a code string of each part in FIG. 1, and FIG. 3 is a block diagram showing a conventional example. 1,2 ... AND gate, 3,4 ... delay circuit, 5 ... specific bit detection and synchronization circuit, 6 ... input terminal, A, B, C ...
Each part waveform.

Claims (1)

(57) [Claims] 1. A block synchronization circuit having a plurality of serial shift registers for inputting a code string having a specific bit inserted therein for every n bits and detecting and synchronizing the specific bit. A delay circuit that branches the code string into two and delays one of them by n bits, and a circuit that includes a gate that takes the logical product or the logical sum of the output of the delay circuit and the input, comprises N stages (N ≧ 2). A block synchronization circuit, comprising: