JPS6390070A - Synchronizing signal detecting system - Google Patents

Abstract

PURPOSE:To improve the detecting capacity of a synchronizing signal by using a delay circuit and a gate circuit to delay reproduced data by integer times the repeating period of a synchronizing signal, and correlate the delayed signal with the original signal. CONSTITUTION:A signal A inputted to an input terminal 10 is delayed by the repeating period of a synchronizing signal through a delay circuit 11. A synchronizing signal detecting circuit 12 detects a synchronizing signal E from the original signal A and the delayed signal B. The signal E is sent to a digital processing circuit 13, various arithmetic processing of the signal B, e.g. error correction and time axis conversion, is executed on the basis of the signal E and the processed signal is outputted to an output terminal 14. Even if data or synchronization is discontinued by the circuit 12, i.e. when the synchronization of an intermittent signal is missed at its head, a synchronizing signal can be detected. Thus, the detecting capacity of the synchronizing signal can be improved by said constitution.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a synchronization signal detection method for digital signals.
In particular, the present invention relates to a synchronization signal detection method for data having discontinuous portions.

[Conventional technology]

In a system for transmitting, recording and reproducing digital signals, it is essential to perform bit synchronization, word synchronization, and block synchronization in order to restore the original data from the reproduced signal. Therefore, by adding a synchronization signal at a fixed period and detecting this synchronization signal during playback, word synchronization and
Measures such as block synchronization are adopted. However, if these synchronizations cannot be detected due to disturbances occurring during transmission, all data in this block will be erroneous. Various synchronization protection schemes have been proposed to deal with this problem. Most of these methods are based on the idea that when a determined synchronization signal is obtained, the subsequent synchronization signal is predicted, and if the reproduced synchronization signal is incorrect, interpolation is performed.

However, in devices using rotating heads or systems in which data transmission is performed intermittently, it is extremely difficult to reproduce the initial synchronization signal for which prediction cannot be applied. For this reason, devices have been proposed which apply other auxiliary means to determine the position of the first synchronization signal. For example, JP-A-58-
A method has been proposed, such as the digital signal transmission device disclosed in Japanese Patent No. 94254, in which specific data is inserted only into the first block to improve the ability to identify the first block. In addition, as in the method for recording and reproducing cue signals in a rotary head type recording and reproducing apparatus disclosed in Japanese Patent Application Laid-Open No. 59-168961, a special recording area for cueing signals is provided separately from the recording area for PCM signals. Several methods have been proposed for recording signals.

[Problem that the invention seeks to solve]

However, these methods require recording a special signal, and if an error occurs at that position, there is a problem that an error in synchronization detection will occur (3).

SUMMARY OF THE INVENTION An object of the present invention is to provide a synchronization signal detection method that can improve the synchronization detection ability of a leading block even in an apparatus that cannot record special signals.

[Means for solving problems]

The present invention is characterized in that the detection efficiency of the synchronization signal is improved by delaying the reproduced data by an integral multiple of the repetition period To of the synchronization signal and correlating it with the original signal.

[Effect]

FIG. 2 shows an example of a timing chart of digital data including a synchronization signal (SY), and the present invention will be explained in detail using this diagram. It is assumed that the input signal A is composed of a dummy data section 2 preceding the synchronizing signal 1 and a digital data section 3. B is a signal obtained by delaying the input signal A by one cycle To of the synchronization signal. A synchronization signal is detected for each of these signals, and the logical sum and AND of these two signals are calculated. If an error occurs in the synchronization signal of the first block, the first synchronization signal will be lost as shown by the dotted line. However, as shown in the figure, the output signal of the OR C is equivalent to the detection of the leading synchronization signal for the delayed data B. By delaying the signal in this manner, it becomes possible to estimate the front synchronization signal from the rear synchronization signal.

Furthermore, in order to detect the synchronization signal, the correlation between the original signal A and the delayed signal B may be determined, and if they match, this may be used as the synchronization signal. Therefore, calculate the exclusive OR of A and B, count the number of matching bits within a certain time width (width of the synchronization pattern), and if the result is greater than the set value, use this as the synchronization signal. good.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1 and 2. The signal A input to the input terminal 10 is processed by the delay circuit 11 so that the synchronization signal repeats at a repetition period T.

[F]). Next, the synchronization signal detection circuit 12
Then, a synchronizing signal is detected from the original signal A and the delayed signal B by means described later. This synchronizing signal E is sent to a digital processing circuit 13, and after various arithmetic processing is performed on the delayed signal B, such as error correction and data time axis conversion, it is outputted to an output terminal 14.

A detailed configuration diagram of the synchronization signal detection circuit 12 is shown in FIG.

Signal A from input terminal 10 is input to first synchronization pattern detection circuit 20 . This circuit detects a synchronization pattern from the signal A and outputs a synchronization detection pulse A/ (not shown) to an AND circuit 22 and an OR circuit 23. Similarly, the output signal B of the delay circuit 11 is transmitted to the second synchronization pattern detection circuit 2.
1 and outputs a synchronization detection pulse B/ (not shown). The output signal of the AND circuit 22 and the output signal C1 of the OR circuit 23 are input to the synchronization determination circuit 24. In this circuit, when the output signal of the AND circuit 22 turns ON, it is assumed that a completely correct synchronization signal has been obtained, and operations such as synchronization prediction, which will be described later, are initialized. If the output signal C from the AND circuit 22 is not obtained for several cycles, the synchronization determination circuit 24 considers the output signal C of the zero-pass circuit 23 to be the correct synchronization signal. As a result, the synchronization signal at the beginning of the diblock is OR
It becomes the output of the circuit and can be detected correctly. Note that after the synchronization detection is confirmed, the synchronization protection processing circuit 25 protects the data from being erroneously detected due to the same pattern as the synchronization signal included in the data.

If the above circuit causes discontinuity in data or synchronization,
That is, even if the synchronization at the beginning of an intermittent signal is incorrect, the synchronization signal can be detected efficiently.

Another embodiment of the present invention will be described with reference to FIG.

This figure shows a portion of the synchronizing signal detection circuit 12 of FIG. 3. First and second synchronization pattern detection circuits 20
, the OR circuit 23 is the same as in FIG. In this example, the signal A from the input terminal 10 and the signal B from the delay circuit 11 are input to the exclusive OR EXOR circuit 30, and the correlation between the two signals is calculated.

The output H of the EXOR circuit 30 and the output of the OR circuit 23 are input to a synchronization determination circuit 31. In this circuit, for example, if the signal C is not ON and the output signal H of the EXOR circuit is
If the number of "1"s becomes equal to or greater than the set value during the synchronization period, this is regarded as a correct synchronization signal. In other words, it is assumed that a synchronization signal can be detected when a synchronization pattern exists in either signal CA or B, and there is a strong correlation between both signals. Further, the synchronization protection processing circuit 25 is the same as that shown in Fig. 11g3, so its description will be omitted.

In the above example, the signal delay is equal to the repetition period of the periodic signal, but it goes without saying that it may be an integral multiple of this.

〔Effect of the invention〕

As described above, according to the present invention, by using a simple delay circuit, gate circuit, etc., it is possible to use a system that processes intermittent data such as a recording/reproducing method using a rotating head. The ability to detect synchronization signals can be greatly improved.

Further, even when a relatively long error occurs due to dropout or the like and the synchronization signal cannot be detected, this circuit has the advantage that the same effect can be obtained and the synchronization detection ability is improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a timing chart showing waveforms of each part of FIG. 1, and FIG.
1 is a diagram showing details of the synchronizing signal detection circuit of FIG. 1, and FIG. 4 is a diagram showing another example of the synchronizing signal detection circuit of FIG. 1. 11...Delay circuit, 12...Synchronization signal detection circuit, 1
3...Digital processing circuit. Ue 1 Zubo 2 Diagram (E)

Claims (1)

[Claims] 1. In a method for transmitting, recording and reproducing digital data including at least two synchronization signals, means for delaying the reproduction signal by an integral multiple of the repetition period To of the synchronization signal; a first synchronization detection means for detecting a synchronization signal position from a delayed signal; and a second synchronization detection means for detecting a synchronization signal position from the reproduced signal before being delayed; A synchronization signal detection method is characterized in that a synchronization signal is determined by performing arithmetic processing on a detected signal. 2. In claim 1, the above-mentioned first and second
A synchronization signal detection method characterized in that a logical sum of synchronization signal detection outputs is used as a synchronization signal. 3. In claim 1, the above-mentioned first and second
After taking the exclusive OR of the synchronization signals, this signal becomes “1”.
A synchronization signal detection method is characterized in that a synchronization signal is determined to be determined when the result of counting the number of for a certain period of time is equal to or greater than a set value.